DIGITAL ASSIGNMENT-II

ECE-2003

DIGITAL LOGIC AND DESIGN

SLOT-A2

PROF: SAKTHIVEL R

Submitted by: Adarsh raj

(16BEC0075)
1) Using continuous assignment statements and the port syntax of the IEEE 1364-2001
standard, write and verify a gate-level model of the four-bit even parity checker (2Marks)
Soln:

Even Parity Checker

Consider that three input message along with even parity bit is generated at the transmitting end.
These 4 bits are applied as input to the parity checker circuit which checks the possibility of error on
the data. Since the data is transmitted with even parity, four bits received at circuit must have an
even number of 1s.

If any error occurs, the received message consists of odd number of 1s. The output of the parity
checker is denoted by PEC (parity error check).

The below table shows the truth table for the even parity checker in which PEC = 1 if the error
occurs, i.e., the four bits received have odd number of 1s and PEC = 0 if no error occurs, i.e., if the
4-bit message has even number of 1s.

The above truth table can be simplified using K-map as shown below.
The above logic expression for the even parity checker can be implemented by using three Ex-OR
gates as shown in figure. If the received message consists of five bits, then one more Ex-OR gate is
required for the even parity checking.

VERILOG CODE :
module Even_Parity_Checker_4 (output C, input x, y, z, p);
xor(w1, x, y);
xor(w2, z, p);
xor(C, w1, w2);
endmodule
Q 2) Write a Verilog model of a circuit whose 32-bit output is formed by shifting its 32-bit
input three positions to the right and filling the vacant positions with the bit that was in the
MSN before the shift occurred (shift arithmetic right).Write a Verilog model of a circuit
whose 32-bit output is formed by shifting its 32-bit input three positions to the left and
filling the vacant positions with 0 (shift logical left). (3Marks).

Soln:

Shiftright_by_3:

module shift_right_by_3_V1995 (output reg [31: 0] sig_out, input [31: 0] sig_in);

always @ (sig_in)
sig_out = {sig_in[31], sig_in[31], sig_in[31], sig_in[31: 3]};
endmodule
module t_shift_right_by_3 ();
wire [31: 0] sig_out_V1995;
wire [31: 0] sig_out_V2001;
reg [31: 0] sig_in;
//shift_right_by_3_V2001 M0 (sig_out_V2001, sig_in);
shift_right_by_3_V1995 M1 (sig_out_V1995, sig_in);
integer k;
initial #1000 $finish;
initial begin
sig_in = 32'hf000_0000;
#100 sig_in = 32'h8fff_ffff;
#500 sig_in = 32'h0fff_ffff;
end
endmodule
Shiftleft_by_3:
VERILOG CODE:
module shiftleft_by_3(out,in);
output reg [31: 0] out;
input [31: 0] in;
always @ (in)
out = {in[28: 0],1'b0,1'b0,1'b0};
endmodule
module shiftleft1_by_3 ();
wire [31: 0] out1;
wire [31: 0] out2;
reg [31: 0] in1;
shiftleft_by_3 F1(out1,in1);
endmodule.
Q3) Develop a verilog code and simulate a behavioral model of the ABCD-to-seven-
segment decoder. An ABCD-to-seven-segment decoder is a combinational circuit that
converts a decimal digit in BCD to an appropriate code for the selection of segments in an
indicator used to display the decimal digit in a familiar form. The seven outputs of the
decoder (a, b, c, d, e, f, g) select the corresponding segments in the display, as shown in
Fig. (a) . The numeric display chosen to represent the decimal digit is shown in Fig. (b) .
Using a truth table and Karnaugh maps, design the BCD-to-seven-segment decoder using
a minimum number of gates. The six invalid combinations should result in a blank
display.

Soln:

Step 1: The first step of the design involves analysis of the common cathode 7-segment display. A
7-segment display consists of an arrangement of LEDs in an ‘H’ form. A truth table is constructed
with the combination of inputs for each decimal number. For example, decimal number 1 would
command a combination of b and c (refer the diagram given below).

7 Segment LED
Step 2: The second step involves constructing the truth table listing the 7 display input signals,
decimal number and corresponding 4 digit binary numbers.

The truth table for the decoder design depends on the type of 7-segment display. As we mentioned
above that for a common cathode seven-segment display, the output of decoder or segment driver
must be active high in order to glow the segment.

The figure below shows the truth table of a BCD to seven-segment decoder with common cathode
display. In the truth table , there are 7 different output columns corresponding to each of the 7
segments.

Suppose the column for segment a shows the different combinations for which it is to be
illuminated. So ‘a’ is active for the digits 0, 2, 3, 5, 6, 7, 8 and 9.

From the above truth table, the Boolean expressions of each output functions can be written as

a = F1 (A, B, C, D) = ∑m (0, 2, 3, 5, 7, 8, 9)

b = F2 (A, B, C, D) = ∑m (0, 1, 2, 3, 4, 7, 8, 9)

c = F3 (A, B, C, D) = ∑m (0, 1, 3, 4, 5, 6, 7, 8, 9)

d = F4 (A, B, C, D) = ∑m (0, 2, 3, 5, 6, 8)

e = F5 (A, B, C, D) = ∑m (0, 2, 6, 8)
f = F6 (A, B, C, D) = ∑m (0, 4, 5, 6, 8, 9)

g = F7 (A, B, C, D) = ∑m (2, 3, 4, 5, 6, 8, 9)

Step 3: The third step involves constructing the Karnough’s map for each output term and then
simplifying them to obtain a logic combination of inputs for each output.

K-Map Simplification

The below figures shows the k-map simplification for the common cathode seven-segment decoder
in order to design the combinational circuit.
From the above simplification, we get the output values as

VERILOG CODE:

module bcd_7seg_decoder(input [3:0] bcd,output reg [6:0] seven_seg);

always @(*)
case (bcd)
4'b0000:seven_seg= 7'b1111110;
4'b0001:seven_seg= 7'b0110000;
4'b0010:seven_seg= 7'b1101101;
4'b0011:seven_seg= 7'b1111001;
4'b0100:seven_seg= 7'b0110011;
4'b0101:seven_seg= 7'b1011011;
4'b0110:seven_seg= 7'b1011111;
4'b0111:seven_seg= 7'b1110000;
4'b1000:seven_seg= 7'b1111111;
4'b1001:seven_seg= 7'b1111011;
4'b1010:seven_seg= 7'bxxxxxxx;
4'b1011:seven_seg= 7'bxxxxxxx;
4'b1100:seven_seg= 7'bxxxxxxx;
4'b1101:seven_seg= 7'bxxxxxxx;
4'b1110:seven_seg= 7'bxxxxxxx;
4'b1111:seven_seg= 7'bxxxxxxx;
endcase
endmodule
OUTPUT:
 OR
module Seven_Seg_Display_V2001 (
output reg [6: 0] Display,
input [3: 0] BCD
);
// abc_defg
parameter BLANK = 7'b000_0000;
parameter ZERO = 7'b111_1110; // h7e
parameter ONE = 7'b011_0000; // h30
parameter TWO = 7'b110_1101; // h6d
parameter THREE = 7'b111_1001; // h79
parameter FOUR = 7'b011_0011; // h33
parameter FIVE = 7'b101_1011; // h5b
parameter SIX = 7'b101_1111; // h5f
parameter SEVEN = 7'b111_0000; // h70
parameter EIGHT = 7'b111_1111; // h7f
parameter NINE = 7'b111_1011; // h7b
always @ (BCD)
case (BCD)
0: Display = ZERO;
1: Display = ONE;
2: Display = TWO;
3: Display = THREE;
4: Display = FOUR;
5: Display = FIVE;
6: Display = SIX;
7: Display = SEVEN;
8: Display = EIGHT;
9: Display = NINE;
default: Display = BLANK;
endcase
endmodule
module t_Seven_Seg_Display_V2001 ();
wire [6: 0] Display;
reg [3: 0] BCD;
parameter BLANK = 7'b000_0000;
parameter ZERO = 7'b111_1110; // h7e
parameter ONE = 7'b011_0000; // h30
parameter TWO = 7'b110_1101; // h6d
parameter THREE = 7'b111_1001; // h79
parameter FOUR = 7'b011_0011; // h33
parameter FIVE = 7'b101_1011; // h5b
parameter SIX = 7'b001_1111; // h1f
parameter SEVEN = 7'b111_0000; // h70
parameter EIGHT = 7'b111_1111; // h7f
parameter NINE = 7'b111_1011; // h7b
initial #120 $finish;
initial fork
#10 BCD = 0;
#20 BCD = 1;
#30 BCD = 2;
#40 BCD = 3;
#50 BCD = 4;
#60 BCD = 5;
#70 BCD = 6;
#80 BCD = 7;
#90 BCD = 8;
#100 BCD = 9;
join
Seven_Seg_Display_V2001 M0 (Display, BCD);
endmodule