AUTOMOTIVE GRADE AUIRFR8405

AUIRFU8405
Features   VDSS 40V
 Advanced Process Technology RDS(on) typ. 1.65m
 New Ultra Low On-Resistance max. 1.98m
 175°C Operating Temperature
ID (Silicon Limited) 211A
 Fast Switching
 Repetitive Avalanche Allowed up to Tjmax ID (Package Limited) 100A
 Lead-Free, RoHS Compliant D
 Automotive Qualified * D
Description
Specifically designed for Automotive applications, this HEXFET® Power MOSFET
utilizes the latest processing techniques to achieve extremely low on-resistance per S S
silicon area. Additional features of this design are a 175°C junction operating G D
G
temperature, fast switching speed and improved repetitive avalanche rating. These
D-Pak I-Pak
features combine to make this design an extremely efficient and reliable device for
AUIRFR8405 AUIRFU8405
use in Automotive applications and wide variety of other applications.
Applications
 Electric Power Steering (EPS) G D S
 Battery Switch
 Start/Stop Micro Hybrid
Gate Drain Source
 Heavy Loads
 DC-DC Converter
Standard Pack
Base part number Package Type Orderable Part Number
Form Quantity
AUIRFU8405 I-Pak Tube 75 AUIRFU8405
Tube 75 AUIRFR8405
AUIRFR8405 D-Pak
Tape and Reel Left 3000 AUIRFR8405TRL
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance and
power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless
otherwise specified.
Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 211
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 150
A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited) 100
IDM Pulsed Drain Current  804
PD @TC = 25°C Maximum Power Dissipation 163 W
Linear Derating Factor 1.1 W/°C
VGS Gate-to-Source Voltage ± 20 V
TJ Operating Junction and -55 to + 175  
TSTG Storage Temperature Range °C 
Soldering Temperature, for 10 seconds (1.6mm from case) 300  
Avalanche Characteristics
EAS Single Pulse Avalanche Energy (Thermally Limited)  208
mJ
EAS (tested) Single Pulse Avalanche Energy (Tested Limited)  256
IAR Avalanche Current  See Fig. 14, 15, 24a, 24b A
EAR Repetitive Avalanche Energy  mJ

Thermal Resistance  
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case  ––– 0.92
RJA Junction-to-Ambient ( PCB Mount)  ––– 50 °C/W
RJA Junction-to-Ambient ––– 110
HEXFET® is a registered trademark of Infineon.
*Qualification standards can be found at www.infineon.com

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Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 40 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.03 ––– V/°C Reference to 25°C, ID = 5mA 
RDS(on) Static Drain-to-Source On-Resistance ––– 1.65 1.98 m VGS = 10V, ID = 90A** 
VGS(th) Gate Threshold Voltage 2.2 3.0 3.9 V VDS = VGS, ID = 100µA
––– ––– 1.0 VDS = 40V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 150 VDS = 40V,VGS = 0V,TJ =125°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
IGSS   nA  
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
RG Internal Gate Resistance ––– 2.3 ––– 
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
gfs Forward Trans conductance 294 ––– ––– S VDS = 10V, ID = 90A**
Qg Total Gate Charge ––– 103 155 ID = 90A**
Qgs Gate-to-Source Charge ––– 26 ––– VDS = 20V
nC  
Qgd Gate-to-Drain Charge ––– 38 ––– VGS = 10V
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 65 –––
td(on) Turn-On Delay Time ––– 12 ––– VDD = 26V
tr Rise Time ––– 80 ––– ID = 90A**
ns
td(off) Turn-Off Delay Time ––– 51 ––– RG = 2.7
tf Fall Time ––– 51 ––– VGS = 10V
Ciss Input Capacitance ––– 5171 ––– VGS = 0V
Coss Output Capacitance ––– 770 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 523 ––– pF   ƒ = 1.0MHz, See Fig. 5
Coss eff. (ER) Effective Output Capacitance (Energy Related) ––– 939 ––– VGS = 0V, VDS = 0V to 32V 
Coss eff. (TR) Effective Output Capacitance (Time Related) ––– 1054 ––– VGS = 0V, VDS = 0V to 32V 
Diode Characteristics  
Parameter Min. Typ. Max. Units Conditions
Continuous Source Current MOSFET symbol
IS ––– ––– 211
(Body Diode) showing the
A
Pulsed Source Current integral reverse
ISM ––– ––– 804
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– 0.9 1.3 V TJ = 25°C,IS = 90A** ,VGS = 0V 
dv/dt Peak Diode Recovery dv/dt ––– 2.1 ––– V/ns TJ = 175°C,IS = 90A** ,VDS = 40V 
trr Reverse Recovery Time ––– 28 ––– TJ = 25°C VR = 34V,
ns
––– 29 ––– TJ = 125°C
IF = 90A**
Qrr Reverse Recovery Charge ––– 19 ––– TJ = 25°C
nC di/dt = 100A/µs 
––– 20 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 1.1 ––– A TJ = 25°C
Notes:
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 100A by source
bonding technology. Note that current limitations arising from heating of the device leads may occur with some lead mounting
arrangements. (Refer to AN-1140)
 Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)
 Limited by TJmax , starting TJ = 25°C, L = 0.051mH, RG = 50, IAS = 90A, VGS =10V. Part not recommended for use above this value.
ISD  90A, di/dt  1304A/µs, VDD V(BR)DSS, TJ  175°C.
 Pulse width 400µs; duty cycle  2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
 When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994
 Ris measured at TJ approximately 90°C.
 Pulse drain current is limited by source bonding technology.
** All AC and DC test condition based on old Package limitation current = 90A.

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AUIRFR/U8405
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

7.0V 7.0V
6.0V 6.0V
5.5V 5.5V
100 5.0V 5.0V
BOTTOM 4.8V BOTTOM 4.8V

100
4.8V 4.8V

10

60µs PULSE WIDTH 60µs PULSE WIDTH

Tj = 25°C Tj = 175°C
1 10
0.1 1 10 100 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig. 1 Typical Output Characteristics Fig. 2 Typical Output Characteristics

2.0
1000

R DS(on) , Drain-to-Source On Resistance

ID = 90A
VGS = 10V
ID, Drain-to-Source Current (A)

T J = 175°C 1.6
100

T J = 25°C (Normalized) 1.2

10

0.8
1

VDS = 10V
60µs PULSE WIDTH
0.1 0.4
2 3 4 5 6 7 8 -60 -20 20 60 100 140 180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)

Fig. 3 Typical Transfer Characteristics Fig. 4 Normalized On-Resistance vs. Temperature

100000 14.0
VGS = 0V, f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
ID = 90A
Crss = C gd 12.0
VGS, Gate-to-Source Voltage (V)

VDS = 32V
Coss = Cds + Cgd
10.0 VDS = 20V
C, Capacitance (pF)

10000
C iss
8.0

C oss 6.0

1000 C rss
4.0

2.0

100 0.0
0.1 1 10 100 0 20 40 60 80 100 120 140
VDS , Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage

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AUIRFR/U8405
1000 10000
OPERATION IN THIS AREA
LIMITED BY R DS(on)

ID, Drain-to-Source Current (A)

T J = 175°C
ISD, Reverse Drain Current (A)

1000
100
100µsec

100
T J = 25°C 1msec
10
Limited by Package
10

10msec
1
1 Tc = 25°C
DC
VGS = 0V Tj = 175°C
Single Pulse
0.1 0.1
0.2 0.6 1.0 1.4 1.8 0.1 1 10 100
VSD , Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig. 7 Typical Source-to-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area

V(BR)DSS , Drain-to-Source Breakdown Voltage (V)

240 48
Id = 5.0mA
210 Limited By Package
47

180 46
ID, Drain Current (A)

150 45

120 44

90 43

60 42

30 41

0 40
25 50 75 100 125 150 175 -60 -20 20 60 100 140 180

T C , Case Temperature (°C) T J , Temperature ( °C )

Fig. 9 Maximum Drain Current vs. Case Temperature Fig 10. Drain-to-Source Breakdown Voltage
0.8 900
ID
EAS , Single Pulse Avalanche Energy (mJ)

0.7 800
TOP 18A
700 37A
0.6 BOTTOM 90A
600
0.5
Energy (µJ)

500
0.4
400
0.3
300
0.2
200
0.1 100

0.0 0
-5 0 5 10 15 20 25 30 35 40 45 25 50 75 100 125 150 175

VDS, Drain-to-Source Voltage (V) Starting T J , Junction Temperature (°C)

Fig. 11 Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. Drain Current

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AUIRFR/U8405
10

Thermal Response ( Z thJC ) °C/W

1
D = 0.50
0.20
0.1 0.10
0.05
0.02
0.01 0.01

SINGLE PULSE
0.001 ( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000

Duty Cycle = Single Pulse

Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Avalanche Current (A)

Tstart =25°C (Single Pulse)

100
0.01

0.05
10 0.10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming  j = 25°C and
Tstart = 150°C.
1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)

Fig 14. Typical Avalanche Current Vs. Pulse width

250 Notes on Repetitive Avalanche Curves , Figures 14, 15:

TOP Single Pulse
(For further info, see AN-1005 at www.infineon.com)
BOTTOM 1.0% Duty Cycle
1. Avalanche failures assumption:
200 ID = 90A
EAR , Avalanche Energy (mJ)

Purely a thermal phenomenon and failure occurs at a temperature far in

excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded.
150 3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
100
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
50
25°C in Figure 13, 14).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
0
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
25 50 75 100 125 150 175
Starting T J , Junction Temperature (°C) PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
Fig 15. Maximum Avalanche Energy Vs. Temperature EAS (AR) = PD (ave)·tav

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AUIRFR/U8405
8.0 4.5

RDS(on), Drain-to -Source On Resistance (m )

ID = 90A

VGS(th) , Gate threshold Voltage (V)

4.0
6.0
3.5

3.0
4.0
T J = 125°C 2.5
ID = 100µA
ID = 250µA
2.0 2.0 ID = 1.0mA
ID = 1.0A
T J = 25°C 1.5

0.0
1.0
4 6 8 10 12 14 16 18 20
-75 -25 25 75 125 175 225
VGS, Gate -to -Source Voltage (V) T J , Temperature ( °C )

Fig 16. On-Resistance vs. Gate Voltage Fig. 17 - Threshold Voltage vs. Temperature

120
IF = 36A
9 110
IF = 36A V R = 34V
100
8 TJ = 25°C
V R = 34V
90
7 TJ = 25°C TJ = 125°C
80
TJ = 125°C
6 QRR (nC) 70
IRRM (A)

5 60

4 50
40
3
30
2
20
1 10
0 200 400 600 800 1000
0
0 200 400 600 800 1000 diF /dt (A/µs)

diF /dt (A/µs)

Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt
100
8 IF = 90A
IF = 90A
7 V R = 34V
V R = 34V 80
TJ = 25°C
6 TJ = 25°C
TJ = 125°C
TJ = 125°C
5 60
QRR (nC)
IRRM (A)

4
40
3

2 20

1
0
0
0 200 400 600 800 1000
0 200 400 600 800 1000
diF /dt (A/µs)
diF /dt (A/µs)

Fig. 20 - Typical Recovery Current vs. dif/dt Fig. 21 - Typical Stored Charge vs. dif/dt

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AUIRFR/U8405
9.0

R DS(on), Drain-to -Source On Resistance ( m)

VGS = 5.5V
VGS = 6.0V
VGS = 7.0V
VGS = 8.0V
VGS = 10V
6.0

3.0

0.0
0 100 200 300 400 500
ID, Drain Current (A)

Fig 22. Typical On-Resistance vs. Drain Current

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AUIRFR/U8405

Fig 23. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
20V I AS
tp 0.01

Fig 24a. Unclamped Inductive Test Circuit Fig 24b. Unclamped Inductive Waveforms

Fig 25a. Switching Time Test Circuit Fig 25b. Switching Time Waveforms

Id
Vds

Vgs

Vgs(th)

Qgs1 Qgs2 Qgd Qgodr

Fig 26a. Gate Charge Test Circuit Fig 26b. Gate Charge Waveform

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AUIRFR/U8405

D-Pak (TO-252AA) Package Outline (Dimensions are shown in millimeters (inches))

D-Pak (TO-252AA) Part Marking Information

Part Number AUFR8405

Date Code
IR Logo YWWA Y= Year


WW= Work Week
XX XX

Lot Code

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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AUIRFR/U8405
I-Pak (TO-251AA) Package Outline (Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

Part Number AUFU8405

Date Code
IR Logo YWWA Y= Year


WW= Work Week
XX XX

Lot Code

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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AUIRFR/U8405

D-Pak (TO-252AA) Tape & Reel Information (Dimensions are shown in millimeters (inches))

TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) FEED DIRECTION 8.1 ( .318 )

FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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AUIRFR/U8405
Qualification Information
Automotive
(per AEC-Q101)
Qualification Level Comments: This part number(s) passed Automotive qualification. Infineon’s
Industrial and Consumer qualification level is granted by extension of the higher
Automotive level.
D-Pak
Moisture Sensitivity Level   MSL1
I-Pak
Class M3 (+/- 400V)†
Machine Model
AEC-Q101-002
Class H1C (+/- 2000V)†
ESD Human Body Model  
AEC-Q101-001
Class C5 (+/- 2000V)†
Charged Device Model
AEC-Q101-005
RoHS Compliant Yes

† Highest passing voltage.

Revision History
Date Comments
 Corrected label on SOA curve Fig 8 on page 4.
10/17/2014
 Updated Package outline on page 9 & 10
 Updated datasheet with corporate template
10/12/2015
 Corrected ordering table on page 1.

Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.

IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third
party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of
the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a
failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.

  12 2015-10-12