Motorola SeminarsandApplicationBooksCMOSDataManualVolume2 SpecialFunctionsOCR

®- MOTOROLA Se,"ic~nductors -
Q quantum
Box 391262
electronics
Br.m'&Y
20.1-8
Selection Guides II
Handling Precautions
Reliability and
Quality Assurance
Publications and Applications

® MOTOROLA
CMOS DATA MANUAL

VOLUME 2
SPECIAL FUNCTIONS
This information has been carefully checked and is believed to be entirely reliable. However, no responsibility
is assumed for inaccuracies. Motorola reserves the right to make changes to any products herein to improve
reliability, function or design. Motorola does not assume any liability arising out of the application or use of
any product or circuit described herein. No license is conveyed under patent rights in any form. When this
document contains information on a new product, specifications herein are subject to change without notice.
© MOTOROLA INC .•
"All Rights Reserved"
First Edition 1983 • 80028
Printed in Switzerland
Introduction
Or how to find the information you need
The European CMOS Data Manuals Volumes 1, 2 and 3 contain all the relevant data
required to design and use Motorola CMOS Functions. The first two volumes replace
the European CMOS Selection Data Book which was published in 1979.
Volume 1 contains data on Standard Logic which is defined as the following functions:
NAND / NOR / AND / OR / Complex Gates
Inverters / Buffers / Level Translators
Schmitt Triggers
Flip Flops / Latches
Shift Registers
Counters
Adders / Comparators
Parity Generators / Checkers
ALU's I Rate Multipliers
Encoders / Decoders
Multiplexers / Demultiplexers / Bilateral Switches
Multivibrators / Oscillators / Timers
Volume 2 contains data on Special Functions which are defined as the following
functions:
PLL Frequency Synthesizers
Display Decoders I Drivers
AID, D/A Converters / Logic Functions
Operational Amplifiers / Comparators
Remote Control Functions
Radio / TV Functions
Miscellaneous Functions
Volume 3 contains data on High Speed CMOS.

Telecommunications functions are listed in the Selection Guide but data is to be found
in the Telecommunications Data Manual.
Microprocessors and peripherals are listed in the Selection Guide, but data is to be
found in the Microprocessors Data Manuals (8 and 16-Bitl.
Memories are also listed in the Selection Guide. This book contains data on the smaller
memories. The data for larger memories is to be found in the Memory Data Manual. See
the selector guides for details.
Ordering Information (page 1-2) - defines the numbering system and suffixes and
gives details of processing options.
Selection Guide by Part Number (page 1-4) - contains a human alphanumeric
listing of all functions with details of suffixes and pins, and where to find detailed
technical data. This section can also be used as a cross reference to find
equivalents for other suppliers' functions.
Selection Guide by Function (page 1-1 2) - lists all devices which are capable of
performing broadly defined functions, and where to find detailed technical data.
PLL Frequency Synthesizer Selector Tables (page 1-15) - give comparative data
for key characteristics of PLL Frequency Synthesizers.
HSCMOS Selector Guide (page 1-1 6) - gives key family characteristics and order-
ing information. Lists devices by function and shows equivalent LSTTL and CMOS
functions.
Gate Arrays (page 1-23) - a brief outline of the MaS Gate Arrays and the design
system.
Technical data for all special functions. Where parts are still at the design and
development stage, then the data consists of either Product Previews or Advance
Information.
The static and latch-up problems associated with MaS are now well understood.
This section lists the precautions to be taken during shipment, assembly and test to
avoid these problems. It is recommended that this section be read thoroughly.
This section describes the key elements of Motorola's reliability and quality
assurance activities, and gives the results of the 1982 tests.
Lists the publications available from Motorola Semiconductors.

On the back cover, there is a list of Motorola Sales Offices and Distributors.
Selection Guides a
Ordering Information
II
MC14001 BAL
~denotes Operating Voltage Range
Operating Temperature Range
Package Material
AL 3 to 18 V, - 55 to + 125°C, Ceramic Package

CL 3 to 18 V, -40 to + 85°C, Ceramic Package
CP 3 to 18 V, -40 to + 85°C, Plastic Package
L Limited Voltage Range, Limited Temperature Range, Ceramic Package
P Limited Voltage Range, Limited Temperature Range, Plastic Package
EFL 3 to 18 V, -55 to + 125°C, Ceramic Package
FL 3 to 18 V, -40 to + 85°C, Ceramic Package
FP 3 to 18 V, -40 to + 85°C, Plastic Package
EVL 3 to 6 V, -55 to + 125°C, Ceramic Package
VL 3 to 6 V, -40 to + 85°C, Ceramic Package
VP 3 to 6 V, -40 to + 85°C, Plastic Package
Z Limited Voltage Range, Limited Temperature Range, Leadless Chip Carrier
Motorola CMOS integrated circuits are manufactured under strict quality control. In-
process screens and tight out-going inspection result in a high order of quality and
reliability.
In addition, Burn-in is an option available on all CMOS packaged products. The
benefits of this option are:
reduced infant mortality (typically 0.2% of the product is screened out);
reduced board and system rework;
reduced equipment downtime;
reduced field failures.
Electrical Electrical
Test Test
Outgoing
quality
control Electrical
sample Test. D.C.
electrical Parameters
test at 25°C
Outgoing quality
control sample
electrical test
VDD 15 V
Temperature 125°C ambient
Time 168 hours
Bias Dynamic for Memories and Analog Circuits, Static for
all others
Ordering Information:
The Burn-in option is selected by adding the suffix D to the part number, for example:
MC14001 BALD
Chips and wafers are available for all CMOS types. For further information, consult your
Motorola Sales Office or authorized Motorola Distributor.
Various options are available, including parts qualified to BS9000, CECC and MIL
STD883B Class B type processed. For further information, consult your Motorola Sales
Office or authorized Motorola Distributor.
Selection Guide by Part Number
Device Function Suffix Pins Page
MC54HCXXX High Speed CMOS Series .............................. J 0

MC68HC04P2 8-Bit Single Chip Microcomputer .................... L,P,Z 28 x
MC68HC04P3 8-Bit CMOS Microcomputer EPROM ............... L,P,Z 28 x
MC68HC05C4 8-Bit Single Chip Microcomputer .................... L,P,Z 40 x
MC68HC09E 8-Bit Microprocessor ................................... L,P,Z 40 x
MC74HCXXX High Speed CMOS Series .............................. J,N 0
MC6172 2400 Baud DPSK Modulator ......................... L,P 24
•
MC6173
MC6220
2400 Baud DPSK Demodulator .....................
4-Bit Microcomputer with PLL Frequency
L,P 24
•
Synthesizer (NMOS Device) .......................... P 28 §
MC6860
MC6862
Low Speed Modem ......................................
Part Number changed to MC61 72 ..................
L,P 24
•
MC14000UB Dual 3-lnput NOR Gate Plus Inverter ............... AL,CL,CP 14
MC14001 B Quad 2-lnput NOR Gate ............................... AL,CL,CP 14
*
MC14001UB Quad 2-lnput NOR Gate ............................... AL,CL,CP 14
*
MC14002B Dual 4-lnput NOR Gate ................................. AL,CL,CP 14
*
MC14002UB Dual 4-lnput NOR Gate ................................. AL,CL,CP 14
*
MC14006B 18-Bit Static Shift Register ........................... AL,CL,CP 14
*
MC14007UB Dual Complimentary Pair Plus Inverter ............. AL,CL,CP 14
*
MC14008B 4-Bit Full Adder ........................................... AL,CL,CP 16
*
*
4009 See MC14049UB - Pin for Pin Equivalent
4010 See MC 14050B - Pin for Pin Equivalent
MC14011B Quad 2-lnput NAND Gate ............................. AL,CL,CP 14
MC14011 UB Quad 2-lnput NAND Gate ............................. AL,CL,CP 14
*
MC14012B Dual 4-lnput NAND Gate .............................. AL,CL,CP 14
*
MC14012UB Dual4-lnput NAND Gate .............................. AL,CL,CP 14
*
MC14013B Dual D Flip-Flop ........................................... AL,CL,CP 14
*
MC14014B 8-Bit Static Shift Register ............................. AL,CL,CP 16
*
MC14015B Dual 4-Bit Static Shift Register ...................... AL,CL,CP 16
*
MC14016B Quad Analog Switch/Multiplexer .................... AL,CL,CP 14
*
MC14017B Decade Counter/Divider ............................... AL,CL,CP 16
*
MC14018B Presettable Divide-By-N Counter .................... AL,CL,CP 16
*
*
4019B See MC 1451 9 B - Normally Pin for Pin
Equivalent
x See the 8-Bit Microprocessors Data Manual.

§ See Data Sheet.
* See the CMOS Data Manual, Volume 1, Standard Logic.
o See the CMOS Data Manual, Volume 3, High Speed CMOS .
• See the Telecommunications Data Manual.
MC14020B 14-Bit Binary Counter .................................. AL,CL,CP 16

MC14021B 8-Bit Static Shift Register ............................. AL,CL,CP 16
*
MC14022B Octal Counter/Divider .................................. AL,CL,CP 16
*
MC14023B Triple 3-lnput NAND Gate ............................. AL,CL,CP 14
*
*
MC14023UB Triple 3-lnput NAND Gate ............................. AL,CL,CP 14 .*
MC14024B 7 -Stage Ripple Counter ................................ AL,CL,CP 14
MC14025B Triple 3-lnput NOR Gate ............................... AL,CL,CP 14
*
MC14025UB Triple 3-lnput NOR Gate ............................... AL,CL,CP 14
*
MC14027B Dual J-K Flip-Flop ........................................ AL,CL,CP 16
*
MC14028B F3CD-to-Decimal/Binary-to-Octal Decoder ........ AL,CL,CP 16
*
MC14029B Binary/Decade Up/Down Counter ................... AL,CL,CP 16
*
*
4030B See MC 14070B - Pin for Pin Equivalent
4031B See MC14557B - Functionally Equivalent
MC14032B Triple Serial Adder (Positive Logic) .................. AL,CL,CP 16
MC14034B 8-Bit Universal Bus Register .......................... AL,CL,CP 24
*
MC14035B 4-Bit Shift Register ...................................... AL,CL,CP 16
*
MC14038B Triple Serial Adder (Negative Logic) ................ AL,CL,CP 16
*
MC14040B 12-Bit Binary Counter .................................. AL,CL,CP 16
*
MC14042B Quad Transparent Latch ............................... AL,CL,CP 16
*
MC14043B Quad NOR R-S Latch .................................... AL,CL,CP 16
*
MC14044B Quad NAND R-S Latch ................................. AL,CL,CP 16
*
MC14046B Phase-Locked Loop ..................................... AL,CL,CP 16
*
2-2
4047B See MC 14528B - Functionally Equivalent
MC14049UB Hex Inverter/Buffer ...................................... AL,CL,CP 16
MC14050B Hex Buffer ................................................. AL,CL,CP 16
*
MC14051B 8-Channel Analog Multiplexer/Demultiplexer .... AL,CL,CP 16
*
MC14052B Dual 4-Channel Analog Multiplexer/
*
Demllttiplexer ............................................. AL,CL,CP 16
MC14053B Triple 2-Channel Analog Multiplexer/
*
Demultiplexer ............................................. AL,CL,CP 16
*
4056B See MC14543B - Normally Pin for Pin
Equivalent
4057B See MC 14581 B - Functionally Equivalent
MC14060B 14-Bit Binary Counter and Oscillator ............... AL,CL,CP 14
*
4061 See MCM 14537 - Functionally Equivalent
4063 See MC14585B - Functionally Equivalent
MC14066B Quad Analog Switch/Multiplexer .................... AL,CL,CP 14
MC14067B 1 6-Channel Analog Multiplexer/Demultiplexer .. AL,CL,CP 24
*
MC14068B 8-lnput NAND Gate ..................................... AL,CL,CP 14
*
MC14069UB Hex Inverter ............................................... AL,CL,CP 14
*
MC14070B Quad Exclusive OR Gate ............................... AL,CL,CP 14
*
MC14071B Quad 2-lnput OR Gate .................................. AL,CL,CP 14
*
MC14072B Dual 4-lnput OR Gate ................................... AL,CL,CP 14
*
MC14073B Triple 3-lnput AND Gate ............................... AL,CL,CP 14
*
MC14075B Triple 3-lnput OR Gate ................................. AL,CL,CP 14
*
*
MC14076B Quad D-Type Register .................................. AL,CL,CP 16

MC14077B Quad Exclusive NOR Gate ............................. AL,CL,CP 14
*
MC14078B 8-lnput NOR Gate ....................................... AL,CL,CP 14
*
MC14081B Quad 2-lnput AND Gate ............................... AL,CL,CP 14
*
MC14082B Dual4-lnput AND Gate ................................ AL,CL,CP 14
*
*
MC14093B Quad 2-lnput NAND Schmitt Trigger ............... AL,CL,CP 14
MC14094B 8-Bit Bus Compatible Shift/Store Latch ........... AL,CL,CP 16
*
MC14097B Dual 8-Channel Analog Multiplexer/
*
.Demultiplexer ............................................. AL,CL,CP 24
*
Equivalent
MC14099B 8-Bit Addressable Latch ............................... AL,CL,CP 16
MC14160B Synchronous Programmable Decade Counter ... AL,CL,CP 16
*
MC14161B Synchronous Programmable 4-Bit Binary
*
Counter ..................................................... AL,CL,CP 16
MC14162B Synchronous Programmable Decade Counter ... AL,CL,CP 16
*
MC14163B Synchronous Programmable 4-Bit Binary
*
Counter ..................................................... AL,CL,CP 16
MC14174B Hex D Flip-Flop ........................................... AL,CL,CP 16
*
MC14175B Quad D Flip-Flop ......................................... AL,CL,CP 16
*
MC14194B 4-Bit Universal Shift Register ......................... AL,CL,CP 16
*
*
MC14400 PCM Monocircuit ........................................ L 16
•
•
MC14402 PCM Monocircuit ........................................ L,
Z
22
28
•
•
•
MC14408
MC14409
Binary-to-Phone Pulse Converter ....................
Binary-to-Phone Pulse Converter ....................
L,P
L,P
16
16
••
MC14410
MC14411
2-of-8 Tone Encoder ....................................
Bit-Rate Frequency Generator. .......................
L,P
L,P
16
24
•
2-7
MC14412 Universal Low Speed Modem ........................ FL,FP,VL, VP 16
•
MC14413 PCM Sampled Data Filter, See Note A ............. L,P,
Z
16
18 •
MC14414 PCM Sampled Data Filter, See Note A ............. L,P,
Z
16
18
•
MC14415 Quad Precision Timer/Driver .......................... EFL,FL,FP 16
EVL, VL, VP *
MC14416
MC14417
PCM Time Slot Assigner
Circuit .....................
Circuit .....................
L,P
L,P
16
18 ••
MC14418
MC14419
2-of-8 Keypad-to-Binary
Circuit .....................
Encoder ...................
L,P
L,P
22
16
•
MC14426 8 x 14-Bit Static Tuning Memory ................... P 16
*
2-10
MC14429 Tuning Memory Control, See Note B ............... P 18 2-13
* See the CMOS Data Manual, Volume 1, Standard Logic.

Note A: Add Suffix 1 or 2. Example MC14413L2.

Note B: Add Suffix B. Example MC14429PB.
MC14430 Input Address Encoder . 2-17
MC14433
MC14442
MC14443
MC14444
3-' /2 Digit A/D Converter
Microprocessor Compatible A/D Converter
6-Channel A/D Converter Subsystem
Microprocessor Compatible A/D Converter
.
.
.
.
2-21
2-33
2-42
2-46
II
MC14447 6-Channel A/D Converter Subsystem . 2-42
4449UB See MC 14049UB, Pin for Pin Equivalent
MC14457 Remote Control Transmitter . P 2-57
MC14458 Remote Control Receiver . P 2-57
MC14466 Low Cost Smoke Detector . P 2-68
MC14467 Low Cost Smoke Detector . P 2-68
MC14468 Interconnect Smoke Detector . P 2-73
MC14469 Addressable Asynchronous Receiver/Transmitter L,P 2-74
MC14490 Hex Contact Bounce Eliminator . L,P 2-82
MC14493 Binary-to- 7 -Segment Latch Decoder/Driver . L,P 2-89
MC14494 Binary-to- 7 -Segment Latch Decoder/Driver . L,P 2-89
MC14495 Binary-to-7 -Segment Hexadecimal Latch/ L,P 2-89
Decoder/Driver, See Note C . L1 ,P1 2-93
MC14497 PCM Remote Control Transmitter . P 2-99
MC14499 4-Digit 7-Segment LED Display Decoder/Driver P 2-104
MC14500B Industrial Control Unit . AL,CL,CP 2-110
MC14501UB Triple Gate . AL,CL,CP
MC14502B Strobed Hex Inverter/Buffer . AL,CL,CP
*
MC14503B Hex 3-State Buffer . AL,CL,CP
*
MC14504B Hex TTL or CMOS to CMOS Level Shifter AL,CL,CP
*
MC14506UB Dual Expandable AOI Gate . AL,CL,CP
*
MC14508B Dual4-Bit Latch . AL,CL,CP
*
MC14510B BCD Up/Down Counter . AL,CL,CP
*
MC14511B BCD-to-7-Segment Latch/Decoder/Driver . AL,CL,CP
*
2-125
MC14512B 8-Channel Data Selector . AL,CL,CP
MC14513B BCD-to-7 -Segment Latch/Decoder/Driver
*
with Ripple Blanking .
4-Bit Transparent Latch/4-to-1 6 Line
Decoder (High) .
4-Bit Transparent Latch/4-to-1 6 Line
Decoder (Low) . AL,CL,CP
MC14516B Binary Up/Down Counter . AL,CL,CP
MC14517B Dual 64-Bit Static Shift Register . AL,CL,CP
MC14518B Dual BCD Up Counter. . AL,CL,CP
MC14519B 4-Bit And/Or Selector . AL,CL,CP
MC14520B Dual Binary Up Counter . AL,CL,CP
MC14521B 24-Stage Frequency Divider . AL,CL,CP
MC14522B Programmable BCD Divide-by-N Counter . AL,CL,CP
MC14526B Programmable Binary Divide-by-N Counter . AL,CL,CP
MC14527B BCD Rate Multiplier . AL,CL,CP
MC14528B Dual Monostable Multivibrator . AL,CL,CP
MC14529B Dual 4-Channel Analog Data Selector . AL,CL,CP
MC14530B Dual 5-lnput Majority Logic Gate .................... AL,CL,CP 16

MC14531B 1 2-Bit Parity Tree ........................................ AL,CL,CP 16
*
MC14532B 8-Bit Priority Encoder ................................... AL,CL,CP 16
*
MC14534B 5-Decade Counter ....................................... AL,CL,CP 24
*
MC14536B Programmable Timer .................................... AL,CL,CP 16
*
MC14538B Dual Precision Monostable Multivibrator .......... AL,CL,CP 16
*
MC14539B Dual 4-Channel Data Selector/Multiplexer. ....... AL,CL,CP 16
*
MC14541B Programmable Oscillator-Timer ...................... AL,CL,CP 14
*
MC14543B BCD-to-7 -Segment Latch/Decoder/Driver ........ AL,CL,CP 16
*
2-153
MC14544B BCD-to-7-Segment Latch/Decoder/Driver
with Ripple Blanking .................................... AL,CL,CP 18 2-1 58
MC14547B High Current BCD-to-7 -Segment
Decoder/Driver ........................................... AL,CL,CP 16 2-164
MC14548B Dual Monostable Multivibrator
(Retriggerable/Resettable) ............................ L,P 16
MC14549B Successive Approximation Register ................ AL,CL,CP 16
*
2-169
MC14551B Quad 2-Channel Analog Multiplexer/
Demultiplexer ............................................. AL,CL,CP 16
MC14553B 3-Digit BCD Counter .................................... AL,CL,CP 16
*
MC14554B 2 x 2-Bit Parallel Binary Multiplier ................... AL,CL,CP 16
*
MC14555B Dual Binary to 1-of-4 Decoder ....................... AL,CL,CP 16
*
MC14556B Dual Binary to 1-of-4 Decoder (Inverting) ......... AL,CL,CP 16
*
MC14557B 1-to-64 Bit Variable Length Shift Register. ....... AL,CL,CP 16
*
MC14558B BCD-to-7-Segment Decoder ......................... AL,CL,CP 16
*
2-183
MC14559B Successive Approximation Register ................ AL,CL,CP 16 2-169
MC14560B NBCD Adder .............................................. AL,CL,CP 16
MC14561 B 9's Complementer ....................................... AL,CL,CP 14
*
MC14562B 128-Bit Static Shift Register ......................... AL,CL,CP 14
*
MC14566B Industrial Time-Base Generator ...................... AL,CL,CP 16
*
MC14568B Phase Comparator and Programmable
*
Counters ................................................... AL,CL,CP 16 2-189
MC14569B Dual Programmable BCD/Binary Counter ......... AL,CL,CP 16
MC14572UB Hex Gate ................................................... AL,CL,CP 16
*
MC14573 Quad Programmable Op Amp ........................ CL,CP 16
*
2-199
MC14574 Quad Programmable Comparator ................... CL,CP 16 2-199
MC14575 Programmable Dual Op Amp/Dual Comparator CL,CP 16 2-199
MC14580B 4 x 4 Multiport Register ................................ AL,CL,CP 24 2-209
MC14581 B 4-Bit Arithmetic Logic Unit ............................ AL,CL,CP 24
MC14582B Look-Ahead Carry Block ............................... AL,CL,CP 16
*
MC14583B Dual Schmitt Trigger .................................... AL,CL,CP 16
*
MC14584B Hex Schmitt Trigger .............................. '....... AL,CL,CP 14
*
MC14585B 4-Bit Magnitude Comparator ......................... AL,CL,CP 16
*
MC14597B 8-Bit Bus Compatible Counter Latch ............... AL,CL,CP 16
*
MC14598B 8-Bit Bus Compatible Addressable Latch ......... AL,CL,CP 18
*
MC14599B 8-Bit Addressable Latch ............................... AL,CL,CP 18
*
*
4734B See MC 1451 3B - Normally Pin for Pin
Equivalent

Equivalent
See MC14585B - Normally Pin for Pin
II
40085B
Equivalent
Equivalent
40101B See MC14531B - Functionally Equivalent
40106B See MC 141 06B - Pin for Pin Equivalent
40108B See MC 14580B - Normally Pin for Pin
Equivalent
40161B See MC 141 61 B - Pin for Pin Equivalent
40162B See MC14162B - Pin for Pin Equivalent
40181B See MC14581 B - Pin for Pin Equivalent
40192B See MC 1451 OB - Functionally Equivalent
40193B See MC 1451 6B - Functionally Equivalent
40194B See MC 14194B - Normally Pin for Pin
Equivalent
Equivalent
MC142100
MC144100
4 x 4 Cross Point Switch ..............................
Duplex Mode 32-Segment LED Driver .............
AL,CL,CP
P
16
24
•
2-214
MC144104 High Performance Remote Control Transmitter P 24 2-225
MC144105 Remote Control Transmitter .......................... P 20 2-226
MC144110 Hex D/A Converter ...... '................................ P 18 2-227
MC144111 Quad D/A Converter .................................... P 14 2-227
MC144115 16-Segment LCD Driver ............................... P 24 2-232
MC144117 4-Digit Duplex Mode LCD Decoder/Driver ........ P 24 2-237
MC144122 Remote Control Receiver .............................. P 16 2-244
MC144124 High Performance Remote Control Receiver ..... P 24 2-245
MC144130 TV Stereo Decoder ...................................... P 28 2-246
MC145000 48-Segment Multiplexed LCD Driver (Master) .. L, P 2 2-247
MC145001 44-Segment Multiplexed LCD Driver (Slave) .... L, P 18 2-247
MC145026 Remote Control Encoder ............................... L,P 16 2-257
MC145027 Remote Control Decoder .............................. L,P 16 2-257
MC145040 Serial A/D Converter .................................... L,P 20 2-268
MC145041 Serial A/D Converter .................................... L,P 20 2-268
MC145100
MC145104
4 x 4 Cross Point Switch ..............................
PLL Frequency Synthesizer ...........................
L,P
P
16
16
•
2-269
MC145106 PLL Frequency Synthesizer ........................... P 18 2-269

2-269
a
MC145109 PLL Frequency Synthesizer ........................... P 16
MC145144 4-Bit Data Bus Input PLL Frequency
Synthesizer ................................................ L,P 16 2-277
Synthesizer ................................................ L,P 18 2-284
Synthesizer ................................................ L,P 20 2-294
MC145151 Parallel Input PLL Frequency Synthesizer ......... L,P 28 2-304
MC145152 Parallel Input PLL Frequency Synthesizer ......... L,P 28 2-312
MC145155 Serial Input PLL Frequency Synthesizer ........... L,P 18 2-320
MC145414 Dual Tuneable Lowpass Sampled Data Filters ... L,P 16 2-348
MC145415 Dual Tuneable Linear Phase Low Pass
MC145420
Sampled Data Filters ....................................
MDPSK Universal Digital-Loop Transceiver
L,P 16
•
MC145422
(4-Wire Master) ..........................................
L 24
•
(2-Wire Master) .......................................... L 22
MC145423 MDPSK Universal Digital-Loop Transceiver
MC145425
(2-Wire Master) ..........................................
MDSPK Universal Digital-Loop Transceiver
L 20
•
MC145426
(4-Wire Slave) ............................................
L 22
•
(2-Wire Slave) ............................................ L 22
•
MC145428
MC145429
Data Set Interface .......................................
Telset Audio Interface ..................................
L,P
L,P
20
18
••
MC145431 Tuneable Lowpass/Bandpass Filter ................. L,P 16
•
MC145432 2600 Hz Tone Signalling Filter ....................... L,P 18
•
MC145433 Tuneable Notch/Bandpass Filter ..................... L,P 16
•
MC145440
MC145441
Low Speed Modem Filter ..............................
Low Speed Modem Filter ..............................
L,P
L,P
18
18
••
MC145445 300 Baud FSK Modem ................................. L,P 22
•
MC145450
MC146805E2
1200 Baud FSK Modem ...............................
8-Bit Microprocessor, Expandable ..................
L,P
L,P,Z
22
40 x
•
MC146805F2 8-Bit Single Chip Microcomputer .................... L,P,Z 28 x
MC146805G2 8-Bit Single Chip Microcomputer .................... L,P,Z 40 x
MC146818 Real-Time Clock/RAM .................................. L,P,Z 24 x
MC146823 Parallel Interface ......................................... L,P,Z 40 x
MC1468705G2 8-Bit Single Chip Microcomputer with EPROM .. L,P 40 x
MCM5101 256 x 4-Bit Static RAM .............................. C,P 22 +
x See the 8-Bit Microprocessors Data Manual.

+ See the Memory Data Manual.
MCM14505 64 x 1-Bit Static RAM .......................... AL,CL,CP 14 2-116

MCM14524 256 x 4-Bit ROM, See Note D.................. AL,CL,CP 16 2-139
MCM65116 2048 x 8-Bit Static RAM .......................... C,P 24 +
MCM65147 4096 x 1-Bit Static RAM .......................... C,P 18 +
MCM65256 32768 x 8-Bit ROM .................................. P 28 +
MCM65516 2048 x 8-Bit Multiplexed Bus ROM ............ L,P 18 +
MCM144102 16 x 16-Bit Static RAM ........................ P 8 2-220
+ See the Memory Data Manual.
Note D: Available only by special order.

Selection Guide by Function
II
Logic Functions
Nand Gates
Nor Gates
.
.
And Gates .
Or Gates .
Complex Gates .
Inverters/Buffers/Level Translators .
Schmitt Triggers .
Flip-Flops/Latches .
Shift Registers .
Counters .
Adders/Comparators .
Parity Generator/Checker .
Alu's/Rate Multipliers .
Encoders/Decoders .
Multiplexers/Demultiplexers/Bilateral Switches .
Multivibrators/Oscillators/Timers .
Microprocessors/Peripherals .
MCM14505 64 x 1-Bit Static RAM . 2-116

MC14580B 4 x 4 Multiport Register . 2-209
MCM14524 256 x 4-Bit Read Only Memory . 2-139
MC14426 8 x 14-Bit Static Tuning Memory . 2-10
PLL Frequency Synthesizer

MC 14046B Phase-Locked Loop . 2-2
MC14568B Phase Comparator and Programmable Counters . 2-189
MC 1451 04 PLL Frequency Synthesizer . 2-269
MC 145106 PLL Frequency Synthesizer . 2-269
(1 IFor details of larger CMOS Memories. see the Memory Data Book.
* See the CMOS Data Manual. Volume 1, Standard Logic.
x See the 8-Bit Microprocessor Data Manual.
MC145143 PLL Frequency Synthesizer . 2-275
MC145144 4-Bit Data Bus Input PLL Frequency Synthesizer . 2-277
MC145145 4-Bit Data Bus Input PLL Frequency Synthesizer . 2-284 1
MC145146 4-Bit Data Bus Input PLL Frequency Synthesizer . 2-294
MC145151 Parallel Input PLL Frequency Synthesizer . 2-304
MC145152 Parallel Input PLL Frequency Synthesizer . 2-312
MC145155 Serial Input PLL Frequency Synthesizer . 2-320
MC6220 4-Bit Microcomputer Unit with PLL Frequency Synthesizer . §
Display Decoders/Drivers
MC 1451 1B BCD-to- 7-Segment Latch/Decoder/Driver . 2-125
MC 1451 3B BCD-to-7-Segment Latch/Decoder/Driver with Ripple Blanking . 2-131
MC 14543B BCD-to- 7-Segment LatchIDecoder/Driver . 2-1 53
MC 14544B BCD-to-7 -Segment Latch/Decoder/Driver with Ripple Blanking . 2-158
MC14547B High Current BCD-to-7-Segment Decoder/Driver . 2-164
MC14558B BCD-to-7-Segment Decoder . 2-183
MC 14493 Binary-to- 7-Segment Latch/Decoder/Driver . 2-89
MC 14494 Binary-to-7 -Segment Latch/Decoder/Driver . 2-89
MC 14495 Binary-to-7 -Segment Hexadecimal Latch/Decoder/Driver . 2-89
MC 14495-1 Binary-to-7 -Segment Hexadecimal Latch/Decoder/Driver . 2-93
MC14499 4-Digit 7-Segment LED Display Decoder Driver . 2-104
MC 144100 3 2-Segment Duplex Mode LED Driver . 2-214
MC144115 16-Segment LCD Driver . 2-232
MC 14411 7 4-Digit Duplex Mode LCD Decoder/Driver . 2-237
MC 145000 48-Segment Multiplexed LCD Driver (Master) . 2-247
MC 14500 1 44-Segment Multiplexed LCD Driver (Slave) . 2-247
A/D, D/A Converters/Logic Functions

MC 14433 3_' /2 Digit A/D Converter . 2-21
MC 14443 6-Channel A/D Converter Subsystem . 2-42
MC 14447 6-Channel A/D Converter Subsystem . 2-42
MC 14442 Microprocessor Compatible A/D Converter . 2-33
MC 14444 Microprocessor Compatible A/D Converter . 2-46
MC145040 Serial A/D Converter . 2-268
MC 145041 Serial A/D Converter . 2-268
MC 14549B Successive Approximation Register . 2-169
MC 145 59B Successive Approximation Register . 2-169
MC144110 Hex D/A Converter . 2-227
MC 144111 Quad D/A Converter . 2-227
Operational Amplifiers/Comparator
MC14573 Quad Programmable Op Amp . 2-199
II
MC 14574 Quad Programmable Comparator . 2-199
MC 14575 Programmable Dual Op Amp/Dual Comparator . 2-199
MC144104 High Performance Remote Control Transmitter . 2-225

MC144105 Remote Control Transmitter . 2-226
MC144122 Remote Control Receiver . 2-244
MC144124 High Performance Remote Control Receiver . 2-245
MC14469 Adressable Asynchronous ReceiverlTransmitter . 2-74
MC145026 Remote Control Encoder . 2-257
MC145027 Remote Control Decoder . 2-257
MC6220 4-Bit Microcomputer Unit with PLL Frequency Synthesizer . §

MC14426 8 x 14-Bit Static Tuning Memory . 2-10
MC14429 Tuning Memory Control . 2-13
MC14430 Input Address Encoder . 2-17
MC144104 High Performance Remote Control Transmitter . 2-225
MC144122 Remote Control Receiver. . 2-244
MC144124 High Performance Remote Control Receiver . 2-245
MC144130 TV Stereo Decoder . 2-246
Miscellaneous
MC14411 Bit Rate Frequency Generator . 2-7
MC14466 Low Cost Smoke Detector . 2-68
MC14467 Low Cost Smoke Detector . 2-68
MC14468 Interconnectable Smoke Detector . 2-73
MC14469 Addressable Asynchronous ReceiverlTransmitter . 2-74
MC14490 Hex Contact Bounce Eliminator . 2-82
MC14500B Industrial Control Unit . 2-110
MC145414 Dual Tuneable Lowpass Filter . 2-348
II
MC145104 MC145106 MC145107 MC145109 MC145112 MC145143
Device Programming Parallel Parallel Parallel Parallel Parallel Parallel
Modulus Single Single Single Single Single Single
Programmable 9+4
N Divider Bits 8 9 8 9 9 Fixed Bits
Ralerence Divider 210 or 211 210 or 211 210 or 211 210 or 211 210 or 211 None
Single·Ended PDout
Yes Yes Yes Yes Yes Yes
(Three Statal
Double·Ended 'V. 'R No No No No No No
Lock Detect Output Yes Yes Yes Yes Yes Yes
Band Switch Outputs No No No No No No
Package (Pins) 16 18 16 16 18 16
Frequancy Tripling
No Yes Yes No No No
Capability
10.24 MHz Oscillator
Yes Yes No No Yes No
Circuit
Extarnal Fraquency
No No Yes Yes No Yes
Relerence Only
Typical Max. F.in at
10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 30 MHz
5 V. 25°C
MC145144 MC145145 MC145146 MC145151 MC145152 MC145155 MC145156 MC145157 MC145158 MC145159'
Device Programming 4-Bit 4-Bit 4-Blt

Data bus Data bus Data bus Parallel Parallel Serial Serial Serial Serial Serial
Modulus Single Single Dual Single Dual Single Dual Single Dual Dual
Number 01 N 512 16,380 1,021 16,380 1,021 16,380 1,021 16,380 1,021 1,021
Divider Values A - - 128 - 64 - 128 - 128 128
Range 01 4- 3- 3- 3- 3- 3- 3- 3- 3- 3-
Divider Values N} 4,092 16,383 1,023 16,383 1,023 16,383 1,023 16,383 1,023 1,023
A} - - 0-
127
- 0-
63
- 0-
127
- 0-
127
0-
127
Range 01 Relerance 3,584- 3- 3- 8- 8- 16- 8- 3- 3- 3-
Dividar Values 3,839 4,095 4,095 8,192 2,048 8,192 2,048 16,383 16,383 16,383
Single·Ended PDout
(three state) Yes Yes Yes Yes No Yes Yes Yes Yes Yes
Double·Ended 'V. 'R No Yes Yes Yes Yes Yes Yes Yes Yes No
Lock Datect Output No Yes Yes Yes Yes Yes Yes Yes Yes Yes
Band Switch Outputs No No No No No Yes Yes No No No
Package Ipins) 16 18 20 28 28 18 20 16 16 20
Typical Max. F.in at
30 MHz 30 MHz 30 MHz 30 MHz 30 MHz 30 MHz 30 MHz 30 MHz 30 MHz 30 MHz
5 V. 25°C
Introducing a new dimension in CMOS'
Motorola's new family of standard-logic High-Speed CMOS integrated circuits provides
the designer with a complete series of functions which approaches the ideal in perfor-
mance.
All of the present CMOS logic family features, including low power dissipation and high
noise immunity, combine with LSTTL speeds, pinouts and drives to offer the
marketplace a new dimension in CMOS standard logic.
• Guaranteed Propagation Delay - 15 ns for 74HCOO
• Wide Operating Range - 2-6 V Recommended
• High Noise Immunity - Typically 45% of Supply Voltage
• Low Quiescent Power Dissipation
• Diode Protection - All Inputs
• High Fanout - 10 LSTTL Loads (4 mA Drive)
• Direct Pin Compatibility with LSTTL Parts (HCXXX or HCTXXX)
and CMOS Parts (HC4XXX)
• Input Logic Compatible with CMOS Parts (HCXXX or HC4XXX)
and/or LSTTL Parts (HCTXXX)
• Proven Reliability and Process
h,mpl,
Mo'oml, Ci,"o" Id,""""
Temperature Range
~
T r
• 74 for Commercial Range (- 40°C to 85°C)
• 54 for Extended Range (-55°C to 125°C)
Package Type
High-Speed CMOS Specification • N for Plastic (74 Series Only)
Identifier
• J for Ceramic
• HC for Buffered High-Speed CMOS
• HCU for Unbuffered High-Speed CMOS' Basic Device Type
• HCT for TTL Input Compatible CMOS' • Not Available On All Devices
• Parts shown are functional equivalent except when preceded by an asterisk (*),
indicating a suggested alternative
• Device numbers preceded by a "*" are new proprietary designs
High-Speed
Device Function
Functional
Equivalent
Functional
Equivalent
CMOS Device
Direct Pin
Compatibility
Number of
Pins
II
Number LSTTL Device MC1XXXXor
MC74/MC54 74/54 CDXXXX
HCOO Quad 2-lnput NAND Gate LSOO 4011 LS 14

HC02 Quad 2-lnput NOR Gate LS02 4001 LS 14
HC03 Quad 2-lnput NAND LS03 *4011 LS 14
with Open Drain Outputs
HC08 Quad 2-lnput AND Gate LS08 4081 LS 14
HC10 Triple 3-lnput NAND Gate LS10 4023 LS 14
HC11 Triple 3-lnput AND Gate LS11 4073 LS 14
HC20 Dual 4-lnput NAND Gate LS20 4012 LS 14
HC27 Triple 3-lnput NOR Gate LS27 4025 LS 14
HC30 8-lnput NAND Gate LS30 4068 LS 14
HC32 Quad 2-lnput OR Gate LS32 4071 LS 14
HC51 2-Wide, 2-lnput/2-Wide, LS51 *4506 LS 14
3-lnput AND-OR-INVERT Gates
*HC58 2-Wide, 2-lnput/2-Wide, *LS51 *4506 14
3-lnput AND-OR Gates
HC86 Quad 2-lnput Exclusive OR Gate LS86 4070 LS 14
HC132 Quad 2-lnput Schmitt-Trigger LS132 4093 LS 14
NAND Gate
HC133 13-lnput NAND Gate LS133 LS 16
HC266 Quad 2-lnput Exclusive NOR Gate LS266 4077 LS/CMOS 14
(Non Open Drain)
HC4002 Dual 4-lnput NOR Gate *LS25 4002 CMOS 14
HC4075 Triple 3-lnput OR Gate 4075 CMOS 14
HC4078 8-lnput NOR Gate 4078 CMOS 14
HC04 Hex Inverter LS04 *4069 LS/CMOS 14

HCU04 Hex Unbuffered Inverter LS04 4069 LS/CMOS 14
HC14 Hex Schmitt-Trigger Inverter LS14 4584 LS/CMOS 14
HC240/ Octal Buffer/Line Driver/Line Receiver, LS240 LS 20
HCT240 3-State, Inverting Output
HCT241 3-State
HCT244 3-State
HC365 Hex 3-State Bus Driver LS365A LS 16
with Common 2-lnput NOR Enable
with Common 2-lnput NOR Enable,
Inverting Output
HC367 Hex 3-State Bus Driver LS367A 4503 LS/CMOS 16
with Separate 2-Bit
and 4-Bit Sections
with Separate 2-Bit
and 4-Bit Sections, Inverting Output
HC540 Octal Buffer/Line Driver/Line Receiver, LS540 LS I 20
3-State Inverting Outputs
HC541 Octal Buffer/Line Driver/Line Receiver, LS541 LS 20
3-State
HC4049 Hex Inverting Buffer 4049 CMOS 16
HC4050 Hex Buffer 4050 CMOS 16
Functional
High-Speed Functional Equivalent
Device Function Equivalent CMOS Device Direct Pin Number of
Number LSTTL Device MC1XXXXor Compatibility Pins
a
SCHMITT TRIGGERS
HC14 Hex Schmitt-Trigger Inverter LS14 4584 LS/CMOS
HC132 Quad 2-lnput Schmitt-Trigger LS132 4093 LS
NAND Gate
BUS TRANSCEIVERS
HC242 Quad Bus Transceiver, 3-State, LS242 LS 14
Inverting Output
HC243 Quad Bus Transceiver, 3-State LS243 LS 14
HC245/ Octal Bus Transceiver, 3-State LS245 LS 20
HCT245
HC640 Octal Bus Transceiver, 3-State LS640 LS 20
HC646 Octal Bus Transceiver and Register, LS646 LS 24
3-State
3-State, Inverting Output
HC85 4-Bit Magnitude Comparator LS85 *4585 LS 16

HC181 4-Bit Arithmetic Logic Unit LS181 4581 LS/CMOS 24
HC182 Carry Lookahead Generator LS182 4582 LS/CMOS 16
HC280 9-Bit Odd/Even Parity LS280 *4531 LS 14
Generator/Checker
HC283 4-Bit Binary Full Adder with Fast Carry LS283 4008 LS 16
HC888 8-Bit Equality Comparator 20
HC4560 NBCD Adder 4560 CMOS 16
HC292 Programmable Frequency Divider/ LS292 LS 16

Digital Timer
HC294 Programmable Frequency Divider/ LS294 LS 16
Digital Timer
HC4046 Phase-Locked Loop *LS297 4046 CMOS 16
HC73 Dual J-K Flip-Flop with Reset LS73A *4027 LS 14

HC74 Dual D-Type Flip-Flop with Set and LS74A 4013 LS 14
Reset, Positive-Edge Triggered
HC75 4-Bit D-Type Latch LS75 *4042 LS 16
HC76 Dual J-K Flip-Flop with Set and Reset LS76A *4027 LS 16
HC107 Dual J-K Flip-Flop with Reset LS107A 4027 LS 14
HC109 Dual J-K Flip-Flop with Set and Reset, LS109A *4027 LS 16
Positive-Edge Triggered
HC112 Dual J-K Flip-Flop with Set and Reset, LS112A *4027 LS 16
Negative-Edge Triggered
HC113 Dual J-K Flip-Flop with Set, LS113 *4027 LS 14
Negative-Edge Triggered
HC174 Hex D-Type Flip-Flop LS174 4174 LS/CMOS 16
with Common Clock and Reset
HC175 Quad D-Type Flip-Flop LS175 4175 LS/CMOS 16
HC259 8-Bit Addressable Latch LS259 *4099 LS 16
HC273 Octal D-Type Flip-Flop LS273 *4175 LS 20
with Common Clock/Reset
HC373/ Octal D-Type Transparent Latch, LS373 LS 20
HCT373 3-State
HC374/ Octal D-Type Flip-Flop, 3-State LS374 LS 20
HCT374
HC533 Octal D-Type Transparent Latch, LS533 LS 20
3-State Inverting Output
Functional
High-Speed Functional Equivalent Direct Pin Number of
Device Function Equivalent CMOS Device
Compatibility Pins
Number LSTTL Device MC1XXXX or
HC534
HC563
Octal D-Type Flip-Flop, 3-State,
Inverting Output
Octal Transparent Latch, 3-State,
Inverting Output
LS534
LS576
LS
LS
LS
20
20
20
II
HC564 LS580
Inverting Output
HC573 Octal Transparent Latch, 3-State LS573 LS 20
HC574 Octal D-Type Flip-Flop, 3-State LS574 LS 20
HC164 8-Bit Serial Input/Parallel Output LS164 *4034 LS 14

Shift Register
HC165 8-Bit Serial or Parallel Input/Serial LS165 *4021 LS 16
Output Shift Register
HC173 4-Bit D-Type Register, 3-State LS173 4076 LS/CMOS 16
HC194 4-Bit Bidirectional Universal LS194A 4194 LS/CMOS 16
Shift Register
HC195 4-Bit Universal Shift Register LS195A *4035 LS 16
HC299 8-Bit Universal Shift/Store Register, LS299 *4094 LS 20
3-State
*HC589 8-Bit Parallel-to-Serial Shift Register *LS597 *4014 16
with Input Latches, 3-State or*4021
HC595 8-Bit Serial-to-Parallel Shift Register, LS595 *4034 LS 16
3-State
HC597 8-Bit Parallel-to-Serial Shift Register LS597 *4014 or LS 16
with Input Latches *4021
HC160 Programmable Decade Counter, LS160A 4160 LS/CMOS 16

Asynchronous Clear
HC161 Programmable 4-Bit Binary Counter, LS161 A 4161 LS/CMOS 16
Asynchronous Clear
HC162 Programmable Decade Counter, LS162A 4162 LS/CMOS 16
Synchronous Clear
HC163 Programmable 4-Bit Binary Counter, LS163A 4163 LS/CMOS 16
Synchronous Clear
HC192 Presettable BCD Decade Up/Down LS192 4510 LS 16
Counter
HC193 Presettable 4-Bit Binary Up/Down LS193 4516 LS 16
Counter
HC390 Dual Decade Counter LS390 *4518 LS 16
HC393 Dual 4-Bit Binary Counter LS393 *4520 LS 14
HC4017 Decade Counter/Divider 4017 CMOS 16
HC4020 14-Stage Binary Ripple Counter 4020 CMOS 16
with Oscillator
HC123 Dual Retriggerable Monostable LS123 *4538 or LS 16

Multivibrator *4528
HC221 Dual Monostable Multivibrator LS221 *4538 or LS 16
*4528
HC423 Dual Monostable Multivibrator LS423 *4538 or LS 16
*4528
HC4538 Dual Precision Retriggerable/Resettable *LS221 4538 CMOS 16
Monostable Multivibrator
I Functional
Device Function Equivalent CMOS Device Compatibility Pins
a HC42
HC137
HC138/
HCT138
BCD to 1-of-1 0 Decoder
1-of-8 Decoder/Demultiplexer
with Latched Inputs, Inverting Output
1-of-8 Decoder/Demultiplexer
LS42
LS137
LS138
*4028
*4028
*4028
LS
LS
LS
16
16
16
HC139 Dual 1-of-4 Decoder LS139 4555 LS/CMOS 16

(Active-Low Outputs)
HC147 10-to-4 Priority Encoder LS147 *4532 LS 16
HC154 4-to-1 6 Decoder LS154 *4514 LS 24
HC237 1-of-8 Decoder/Demultiplexer *LS137 *4028 16
with Latched Inputs
HC4511 BCD-to-7 -Segment *(LS46- 4511 LS/CMOS 16
Latch/Decoder/Driver LS49)
HC4514 4-Bit Latch/4-to-1 6 Line Decoder 4514 CMOS 24
HC4543 BCD-to- 7 Segment *(LS46- 4543 CMOS 16
Latch/Decoder/Driver LA49)
for Liquid-Crystal Displays
HC173 4-Bit D-Type Register, 3-State LS173 4076 LS/CMOS 16

HCT240 3-State, Inverting Output
HCT241 3-State
HC242 Quad 3-State Bus Transceiver, LS242 LS 14
Inverting Output
HC243 Quad 3-State Bus Transceiver LS243 LS 14
HCT244 3-State
HC245/ LS245 LS 20
HCT245 Octal Bus Transceiver, 3-State
HC251 8-lnput Multiplexer, 3-State LS251 *4512 LS 16
HC253 Dual 4-lnput Multiplexer, 3-State LS253 *4539 LS/CMOS 16
HC257 Quad 2-lnput Data Selector/Multiplexer, LS257 *4519 LS 16
3-State
HC299 8-Bit Universal Shift/Store Register, LS299 *4094 LS 20
3-State
with Common 2-lnput NOR Enable
with Common 2-lnput NOR Enable,
Inverting Output
HC367 Hex 3-State Bus Driver with Separate LS367A 4503 LS/CMOS 16
2-Bit and 4-Bit Sections
HC368 Hex 3-State Bus Driver with Separate LS368A LS 16
2-Bit and 4-Bit Sections,
Inverting Output
HC373/ LS373 LS 20
HCT373 Octal Transparent Latch, 3-State
HC374/ LS374 LS 20
HCT374 Octal 0- Type Flip-Flop, 3-State
HC533 Octal D-Type Transparent Latch, LS533 LS 20
: -
Functional
High-Speed Functional Equivalent
Device Equivalent CMOS Device Direct Pin Number of
Function Compatibility Pins
Number LSTTL Device MC1 xxx x or
HC534
HC540
Inverting Output
Octal Buffer/Line Driver/Line Receiver,
3-State Inverting Outputs
LS534
LS540
LS
LS
20
20 II
HC541 Octal Buffer/Line Driver/Line Receiver, LS541 LS 20
3-State
HC563 Octal Transparent Latch, 3-State, LS576 LS 20
Inverting Output
HC564 Octal D-Type Flip-Flop, 3-State, LS580 LS 20
Inverting Output
HC573 Octal Transparent Latch, 3-State LS573 LS 20
HC574 Octal D-Type Flip-Flop, 3-State LS574 LS 20
*HC589 8-Bit Parallel-to-Serial Shift Register *LS597 *4014 or 16
with Input Latches, 3-State 4021
HC595 8-Bit Serial-to-Parallel Shift Register, LS595 *4034 LS 16
3-State
3-State
3-State
HCT138 1-of-8 Decoder/Demultiplexer LS138 *4028 LS 16

HCT240 Octal Buffer/Line Driver/Line Receiver, LS240 LS 20
3-State
3-State
HCT245 Octal Bus Transceiver, 3-State LS245 LS 20
HCT373 Octal D-Type Transparent Latch, LS373 LS 20
3-State
HCT374 Octal D-Type Flip-Flop, 3-State LS374 LS 20
HC151 8-Channel Digital Multiplexer LS 151 *4512 LS 16

HC153 Dual 4-Channel Digital Multiplexer LS 153 4539 LS/CMOS 16
HC157 Quad 2-lnput Data Selector/Multiplexer LS157 *4519 LS 16
HC158 Quad 2-lnput Data Selector/Multiplexer, LS158 LS 16
Inverting Output
HC253 Dual 4-lnput Multiplexer, 3-State LS253 *4539 LS/CMOS 16
HC257 Quad 2-lnput Data Selector/Multiplexer, LS257 *4519 LS 16
3-State
HC298 Quad 2-lnput Multiplexer with Storage LS298 LS 16
HC4016 Quad Analog Switch 4016 CMOS 14
HC4051 8-Channel Analog 4051 CMOS 16
Mu Itiplexer /Dem ultiplexer
Multi plexer /Dem ult iplexer
Multiplexer /Demu Iti plexer
HC4066 Quad Analog Switch 4066 CMOS 14
Functional
Device Function Equivalent CMOS Device Pins
Compatibility
a *HC4316
*HC4351
*HC4352
Quad Analog Switch
with Level Translator
Quad Analog MultiplexerlDemultiplexer
with Latched Select Inputs
Dual 4-Channel Analog
*4016
*4051
*4052
16
18
18
Multiplexer IDem ultiplexer
*HC4353 Triple 2-Channel Analog *4053 18
Multiplexer IDem ultiplexer
Motorola is introducing a range of 31-1 High-Density CMOS Gate Arrays, with gate
counts from 600 to 6000 gates. 4 parts will be introduced in 1983 and 2 more in
1984.
Key features of the range are:
a
• System speed similar to LSTTL
• Low power consumption
• Option of CMOS or LSTTL compatible inputs
• Output drive capability of 10 LSTTL loads
• Simple design procedure
Design of the gate arrays is a very simple procedure, using the Motorola CAD system.
This system has all of the design aids necessary for the designer to simulate his design,
automatically place and route the circuit, complete an accurate timing analysis and
prepare a test program for testing the finished product.
The CAD system is an improved version of the system which has been successfully
used for several years for the design of Motorola ECL and TTL Macrocell Arrays. The
same design system can be used for all three technologies. The designer needs no
knowledge of I.C. design or computer programming to design a Motorola Gate Array.
The designer works in his own office using a simple printing terminal with Modem or
acoustic coupler, and connects to the Motorola computer by dialling the nearest
Motorola Sales Office. From here, connection to the Motorola computer in Phoenix,
Arizona, is over the Motorola worldwide communications network.
Using a comprehensive library of SSI and MSI functions, the designer describes his cir-
cuit as a list of functions and interconnections which then becomes the input to the
CAD system.
Future plans include the addition of analog and memory functions, and using a 21-1
HCMOS process which will increase speed.
For further information on the Motorola range of CMOS, TTL and ECL Arrays, contact
your nearest Motorola Sales Office.
® MOTOROLA
PHASE-LOCKED LOOP
The MC 14046B phase-locked loop contains two phase compara-
tors, a voltage-controlled oscillator (VCOL source follower, and
zener diode. The comparators have two common signal inputs.
PCAin and PCBin- Input PCAin can be used directly coupled to large
voltage signals, or indirectly coupled (with a series capacitor) to
small voltage signals_The self-bias circuit adjusts small voltage signals PHASE-LOCKED
in the linear region of the amplifier. Phasecomparator 1 (an exclu- LOOP
sive OR gate) provides a digital error signal PClout, and maintains
900 phase shift at the center frequency between PCAin and PCBin
signals (both at 50% duty cycle). Phasecomparator 2 (with leading
edge sensing logic) provides digital error signalsPC20ut and PCPout,
and maintains a 00 phase shift between PCAin and PCBin signals
(duty cycle is immaterial). The linear VCO produces an output signal
VCOout whose frequency is determined by the voltage of input
VCOin and the capacitor and resistors connected to pins CIA, CIB.
RI, and R2. The source-follower output SFout with an external re-
sistor is used where the VCOin signal is needed but no loading can be
tolerated. The inhibit input Inh, when high, disables the VCO and
source follower to minimize standby power consumption. The zener
diode can be used to assist in power supply regulation.
Applications include FM and FSK modulation and demodulation,
L SUFFIX P SUFFIX
frequency synthesis and multiplication, frequency discrimination,
CERAMIC PACKAGE PLASTIC PACKAGE
tone decoding, data synchronization and conditioning, voltage-to·
CASE 620 CASE 648
frequency conversion and motor speed control.
• VCO Frequency = 1.4 MHz Typical @VDD = 10 Vdc
• VCO Frequency Drift with Temperature = 0.04%/oC Typical
@VDD= 10 Vdc
• VCO Linearity = 1%Typical
• Quiescent Current = 5.0 nA/package typical @ 5 Vdc
• Low Dynamic Power Dissipation - 70 IJ.WTypical @fO = 10 kHz,
VDD = 5.0 Vdc, R1 = 1.0 MH, R2 =~, RSF = ~
• Buffered Outputs Compatible with MHTL and Low·Power TTL
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 to 18 Vdc
• Pin·for·Pin Replacement for CD40468
• Phase Comparator 1 is an Exclusive Or Gate and is Duty
Cycle Limited
• Phase Comparator 2 switches on Rising Edges and is not
Duty Cycle Limited
This device contains circultrv to protect

the inputs against damage due to high static
voltages or electric fields; ho\lWver. It is
advised that normal precautions t. taken
13 PC20ut
to aVOid application of any voltage higher
, PCPout than maximum rated voltages to this high
Impedance circuit. For proper operatton it
• VCOout
is recommended that Vin and Vout be
11 Rl
constrained to the range VSS .-;;(V In or
12 R2
Voutl .-;;VOO'
6 CIA
7 C's Unused inputs must always be tied to 8n
appropriate logic voltage level (e.g., either
Vss or VOO). Pins 6. 7, 10, 11, 12, and
15 if unused must be left open.
Rating Symbol Value Unit
DC Supply Voltage VOO -0.5 to +18 Vdc
Input Voltage, All Inputs V," -0.510 VOO + 0.5 Vdc
DC Current Drain per Pin I 10 mAde
Operating Temperature Range -- AL DevIce TA -55 to +125 °c
CLlCP Device -40 to +85
Storage Temperature Range Tug -65to·150 °c
VOl> Tlow
. 25°C Th·oh·
Chereeterirtic Symbol Vdc Min Mo. Min Typ Mo. Min M•• Unit
-
II
Output Voltage "0" Level VOL 5.0 0.05 - 0 0.05 - 0.05 Vdc
Vin"VDDorO 10 - 0.05 - 0 0.05 - 0.05
15 - 0.05 - 0 0.05 - 0.05
"'" Level VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vdc
Vin ;OorVDD 10 9.95 - 9.95 10 - 9.95 -
15 14.95 - 14.95 15 - 14.95 -
Input Voltage~ "0" Level VIL Vdc
1VO = 4.5 or 0.5 Vdcl 5.0 - 1.5 - 2.25 1.5 - 1.5
(VO = 9.0 or 1.0 Vdcl 10 - 3.0 - 4.50 3.0 - 3.0
1VO = 13.5 or 1.5 Vdcl 15 - 4.0 - 6.75 4.0 - 4.0
"'" Level VIH
(VO' 0.5 or 4.5 Vdcl 5.0 3.5 - 3.5 2.75 - 3.5 - Vdc
evO' 1.0 or 9.0 Vdcl 10 7.0 - 7.0 5.50 - 7.0 -
(VO = 1.5 or 13.5 Vdcl 15 11.0 - 11.0 8.25 - 11.0 -
Output Drive Current (AL Device' IOH mAdc
IVOH • 2.5 Vdcl Source 5.0 -1.2 - -1.0 -1.7 - -0.7 -
1VOH = 4.6 Vdcl 5.0 -0.25 - -0.2 -0.36 - -0.14 -
(VOH • 9.5 Vdcl 10 -0.62 - -0.5 -0.9 - -0.35 -
(VOH' 13.5 Vdc) 15 -1.8 - -1.5 -3.5 - -1.1 -
(VOL' 0.4 Vdcl Sink IOL 5.0 0.64 - 0.51 0.88 - 0.36 - mAdc
(VOL' 0.5 Vdc) 10 1.6 - 1.3 2.25 - 0.9 -
(VOL' 1.5 Vdc) 15 4.2 - 3.4 8.8 - 2.4 -
Output Drive Current (CLlCP Device I IOH mAdc
1VOH = 2.5 Vdc) Source 5.0 -1.0 - -0.8 -1.7 - -0.6 -
1VOH • 4.6 Vdcl 5.0 -0.2 - -0.16 -0.36 - -0.12 -
(VOH • 9.5 Vdc) 10 -0.5 - -0.4 -0.9 - -0.3 -
(VOH' 13.5 Vdcl 15 -1.4 - -1.2 -3.5 - -1.0 -
1VOL • 0.4 Vdc) Smk IOL 5.0 0.52 - 0.44 0.88 - 0.36 - mAdc
(VOL' 0.5 Vdc) 10 1.3 - 1.1 2.25 - 0.9 -
eVOL • 1.5 Vdcl 15 3.6 - 3.0 8.8 - 2.4 -
Input Current (AL Device) 'in 15 .0.1 .0.00001 .0.1 t'.O ••Adc
Input Current (CLlCP Devicel lin 15 - .0.3 - .0.‫סס‬oo1 .0.3 - '1.0 ••Adc
Input Capacitance Cin - - - - 5.0 7.5 - - pF
(Vin' 01
Quiescent Current (AL Device) 100 5.0 5.0 0.005 5.0 150 J'Adc
tPer Package) 10 - 10 - 0.010 10 - 300
lInh' "I" 000PCA' "1'" 15 - 20 - 0.015 20 - 600
Quiescent Current ICLlCP Device) 100 5.0 - 20 - 0.005 20 - 150 ~Adc
(Per Package) 10 - 40 - 0.010 40 - 300
lInh' "I" ond PCA' "1'" 15 - 80 - 0.015 80 - 600
Total Supply Current t IT 5.0 IT' 11.46 ~A/kHzl f + 100 ",Adc
lInh' "0", 'o' 10 kHz, CL • SO pF, 10 IT = 12.91 ~A/kHz) f + 100
Rl • 1 MO, R2' -, RSF • -,000 15 IT = (4.37 ~A/kHzl f + 100
60" DutY Cycle)
-Tlow'" -55°C for AL DeVice, -40oC for CL/CP Device.
Thigh '" +'250C for AL Device. +850C for Cl/CP Device.
aNoise Immunity specified for worst-case input combination.
Noise Margin for both "'" and "0" level'" 1.0 Vdc min@ VOO '" 5.0 Vdc
2.0 Vdc min@ VOO = 10 Vdc
2.5 Vdc min@ VOO = 15 Vdc
tTo Calculate Totet Curr.nt in G.neral:
IT" 2.2. VOO (VCOin -1.65 + VOO -1.35\3/4 VCO' - 1.65) 3/4
+ 1.6x ( In + 1 x 10-3(CL +9) VOD f+
Rl R2 J R~ .
1 .10-1 V002 Coo." OUlyl:de 01 PCAin) + 10 _0: IT in ~A, CL in pF, VCOin, VOO in Vdc, 1 In KHz, 000
R I, R2, RSF in MO, CL on VCOo;'"
Minimum MilJCimum
VDD AL CLlCP TYPlcill AL CLlCP

Ctwr.ct.istic Symbol Vd. Deyice Deyice AIITy_ Device Device Units
Output RIse Time tTLH ns

tTLH • t3.0 ns/pFI CL + 30 ns 5.0 - 180 350 400
tTLH. 11.5 ns/pFI CL + 15 ns 10 - - 90 150 200
tTLH = (1.1 ns/pFI CL1' 10 ns 15 65 110 160
Output Fall Time tTHL ns
tTHL • 11.5 ns/pFI CL + 25 ns 5.0 -- 100 175 200
tTHL • 10.75 ns/pFI CL + 12.5 ns 10 - - 50 75 100
tTHL '10.55 ns/pFI CL + 9.5 ns I 15 - 37 55 80
Input Resistance - PCA1n Aon 5.0 1.0 1.0 2.0 Mn

10 0.2 0.2 04 - -
15 01 0.1 02 -
-- PCB,n A,n 15 150 15 1500 - Mil
I Minimum Input Sensitivity V,n 5.0 - - 200 300 400 mV pop
AC Coupled - PCAin 10 400 600 800
C series =: 1000 pF. f '" 50 kHz 15 700 1050 1400
DC Coupled _. PCAin, PCB11l 5 to 15 See NOise Immun,ty
Maximum Frequency fmax 5.0 0.50 0.35 0.70 - MHz

IVCo,n' VOO. Cl = 50 pF. 10 1.0 0.7 1.4 -
R1 '" 5 kH. and R2::....,) 15 1.4 1.0 19 -
Temperature Frequency Stability 5.0 - - 012 %ioC
IA2' -I 10 - 0.04 -
15 - - 0.015 -
Linearity (A2 =: ••.• )
""
IVCo,n' 2.50 V • 030 V. Al " 10 k1!J 5.0 -- - 1 - -
(VCO,n' 5.00 V' 2.50 V. Al ~ 400 klll 10 -- I - -
(VCOon = 7.50 V! 5.00 V. Al ;, 1000 kHi 15 .- 1 -
5 to 15 - - 50 -
Output
Input
Duty
Resistance
Cycle
- VCOln Aon 15 150 50 1500 MIl

"
Offset Voltage
_. 5.0 - - 1.65 2.2 2.5 Vdc
(VCOIO minus SFout' RSF > 500 kU) 10 - - 1.65 2.2 2:5
15 - - 1.65 2.2 25
Ltneatlty - °'0
IVCo,n' 2.50 V! 0.30 V, ASF > 50 klll 5.0 - 0.1 -
IVCo,n' 5.00 V! 2.50 V, ASF .> 50 knl 10 .- .- 0.6 -
IVCo;n = 7.50 V! 5.00 V, ASF > 50 klll 15 - - 08 - -
ZENER DIODE
Zener Voltage (I =: 50 ",AI
DynamiC Resistance (lz '" 1 mAl
• The formulae given are for the typical characteristics only.

FIGURE 1 - PHASE COMPARATORS STATE OIAGRAMS
PHASE COMPARATOR 1
PCAin ~ PCBin
CIw,.et_istic Using Pha •• Comperltor 1 Using P•••• Com •••• eto< 2

No signal on input PCAin. vea in PlL system adjusts to center frequency vea in PLL system adjusts to minimum fre-
(fO)· qUIncy ('min).
Phllae Ingle between PCAin.nd PCB in. 90" et center frequency (fOI. opprooching 00 Always ao in lock (positive rising edgesL
end 1800 et end. of lock •• ngo 12fLI.
Locks on harmonics of center frequency. Ves No
Signel input noise rejection. High Low

Lock frequency renge (2!L). The frequency renge of the input signel on which the loop will stay locked if it WIS
initially in lock. 2fl - full vea frequency r.nge· fmax - 1min.
Capture frequency range (2f C). The frequency rlnge of the input signal on which the loop will lock if it was initially
out of lock.
Oepends on low-pess filter characteristics fC -fL

1_ Figure 3). fC <; fL
Center frequency (fO~. The frequency of VCOout. when VCOin - 1/2 VOD
VCO output frequency Ifl.
Note: These equ.tlon. ~re intended

to be e design guide. Since celculeted
fmin
- I
R2(Cl+ 32 pF)
(V CO input - VSS)
compotMlnt Velues may be in error

by • much • e focto< of 4, lebar· I
1m•x • 1min (VCO input· VOO)
otory experimentation mey be re- R1(CI +32pFI +
qui ••• for fixed design•• Pert to pert
frequency wriltion with identical
~ comPQn4tnts is 1- then Who.-: 10K<;Rl <; 1M
>201'. 10K<;R2'"1M
l00pF <;Cl <; .01 I'F
rE"hr~.I-'"
+N
L_c~~~..J
PHASE LOCK EO LOOP - LOW PASS FILTER DESIGN
PDoul~VCO
Al _...L
.Ao-- C
·vo--
I
Fls) = __ 1__
A1CS + 1
Bl PDOut vca
V'
Al
·Ao-- "."VCO
A2 NCIA1 + R2)
·vo--
I
-
DEFINITIONS: N = Total Division Ratio in feec'back loop

Kca = Voo/4n for Phase Comparator 1
Kca = Voo/4n for Phase Comparator 2
"vco = 2. t.fvco
I1Vvco
for a typicar design W N :II ~ lat phase detector input)
10
~ '" 0.707
voo
PCAin
~ Vss
I 0
I I
' VOH
"csin
I:
I I
~
: I VOL
"CPout
--;1U °U'
-
VOH
VOL
H
PC20ut ----J - U-----
l:
-----VOL
VOH
Note: for further information. see: -VOH
(1) F. Gardner, "Phase-Lock Techniques", John Wiley and Son, New York, 1966.
(2) Garth Nash, "Phase-Lock Loop Design Fundamentals", AN-535, Motorola Inc.
@MOTOROLA
The MC14411 bit rate generator is constructed with complementary

MOS enhancement mode devices. It utilizes a frequency divider net-
work to provide a wide range of output frequencies.
•
A crystal controlled oscillator is the clock source for the network. A
two-bit address is provided to select one of four multiple output clock
rates.
Applications include a selectable frequency source for equipment in
L SUFFIX
the data communications market, such as teleprinters, printers, CRT CERAMIC PACKAGE
terminals, and microprocessor systems. CASE 623
• Single 5.0 Vdc (±5%l Power Supply

• Internal Oscillator Crystal Controlled for Stability (1.8432 MHzl
• Sixteen Dillerent Output Clock Rates
• 50% Output Duty Cycle
• Programmable Time Bases for One of Four Multiple Output Rates
•
•
•
•
Bullered Outputs Compatible with low Power TTl
Noise Immunity=45%
Diode Protection on All Inputs
of VDD Typical
External Clock May be Applied to Pin 21

PSUFFIX
PLASTIC
CASE
PACKAGE
709
4!".
.~
24
1 -
.•..~ ~ ::
1 ~ .. -
~~~ -
• Internal Pullup Resistor on Reset Input

PIN ASSIGNMENT
F1 VDD
F3 23 RSA
F5 22 RSB
Rating Symbol Value Unit F7 21 Xta1in

DC Supply Voltage Range VDD 5.25 to -0.5 V FB 20 Xta10ut
Input Voltage, All Inputs Vin VDD+0.5 to V
F10 19 F16
VSS-05
DC Current Drain per Pin I 10 mA F9 lB F15
Operating Temperature Range TA -40 to +85 °C
F11 17 F2
Storage Temperature Range Tstg -8510 +150 °C
F14 16 F4
Reset 15 F6
Not Used 14 F12

1 F1 13 F13
VSS
17 F2
2 F3
VDD= Pin 24
16 F4
Rate SelectA 23 VSS = Pin 12
3 F5
Rate SelectB 22
15 F6
4 F7
DIViders This device contains circuitry to protect the
5 F8 inputs against damage due to high static
7 F9 voltages or electric fields; however. it is ad-
6 F10 vised that normal precautions be taken to
avoid application of any voltage higher than
8 Fll
maximum faled voltages to this high im-
14 F12 pedance circuit. For proper operation it is
13 F13 recommended that Vin and Vout be con·
9 F14 strained to the range VSS:s (Vin or
Voutl:sVDD·
* See Figure 2 for typical 18 F15 Unused inputs must always be tied to an
crystal oscillator circuits. appropriate logic voltage level {e.g.. either
19 F16
VSS or VDDI.
* * When Reset=O, outputs F1 thru F14=0, outputs F15 and F16= 1.
Voo 4Q°C 25°C + 85°C
Characteristic Symbol Unit
Vdc Min Max Min Tvn Max Min Max
Supply Voltage V"" - 4.75 5.25 4.75 5.0 5.25 4.75 525 V
Output Voltage "0" Level 5.0 - 0.05 - 0 0.05 - 0.05 V
Vout
"1" Level 5.0 495 - 4.95 50 - 4.95 - V
Input Voltage
1VO=4.5 or 0.5 VI VIL 5.0 - 1.5 - 2.25 1.5 - 15 V
1VO = 0.5 or 4.5 Vdcl VIH 5.0 3.5 - 35 2.75 - 3.5 - V
Output Drive Current
II
1VOH=2.5 VI Source IOH 5.0 -0.23 - -0.20 -1.7 - -0.16 - mA
1VOL =0.4 VI Sink IOL 5.0 0.23 - 020 0.78 - 0.16 - mA

Input Current
Pins 21, 22, 23 I,n - - ±0.1 - ±O.OOOOl ±0.1 - ± 1.0 ~A
Pin 10 50 - - -1.5 - -7.5 - - ~A
Input Capacitance IV,n = 01 Cin - - - - 5.0 - - - pF
Quiescent Dissipation Po 5.0 - 2.5 - 0.015 2.5 - 15 mW
Power Dissipation·· t
(Dynamic plus Quiescent) Po 5.0 PO=17.5 mW/MHzl f+PO mW
IC, = 15 pFI
Output Rise Time'"· lTLH 5.0 - - - 70 200 - - ns
tr = 13.0 nsl pFI CL + 25 ns
Output Fall Time·· tTHL 50 - - - 70 200 - - ns
tf= 11.5 ns/pFI CL +47 ns
Input Clock Frequency fCL 5.0 - 1.85 - - 1.85 - 1.85 MHz
Clock Pulse Width tWICI - 200 -' 200 - - 200 - ns
Reset Pulse Width tWIRl - 500 - 500 - - 500 - ns
tFor dissipation at different external capacitance (eL) refer to corresponding formula:

PTICL = PO+2.6x 1O-31CL -15 pFI voo2f
where: PT, Po in mW, CL in pF, VOO In Vdc, and f in MHz.
··The formula given is for the typical characteristics only.
Rate Select
Rate
8 A
0 0 Xl
0 1 X8
1 0 X16
1 1 X64
Output Output Rates IHzl

Number X64 X16 X8 Xl
Fl 614.4 k 153.6 k 76.8 k 9600
F2 460.8 k 115.2 k 57.6 k 7200
F3 307.2 k 768 k 38.4k 4800
F4 230.4 k 57.6 k 28.8 k 3800
F5 153.6 k 38.4k 19.2 k 2400
F6 115.2 k 28.8 k 14.4 k 1800
F7 76.8 k 19.2 k 9600 1200
F8 38.4k 9600 4800 600
F9 19.2 k 4800 2400 300
F10 12.8 k 3200 1600 200
F11 9600 2400 1200 150
F12 8613.2 2153.3 1076.6 134.5
F13 7035.5 1758.8 879.4 109.9
F14 4800 1200 600 75
F15 921.6 k 921.6 k 921.6 k 921.6 k
F16· 1.843 M 1.843M 1.843 M 1.843 M
20 ns 20 ns
~VDD
Input 10% VSS
Output 10%~-::~
~ ~ -1 ~THL
-,
..
::;:
....L...
5 pF
-,
.-.....
_T12pF
Crystal Specifications
Crystal Mode Parallel
Fr~Quency 1.8432 MHz ±0.05%@13pF
RS 540 0 max
Co 7.0 pF max
Temperature Range o to 70°C
Test Level 1mW
Test Set TS - 330/TSM or Equivalent
Circuit diagrams utilizing Motorola products are included as a means

of illustrating typical semiconductor applications; consequently.
complete information sufficient for construction purposes is not
necessarily given. The information has been carefully checked and is
believed to be entirely reliable. However, no responsibility is assum-
ed for inaccuracies. Furthermore, such Information does not convey
to the purchaser of the semiconductor devices described any license
under the patent rights of Motorola Inc .. or others.
® MOTOROLA
CMOS
TUNING MEMORY SYSTEM
The MC14426 Memory Circuit provides the storage of the tuning MEMORY CIRCUIT
voltage and band information for 8 TV stations when used in con-
junction with the MC14429 Control Unit.
• 8 static shift registers of 14 bit length

• Expansion of up to 32 channels possible without external logic
• Output available indicating addresschange
• Low voltage (1 volt) technology requires a single cell battery as
back up power source
• Extremely low power consumption
P SUFFIX
PLASTIC PACKAGE
CASE 648
MEMORY
COPY
CLOCK
~~ADDRESS CHIP
INPUTS SELECT
DC Supply Voltage VOO +6 to -0.5 Vde
Input Voltage, All inputs Vin VOO to --{).5 Vde
DC Current drain per pin I 10 mA
Operating Temperature Range TA o to +70 °c

Storage Temperature Range Tstg -65 to +150 °c
EI
Characteristic Symbol Min. Typ. Max. Unit
Operating Supply Voltage VOO 4.0 5.2 6.0 Vde
Standby Supply Voltage' VOO 1.2 1.5 6.0 Vde
Quiescent Current (VOO = 1.5 VI 'DO 0.008 2.0 /lAde

(VOO = 5V) 0.5 15.0
Input Voltage (VOO = 5 V) VIL 0.5 Vde

VIH 4.5
Input Voltage (VOO = 5 V) VIL 1.0 Vde

VIH 4.0
Input Current all Inputs Except Pin 3. (VOO = 5 V) IIN 10 pAde
1
Input Current (VOO = 5V) IIN -1.5 -3.0 -6.0 /lAde
Input Capacitance all Inputs (VIN =OV) CIN 5.0 12.0 pF
Output Current all Outputs (sinking) (VOL = 0.4 V) IOL 0.4 mAde
Three State Output ITL /lA

Leakage Current (sinking) (VOO = 5 V) ±0.001 ±5.0
.
Clock Input Frequency (VOO = 5 VI fmax. 400 700 kHz
fmin. 25 100
I Standby mode is obtained by lowering Supply OK input to VSS during a few read/write cycles. VDD can then be lowered to its standby
value, Pin 1 staying tow.
In Standby mode no read/write operation can be performed.
:z An internal pull-up resistor is present on pin 3.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields:
however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be con-
strained to the range VSS ,,; (Vin or Vout) ~ VOO'
Unused inputs must always be tied to an appropriate logic voltage level (e.g. either VSS or VOO)'
DATA IN/OUT - The input/output control section pro- ADDRESS INPUTS - To select the 8 memory words
vides the interface between the memory and the control only three A. B. C address bits are required. (pins 14,
circuit MC14429 via pins 5 and 4. The output network is 13.12.)
active only when the chip is selected and supply OK (pin
Channel A B C
1) is at 1. The relationship between clock and input/out-
put signals is shown below: 1 0 0 0
2 1 0 0
CLOCK IN 3 0 1 0
4 1 1 0
DATA IN
ASSUMING 5 0 0 1
1010 ... 6 1 0 1
DATA OUT 7 0 1 1
ASSUMING 8 1 1 1
1010 ...
DATA OUT
ASSUMING
0101 ...
CHIP SELECT - To facilitate the parallel connection of
several MC14426 memory circuits. four additional inputs
D. D*. E. E* are provided for chip select.
The truth table of chip select inputs is given below.
Chip Selected Channel 0 0* E E*

It should be noted that the memory copy information
on pin 3 input is inserted into the serial data transfer line 1 1 to 8 0 0 0 0
which goes to the control circuit during period T 2. 2 9 to 16 1 1 0 0
3 17 to 24 0 0 1 1
MEMORY COPY - This input is controlled by connecting 4 24 to 32 1 1 1 1

pin 3 to VSS (ground). which in turn holds down the None - Any other combination
memory output signal during period T2. This function
allows to transfer the content of the 14 bit shift register D* and E* are programming inputs of the chip select
of the control circuit MC 14429 into any memory loca- network and are normally connected to VSS or VDD.
tion as long as this command is present. The logic levels on these inputs specify the levels of the D
Its utilisation is two-fold: and E inputs for chip selection.
The chip is selected if D = D* and E = E*.
To resume search for a TV station starting from the
As shown in the above truth table up to four circuits
last selected station rather than from a random tuning
(32 channels) can be connected in parallel without ex-
voltage.
ternal decoding.
To copy the content of a shift register into a different
location. This permits to change the order of TV
programs according to the user wish.
ADDRESS CHANGE - An additional function (pin 15) is
available to mute the sound section of the TV set during
SUPPLY OK - In case of power failure this input (pin 1) each address change. The 400msec. one-shot on the
is used to deactivate all functions of the chip so that no control circuit (MC14429) provides this feature. This
data is lost. rpovided that VDD is held at 1 volt minimum. one-shot is triggered by the address change signal sup-
(See note 1.) plied by the memory circuit. If the address is changed.
The supply OK signal is enabled in such a way that the AC signal appears on the leading edge of the internal
deactivation during transfer of information is prevented. strobe pulse and lasts one (T1 + T2) cycle.
® MOTOROLA
CMOS
The MC14429PB control circuit will perform the following func-
tions when used in conjunction with the MC14426 Memory and TUNING MEMORY SYSTEM
the UAA 1OOBA/C Linear Processors:
• LC Clock generator
CONTROL CIRCUIT
II
• Underflow protected UPIDOWN Counter providing information
for memory
• Rate multiplier for DIA conversion
• Shift register for memory data access and storage of new data
• 2.3 or 4 TV band counter with automatic or manual switching
• Control section for automatic or manual TV station search
• Automatic volume muting control during each search and pro- PB SUFFIX
gramme change PLASTIC PACKAGE
CASE 707
DC Supply Voltage VoO +6 to -0.5 Vde
Input Voltage, All inputs Vin VoO to -0.5 Vde
DC Current Drain per Pin I 10 mA

Characteristic Symbol Min. Typ. Max. Unit
Power Supply Operating Range VOO 4.95 5.2 6 Vde
Input Current, All Inputs (except pins 5,7) lin - 10 - pAde
Enable Output Current (VoH = VOO -0.4 VI IOH 280 - - "Ade

(VOL = 0.4 VI tOL 280 - -
Band Switching Output Current (VOH = VOO -0.4 VI IOH 280 - - "Ade
(VOL = 0.4 VI tOL 280 - -
Other Output Currents (VOH = VOO -0.4 VI IOH 2BO - - "Ade

(VOL = 0.4 VI IOL 2BO - -
One Shot Output, Search & Mute (see I )

(VOL = 0.41 IOL 280 - - "A
Oscillator (VOH = VOO -0.4 VI loH 160 - - "A

(VOL = 0.4VI IOL 160 - -
Power Dissipation @ 300 kHz Po 7.5 mW
Oscillator Frequency fa 50 350 kHz
Band Pin 14 Pin 13 Ramp Speed! Band Skip Connect
UHF 0 0 7 sec. CABLE Pin 2 to Pin 13

VHF 1 1 0 7 sec.
VHF 3 0 1 7 sec. VHF 3 & CABLE Pin 2 to Pin 14
CABLE 1 1 7 sec.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is
advised that normal precautions be taken to avoid application 01 any voltage higher than maximum rated voltages to this high
impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ~(Vin or Voutl
~VOo·
Unused inputs must always be tied on an appropriate logic voltage level (e.g., either VSS or VOO).
CLOCK OUT - Clock pulses (PIN 1) control the transfer linear processor UAA 1008A_ When at 0 the Search FF,
of data between the MC14429A control chip and the analyse FF and Band skip FF are all reset. The
MC14426 memory chip via pins 4 and 17. For best system UP/DOWN control logic is not inhibited and a 1 on the
performance the oscillator circuit should generate a pulse UP or DOWN inputs still could modify the content of the
train of approximately 300 KHz, however frequency value shift register.
is not critical. However, due to the fact that the memory circuit does
L:::::nJ
The clock out signal timing is shown below.
hn T, • ''''' ••• -m
not send any information when Supply OK is at 0, no
data can be modified.
TIME BASE - This input (pin 6) receives a 1 whenever

2
J ~~~~~~~u~~~~m
coincidence between fly-back and video sync signals has
q I~l I
been detected by the linear processor circuit UAA1008A.
In the search mode the presence of a 1 on pin 6 is checked
by the analyse flip-flop set by the one shot. If time base
f = Oscillator frequency;
information is present before the one shot is timed out
T1 + T2 = Rate Multiplier;
Tt = Shift Cycle. (usually 400 msec. from ramp stop) the analyse FF is
reset, search/mute ends and a stable situation reached.
Should time base be 0 when the one shot times out,
BRM OUTPUT - The binary rate multiplier output is
search wi II resume.
available on pin 10.
If in Memory/Normal mode, the presence of a 1 on pin 6
The binary word cycle is approximately 13 msec for a
will force Enable Out to low, if at 0 Enable Out will go to
clock frequency of 300 KHz (3.3 Ilsec pulse width). The
the tristate condition.
output provides pulses symmetrically spaced to facilitate
the filtering when doing D/A conversion. ENABLE OUT - This output (pin 8) is used to control
In the block diagram of Figure 1. the least significant bit
the AFC OUT gate and UP/DOWN overlap in the linear
is to the right. Bits 13 and 14 represent band information,
processor circuit UAA 1008A.
therefore overflow of the rate multiplier control word
Its truth-table is the following:
automatically increments band information.
SEARCH & MUTE - Search mode is initiated by pre- Search FF Analyse FF Time Base IN Enable OUT
(internal) (internal) (PIN 61 (PIN 81
senting a 0 on pin 7. For trouble free operation the signal
on pin 7 is debounced internally on both edges for 0 0 0 Tristate
13 msec. As soon as search is initiated and the debounce 0 0 1 0
cycle is terminated this pin becomes an output for the 0 t 0 0
mute signal which is available during the whole cycle. The 0 1 t 0
t X X 1
search cycle ends when a valid station is found and the
0 0 X Tristate
one shot (R/C on pin 5) has timed out. The mute signal is
available also at address change and during any other time
the one shot is active. Each time the oneshot is reset the
mute output will momentarily go to high and back to low
for less than 13 mtec. It is therefore recommended to The first line of the truth table indicates that the
introduce a proper time constant on this line to smooth system is in its memory mode and that no TV station is
out the mute function. received.
Mute is also provided when supply OK input (pin 3) is The second line indicates that a valid TV station is
VSS· received and system is in its normal memory mode.
Two ramp modes are present: The third line shows the states during the "oneshot"
1. Search mode, with a rate of change of 8 steps per clock period, e.g. the search function has been interrupted
cycle and a scan time of 7 seconds. temporarily and waits for Time Base signal.
2. Tracking mode, used for manual search or normal The fourth line is as above but Time Base is present.
locked on conditions, with a rate of change of 1 step The fifth line represents Search mode, the search FF is
per clock cycle and a scan time of 56 seconds. set and enable out is forced to 1.
Search mode is terminated by the simultaneous presence The sixth line represents Address Change, enable out
of a 1 on both inputs UP (pin 11) and DOWN (pin 12). goes tristate during the on time of the one shot.
SUPPLY OK - An input (pin 3) is provided to ensure UP & DOWN - These two inputs (pin 11 & 12) have two
that during power failures, flash-overs, low supply volta- modes of operation.
ges, etc ... no memory information can be modified or lost. When the system is in search, only the simultaneous
In operating conditions it should receive a 1 from the presence of an UP and a DOWN signal, both of them at 1,
will interact with the system by stopping the search ramp. BAND CODE - Refer to band selection logic table for
A 1 on only one of the two inputs does not stop search output code. (pin 13 MSB, pin 14 LSB).
nor reduce search speed. Logic has been included to A maximum of four bands are available. Three or two
improve the "Stop process" by making it independent of bands only can be obtained by connecting pin 2 to pin 13
the up and down width when both at 1. or 14 as per band selection logic table.
When the circuit is not in search, a 1 on the UP or DOWN Note that no debounce network is included on pin
inputs results in adding or subtracting a one to or from 2 input. Therefore, if manual band skip is required,
the content of the 14 bit shift register during each rate provision for a bounce-free input signal has to be made.
multiplier cycle. Built-in underflow protection prevents a
band change if the digital word is zero and a DOWN com-
mand is initiated.
II
Cl
3.9nF r 1
C2
560
PF
@MOTOROLA
CMOS
The MC14430 is an integrated circuit designed for program selection

address in TV and radio receivers by means of push button switches.
• 8 program inputs
• Binary coded open drain latched output
• Push button type keyboard allows for electrical isolation in live
chassis applications
• Single or double keying operation possible
• Up to four circuits can be cascaded
• Normally closed or normally open switches can be used.
P SUFFIX
PLASTIC PACKAGE
CASE 648
+voo
~
l-
i)
2
0
0 16
"
I-
15
[\ '"
c
~
z
C
!i
"13
12
z 11
~ 10
9
DC Supply Voltage VOO +10 to -0.5 Vde
Input Voltage. All Inputs Vin VOO to -0.5 Vde

however. it is advised that normal precautions be taken to avoid application of any voltage higher than maximum
strained to the range VSS .;; (Vin or Vout)';; VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g. either VSS or VDD).
Characteristics Symbol Min. Typ. Max. Unit
Operating Supply Voltage VOO 4 5.2 6 Vde
Quiescent Current per Package (Pins 16,1,2, 100 !lAde

3.4,5,6.7 open or grounded) VOO =5V - 0.068 10
Input Voltage "0" Level VIL - 2.25 1.5 Vde

",,' Level VIH 3.5 2.75 -
Input Current VOO 5 V = lin !lAde
Vin 1V = - 2.1 -
Vin = 2 V - 2.6 -
Vin = 5 V - 2.6 6.0
Output Drive Current IOL mAde

(VOL = 0.5 V) VOO =5V 2.5 6.2 -
Output Drive Current IOL mAde

(VOL = 0.5 V) VOO =5V 0.9 2.25 -
Incorrect encoding of the selected program number can

occur whenever the last bounce. on opening a normally
open switch. is 40 to 60 Ilsec. wide. Should the type of
switch used have a characteristic within this timing, the
switch configuration opposite is recommended.
By pulsing the common switch line at a rate lower than
the whole bounce period (15 msec. max.). chances of
misfunction are reduced. 20ms
Pulsing can be provided by a unijunction transistor
H
relaxation oscillator or by a switching transistor driven
by the vertical deflection flyback signal or others. The
VDD'lfLJ
vss
pulse width can vary between few hundred Ilsec. and few O.5~
milliseconds.
B
DO 13
"
L " L
13
" "
lO MC14430
• 10 MC14430
•
16 1 2 3. 5
• 7 16 1 2 3
• 5
• 7
1 i 3 • 5
\I
• 7
• 1 2 3
• 5
• 7
•
9 I;>
SINGLE/DOUBLE KEYING - Single Keying Mode PRIORITY ENCODER - When two or more keys
(SKM) is selected by connecting pin 10 to VDD. Double belonging to the same chip are activated simultaneously,
Keying Mode (DKM) is obtained by connecting pin 10 the key having the lowest number will have priority and
to ground. the corresponding code will be selected.
In SKM, input pins: 16, 1, 2, 3, 4, 5, 6, 7 select In Double Keying Mode, key 1 has priority over keys 2,3
programs 1 to 8 respectively. The corresponding binary and 4, key a has priority over keys b, c and d.
coded output (000 for program 1) will appear on lines
A, B, C. Output D (pin 11) is a chip select output and MUL TI CHIP SYSTEM - As long as one key is
will remain activated (at VSS) as long as the chip is activated the chip select pin 9 of the corresponding chip
selected. Refer to application information. is pulled to ground.
In DKM, keys are divided into two groups: keys 1, 2, 3, That chip is now selected and any other chip connected
4 (pin 16, 1, 2, 3) and keys a, b, c, d, (pin 4, 5, 6, 7) in parallel will be disabled.
which affect output lines A, B, and C, D respectively If two or more keys belonging to different chips are
(see application information). acutated at the same time, the chip corresponding to the
Keying sequence is important since output lines A and B first actuated key will be selected. When releasing the
are reset every time a, b, c, d are actuated. keys, the chip corresponding to the last released key will
For example: program b3 is selected by keying b first, remain selected.
then 3. If key d is then actuated, program d1 is selected.
BINARY CODED OUTPUT - In SKM, binary coded
program number minus one is present on lines A, B, C
(pin 14, 13, 12).
POWER ON RESET - When power is switched on, Output D (pin 11) goes low when the corresponding
channell (or channell a in DKM) will be automatically chip is selected. In DKM the binary code output is
selected. present on lines A, B, C, D.
® MOTOROLA
3% DIGIT AID CONVERTER

The MC14433 is a high performance, low power, 3Y. digit AID
converter combining both linear CMOS and digital CMOS circuits on
a single monolithic IC. The MC14433 is designed to minimize use of
external components. With two external resistors and two external
capacitors, the system forms a dual slope AID converter with
automatic zero correction and automatic polarity.
The MC14433 is ratiometric and may be used over a full-scale
II
range from 1.999 volts to 199.9 millivolts. Systems using the
MCl4433 may operate over a wide range of power supply voltages
for ease of use with batteries, or with standard 5 volt supplies. The
output drive conforms with standard B-Series CMOS specifications
and can drive a low·power Schottky TTL load. L SUFFIX
ERAMICPACKAGE
The high impedance MOS inputs allow applications in current and
CASE 623
resistance meters as well as voltmeters. In addition to DVM/DPM
applications, the MC14433 finds use in digital thermometers, digital
scales, remote AID, AID control systems, and in MPU systems.
• Accuracy: ±0.05% of Reading ±1 Count 24
• Two Voltage Ranges: 1.999 V and 199.9 mV ~
• Up to 25 Conversionsls
• Zin> 1000 M ohm
• Auto-Polarity and Auto-Zero
• Single Positive Voltage Reference
• Standard B·Series CMOS Outputs-Drives One Low Power ,',,, "X ~
Schottky Load PLASTIC PACKAGE 1
• Uses On-Chip System Clock, or External Clock CASE 709
• Low Power Consumption: 8.0 mW typical @ ±5.0 V

• Wide Supply Range: e.g., ±4.5 V to ±8.0 V
• Overrange and Underrange Signals Available
• Operates in Auto Ranging Circuits Suffix Cenot ••
• Operates with LED and LCD Displays
• Low External Component Count T- L C ••.• mic Package
• See also Application Notes AN-769 and AN-770. t: P Pl•• tic P.ck •••
V ref Reference Vol,...
VAG AnalOi Ground
3 VX AnalogInput
Voo· Pin 2.
Vss • Pin 13
VEE - Pin 12
This device contains circuitry to protect
Rati"9 Symbol Value Unit
the inputS' against damage due to high static
DC Supply Voltage Vaa '0 VEE -O.S '0 +18 Vdc voltages or electric fields; however, it is
Voltage, any pin, referenced to Vee V -0.5 to Vdc advised that normal precautions be taken
to avoid application of any voltage higher
Vaa +O.S
than maximum rated voltages to this high
DC Current Drain per Pin I 10 mAdc impedance circuit. For proper operation it
Operating Temperature Range TA -40 to +85 °c is recommended that Vin and Vout be
constrained to the range Vee ~ IV 10 or
You') <;; Vaa·
Param.t.r Symbol Value Unit

DC Supply Voltage - VDD to Analog Ground Vaa +5.0 to +8.0 Vdc.
Vee to Analog Ground VEE -2.8 to -8.0
Clock Frequency fClk 32 to 400 kHz
Zero Offset Correction Capacitor Co 0.1±20% ~F
ELECTRICAL CHARACTERISTICS ICI= 0.1 ~F mylar. AI =

470 kn@lVref =
2.000 V. AI =
27 kll @lVref 200.0 mY. =
Co::: 0.1 ,.,F, RC::: 300 kH; all voltages referenced to Analog Ground, pin 1.1
-40°C 2SoC 8SoC

Voo Vee
Ch.ract.ristic Symbol Vdc Vdc Min Max Min Typ Ma. Min Ma. Unit
linearity-Output Reading (Note 1) - %rdg
IV ref = 2.000 V) S.O -S.O - - -O.OS -O.OS +O.OS - --
-Count +Count
IV ref = 200.0 mV) S.O -S.O - - - ,O.OS - - -
Stability - Output Reading S.O -S.O LSD
IVX =
199.0 mY. Vref = 200.0 mVI
Suffix PS or L5 2
P9 or L9 3
Symmetry - Output Aeading INote 2) 5.0 -5.0 LSD

IVref = 2000 mV)
Suffix P5 or L5 2
P9 or L9 3
Zero-Output Reading - 5.0 -5.0 - - - 0 0 - - LSD

1VX = 0 V. Vref = 2.000 VI
Bias Current - Analog Input - 5.0 -5.0 - - - ,20 ,,00 - - pAdc
Reference Input 5.0 -5.0 - - - '20 -100 - -
Analog Ground 5.0 -5.0 - - - ,20 ,500 - -
Common Mode Rejection - 5.0 -S.O - - - 65 - - - d8
1VX -1.4V. Vref- 2.0OOV.
foe = 32 kHz)
Output Voltage ~ Pins 14 to 23 Vde
IVSS = 0 V) "0" Level VOL 5.0 -5.0 - 0.05 - 0 0.05 - 0.05
"1" Level VOH 5.0 -5.0 4.9S - 4.95 5.0 - 4.95 -
IVSS = -5.0 V) "0" Level VOL 5.0 -5.0 - 4.9S - -5.0 -4.95 - -4.95
"1" Level VOH 5.0 -5.0 4.95 - 4.95 5.0 - 4.95 -
Output Current - Pins 14 to 23 mAde
IVSS = 0 VI
(VOH • 4.6 VI Source IOH 5.0 -5.0 -0.25 - -0.2 -0.36 - -0.14 -
IVOL - 0.4 V) Sink IOL 5.0 -5.0 0.64 - 0.51 0.88 - 0.36 -
(VSS - -5.0 VI
(VOH • 4.5 V I Source IOH 5.0 -5.0 -0.62 - -0.5 -0.9 - -0.35 -
(VOL - -4.5 V) Sink IOL 5.0 -5.0 1.6 - 1.3 2.25 - 0.9 -
Clock Frequency fClk 5.0 -5.0 - - - 66 - - - kHz
lAC - 300 knl
Input Current OU IOU 5.0 -5.0 - '0.3 - ,0‫סס‬oo1 '0.3 - , 1.0 ~Adc
Quiescent Current IQ 5.0 -5.0 - 3.7 - 0.9 2.0 - 1.6 mAde
(VOO to VEE. 'SS • 0) 8.0 -8.0 - 7.4 - 1.8 4.0 - 3.2
DC Supply Rejection 5.0 -5.0 - - - 0.5 - - - mVN
(VOD to VEE. 'SS • O. Vref' 2.0ooVI
Note 1: Accuracy - The accuracy of the meter at full scale is the accuracy of the setting of the reference voltage. Zero is recalculated during
each conversion cycle. The meaningful specification is linearity. In other words, the deviation from correct reading for all inputs
other than positive full scale and zero is defined as the linearity specification.
Note 2: Symmetry - Defined as the difference between a negative and positive reading of the same voltage at or near full scale.
VEJ. -8 V
- :--......
VOO"+8V
-r-- --
I-"'"
~ ~
VEP -~ V
-..::.:~
VOO" +5 V
-NOTE: ROLLOVER ERROR IS THE DIFFERENCE IN

OUTPUT REAOING FOR THE SAME ANALOG
- INPUT SWITCH EO FROM POSITIVE TO NEG·- ~
ATiVE.
~.O
4.0
;; ;;
~ ~
.. -4lJO C
..
i
3.0 -4lJOC z
./ -- ~ I
---....-
~ -2.0
+2~' C
+250 C
~ w
V .....- +850 C
~ 2.0
in // ./" +8SoC -
u
'"::>
~ '1.0
./
./ •.....
ci
1.0
V ~ / ~ V
~ ~ I'
" 1.0 2.0 3.0

Vos, ORAIN·TO·SOURCE VOLTAGE (Vd,)
4.0
IP
-1.0 -2.0 -3.0
VOS, ORAIN ·TO-SOURCEVOLTAGE (Vd')
-4.0
Wi 3.0
li
~ 2.0
!!
~ 1.0
~
::>
~ -1.0
'"9
u
-2.0
u
§ -3.0
CONVERSION RATE _ CLOCK FREQUENCY .1 6"

16.<lOO L •
MULTIPLEX RATE _ CLOCK FREQUENCY

80
ANALOG GROUND (VAG, Pin 1) f:,V + Vx to exceed Voo. The 0.5 V factor in the
Analog ground at this pin is the input reference level above equation for f:,V is for safety margin.
for the unknown input voltage (VXI and reference
voltage (Vref). This pin is a high impedance input. OFFSET CAPACITOR IC01, C02; Pins 7,8)
These pins are used for connecting the offset
REFERENCE VOL TAGE (Vref, Pin 21 correction capacitor. The recommended value is O.IIlF.
UNKNOWN INPUT VOLTAGE (VX, Pin 3)
This AID system performs a ratiometric AID conver· DISPLAY UPDATE INPUT (OU, Pin 9)
sian; that is, the unknown input voltage, VX, is mea· If a positive edge is received on this input prior to the
sured as a ratio of the reference voltage, V ref. The full ramp·down cycle, new data will be strobed into the
scale voltage is equal to that voltage applied to Vref. output latches during that conversion cycle. When this
Therefore, a full scale voltage of 1.999 V requires a pin is wired directly to the EOC output (pin 141. every
reference voltage of 2.000 V while full scale voltage of conversion will be displayed. When this pin is driven
199.9 mV requires a reference voltage of 200 mV. Both from an external source, the voltage should be
Vx and Vref are high impedance inputs. In addition to referenced to VSS.
being a reference input, pin 2 functions as a reset for the
AID converter. When pin 2 is switched to VEE for at CLOCK IClk I,Clk O,Pins 10,11)
least 5 clock cycles, the system is reset to the beginning The MC14433 device contains its own oscillator
of a conversion cycle. system clock. A single resistor connected between pins
10 and 11 sets the clock frequency. If increased stability
EXTERNAL COMPONENTS (RI, RI/C" CI; Pins 4, 5, 6) is desired, these pins will support a crystal or LC circuit.
These pins are for externdl components for the The clock input, pin 10, may also be driven from an
integration used in the dual ramp AID conversion. A external clock source which need have only standard
typical value for the capacitor is 0.1 IlF (mylar) while CMOS output drive. For external clock inputs this pin is
the resistor should be 470 kG for 2.0 V full scale opera· referenced to VEE. A 300 kG resistor results in clock
tion and 27 kG for 200 mV full scale operation. These frequency of about 66 kHz. (See the typical
values are for a 66 kHz clock frequency which will pro- characteristic curves.) For alternate circuits see Figure 7.
duce a conversion time of approximately 250 ms. The
equations governing the calculation for the values for NEGATIVE POWER SUPPLY (VEE, Pin 12)
integrator components are as follows: This is the connection for the most negative power
supply voltage. The typical current is 0.8 mA. Note the
RI ~ Vx(max) x 2- current for the output drive circuit is not returned
CI AV through this pin, but through pin 13.
AV ~ Voo - Vx(max) - 0.5

NEGATIVE POWER SUPPLY FOR OUTPUT
CIRCUITRY (VSS, Pin 13)
T ~ 4000 x _.1-
fClk This is the low voltage level for the output pins of the
where: MC14433 (BCD, Digit Selects, EOC, OR). When this pin
RI is in kG is connected to analog ground, the output voltage is from
Voo is the voltage at pin 24 referenced to VAG analog ground to Voo. When connected to VEE, the
Vx is the voltage at pin 3 referenced to VAG, in V output swing is from VEE to Voo. The allowable operat-
ing range for VSS is between Voo - 3.0 volts and VEE.
fClk is the clock frequency at pin lOin kHz
CI is in IlF, f:,V is in Volts
END OF CONVERSION (EOC, Pin 14)
Example:
The EOC output produces a pulse at the end of each
CI ~ O.IIlF
conversion cycle. This pulse width is equivalent to one
Voo ~ 5.0 volts
half the period of the system clock (pin Ill.
fClk ~ 66 kHz
For Vx(max) ~ 2.0 volts
OVER RANGE lOR, Pin 15)
RI ~ 480 kG (use 470 kG ± 5%)
The OR pin is low when Vx exceeds Vref. Normally
For Vx(max) ~ 200 mV
it is high.
RI ~ 28 kG (use 27 kG ± 5%)
Note that for worst case conditions, the minimum DIGIT SELECT (054,053,052, DS1; Pins 16,17,18,
allowable value for R I is a function of CI min, Voo min, 19)
and fClk max. The worst-ease condition does not allow The digit select output is high when the respective
digit is selected. The most significant digit (I', digiti turns Coded Condition BCD to 7 Segment
on immediately after an EOC pulse followed by the reo ofMSD Q3 Q2 Q1 QO Decodi"9
maining digits, sequencing from MSD to LSD. An inter· +0 1 1 1 0 Blank
digit blanking time of two clock periods is included to -0 1 0 1 0 Blank
ensure that the BCD data has settled. The multiplex rate +0 UR 1 1 1 1 Blank
is equal to the clock frequency divided by BO. Thus, -OUR 1 0 1 1 Blank
+1 0 1 0 0 Hook up
with a system clock rate of 66 kHz, the multiplex rate 4~1}
0~1
-1 0 0 0 0 onlv seg b
would be 0.8 kHz. Relative timing among digital select +10R 0 1 1 1 7~1 and c to
ouptut and EOC signals is shown in the Digit Select -lOR 0 0 1 1 3~1 MSD
Timing Diagram, Figure 8. Notes for Truth Table
Q3 - % digit, low for "''', high for "0"
BCD DATA OUTPUTS (Qo, Q1, Q2, 03, Pins 20, 21, Q2 - Polarity: "'" - positive, "0" '"' negative
22,23) 00 - Out of range condition exists if ao • 1. When used in
conjunction with Q3 the type of out of range condition
Multiplexed BCD outputs contain 3 full digits of
is indicated. Le., 03 =: 0 - OR or Q3 = 1 - UA.
information during DS2, 3, 4, while during DS1, the I',
digit, overrange, underrange and polarity are available. When only segment band c of the decoder are connected
to the % digit of the display. 4, O. 7 and 3 appear 8S 1.
The adjacent truth table shows the formats of the infor·
The overrange indication (03 = 0 and 00 •••1) occurs
mation during DS1. when the count is greater than 1999, e.g.,' 1.999 V for a
reference of 2.000 V. The underrange indication, useful for
POSITIVE POWER SUPPLY (VDD, Pin 241 autoranging circuits, occurs when the count is less than 180.
The most positive supply 'voltage pin. e.g .• 0.180 V for a reference of 2.000 V.
C.ution: If the most significant digit is connected to a display
other than a "1" only; such as a full digit display. segments
other than band c must be disconnected. The BCD to seven
segment decoder must blank on BCD inputs 1010 to 1111.
C2 C
1 1f--i;~
For L - 5 mH and C • 0.01 jJ.F. f iil 32 kHz
eoc~
n~1/2 Clock Cycle
_
I 118 Clock Cycles
~;;'D;.It J-----I _
\MSDI
2 Clock Cycles~ F
-----,
FIGURE 10 - EQUIVALENT CIRCUIT DIAGRAMS OF THE
ANALOG SECTION DURING SEGMENT 4
OF THE TIMING CYCLE
Time
Segment
Number
EI
The MC14433 CMOS integrated circuit, together with and integrator amplifiers, is charged during this period.
a minimum number of external components, forms a Also, the integrator capacitor is shorted. This segment
modified dual ramp AID converter. The device contains requires 4000 clock periods.
the customary CMOS digital logic providing counters, Segment 2 - The integrator output decreases to the
latches, and multiplexing circuitry as well as the CMOS comparator threshold voltage. At this time a number of
analog. circuitry providing operational amplifiers and counts equivalent to the input offset voltage of the com·
comparators required to implement a complete single parator is stored in. the offset latches for later use in the
chip AID. Autozero, high input impedances, and autozero process. The time for this segment is variable,
autopolarity are features of this system. Using CMOS and less than 800 clock periods.
technology, an AID with a wide range of power supply Segment 3 - This segment of the conversion cycle is
voltage and low power consumption is now available the same as Segment 1.
with the MC14433. Segment 4 - Segment 4 is an up·going ramp cycle
During each conversion, the offset voltages of the with the unknow'l input voltage (Vx) as the input to the
internal amplifiers and comparators are compensated for integrator. Figure 10 shows the equivalent configuration
by the system's autozero operation. Also each of the analog section Of the MC14433. The actual
conversion 'ratiometrically' measures the unknown input configuration of the analog section is dependent upon
voltage. In other words, the output reading is the ratio the polarity of the input voltage during the previous
of the unknown voltage to the reference voltage with a conversion cycle.
ratio of 1 equal to the maximum count 1999. The entire Segment 5 - This segment is a down·going ramp
conversion cycle requires slightly more than 16000 clock period with the reference voltage as the input to the
periods and may be divided into six different segments. integrator. Segment 5 of the conversion cycle has a time
The waveforms showing the conversion cycle with a equal to the number of counts stored in the offset
positive input and a negative input are shown in Figure storage latches during Segment 2. As a result, the system
9. The six segments of these waveforms are described zeros automatically.
below. Segment 6 - This is an extension of Segment 5. The
time period for this portion is 4000 clock periods. The
Segment 1 - The offset capacitor (Col. which results of the AID conversion cycle are determined in
compensates for the input offset voltages of the buffer this portion of the conversion cycle.
MC1403
+5V
+5V +5V
Segment Resistors
150n {7)
Vx 3
1
4
2 .• 7
6
10
11
R1'
4
3
5
.•
M
"
5
4
M
; 12
13
5 "U 3
U
~ 14
6
MCl4433 ~ 2 15
O.lJJF* • 13 -5 V 1 16
7 -5V
8 Minus Sign
-5V
0.1JJf 15 200n
* R1 =- 470 kn for 2 V Range MP$·

R1 ,., 27 kO for 200 mV Range A12
*. Mvlar Capacitor (4)
3'h DIGIT VOLTMETER - COMMON ANODE

The display usesan LED display with common anode
DISPLAYS, FLASHING OVERRANGE
digit lines driven with an MC14543B decoder and an
An example of a 3Y. digit voltmeter using the MC1413 LED driver. The MC1413 contains 7 darlington
MC14433 is shown in the circuit diagram of Figure 11. transistor drivers and resistors to drive the segments of
The reference voltage for the system uses an MC1403 the display. The digit drive is provided by four MPS-A 12
2.5 V reference IC. The full scale potentiometer can darlington transistors operating in an emitter follower
calibrate for a full scale of 199.9 mV or 1.999 V. When configuration. The MC14543B, MC14013B and LED
switching from 2 V to 200 mV· operation, RI is also displays are referenced to VEE via pin 13 of the
changed, as shown on the diagram. MC14433. This places the full power supply voltage
When using RC equal to 300 kil, the clock frequency across the display. The current for the display may be
for the system is about 66 kHz. The resulting conversion adjusted by the value of the segment resistors shown as
time is approximately 250 ms. 150 ohms in the above figure.
When the input is overrange, the display flashes on The power supply for the system is shown as a dual
and off. The flashing rate is one-half the conversion rate. ±5 V supply_ However, the MC14433 will operate over a
This is done by dividing the EOC pulse rate by 2 with Y.. wide range of voltages, and balance between the +5 and
MC14013B flip-flop and blanking the display using the -5 V supplies is not required. see the recommended
blanking input of the MC14543B. operating conditions and Figure 1, on pages2 and 3.
f
9
VD0
t for V ref'" 200.0 mV

VX: 199.9 mV full scale
(change 470 kH to AI •• 27 kn
and decimal point position)
-To increase srgment current

capability add two MC75491
ICs between MC145118 and
Aesistor ~etwork. The use of
the MC1413 as digit driver
increases digit current capability
over the MC75492. Peak digit
current for an eight displayed
is 7 times the segment current. 0'
MC1413-
•• VEE cen range between -2.8 end
Digit Drivers
-11 V. AI.o ••• Figure 18for
neptly •• upply generated from a
po.ltive .upply.
3Y. DIGIT VOLTMETER WITH LOW COMPONENT display are the choice of the designer, the values of
COUNT USING COMMON CATHODE DISPLAYS resistorsR, RM, RDP, and R R that govern brightness are
The 3% digit voltmeter of Figure 12 is an example of not given.
the use of the MC14433 in a system with a minimum of During an over range condition the 3% digit display is
components. This circuit uses only 11 components in blanked at the BI pin on the MC14511B. The decimal
addition to the MC14433 to operate the MC14433 and point and minus sign will remain on during a negative
drive the LED displays. overrange condition. In addition, an' alternate overrange
In this circuit the MC14511B provides the segment circuit with separate LED is shown. There are leftover
drive for the 3% digits. The MC75492 or MC1413 sections in either the MC75492 or MC1413.
provides sink for digit current. (The MC75492 or
MC1413 are devices with 6 or 7 darlingtons respectively 3Y. DIGIT VOLTMETER WITH LCD DISPLAY
with common emitters.) The worst case digit current is 7 A circuit for a 3% digit voltmeter with a liquid crystal
times the segment current at ~ duty cycle. The peak display is shown in Figure 13. Three MC14543B LCD
segment current is limited by the value of R. The current latch/decoder/display drivers are used to demultiplex,
for the display flows from VDD (+5 VI to ground and decode the three digits, and drive the LCD. The half
does not flow through the VEE (negative) supply. The digit and polarity are demultiplexed with the MC14013B
minus sign is controlled by one section of the MC75492 dual 0 flip·flop.
or MC1413 and is turned off by shunting the current Since the LCD is best driven by an ac signal across the
through RM to ground, bypassing the minus sign LED. LCD, the low-frequency square wave drive for the LCD
The minus sign is derived from the 02 output. The is dedved from the MC14024B binary counter which
decimal point brightness is controlled by resistor RDP. divides the digit select output from the A/D. This low
Since the brightness and the type and size of LED frequency square wave is connected to the backplane of
the LCD and to the individual segments through the
combination of the output circuitry of the MC14543B
and the exclusive 0 R gates at the outputs of the
MC14013B. Alternatively the square wave can be
derived from a 50/60 Hz input signal when available.
The minus sign and the decimal point to the right of
the half digit are connected to the inverted low
frequency square wave signal. Unused decimal points are
tied directly to the low frequency square wave.
The system shown operates from two power suppl ies
(plus and minus). Alternatively one supply can be used
when VSS is connected to VEE. In this case a level must
be set for analog ground, VAG, which must be at least
2.8 V above VEE. This circuit may be implemented
with a resistor' network, resistor/forward-biased diode
network or resistor-zener diode network. For example, a
9 V supply can be used with 3 V between VAG and
VEE, leaving 6 V for VDD to VAG. This system leavesa
comfortable margin for battery degeneration (end of
life). Two versions of this circuit for single supply
operation is.shown in Figure 14.
For panel meter operation from a single 5 V supply, a
negative supply can be generated as shown in Figure 18.
MPS"'"
PlulS,9'"
c IIO!!
0.11(100'
~
'"
.EU1B
@dP
OK"""'o,n"" o.c"m,.,.o,nl,n
ls.gmef'lI D,q)I••••
1 s.tmenl D'WlilY
mO ••pl ••••
ISO II
AII:r Input NAND MCl401l1
•••11. InlNl NAND MC140118
All It, •••" •• , MC1400lHl
AlIT'_''''Of\G.le1 MC140MI
314 DIGIT AUTORANGING MUl T1METER PARAllEL BCD DATA OUTPUT CIRCUIT
An autoranging multimeter including ac and dc The output of the MC14433 may be demultiplexed
voltage ranges from 200 mV to 200 V, ac and dc current to produce parallel BCD data as shown in Figure 16.
from 2 mA to 2 A fullscale and resistance ranges from 2 Two levels of latches are required for a complete
kG to 2 MG full scale is shown in Figure 15. In this demultiplexing of the data since the outputs of the
multi meter only two input jacks are required for all MC14042B latches change sequentially with the DS1 to
ranges and functions, eliminating the need for changing DS4 strobe pulses. To key output validity to one leading
leads on the instrument when changing ranges or edge, i.e., that of the EOC signal of the MC14433,
functions. Although only four ranges are provided for information is transferred to the second set of latches
each function, the technique used may be expanded to (MC14175B latches). A single set of latches can be used
more ranges if desired. Range switching uses mechanical when reading of output is restricted to within 12,000
relays. However, the relays may be replaced with solid clock pulses after EOC. This requires synchronous
state analog switches. system operation with respect to the BCD data bus.
The MC14433 provides the overrange and underrange In this system the output ground level is VSS. In
control signals for the automatic ranging circuits. For most cases. a two supply system with VSS connected to
additional information, see Motorola Application Note VAG is recommended. This allows connecting analog
AN-769, "Autoranging Digital Multimeter Using the ground and digital ground together without destroying a
MC14433 CMOS AID Converter." power supply. This circuit works well with that of
Figure 12.
+5
-5
IRa
R •• t.rt
RIW
Voo IRQ" A
OS4 PB7
Co DS3 PB6
AG MC OS2 PB5
14433 OSl PB4
Vx 03 PB3
Clk 0 02 PB2
II
01 PBl
Clk I 00 PBe
VSS OU eoc
Xl C
B
XO ~ A
Vee > 1NH
Add'os.
Bu.
}
8 CHANNEL DATA ACQUISITION NETWORK lines CB 1 and CB2 are used for data flow control and
Figure 17 shows an 8 channel data acquisition are connected to DU and EOC of the MC14433.
network using the MC14433 and an M6800 A more detailed explanation of this system including
microprocessor system. The interface between the the actual software required for the M6800
microprocessor data bu's and the AID system is done microprocessor may be found -in Motorola Application
with an MC6820 PIA. One hal¥ of the PIA is used with Note AN· no, "Data Acquisition Networks With NMOS
the BCD and digit select outputs of the MC14433, while and CMOS."
the ~cond half of the PIA selects the channel to be
measured via the MCI4051B analog multiplexer. Control
VOO· 5 V NEGATIVE SUPPLY GENERATED FROM POSITIVE

SUPPLY
Vss - 0
When only +5 V is available, a negative supply voltage
can be generated with the circuit of Figure 18 using one
MC14049B. Two inverters from CMOS hex inverter are
used as an oscillator ("" 3 kHz) with the remaining
inverters used as buffers for higher current output. The
square wave output from the oscillator is level·translated
to a negative going signal. This signal is rectified and
filtered. A VDD voltage' of +5 V for the hex buffer will
result in a -4.3 V no load output voltage while the out·
put with a 2 mA load is "" 3.4 V.
+
50IlFFfN4001
-Vout to Vee
lN4001 50IlF
~ +1
@MOTOROLA
CMOS LSI
(LOW-POWER SILICON GATE
COMPLEMENTARY MOS)
MICROPROCESSOR-COMPATIBLE
The MC14442 ADC is a 28-pin bus-compatible B-bit AID converter
with additional digital input capability. The device operates from a ANALOG- TO-DIGITAL CONVERTER
single 5 V supply and provides direct interface to the MPU data bus
used with all Motorola M6800 family parts. It performs an 8-bit conver-
sion in 32 machine cycles and allows up to 11 analog inputs. In addition,
the part can accept up to 6 digital inputs. These inputs are designed to
be either analog or digital inputs. All necessary logic for software con-
II
figuration, channel selection, conversion control and bus interface is in-
cluded.
• Direct Interface to M6800 Family MPUs

• Dynamic Successive Approximation AI D
• 32"s Conversion at fE= 1.0 MHz
• Ratiometric Conversion
• Completely Programmable
• Completely Software Compatible with the MC14444 ADC
• 5 Dedicated Analog Inputs ORDERING INFORMATION
• 6 Inputs Usable for Either Analog or Digital Signals
MC14XXXt~ Suffix Denotes
• Completely TTL Compatible Inputs at Full Speed with Supply
Voltage of 5 V ± 10% Ceramic Package
Plastic Package
BLOCK DIAGRAM AND PIN ASSIGNMENT
VAG Vref
11 11 ANO
AN2-AN5
PO-P5 VAG 1 28 vrel
Vss 27 Voo
07 26 AND
D6 25 AN2
Po-P5
DO 2. AN3
4 D4 6 23 AN'
6
SC 03 7 22 ANS
02 8 21 PO(AN10l
Analog
Data
Register
01
DO
•
10
20 PllAN111
P2lANBl
(Read Only) R/W 11 "18 P3lAN91
Ao-3 4 12 17
Digital P4(AN61
Dat8 Rsl 13 16 P5(AN71
a Register CS IS Reset
00-07 !Read Only) "
R/W a a
cs Bus a
Control
RS1 Logic
Reset
Supply Voltage VDD -0.5 to + 6.5 Vdc
Input Voltage Vin -0.5 to VDD +0.5 Vdc
Input Current, Per Pin lin ±1O mA
Input Current, Per Package lin ±20 mA
Operating Temperature Range (Ambient) TA -40 to +85 °C
Storage Temperature Range Tstg -65 to + 150 °C
This device contains circuitry to protect the inputs against damage due to high static voltages or electric
fields: however, it is advised that normal precautions be taken to avoid application of any voltage higher
than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that
Vin and Vout be constrained to the range VSS ,,:;(Vin or Vout) ,,:;VDD'
Unused inputs must always be tied to an appropriate logic voltage level (e.g. either VSS or VDD)'
DC ELECTRICAL CHARACTERISTICS IVDD= 5.0 V ± 10%, VSS=O V, TA = TL to TH unless otherwise noted)

I Charactaristic I Symbol I Conditions I Min I Max I Unit
Bus Control Inputs (R/W, Enabla, ReSet, RS1, CSI
Input High Voltage
Input Low Voltage
Input Leakage Current Vin = 0 to 5.5 Vdc
Data Bus (00-07)
Input High Voltage VIH 2.0 - Vdc
Input Low Voltage VIL - 0.8 Vdc
Three-State 10ff State) Input Leakage Current ITSI VDD ~ 5.5 Vdc, - ±10 ~Adc
VSSSVinSVDD
Ouput High Voltage VOH 10H- -1.6 mA 2.4 - V
Output Low Voltage VOL IOL-l.6mA - 0.4 V

Input Low Voltage VIL - 0.8 Vdc
Input Leakage Current lin VDD - 5.5 Vdc, - ± 1.0 ~Adc
VSSsVinsVDD
Current ReqUirements
I Supply Current
ANALOG CHARACTERISTICS
Characteristic
Analog Multiplexer
Leakage current between all deselected analog inputs and any selected
analog input with all analog input voltages between VSS and VOO
AID Converter {VSS~O V, VAG=O V, 4.5 VSVrefSVODS5.5 V, TA~ -40° to +85°CI
Resolution Number of bits resolved by the AID 8 - Bits
Nonlinearity Maximum deviation from the best straight line through the AID transfer - ± Y2 LS8
characteristic
Zero Error Difference between the output of an ideal and an actual AID for zero - ±Y. LSB
input voltage
Full-Scale Error Difference between the output of an ideal and an actual AID for full-scale - ±Y. LS8
input voltage
Total Unadjusted Error Maximum sum of Nonlinearity, Zero Error, and Full-Scale Error - ±% LSB
Quantization Error Uncertainty due to converter resolution - ±Y. LS8
Absolute Accuracy Difference between the actual input voltage and the full-scale weighted - ± 1.0 LSB
equivalent of the binary output code, all error sources included
Conversion Time Total time to perform a single analog-to-digital conversion - 32 E cycles
Sample Acquisition Time Time required to sample the analog input - 12 E cycles
ee ·jaure
Characteristic Signal Symbol Min Max Unit
Enable Clock Cycle Time (lIfE) E tcyclE) 943 - ns
Enable Clock Pulse Width, High E PWHIEI 440 - ns
Enable Clock Pulse Width, Low E PWLlEI 410 - ns
Clock Rise Time E tdEI - 25 ns
Clock Fall Time E tflEI - 30 ns
Address Setup Time AS1, A/W, CS tAS 145 - ns
Data Delay I Aeadl 00-07 tDDA - 335 ns
Data Setup IWritel 00-07 185 - ns
B
tDSW
Address Hold Time AS1, A/W, CS tAH 10 - ns
Input Data Hold Time 00-07 tOHW 10 - ns
Output Data Hold Time 00-07 tOHA 10 - ns
tyciEI
A/W,
CS,
AS1
Pin No. Pin Name Function Type
Bidirectional Data Bus (DO-D7) - The bidirectional data
1 VAG AID Converter Analog Ground Input
lines 00-07 comprise the bus over which data is transferr~d
2 VSS Digital Ground Input in parallel to and from the MPU. The data bus output drivers
3 07 Data Bus Bit 7 IMSBI Input/Output are three-state devices that remain in the high-impedence
state except during an MPU read of an ADC data register
4 06 Data Bus Bit 6 Input/Output
5 05 Data Bus Bit 5 Input/Output Enable Clock (E) - The enable clock provides two func-
tions for the MCl4442. First, it serves to synchronize data
6 D4 Data Bus Bit 4 Input/Output
transfers into and out of the ADC. The timing of all other ex-
7 03 Data Bus Bit 3 Input/Output ternal signals is referenced to the leading or trailing edge of
the enable clock. Secondly, the enable clock is used internal-
II
ly to derive the necessary SAR A/D conversion clocks.
9 01 Data Bus Bit 1 Input/Output Because this conversion is a dynamic process, enable clock
10 DO Data Bus Bit a ILSBI Input/Output must be a continuous signal into the ADC during an AID
conversion.
11 A/W Aead/Write Input
12 E EnableClock 10/>21 Input ReadlWrite (R/W) - The R/W signal is provided to the
MCl4442 to control the direction of data transfers to and
13 ASl Register Select Input
from the MPU. A low state on this line is required to transfer
14 CS Chip Select Input data from the M PU to the ADC control register. A high state
is required on A/IN to transfer data out of either of the ADC
15 Reset Reset Input
data registers.
16 P51AN71 Digital Port or Analog Channel7 Input
Reset (Reset) - The reset line supplies the means of
17 P41AN61 Digital Port or Analog Channel 6 Input
externally forcing the MCl4442 into a known state. When a
18 P31AN91 Digital Port or Analog Channel9 Input low is applied to the Reset pin, the start conversion bit of
19 P21AN81 Digital Port or Analog Channel8 Input the control register is cleared. Analog channel 0 is
automatically selected by the analog multiplexer. The AID
20 PlIANlll Digital Port or Analog Channel 11 Input status bit is also cleared. Any AID results present in the
21 POIAN101 Digital Port or Analog Channel 10 Input Analog Data register are not affected by a reset. Reset forces
the data bus output drivers to the high-impedance state. The
22 AN5 Analog Channel5 Input
internal byte pointer (discussed in the following pages) is set
23 AN4 Analog Channel4 Input to point to the most significant byte of any subsequently
selected internal register. In order to attain an internally
stable reset state, the Reset pin must be low for at least one
25 AN2 Analog Channel 2 Input complete enable clock cycle.
26 ANa Analog Channela Input
Chip Select (CS) - Chip select is an active low input used
27 VDD Supply Voltage Input by the MPU system to enable the ADC for data transfers. No
28 Vref AID Converter Positive Reference Input data may be passed to or from the ADC through the data bus
Voltage pins unless CS is in a low state. A selection of MPU address
lines and the M68(X) VMA signal or its equivalent should be
utilized to provide chip select to the MCl4442.
MCl4442 ANALOG INPUTS AND DIGITAL INPUTS

(Refer to the ADC Block Diagram)
Dedicated Analog Channels (ANO, AN2-AN5) - These Shared Analog Channels (AN6-ANll) - These input pins
input pins serve as dedicated analog channels subject to A/D are also connected to the analog multiplexer and may be
conversions. These channels are fed directly into the internal used as analog channels for AID conversion. However,
12-to-1 analog multiplexer which feeds a single analog these pins may also serve as digital input pins as described
voltage to the AID converter. next.
Shared Digital Inputs (PO-PS) - PO-P5 comprise a 6-bit may be degraded if VAG is wired to VSS at the ADC
digital input port whose bits may also serve as analog chan- package unless V SS has been sufficiently filtered to remove
nels. The state of these inputs may be read at any time from switching noise. Ideally VAG should be single-point ground-
the ADC digital data register. The function of these pins is ed to the system analog ground supply.
not programmed, but instead is simply assigned by the
system designer on a pin-by-pin basis.
CAUTION: Digital values read from the PO-P5 bit The MCl4442 ADC has three 16-bit internal registers. Each
locations do not guarantee the presence of true dig- register is divided into two 8-bit bytes: a most significant
ital input levels on these pins. PO-P5 pass through a (MSI byte (bits 8-15) and a least significant (LSI byte (bits
TTL-compatible input buffer and into the digital data 0-7!. Each of these bytes may not be addressed externally,
register. These buffers are designed with enough but instead are normally addressed by a single 16-bit instruc-
hysteresis to prevent internal oscillations if an analog tion such as the M6800 LOX instruction. An internal byte
II
voltage between 0.8 and 2 V is present on one or pointer selects the appropriate register byte during the two E
more of these six pins. cycles of a normal 16-bit access. In keeping with the M6800
X register format, the pointer points first to the MS byte of
any selected register. After the E cycle in which the MS byte
is accessed, the pointer will switch to the LS byte and remain
Positive Supply Voltage (VDD) - VDD is used internally there for as long as chip select is low. The pointer moves
to supply power to all digital logic and to the chopper back to the MS byte on the falling edge of E after the first
stabilized comparator. 8ecause the output buffers con- complete E cycle in which the ADC is not selected. I See
nected to this supply must drive capacitive loads, ac noise on Figure 2a for more detail.l The MS byte of any register may
this supply line is unavoidable internally. Analog circuits us- also be accessed by a simple 8-bit instruction as shown in
ing this supply within the MCl4442 were designed with high Figure 2b. However, the LS byte of all registers may be
VDD supply rejection; however, it is recommended that a accessed only by 16-bit instructions as described above. By
filtering capacitance be used externally between VDD and connecting the ADC register select IRSlI to the MPU
VSS to filter noise caused by transient current spikes. address line A 1, the three rellisters may be accessed sequen-
tially by 16-bit operations.
Ground Supply Voltage (VSS) - VSS should be tied to
system digital ground or the negative terminal of the VDD CAUTION: RSl should not be connected to
power source. Again, the output buffers cause internal noise address line AO and the addressing of the ADC
on this supply, so analog circuits were designed with high should be such that RSl does not change states
VSS rejection. during a 16-bit access.
Positive AI D Reference Voltage IV ref) - This is the

voltage used internally to provide references to the analog
comparator and the digital-to-analog converter used by the Addressing Signals
SAR AID. The analog-to-digital conversion result will be ReSet CS R/W RSl ADC Response
ratiometric to Vref- VAG (full scale!. Hence Vref should be a
0 X X X Reset
very noise-free supply. Ideally Vref should be single-point
connected to the voltage supply driving the system's 1 0 0 0 No Response
transducers. V ref may be connected to VDD, but degrada-
1 0 0 1 MPU Write to Control Register
tion of absolute AID accuracy may result due to switching
noise on VDD. 1 0 1 0 MPU Read from Analog Data
Register
AID Ground Reference Voltage (VAG) - This supply is 1 0 1 1 MPU Read from Digital Data
the ground reference for the internal DAC and several Register
reference voltages supplied to the comparator. It should also
1 1 X X Chip Deselected(No Response)
be noise-free to guarantee AID accuracy. Absolute accuracy
Internal
Byte Pointer
Reset 10 MS Byte
MCl4442 CONTROL REGISTER
(Write Only)
15 o
X AO
IMSBI ILSBI
Analog Multiplexer Address (AG-A3) - These four will begin immediately after the completion of the control
address bits are decoded by the analog multiplexer and used register write.
to select the appropriate analog channel as shown below.
Unused Bits (X) - Bits 4-7 and 9-15 of the ADC Control
Register are not used internally.
HexadecimalAddress (A3~ MSBI Select
o ANO
1 Vre!
2-5 AN2-AN5
6-B AN6-AN11
C-F Undefined NOTE: A 16-bit control register write is required to change
the analog multiplexer address. However, B-bit writes to the
MCl4442 can be used to initiate an AID conversion if the
analog MUX is already selecting the desired channel. This is
Start AID Conversion (SC) - When the SC bit is set to a useful when repeated conversions on a particular analog
logical 1, an AID conversion on the specified analog channel channel are necessary.
MCl4442 ANALOG DATA REGISTER

(Read Only)
15 o
EOC RO
IMSBI ILSBI
AID Result (RG-Rl) - The LS byte of the analog data bit is cleared by either an B-bit or a 16-bit MPU write to the
register contains the result of the AI D conversion. R7 is the ADC control register. The r.emainder of the bits in the MS
MSB. and the converter follows the standard convention of byte of the analog data register are always set to a logical 0
assigning a code of $FF to a full-scale analog voltage. There to simplify MPU interrogation of the ADC status. For exam-
are no special overflow or underflow indications. ple. a single M6800 TST instruction can be used to determine
the status of the AI D conversion.
AID Status (EOC) - The AID status bit is set whenever a
conversion is successfully completed by the ADC. The status
MCl4442 DIGITAL DATA REGISTER

(Read Only)
Shared Digital Port (PO-P5) - The voltage present on

these pins is interpreted as a digital signal and the corres-
ponding states are read from these bits.
Analog Multiplexer Address (AG-A3) - The number of the WARNING: A digital value will be given for each pin even
analog channel presently addressed is given by these bits. if some or all of the pins are being used as analog inputs.
ANALOG SUBSYSTEM
(See Block Diagraml
2 enable clock cycles for the write into the control register
even if only one byte is written. In this case, the second E
The analog subsystem of the MCl4442 is composed of a cycle does not affect any internal registers. During the next
12-channel analog multiplexer, an B-bit capacitive DAC 12\1, enable cycles following a write command, the analog
(digital-to-analog converterl, a chopper-stabilized com- multiplexer channel is selected and the analog input voltage
parator, a successive approximation register, and the is stored on the sample and hold DAC. It is recommended
necessary control logic to generate a successive approxima- that an input source impedance of 10 KIl or less be used to
tion routine. allow complete charging of the capacitive DAC.
The analog multiplexer selects one of twelve channels and During cycle 13 the AID is disconnected from the
directs it to the input of the capacitive DAC. A fully- multiplexer output and the successive approximation AID
capacitive DAC is utilized because of the excellent matching routine begins. Since the analog input voltage is being held
characteristics of thin-oxide capacitors in the silicon-gate on an internal capacitor for the entire conversion period, it is
CMOS process. The DAC actually serves several functions. required that the enable clock run continuously until the AID
During the sample phase, the analog input voltage is applied conversion is completed. The new 8-bit result is latched into
to the DAC which acts as a sample-and-hold circuit. During the analog data register on the rising edge of cycle 32. At this
the conversion phase, the capacitor array serves as a digital- point the end of conversion bit I EOC) is set in the analog
to-analog converter. The comparator is the heart of the data register MS byte. ISee Figure 3, AID Timing
ADC; it compares the unknown analog input to the output of Sequence. I
the DAC, which is driven by a conventional successive-
approximation register. The chopper-stabilized comparator
was designed for low offset voltage characteristics as well as
VDD and VSS power supply rejection. NOTE: The digital data register or the analog data register
may be read even if an AID conversion is in progress. If the
analog data register is read during an AID conversion, valid
results from the previous conversion are obtained. However,
An AID conversion is initiated by writing a logical 1 into the EOC bit will be clear 1I0gic Ol if an AID conversion is in
the SC bit of the ADC control register. The MC14442 allows progress.
MPU Write
To ADC
Control
Register SampleAnalog Input
M ~lInput Should Be Stablel_I""."-------SAR AID Conversion _I

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RS1
Analog Data New

Register IRO-R7 Data
and EOCI Valid,
EOC-1
Latch!
Decoderl
Driver
II'-'II
I I I 11 I
® MOTOROLA
MC14443
MC14447
ANALOG TO DIGITAL CONVERTER

LINEAR SUBSYSTEM
The MC14443 and the MC14447 devices are 6 channel, single

slope, 8-10 bit analog to digital converter linear subsystems for MICROPROCESSOR BASED
,..
microprocessor based data and control, systems. Contained in both
devices are a one of 8 decoder, an 8 channel analog multiplexer,
a buffer amplifier, a precision voltage to current converter, a ramp
start circuit, and a comparator. The output driver of the MC14443
-
comparator is an open·drain N-ehannel capable of sinking up to
5 mA of current. The output of the MC14447 comparator has a
. , I
--
standard B·SeriesP·channel,N·channel pair.
16 1 ; 16 1
A processor system (such as the MC6800, MC141000 or
MC3870) provides the addressing,timing, counting, and arithmetic
L SUFFIX P SUFFIX
operations required for implementing a full analog to digital CERAMIC PACKAGE PLASTIC PACKAGE
converter system. A system made up of a processor and the linear CASE 620 CASE 648
subsystem has features such as automatic zeroing and variable scaling

(weighting) of six separateanalog channels.
• Quiescent Current 0.8 mA Typical at Vaa = 5 V Suffix Denotes
• Single Supply Operation +4.5 to +18 Volts T- L C"amic Package
• MPU Compatible
t: P PlastIc Package
• Typical Resolution - 8 Bits

• Typical Conversion Cycle as Fast as 300 J.lS
• Ratio Metric Conversion Minimizes Error
'5
Ch'
'3
Ch2
Ch3
Ch4
Ch5
Ch6
Voo = Pin 14
VSS'" Pin 5
the inputs against damage due to high
Rating Symbol Value Unit static voltages or electric fields; however.
DC Supply Voltage VOO -05to +18 Vdc it is advised that normal precautions be
taken to avoid application of any voltage
Input Voltage. All Inputs Von -0.5 to VOO + 0.5 Vdc
htgher thiln maximum rated voltages to
OC Current Oraln per Pm I 10 mAde this htgh impedance circuit. For proper
Operating Temperature Range TA °c operation it is recommended that V in and
-40 to +85 Vout be constrained to the range VSS "
(V in or Vout)'" Voo.
Storage Temperature Range T stg -65 '0 +150 °c
Voo Tlow 25°C Thi h

Characteristic Symbol Vdc Min Max Min Typ Max Min Max Unit
Output Voltage-Comparator "0" Level VOL 5.0 - 0.05 - 0.01 0.05 - 0.05 Vdc
Vin@Pin4=OV 10 - 0.05 - 0.01 0.05 - 0.05
15 - 0.05 - 0.01 0.05 - 0.05
Vin@Pin4 1.0V
z "1" Level .VOH 5.0 4.95 - 4.95 4.99 - 4.95 - Vdc
(RL • 10 k. MC14447 only) 10 9.95 - 9.95 9.99 - 9.95 -
15 14.95 - 14.95 14.99 - 14.95 -
Input Voltage·Address. Ramp St~Ht "0 Level" VIL Vdc
(VO "4 ..5 or 0.5 Vdcl 5.0 - 1.5 - 2.25 1.5 - 1.5
(VO • 9.0 or 1.0 Vdc) 10 - 3.0 - 4.50 3.0 - 3.0
(VO" 13.5 or 1.5 Vdc) 15 - 4.0 - 6.75 4.0 - 4.0
"1" Level VIH Vdc
(VO = 0.5 or 4.5 Vdcl 5.0 3.5 - 3.5 2.75 - 3.5 -
(VO • 1.0 or 9.0 Vdcl 10 7.0 - 7.0 5.50 - 7.0 -
(VO = 1.5 or 13.5 Vdc) 15 11.0 - 11.0 8.25 - 11.0 -
Output Drive Current-Comparator IOH mAdc
Vin @ Pin 4 = 1.0 V (MC14447 only)
(VOH • 2.5 Vdc) 5.0 -2.5 - -2.1 -4.2 - -1.7 -
(VOH • 4.6 Vdcl 5.0 -0.52 - -0.44 -0.88 - -0.36 -
(VOH = 9.5 Vdcl 10 -1.3 - -1.1 -2.25 - -0.9 -
(VOH • 13.5 Vdc) 15 -3.6 - -3.0 -8.8 - -2.4 -
Vin @ Pin 4 ""0 V 'OL mAdc
(VOL' 0.4 Vdc) 5.0 0.52 - 0.44 0.88 - 0.36 -
(VOL' 0.5 Vdcl 10 1.3 - 1.1 2.25 - 0.9 -
(VOL = 1.5 Vdc) 15 3.6 - 3.0 8.8 - 2.4 -
Input Current-Address, Ramp Start lin 15 - !0.3 - - !0.3 - '1.0 ,lJ.Adc
Input Current-Analog Inputs lin 15 - - - !0.1 ! 10 - - nAdc
Input Capacitance-Address, Ramp Start Cin 15 - - - 5.0 7.5 - - pF
Vin:: 0 V
Quiescent Current 100 5 - - - 0.8 - - - mAde
10 - - - 1.5 - - -
15 - - - 1.'7 - - -
Crosstalk Between Any Two Input Channels VCr - - - - 0 4.0 - - mVdc
Reference Current Range IR - - - 10 - 50 - - ,lJ.Adc
Channel Input Voltage Range VCM 5 - - 0 - 2.5 - - Vdc
10 - - 0 - 7.0 - -
15 - - 0 - 12 - -
Buffer Amplifier Output Offset V80 5 - - - 0.285 - - - Vdc
10 - - - 0.400 - - -
15 - - - 0.420 - - -
Comparator Threshold VTC 5 - - 0 0.195 V80 - - Vdc
10 - - 0 0.275 V80 - -
15 - - 0 0.290 VAn - -
Reference Voltage Range VR 5 - - 2.0 - 3.0 - - Vdc
10 - - 2.0 - 8.0 - -
15 - - 2.0 - 13.0 - -
Conversion Linearity LC - - - - 0.15 0.5 - - '" Full
Vin - VOO - 3 V for C > 100 pF Scale
VOO
Ch.racteristic Sumbol Min Typ M.x Unit
Vd.
Output Rise Time-Comparator IMC144470nlyl tTLH 5.0 - 120 240 ns
10 - 75 150
15 - 65 130
Output Fall Time-Comperltor tTHL 5.0 - 250 500 ns
10 - 350 700
15 - 650 1300
Propagation Delay Time-Comparator MCl4443 tPLH 5.0 - 550 1100 ns
(RL' 10 k to VOOI 10 - 500 1000
15 - 550 1100
tPHL 5.0 - 350 700 n.
II -
10 300 600
15 - 300 600
MC14447 tpLH 5.0 - 600 1200 ns
10 - 475 950
15 - 500 1000
tPHL 5.0 - 450 980 ns
10 - 540 1080
15 - 750 1500
Multiplexer Propagation Delay tM 5.0 - 180 360 ns
10 - 125 250
15 - 110 220
Ramp Start Delav Time 'TS 5.0 - 40 80 ns
10 - 25 50
15 - 20 40
Acquisition Time· tA 5.0 - 30 60 ~s
C =1000pF 10 - 15 30
RREF =
100 kQ 15 - 14 28
ADDRESS INPUTS SELECT (AO, A1, A2, Pins 1, 2, 16) The input voltage source to be presented to the measuremenl
system according to the Truth Table shown in Figure 2.
RAMP START (Ramp Start, Pin 3) When the Ramp Start is low, the ramp capacitor is charged to a voltage associated with
the selected input channel. When the Ramp Start is brought high,the connection to the input channel is broken and the
capacitor begins to ramp toward VSS.
RAMP CAPACITOR (Ramp Cap, Pin 4) The ramp capacitor is used to generate a time period when discharged from a selected
voltage via a precise reference current.
REFERENCE CURRENT (Ref Current, Pin 6) To discharge the ramp capacitor, the reference current is fixed via a resistor
(RRef) to a positive supply from pin 6. Typical current is equal to (VOO - VRefl/RRef.
COMPARATOR OUTPUT (Comp Out, Pin 7) This output is low when the capacitor has reached the discharged voltage and
is high otberwise.
INPUT CHANNELS (Pins 9, 10,11, 12, 13, 15) Input channels 1 through,6 are used to monitor up to six separate unknown
voltages. Selection is via the address inputs.
(VSOlcount'" to
(Vx 't VSOlcount" tx
(VA + Veo)count = tA
(V A )count •• tA·- to
(VX1count = tx - to
(Vxlcou~= tx - to
(VA)c'ount tA - ~O
tx - to
(VX1C'" (VAIC ---
tA - 10
A2 Al AO Input Selected
0 0 0 VSS Channe~ 0 (ground I
0 0 1 ChI Channell
0 1 0 Ch2 Channel 2
0 1 1 Ch3 Channel 3
1 0 0 Ch4 Channel 4
1 0 1 Ch5 Channel 5
1 1 0 Ch6 Channel 6
1 1 1 VRel Channel 7 (External Reference)
Address Lines ~
from the
I
1 16
Microprocessor
2 15
Aamp start 3 M •...
14
I Channel 1
from the - Aamp C:~pacitor
, 4 ""
""
:! :! 13 Channel 2
M icroprocesso
Rl
Rr.f I
1\
5 uu 12 Channel 3
} ".".0"
Analog
Comparator
f 6
:i:i 11 Channel 4
Voltage
Inputs
Output to 7 10 ChannelS
M icroproces$o , 8 Channel 6
9
R2
Step No. A2 Al AO Ramp Start Comment

1. 1 1 1 0 Channel 7 Selected (Reference Voltage)
2. 1 1 1 1 Record time until Pin 7 goes low
3. 0 0 0 0 Channel 0 Selected (Ground)
5. 0 0 1 0 Channell Selected
Calculate tCh7 - tChO = tChi Step 2-Step 4
Calculate tChl - tChO - tChl' Step 6-Step 4
Calculale Vunknown - VCh7hChl'ltCh7')
7, 0 I I 0 I Channel 2 Selected
8. 0 I I 1 I Record time until Pin 7 goes low
Calculate tCh2 - tChO - tChi
Calculale Vunknown' VCh7 I'chil'chil
etc.
® MOTOROLA
CMOS LSI
(lOW-POWER SILICON GATE
COMPLEMENTARY MOS)
MICROPROCESSOR-COMPATIBLE
The MC14444 ADC is a 4O-pin bus-compatible 8-bit A/D converter ANALOG- TO-DIGITAL CONVERTER
with additional digital 110 capability. The device operates from a single
5 V supply and provides direct interface to the MPU data bus used with
all Motorola M6800 family parts. It performs an 8-bit conversion in 32
machine cycles at 1 MHz and allows for up to 15 analog inputs. In addi-
tion, the part has a 3-bit digital I/O port and can accept up to 9 digital
inputs. Six of these inputs are designed to be either analog or digital
,
. . . . .
,
P SUFFIX
inputs. All necessary logic for software configuration, channel selec- 40. PLASTIC PACKAGE
tion, conversion control, bus interface and maskable interrupt capability
~ 1 CASE 711
is included.
• Direct Interface to M6800 Family MPUs
• Dynamic Successive Approximation A/D "
• 32 /'s Conversion at fE ~ 1.0 MHz

40 , l SUFFIX
• Ratiometric Conversion ~1 CERAMIC PACKAGE
• Completely Programmable CASE 734
• Polled or Interrupt Driven Operation
• 3 Dedicated Digital Inputs
• 3-Bit Digital I/O Port
• 9 Dedicated Analog Inputs MC14XXX1=~ Sulfix Denotes
• 6 Inputs Usable for Either Analog or Digital Signals Ceramic Package
• Completely TTL Compatible Inputs at Full Speed with Supply Plastic Package
Voltage of 5 V ± 10%
BLOCK DIAGRAM
vAG
Analog
Data
Register
(Rea<! Onlvl
Bus
Control
Log;,;
Supply Voltage VDD -05 to +6.5 Vdc
Input Voltage Vin - 0.5 to VDD + 0.5 Vdc
± 10 mA at any pin, not to

Input Current I,n mA
exceed ± 20 mA per package
Operating Temperature Range IAmbientl TA -40 to +85 ·C
Storage Temperature Range T 5tg -65 to + 150 ·C
Vin and Vout be constrained to the range VSS ~ (Vin or Vout) ~ VOO'
Input HIgh Voltage VIH 20 - Vdc
Input Low Voltage VIL - 08 Vdc
Input Leakage Current I,n V,n=O to 5 5 Vdc - ± 1 pAdc
Interrupt Output (iRa)

Output Low Voltage ILoad= 16 mAdc
Output Leakage Current lOft State) VOH=VDD=5 5 Vdc
Data Bus (DO-D71
Three-State IOff Statel Input Leakage Current ITS I VDD= 55 Vdc. - ±1O pAdc
VSS",V,n",VDD
Input High Voltage VIH 20 - Vdc
Input Leakage Current DI3-DI5. PO-P5 I,n VDD=55 Vdc. - ±10 pAdc
VSS"'V,n",VDD
Output High VOltage DIDO-DI02 VOH IOH = -0 19 mAde VDD -04 - Vdc
Output low Voltage DIDO-DI02 VOL IOL = 0 975 mAde - 04 Vdc
Three-State (Off State) Input Leakage Current DIDO·DI02 ITSI VDD= 55 Vde - ±1O pAde
VSS",Vout"'VDD
Supply Current IDD VDD = 5.5 Vdc. IE = 1 MHz - 10 mAde
Converter Input Current IADC Analog Input current at - ±500 nA

'E = 1 MHz wIth multiplexer
Inputs between VSS and VOO
On Resistance Resistance between each analog input and multiplexer output - 5 kO
Leakage Current Leakage current between all deselected analog Inputs and any selected - ±400 nAdc
analog Input with all analog Input VOltages between VSS and VDO
Resolution Number of bIts resolved by the AI D 8 - Bits
Nonlinearity Maximum deviation from the best straight hne through the AID transfer - ±lh LS8
characteristic
Zero Error Difference between the output of an Ideal and an actual AID for zero - ±}\ LSB
input voltage
Full-Scale Error Difference between the output of an Ideal and an actual AID for full-scale - ±}\ LSB
Input voltage
Total Unadjusted Error Maximum sum of Nonlinearity. Zero Error. and Full-Scale Error - ±}\ LSB
Quantization Error Uncertainty due to converter resolution - ± Y2 LSB
Absolute Accuracy Difference between the actual input voltage and the full-scale weighted - ± 1.0 LSB
equivalent of the binary output code. all error sources included
Conversion Time Total time to perform a single analog-to-digital conversion - 32 E cycles
Sample AcquIsition TIme Time required to sample the analog input - 12 E cycles
(See Figure 11
Characteristic Signal Symbol Min Max Unit
Enable Clock Cycle Time (l/fEI E tcyeE 943 - ns
Enable Clock Pulse Width, High E PWEH 440 - ns
Enable Clock Pulse Width, Low E PWEL 410 - ns
Clock Rise Time E tEr - 25 ns
Clock Fall Time E tEl - 30 ns
Address Setup Tiffle RS1. R/W, CS tAS 145 - ns
Data Delay !READI DQ.D7 tDDR - 335 ns
Data Setup (WRITEI DQ.D7 tDSW 185 - ns
Address Hold Time RS1, R/W, CS tAH 10 - ns
Input Data Hold Time 00-07 tDHW 10 - ns
Output Data Hold Time DQ.D7 tDHR 10 - ns

Pin No. Pin Name Function Type
Bidirectional Data Bus (DO-D7) _. The bidirectional data
1 VAG AID Converter Analog Ground Input
lines DO-D7 comprise the bus over which data is transferred
2 VSS Digital Ground Input in parallel to and from the MPU. The data bus output drivers
are three-state devices that remain In the high-impedence
3 0100 Digital Port Input/Output
state except during an MPU read of an ADC data register.
4 0101 Digital Port Input/Output
5 0102 Digital Port Input/Output Enable Clock IE) - The enable clock provides two func-
tIons for the MCl4444. First, 1\ serves to synchronize data
6 013 Digital Port Input transfers into and out of the ADC. The timing of all other ex-
7 014 Digital Port Input ternal signals is referenced to the leading or trailing edge of
the enable clock. Secondly, the enable clock is used Internal-
8 015 Digital Port Input
II
ly to derive the necessary SAR A/D converSion clocks.
9 07 Data 8us BIt 7 IMSBI Input/Output Because this conversion IS a dynamIC process, enable clock
must be a c~ntinuous signal into the ADC during an A/D
conversion.
12 D4 Data Bus Bit 4 Input/Output Read/Write (R/W) The R/Vii signal IS provided to the
MCl4444 to control the directIon of data transfers to and
from the MPU. A low state on this line is required to transfer
14 02 Data Bus Bit 2 Input/Output data from the MPU to the ADC control register. A high state
ISrequired on R/Vii to transfer data out of eIther of the ADC
data regIsters.
16 DO Data Bus Bit 0 ILSBI Input/Output
Read/Wllte Reset (RESET) - The reset line supplies the means of

17 R/W Input
externally forcing the MCl4444 into a known state. When a
18 E EnableClock 1.p21 Input low is applied to the RESET pIn, the start converSIon, inter-
19 RSl Register Select Input rupt enable and I/O port data direction bits of the control
register are cleared. Analog channel 0 is automatically
20 CS Chip Select Input
selected by the analog multiplexer. The A/D status bit is also
21 Reset Reset Input cleared. Any A/D resul1s present In the Analog Data register
are not affected by a reset. Reset forces the data bus and I/O
22 P51AN151 Digital Port or Analog Channel 15 Input
port output drivers to the high-impedance state. The internal
23 P41AN141 DIgital Port or Analog Channel 14 Input byte pointer Idiscussed in the following pagesl is set to point
24 P31AN13J Digital Port or Analog Channel 13 Input
to the most sIgnificant byte of any subsequently selected in-
ternal register. In order to attaIn an Internally stable reset
25 P21AN121 Digital Port or Analog Channel 12 Input state, the RESET pin must be low for at least one complete
26 PlIAN11J Digital Port or Analog Channel 11 Input enable clock cycle.
27 POIAN1OJ Digital Port or Analog Channel 10 Input

Chip Select (CS) - Ch,p select ISan actIve low Input used
28 AN9 Analog Channel9 Input by the MPU system to enable the ADC for data transfers. No
data may be passed to or from the ADC through the data bus
pins unless CS is in a low ·state. A selection of MPU address
30 AN7 Analog Channel 7 Input lines and the M6800 VMA signal or its equivalent should be
31 AN6 Analog Channel 6 Input utilized to provIde chip select to the MCl4444.
33 AN4 Analog Channel4 Input MCl4444 ANALOG INPUTS AND DIGITAL I/O
IRefer to the ADC Block Diagram)
35 AN2 Analog Channel 2 Input Dedicated Analog Channels (ANO, AN2-AN9) - These
input pins serve as dedicated analog channels subject to A/ D
36 ANO Analog Channel 0 Input
conversIons. These channels are fed directly Into the internal
37 MO Analog Multiplexer Output Test Only 16-to-l analog multiplexer which feeds a single analog
36 IRO Interrupt Request Open Drain voltage to the A/ D converter.
Output
Shared Analog Channels (ANlo-AN15) - These input
39 VDD Supply Voltage Input
pins are also connected to the analog multiplexer and may be
40 VREF AID Converter Positive Reference Input used as analog channels for A/D converSion. However,
Voltage these pins may also serve as digital input pins as described
next.
Shared Digital Inputs (PO-P5) - Po-P5 comprise a 6-bit AID Ground Reference Voltage (VAG) - This supply is
digital input port whose bits may also serve as analog chan- the ground reference for the internal OAC and several
nels. The state of these inputs may be read at any time from reference voltages supplied to the comparator. 't should also
the AOC digital data register. The function of these pins is be noise-free to guarantee AID accuracy. Absolute accuracy
not programmed, but instead is simply assigned by the may be degraded if VAG is wired to VSS at the AOC
system designer on a pin-by-pin basis. package unless VSS has been sufficiently filtered to remove
switching noise. Ideally VAG should be Single-pOint ground-
CAUTION: Digital values read from the PO-P5 bit ed to the system analog ground supply.
locations do not guarantee the presence of true dig-
ital input levels on these pins. PO-P5 pass through a Multiplexer Output (MO) - The analog multiplexer selects
TTL-compatible input buffer and into the digital data one of 16 analog Input channels and connects It to the input
register. These buffers are designed with enough of the AID converter. The multiplexer output IS Internally
hysteresis to prevent internal oscillations If an analog connected to the AID Input and requires no external
voltage between 0.8 and 2 V is present on one or Jumpers. Since loading of the MO pin affects the charging
more of these six pins. time of the OAC, it is recommended that no connection be
made to the MO pin.
Digital 110 Port (0100-0102) - These pins serve as a 3-bit
digital 1/0 port. At reset the port is configured as an input
and may be read from the AOC digital data register. The port
may be programmed as an output by setting the 001 R bit in
the control register to a logical 1 See the control register The MCl4444 AOC has three 16-blt internal registers. Each
discussion for further details. When configured as an output, register is divided into two 8-bit bytes: a most significant
the 010 port will provide CMOS logic levels for limited dc (MSI byte Ibits 8-151 and a least significant ILSJ byte (bits
load currents. (Refer to the Electrical Specifications for the 0-71. Each of these bytes may not be addressed externally,
dc drive capability of this port. 1 New output states are but instead are normally addressed by a Single 16-bit instruc-
transferred to the external pins on the last falling edge of E tion such as the M6800 LOX instruction. An Internal byte
during a 16-blt write to the control register. When configured pOinter selects the appropriate register byte dUring the two E
as an input, the port will accept both TTL and CMOS logiC cycles of a normal 16-blt access. In keeping With the M6800
levels. X register format, the pOinter pOints first to the MS byte of
any selected register. After the E cycle In which the MS byte
Dedicated Digital Inputs (013-015) - These three pins are ISaccessed, the pOinter Will switch to the LS byte and remain
dedicated as digital inputs whose values may be read from there for as long as chip select is low. The pOinter moves
the AOC digital data register. They are also TTL and CMOS back to the MS byte on the falling edge of E after the first
compatible. complete E cycle in which the AOC IS not selected. (See
Figure 2a for more detail.) The MS byte of any register may
also be accessed by a simple 8-bit Instruction as shown in
Figure 2b. However, the LS byte of all registers may be
accessed only by 16-bit instructions as described above. By
Positive Supply Voltage (VOO) - VOO is used internally connecting the AOC register select IRSlI to the MPU
to supply power to all digital logic and to the chopper address line A 1, the three registers may be accessed sequen-
stabilized comparator. Because the output buffers con- tially by 16-bit operations.
nected to this supply must drive capacitive loads, ac noise on
this supply line is unavoidable Internally. Analog CirCUits us- CAUTION: RSl should not be connected to
ing thiS supply within the MCl4444 were designed With high address line AD and the addressing of the AOC
VOO supply rejection; however, It IS recommended that a should be such that RS1 does not change states dur-
filtering capacitance be used externally between VOO and Ing a 16-bl t access.
VSS to filter noise caused by transient current spikes.
Ground Supply Voltage (VSS) - VSS should be tied to

system digital ground or the negative terminal of the VOO
power source. Again, the output buffers cause internal noise
on this supply, so analog circuits were designed with high Addressing Signals
V SS rejection. RESET CS R/W RSt ADC Response
0 X X X Reset
Positive AID Reference Voltage (VREF) - This is the
voltage used internally to provide references to the analog , 0 0 0 No Response
comparator and the digital- to-analog converter used by the
SAR AID. The analog-te-digital conversion result Will be
1 0 0 , MPU Write to Control RegIster
ratiometric to VREF - VAG (full scalel. Hence VREF should 1 0 1 0 M PU Read from Analog Data
be a very noise-free supply. Ideally VREF should be single- Register
point connected to the voltage supply driving the system's 1 0 1 1 MPU Read from Digital Data
transducers. VREF may be connected to VOO, but degrada- Register
tion of absolute AID accuracy may result due to SWitching
1 1 X X Chip DeselectedINo Response)
noise on VOO.
Internal
Byte Pointer
Reset to MS Byte
MCl4444 CONTROL REGISTER
(Write Only)
15 o
o AO
IMSBJ ILSBI
Analog Multiplexer Address (AD-A31 - These four will begin immediately after the completion of the control
address bits are decoded by the analog multiplexer and used register write.
to select the appropriate analog channel as shown below.
Unused Bits (Xl - Bits 9-13 of the ADC Control Register
are not used internally.
HexadecimalAddress IA3= MSBJ Select
o ANO Interrupt Enable liE) - The interrupt enable bit, when set
1 VREF to a logical 1, allows the TRQ pin to be activated at the com-
2-9 AN2-AN9 pletion of the next analog to digital conversion.
A-F ANlO-ANI5IPO-P51
Control Register MSB - The MSB of the most significant
byte of the ADC control register must be wntten as a logical
Digital 1/0 Output (OlOO-DI021 - When the MPU con- O.
figures the 3-bit 1/0 port as an output, these are thebit loca-
tions into which the output states are written.
1/0 Port Data Direction (DDIR) - This is the data direc- NOTE: A 16-bit control register write ISrequired to change
tion bit for the 3-bitl/0 port.·A logical 1 configures the port the analog multiplexer address or to update the DIO port.
as output while a logical a configures the port as input. However, S-bit writes to the MCl4444 can be used to initiate
an AID conversion if the analog MUX is already selecting the
Start AID Conversion (SCI - When the SC bit is set to a desired channel. This is useful when repeated conversions
logical 1, an AI D conversion on the specified analog channel on a particular analog channel are necessary.
MCl4444 ANALOG DATA REGISTER

(Read Only)
15 o
EOC RO
IMSBI ILSBJ
AID Result (RD-Rl) - The LS byte of the analog data conversion is successfully completed by the ADC. The status
register contains the result of the AID conversion. R7 is the bit is cleared by either an S-bit or a 16-bit MPU write to the
MSB, and the converter follows the standard convention of ADC control register. The remainder of the bits in the MS
assigning a code of SFF to a full-scale analog voltage. There byte of the analog data register are always set to a logical a
are no special overflow or underflow indications. to simplify MPU interrogation of the ADC status. For exam-
ple, a single S-bit M6800 TST Instruction can be used to
determine the status of the AID conversion.
MCl4444 DIGITAL DATA REGISTER
(Read Only)
Digital 1/0 Port (0100-0102) - The states of the three Shared Digital Port (PO-P5) - The voltage present on
digital 1/0 pins are read from these bits regardless of these pins IS interpreted as a digital signal and the corres-
whether the port is configured as input or output. ponding states are read from these bits.
Dedicated Digital Input (013-015) - The states of the WARNING: A digital value will be given for each pin even
three dedicated digital inputs are read from these bits. if some or all of the pins are being used as analog inputs.
Analog Multiplexer Address (AQ-A3) - The number of the

analog channel presently addressed is given by these bits.
ANALOG SUBSYSTEM
(See Block Diagram)
2 enable clock cycles for the write into the control register
even if only 8 bits are written. In this case, the second E cycle
The analog subsystem of the MC14444 is composed of a does not affect any internal registers. During the next 12Yz
16-channel analog multiplexer, an 8-blt capacitive DAC enable cycles following a write command, the analog
(digital-to-analog converter), a chopper-stabilized com- multiplexer channel is selected and the analog input voltage
parator, a successive approximation register. and the is stored on the sample and hold DAC. It is recommended
necessary control logic to generate a successive approxima- that an input source impedance of 10 KG or less be used to
tion routine. allow complete charging of the capacitive DAC.
The analog multiplexer selects one of sixteen channels and During cycle 13 the AlDis disconnected from the
directs it to the input of the capacitive DAC. A fully- multiplexer output and the successive approximation AID
capacitive DAC is utilized beca.use of the excellent matching routine begins. Since the analog input voltage is being held
characteristics of thin-oxide capacitors in the silicon-gate on an internal capacitor for the entire conversion period, it is
CMOS process. The DAC actually serves several functions. required that the enable clock run continuously until the AID
During the sample phase, the analog input voltage is applied conversion is completed. The new B-bit result is latched into
to the DAC which acts as a sample-and-hold circuit. During the analog data register on the rising edge of cycle 32. At this
the conversion phase, the capacitor array serves as a digital- point the end of conversion bit IEOC) is set in the analog
to'analog converter. The comparator is the heart of the data register MS byte, and the interrupt request IIRO) pin
ADC; it compares the unknown analog input to the output of goes low if interrupt has been enabled by the IE bit of the
the DAC, which is driven by a conventional successive- control register. ISee Figure 3, AID Timing Sequence.)
approximation register. The chopper-stabilized comparator
was designed for low offset voltage characteristics as well as
VDD and VSS power supply rejection. NOTE: The digital data register or the analog data register
may be read even If an AID conversion is in progress. If the
analog data register is read during an AID conversion, valid
results from the previous conversion are obtained. However,
An AID conversion is initiated by writing a logical 1 into the EOC bit will be clear Ilogical 0) if an AID conversion is in
the SC bit of the ADC control register. The MC14444 allows progress.
MPU Write
To ADC
Control
Register Sample Analog Input I
1-1 ~llnput Should Be Stablel~4( SAR AID Conversion •
1 2 3 4 5 6 7 B 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2526 2728 29 30 31 32
Analog Data
Register I RO-R7
and EOCI
B
iRO
Ilf Enabledl
Duct
Damper
Control
® MOTOROLA

LINEAR SUBSYSTEM
The MC14443 and the MC14447 devices are 6 channel, single

MICROPROCESSOR BASED
slope, 8-10 bit analog to digital converter linear subsystems for
microprocessor based data and control, systems, Contained in both
II devices are a one of 8 decoder, an 8 channel analog multiplexer,

a buffer amplifier, a precision voltage to current converter, a ramp
start circuit, and a comparator. The output driver of the MC14443
comparator is an open-drain N-channel capable of sinking up to
5 mA of current. The output of the MC14447 comparator has a
standard B·SeriesP-channel,N-channel pair.
A processor system (such as the MC6800, MC141000 or
MC3870) provides the addressing,timing, counting, and arithmetic L SUFFIX P SUFFIX
operations required for implementing a full analog to digital CERAMIC PACKAGE PLASTIC PACKAGE
converter system. A system made up of a processor and the linear CASE 620 CASE 648
subsystem has features such as automatic zeroing and variable scaling

(weighting) of six separateanalog channels.
Suffix Denotes
• Quiescent Current 0.8 mA Typical at VOO = 5 V
• Single Supply Operation +4.5 to +18 Volts T- L Ceramic Package
L P Plastic Package
• MPU Compatible
• Typical Resolution - B Bits
• Typical Conversion Cycle as Fast as 300 IlS
• Ratio Metric Conversion Minimizes Error
• Analog Input Voltage Range: VSS to VOO - 2V
VOD'Eo Pin 14
VSS"" Pin 5
® MOTOROLA
MC14457
MC14458
MC14457 TRANSMITTER
MC14458 RECEIVER
The MC14457 and MC14458 are a transmitter and receiver pair

of integrated circuits constructed in CMOS monolithic technology.
TRANSMITTER
These units are designed for ultrasonic or infrared remote control
of TV receivers, converters, communication receivers, and games. RECEIVER
Channel selection up to 16 channels can be done single entry; or,
up to 256 channels can be done double entry.
• Low External Component Count
~-
• High Noise Immunity
• Error Free Operation
• One Analog Output From Receiver
• On-Signal Provision
1 1
• Low Power
Receiver
• Operating Voltage Range P SUFFIX P SUFFIX
4.5-10.0 Vdc for MC14457 PLASTIC PACKAGE PLASTIC PACKAGE
CASE 709 CASE 648
4.5-5.5 Vdc for MC14458

voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
Rating Symbol Value Unit mum fated voltages to this high impedance
circuit. For proper operation it is recommended
DC Supply Voltage MC14457 VOO -0.5'0 +12 Vde
that V in end Vout be constrained to the range
MC14458 -0.5 to +6.0
VSS <: (Vin or Vou.) <: VOO'
Input Voltage, All Inputs Vin -0.5'0 VOO + 0.5 Vdc
Unused inputs must always be tied to an
DC Current Drain per Pin 1 10 -mAde appropriate logic voltage level (e.g., either
Operating Temperature Range TA -40'0 +85 °c VSSor VOO),
PIN ASSIGNMENTS
MCl4457 MCl4458
TRANSMITTER RECEIVER
16 24
15 2 23
14 3 22
4 13 4 21
5 12 5 20
6 11 6 '9
'1 10 18
7
8 9 8 17
9 16
10 15
11 14
12 13
TRANSMITTER MC14457
ELECTRICAL CHARACTERISTICS
Ttow 25"<:
Voo " Th· h"
Characteristic Symbol Vd. Min Mox Min Typ Mox Min Mox Unit
Output Voltoge "0" Level VOL 5.0 - 0.05 - 0 0.05 - 0.05 Vdc
Vin - VOO orO 10 - 0.05 - 0 0.05 - 0.05
''I'' Levol VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vde
Vin""'OorVOD 10 9.95 - 9.95 10 - 9.95 -
Input Voltoge # "0" Level VIL Vdc
(VO - 4.5 or 0.5 Vdc) 5.0 - 1.5 - 2.25 1.5 - 1.5
(VO - 9.0 or 1.0 Vde) 10 - 3.0 - 4.50 3.0 - 3.0
VIH
"'" Lwei
(Va - 0.5 or 4.5 Vdel 5.0 3.5 - 3.5 2.75 - 3.5 - Vdc
(VO = 1.0 or 9.0 Vde) 10 7.0 - 7.0 5.50 - 7.0 -
Output Drive Current - Pins 14, 15
(Out 1, 2) IOH mAde
(VOH = 2.5 Vdc) Source 5.0 -6.0 - -5.0 -9.0 - -3.5 -
(VOH = 9.5 Vdcl 10 -3.2 - -2.6 -4.5 - -1.8 -
(VOL - 2.5 Vdc) Sink IOL 5.0 6.0 - 5.0 9.0 - 3.5 - mAde
(VOL =-0.5 Vdc) 10 3.2 - 2.6 4.5 - 1.8 -
Output Drive Current - Pin 13 (Mod) IOH mAde
(VOH - 4.6 Vdcl Source 5.0 -0.26 - -0.22 -0.44 - -0.18 -
(VOH ·9.5 Vdc) 10 -0.6 - -0.55 -1.12 - -0.45 -
(VOL· 0.4 Vdc) Sink IOL 5.0 0.26 - 0.22 0.44 - 0.18 - mAde
(VOL - 0.5 Vdc) 10 0.6 - 0.55 1.12 - 0.45 -
I npJJt Cu rrent Pull-ups lin 10 50 500 1000 - IolAdc
Input Current - Pin 11 (Oscin) 'in 10 - ±0.3 - ±O.OOOOI ±0.3 - ±1.0 IolAdc
(Vin = 0)
Quiescent Current - Per Package 100 5.0 - 50 - 0.008 50 - 375 "Ade
(OSCin• Low) 10 - 100 - 0-016 100 - 750
·-Total Supply Current at an External IT /JAde
Load Capacitance (eL) of Figure 4. 5.0 - - - 5.0 - - -
f- 500kHz 10 - - - 10 - - -
(with any Analog command)
RECEIVER - MC14458
ELECTRICAL CHARACTERISTICS
-
VOO T,ow· 25"<: Thigh"
Ch8ract.ristic Symbol Vd. Min Mox Min Typ Mox Min Mox Unit
Output Voltoge "O".Level VOL 5.0 - 0.05 - 0 0.05 - 0.05 Vd.

VinE VODorO
••,,, Level
VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vde
Vin-OorVOD
Input Voltoge" "0" Level VIL Vdc
(VO· 4.5 or 0.5 Vde) 5.0 - 1.5 - 2.25 1.5 - 1.5
"I" Level VIH
(VO - 0.5 or 4.5 Vde) 5.0 3.5 - 3.5. 2.75 - 3.5 - Vdc
Output Drive Current IOH .' mAde
(VOH = 2.5 Vdc) Source 5.0 -0.5 - -0.5 -1.7 - -0.4 -
(VOL· 0.4 Vd.) Sink IOL 5.0 0.45 - 0.4 0.78 - 0.34 - mAde
Input Current (OSCio. Din) lin 5.0 - ±0.3 - ±O.OOOOI ±0.3 +1.0 "Ade
Inpu't Current (PORI 1;" 5.0 - - 10 50 400 - - "Ade
(Vin'O)
Quiescent Current 100 5.0 - 5.0 - 250 1000 - - "Ade
(Per Peckoge)
Data Input Hysteresis VH". 5.0 - - - 0.25 - - - "Adc
--Totel Supply Current at en IT 5.0 - 400 - - - "Ade
External Load Capacitance
(CLI of Figure 6
f· 500 kHz
"Tlow-~C #Noise immunity specified for worst-case input combination

Thigh - +850C Noise Margin for both "1" and "O"'evel = 1.0 Vdc min@Voo = 5.0 Vdc
·-The formulas given are for the typical characteristics only at 250(: 2.0 Vdc min@ VOO - 10 Vdc
Characteristic Symbol Min Typ M.x ·Unit
Output Rise and Fall Time - Receiver tTLH, tTHL - 0.3 1.0 1"
CL' 100 pF
Oscillator Start-Up Time - Transmittll Ion - 8.0 - j.IS
Clock Pulse Frequency PRF - 1500 600 kHz
Osc O,e
In Out
11 12
I '
3
1 40
5
t<.eybo.rd
Decode
ond
Oebounce
: Mod
1 go
100-
(Data
Code)
VOO - Pin 16,
VSS - PinS
5·Bit Keyboard
renCOded latched 08ta--1
VI/I/1 VI1 V1/J Vi1 VI1
c=J I LF+I 0 I ' I 0 I 0 I ' I I I
Low Frequency
High Frequency ~
Zero
Start
One
Start .,
Funct LSB LSB L~B
·2
M~B
II
Hi Freq '"
4,1.67 kHz
I
_ILJ
P,. Function
Surt Bit
LoY<' F "0"
INPUT/OUTPUT FUNCTIONS - MC14457; OSCILLATOR (OSCin;OSCout; Pins 11, 12)

TRANSMITTER
These pins are the input/output terminals of the
oscillator. It can be used with ceramic resonator or
crystal. The oscillator is automatically turned off after
These pins are the row inputs and are active in the the data is transmitted for low current quiescent
low state. operation.
If an external oscillator is used, a current limiting
resistor should be added due to the presence of an in-
ternal pull-down device on the oscillator input.
These pins are the column inputs and are active in
the low state.
OUTPUT (Out 1, Out 2; Pins 14, 15) This pin is a data code output. There is no power-up
reset.
These pins provide push-pull output and can be used
with ceramic transducers or LEOs. In the non-
operating condition, both outputs are at ground poten-
tial.
Kov Row Column Transmitter Data & Receiver Output Address VA
Operation Notes
Number (Active Low) (Active Low) MSB/A3 LSB+2/A2 LSB+1/A1 LSB/AO Function Pulse
1 Digit 0 R1 C1 0 0 0 0 0 - 1
2 Digit 1 Rl. C2 0 0 0 1 0 - 1
3 Digit 2 R2 Cl 0 0 1 0 0 - 1
4 Digit 3 R2 C2 0 0 1 1 0 - 1
5 Digit 4 R3 Cl 0 1 0 0 0 - 1
6 DigitS R3 ·C2 0 1 0 1 0 - 1
7 Digit6 R4 Cl 0 1 1 0 0 - 1
8 Digit 7 R4 C2 0 1 1 1 0 - 1
9 Digit 8 RS Cl 1 0 0 0 0 - 1
10 Digit 9 RS C2 1 0 0 1 0 - 1
11 Spare Rl C3 0 0 0 0 1 ..j 2
12 Spare Rl C4 0 0 0 1 1 ..j
2
13 Fine Tuning ..j
R2 C3 0 0 1 0 1 3
14 R2 ..j
Fine Tunin'g C4 0 0 1 1 1 3
15 . R3 ..j
Spare C3 0 1 0 0 1 3
16 Spare ..j
R3 C4 0 1 0 1 1 3
17 Vol 1 R4 C3 0 1 ..j
1 0 1 3
18 Vol t R4 C4 ..j
0 1 1 1 1 3
19 Mute on/off RS C3 1 0 0 0 1 V 2
..j
20 Off RS C4 1 0 0 1 1 2
21 Digit 10 R2 + AS Cl 1 0 1 0 0 - 1
22 Digit 11 R2 + RS C2 1 0 1 1 0 - 1
23 Diait 12 R3 + RS Cl 1 1 0 0 0 - 1
24 Digit 13 R3 + RS C2 1 1 0 1 0 - 1
25 Digit 14 A2+A3+AS Cl 1 1 1 0 0 - 1
26 Digit 15 A2+A3+AS C2 1 1 1 1 0 - 1
27 Spare A2 + AS C3 1 0 1 0 1 - 3
28 Spare A2 + AS C4 1 0 1 1 1 - 3
29 Spare R3 + RS C3 1 1 0 0 1 - 3
30 Spare A3 + AS C4 1 1 0 1 1 - 3
31 Spare A2+A3+AS C3 1 1 1 0 1 - 3
32 Spare R2+R3+R5 C4 1 1 1 1 1 - 3
Notes
1. Channel Select Keys (Function Bit = 0), Data is trans·
mitted once each time a key is activated.
2. Toggling type On/Off or counter advance type keys.
Data is transmitted once each time a key is activated.
3. Analog Up/Down or On/Oft' keys, i.e., one key for
Down or .Off and another key for Up or On. Data
transmission is repeated as long as the key is operated.
In Table 1 all channel select data is noted by the func· The twelve remaining analog keys (Vol, Tint, Color,
tion bit equal to zero. For functions other than channel, etc.) transmit data as long as the key is activated. The
the function bit equals one. keys' functions are arranged to provide the most typical
The four toggling or counter advance type keys that application without grounding of multiple row or
transmit data once each time a key is activated are Mute, columns required.
Off, Channel Search Up, and Channel Search Down.
16 L8
15 L4
14 L2
13 Ll
B MB
9 M4
10 M2
11 Ml
•• 06 UHF/VHF
17 OR
4 AFT
This transmitter integrated circuit is used for encoding As one example of operation, a free-running ceramic
keyboard position into frequency·modulated biphase resonator oscillator (at 500 kHz), triggered by the depres·
data. This integrated circuit can function with a keyboard sion of any key, is divided by 12 or 13 to provide fre-
from 20 to 32 keys and provide either channel selectl quencies of 41.67 kHz or 38.46 kHz. The transmitted
toggle information (single-word transmission) or analog data 'zero' consists of 256 periods of the lower frequency
information (continuous transmission of the data word followed by an equal number of the higher frequency.
for duration of key press). Mark to space ratio is kept at 1: 1 in each case. Data 'one'
When used in conjunction with the receiver, selection reverses the order of the two frequencies.
capability is: any single or two-digit channel select up to Rowand column information from the keyboard is
256 channels with appropriate keyboard; a maximum of encoded into a Sobit word and loaded onto data latches
12 analog control functions; 4 toggle type commands. At on the edge of transmit enable. This data, preceded by
an operating voltage of 9.0 volts, the high output drivers two bits, 0 and 1, is used in sequence to provide biphase
provide 4 V pp into a 1 kO load 'via an output bridge control of the divider and, consequently, the bit pattern
configuration. The chip features low standby power as all transmitted from the unit. Each 7-bit word begins and
portions are shut off after data transm ission, with the ends with a low frequency burst. Operation of a channel
counter-chain held in the reset position. select key produces an output data stream for a duration
of approx imately lOOms.
A negative going pulse with a duration of 768 /lS ap-
DATA (Din; Pin 2)
pears at pin 18 approximately 0.1 second after an analog
The amplified ultrasonic data signal (after amplifica- on/off key on the remote control transmitter keyboard is
tion and limiting forms a square wave with a peak-to- operated. Either edge of this pulse may be used 'for con-
peak value of Voo) is applied to this input terminal. trol of add-on circuits.
The Valid Address pulse is repeated every 102.4 ms for
as long as a key is operated which provides repeated trans-
The oscillator input pin of the receiver is con- mission of data when held down. '
nected to an oscillator providing, for example, a 500 kHz The Valid Address signal may be used in conjunction
square·wave signal. A typical oscill~tor circuit is shown in with the Address Outputs to drive memories to provide
II
Figure 5. Accuracy of 1% relative to the oscillator fre· additional control functions such as color, tint, etc.
The Valid Address pulse may be used to provide a
quency in the transmitter is recommended for satisfactory
performance in very high echo·producting environments. stepping clock for up/down counters in a memory. The
least significant address line (AO) is used to identify the
CHANNEL OUTPUTS (Ll, 2, 4, 8, MI, 2, 4, 8; up or down mod~ and the remaining address lines (A I,
Pins 13, 14, 15, 16, II, 10, 9, 8) A2, A3) are decoded to enable each individual control
circuit.
The eight data output pins provide latched data corres· By adding up/down counters to the Data Outputs, it is
ponding to the channel selected on the transmitter key- possible to use the Valid Address pulse and a decoded
board. L1 through L8 are the least significant bits; M 1 address for implementing a channel up/down stepping
through M8 are the most significant bits. The data on function from the remote control. Additional On/Off
these pins is accompanied by a Data Ready signal. functions may be obtained by using the Valid Address
pulse' in combination with a decoded address for setting
and resetting of latches. The Valid Address signal is dis-
A positive pulse with a duration of 768 /lS appears at abled in the standby mode (On output at logical 0).
pin 17 of the transmitter approximately 0.1 second after
a complete command is entered on the remote control
transmitter keyboard. The negative going edge of this
pulse may be used for triggering purposes. This pin of the receiver provides a low level when the
NOTE: A complete command is one digit in the single selected channel is a VHF channel (00 to 13, or 84 to 99).
entry mode or two digits in the double entry mode. A high level on pin 6 identifies selection of a UHF
channel (14 to 83). This signal is provided to permit
switching of VHF and UHF tuners.
AFT ENABLE (AFT; Pin 4)
The voltage level at this pin is low for a time duration
ON (Pin 5)
of 0.393 second following a change in selected channel to
allow disabling the tuner AFT circuit. Also, miscellaneous This pi n of the receiver provides a low level following
commands 0000,0001,0010, and 0011 (Channel Search operation of the Off command (1001) on the remote-
Up/D6wn, Fine Tuning Up/Down) will cause this disable control transmitter. The signal on this pin changes to a
feature. high level when a channel is selected.
ANALOG OUT (Vol; Pin 23)

Th is pin is low for power-on reset of the analog output
An analog voltage in the range between 0 V and VDD
to 0 pulse width and off/on output to O. An internal
is obtained by integrating the signal at the Analog Out pin
pull·up device of 10 to 400 /lA will charge an external
through a low pass filter. The analog voltage resolution
capacitor. Reset occurs until the input voltage reaches
has been chosen to be 64 steps. Its value can be incre·
70% VDD. All internal registers will also be reset.
mented or decremented in steps of one by keys providing
ADDRESS (AD, I, 2, 3; Pins 19, 20, 21, 22) commands 0111 and 011 0, respectively. (See Table 1.)
The Address outputs of the receiver identify selected The analog voltage can be varied up or down at a
analog and on/off commands for use in system expansion. speed of approximately 10 steps per second. The D/A
The data on these lines is valid when accompanied by a conversion is performed with an underflow and an over-
Valid Address pulse. flow limiting circuit. The Analog Out pin is normally used
for the control of volume. The first time power is applied LOW BAND (LBV; Pin 7)
to the remote-control receiver, the volume output is 0 This pin will go HIGH whenever channels 02,03,04,
volts. 05, or 06 are selected. The output is LOW for channels
The Analog Out signal may be increased after a chan· 00, 01, and 07 through 99.
nel has been selected by operating the key providing a
command 0111. (Volume Up)
The Analog Out signal may be muted by operating a
key on the transmitter providing command 1000. Return The receiver can be placed in a single-digit mode of
to the original output prior to muting may be achieved by operation by connecting the M4 data output (pin 9) to
operating the mute key a second time or by operating the VOO and the UHF output (pin 6) to VSS' In this mode,
volume-up key. the L 1 through L8 channel outputs will change immedi-
In the muted mode the analog level is memorized ately after the entry of a single digit on the transmitter
B and cannot be varied by the up/down controls on the

transmitter.
keys. The M 1 through M8 outputs are not used in this
mode. (SeeFigure 6.)
Function
Bit MSB MSB-l LSB+ 1 LSB Command
0 0 0 0 0 Channel Digit 0
0 1 1 0 1 ~hannel Digit 13
1 0 0 0 0 Channel Search Down
1 0 0 0 1 Channel Search UP
1 0 0 1 0 Fine Tuning Down
1 0 0 1 1 Fine Tuning Up
1 0 1 0 0 Miscellaneous Command Spare
1 0 1 1 0 Volume Down
1 0 1 1 1 Volume Up
1 1 0 0 0 Mute On/Off
1 1 0 0 1 Set Off
100pF 1000pF,
Ultrasonic
Ceramic
R2 Microphone
R3
R4
MC14457
16
+9 V
II
3 8
R5
C1 C2 C3 C4
6 7 10 9
Note: Cera",ic Aesonator is

RMC Type CA-30
or Equivalent
680
11 12
14
R1
4 15 330
R2
..•
R3 MC14457
.•
~+6V
Z
iii
~
16
R4 ":" ":"
50llF
3 8
R5
C1 C2 C3 C4
6 7 10 9 ':"
From:
Radio Materials Corp.
Chicago, USA
r
-Bias for I
Photodiode Only I 120k 1 Meg
00P~'00PF .
'000
pF
~
+5V
100 pF
+5V
1100 pF
+5V
100 pF I
1/6MC14069usI 1/6MC14069UB 1/6MC14069UB
560 -::- -::- -::-
II
}~,
8
8
9
4
10
" Data Outputs
: ::-}LSO
13
10PF! 'OOpF T 17
22
A3
21
A2
A1
20 }"._ 0."."
AO '9
18
VA
On/Off
23
Vol
Note:
0.47 I It is mandatory to us. an infr.red filter

-in front of the photodiode. Type Kodak
JlF -= Low Sand VHF
87C or similer.
UHF/VHF
AFT
APPliCATION INFORMATION
Typical circuits for the transmitter and receiver chips using three of the four hex inverters in the MC14069UB
are shown in Figure 3 through B. package. A fourth inverter from the same package operates
The transmitters, with the keyboard shown, transmit a 500 kHz oscillator circuit.
the first twenty codes from Table 1. The circuits of Figure 6 shows a block diagram of a PLL system. The
Figure 3 transmit via ultrasonic; whereas, the circuit of receiver directly addresses a synthesizer. In this diagram,
Figure 4 transmits infrared light. In Figure 3, push-pull a complete command consists of two channel digits
output at pins 14 and 15 allows a balance drive to the followed by an Enter code. The Enter code into the
ceramic microphone, which virtually doubles the trans- synthesizer is a 0101 in complementary logic. The trans-
mitted power, compared to a single-ended output. mitted code from the transmit~er is 1010, which is
The diagram in Figure 5 shows an amplifier connected Function 10 from Table 1.
to a remote receiver. The bias resistor (photodiodel of A block diagram of a tuning address system is shown
the amplifier requires bias. The bias voltage is determined in Figure 7. This block diagram incorporates a one-chip
by the choice of photodiode and system considerations microcomputer that would be programmed to the sys-
such as ambient light. Most of the required gain is realized tem's needs. The system can be expanded up to 256
channels.
'6 3
MC14458
Remote '5 6
Receiver
'4 2
'3 10 4
"::" "::" 12 12 E
+ 5V
"::"
R
C
Binarv
Complement
Diode
Logic
Note: Adjust A and C to give a "0"

on E which is long enough to
enter data witl:lout problem.
·MC141000 is a 4 bit microprocessor

internallv programmed to customer
needs.
® MOTOROLA
MC14466
MC14467
CMOS MSI
(LOW-POWER COMPLEMENTARY MOS)
The MC14466, or the MC14467, together with an ionization
chamber, will detect smoke using a minimum of external com-
ponents. When smoke is sensed, an alarm is sounded via an ex-
ternal piezoelectric transducer and internal drivers. This circuit is
B
designed to comply with the U.L. 217 specification.
• Ionization Type with On-Chip FET

• Piezoelectric Horn Driver
• Guard Outputs on Both Sides of Detect Input
• Input Protection Diodes on the Detect Input (MC144671
• Low Battery Trip Point Internally Set Can Be Altered
Via External Resistor
• Detect Threshold Internally Set Can Be Altered Via
External Resistor P SUFFIX
PLASTIC PACKAGE
• Pulse Testing for Low Battery Uses LED for CASE 648B> (MC144661
Battery Loading CASE 648 (MC14467)
• Comparator Outputs for Detect and Low Battery

• Internal Reserve Battery Protection • * Pins 1 5 and 16 are connected via metal
shorting bar. See package details in chap-
ter 3.
Detect
Guard
Camp Out
Detect
N/C
Input
Low V
Set Guard
Low V Sensitivity
Camp Out Set
Doc
LED Capacitor
VOO Horn
Out 3
Timing Horn
Resistor Out 2
Horn
Out 1 vSS
Input Voltage, All Inputs Vin -0.25 to VOO + 0.25 Vdc
DC Current Drain per Input Pin I 10 mAdc
DC Current Drain per Output Pin I 30 mAde
Reverse Battery Time tRB 5.0 ,
Parameter Symbol Value Unit

Supply Voltage VOO 9.0 Vdc
Timing Capacitor - 0.1 ~F
Timing Resistor - 8.2 Mn
Battery Load (Resistor or LEDI - 10 mAdc
Voo
Characteristic Symbol Vdc Min Typ M.x Unit
Operating Voltage VOO - 6.0 - 10 Vdc
Output Voltage Vdc
Piezoelectric Horn Drivers (I0H = 16 mA) VOH 7.4 6.5 - -
Comparators UOH = 0.1 mAl 9.0 8.5 8.8 -
Piezoelectric Horn Drivers llOL::O: -16 mA) VOL 7.4 - - 0.9
Comparators (I0L = -0.1 mAl 9.0 - 0.1 0.5
Output Current - LED Driver IOL 7.4 10 - - mAdc
(VOL: 3.0 Vdc)
Operating Current 100 9.0 - 5.0 9.0 IJAdc
(RBia, = B.2 Mn)
Input Current - Detect (40% R.H.1 lin 9.0 - - t 1.0 pAdc
Internal Set Voltage - Low Battery V Low 9.0 7.4 - B.O Vdc
- Sensitivity VSet - 47 50 53 ""VOO
Hysteresis VHy, 9.0 75 100 150 mVdc
Offset Voltage VOS mVdc
Active Guard 9.0 - - t 100
Detect Comparator 9.0 - - t 50
strained to the range VSS .;; (Vin or Vout) .;; VOO'
Characteristics Symbol Min Typ Max Units
Oscillator Period No Smoke tCI 1.34 1.67 2.0 s
Smoke 32 40 48 ms
Oscillator Pulse Width PWCI 8 10 12 ms
Horn Output On Time PWon - 200 - ms
(During Smoke) Off Time PWofl - 40 - ms
LED Output Between Pulses tLED 32 40 48 s
On Time PWon 8 10 12 ms
Horn Output On Time ton 8 10 12 ms
(During Low Battery) Between Pulses toff 32 40 48 s
No Smoke Smoke Smoke No Smoke

~No Low Battery I • No Low Battery - __ --Low Battery I• Low Battery--1
1.67 s -+---t- -I 1--40 ms 10ms =1f--
~
Tlr
~~,~.=~~ ~24 Clock Cycles~24

40s
Clock Cycles---t
1 s
U
NOTES: 1. Horn modulation is self-completing. When going from smoke to no smoke, the alarm
condition will terminate only when horn is off.
2. Comparators are strobed on once per clock cycle (1.67 s for no smoke, 40 ms for smoke).
3. Low battery comparator information is latched only during LED pulse.
TIMING SENSITIVITY/LOW BATTERY THRESHOLDS
The internal oscillators of the MC 1 4466 and the Both the sensitivity threshold and the low battery
MC14467 operate with a period of 1.67 seconds dur- voltage levels are set internally by a common voltage
ing no-smoke conditions. Each 1.67 seconds, internal divider connected between VDD and VSS. These voltages
power is applied to the entire IC and a check is made for can be altered by external resistors connected from pins
smoke. Every 24 clock cycles a check is made for low 3 or 13 to either VDD or VSS. There will be a' slight
battery by comparing Voo to an internal zener voltage. interaction here due to the common voltage divider
Since very small current are used in the oscillator, the network.
oscillator capacitor should be of a low leakage type.
TEST MODE
DETECT CIRCUITRY Since the internal op amps and comparators are power
If smoke is detected, the oscillator period becomes strobed, adjustments for sensitivitY or low battery level
40 ms and the piezoelectric horn oscillator circuit is could be difficult and/or time-eonsuming. By forcing
enabled. The horn output is modulated 200 ms on, 40 ms pin 12 to VSS, the power strobing is bypassed and the
off. During the off time, smoke is again checked and will outputs, pin 1 and 4, constantly show smoke/no smoke
inhibit further horn output if no smoke is sensed. During and good battery/low battery, respectively. Pin 1 = VDD
smoke conditions the low battery detection is inhibited, for smoke and 'pin 4 = VDD for low battery. In this mode
but the LED pulses at a 1.0 Hz rate. and during the 10 ms powe, strobe, chip current rises to
An active guard is provided on both pins adjacent approximately 50/lA.
to the detect input. The voltage at these pins will be
within 100 mV of the input signal. This will keep surface LED PULSE
leakage currents to a minimum and provide a method The 9-volt battery level is checked every 40 seconds
of measuring the input voltage without loading the during the LED pulse. The battery is loaded via a 10 mA
ionization chamber. The active guard op amp is not power pulse for 10 ms. If the LED is not used, it should be
strobed and thus gives constant protection from surface replaced with an equivalent resistor such that the battery
leakage currents. Pin 16 of the active guard is connected loading remains at 10 mA.
to pin 15 (the detect input) during shipping to protect
pin 15 from static damage. HYSTERESIS
When smoke is detected, the resistor/divider network
that sets sensitivity is altered to increase sensitivity. This
yields approximately 100 mV of hysteresis and avoids
false triggering.
r
t===t= VOO - 9.0 Vdc
TA -15'C
=
I~
4' .....•..
....r-~ I
E
~ 10.0
VOO' 71 Vdc
~
az
~ 1.0
!2
FIGURE 4 - TYPICAL P HORN DRIVER OUTPUT

I - V CHARACTERISTIC
I I TA'" 25°C +---i 1000.0~~E~~~!~!~!~~~~~~~~~~

f--+ ~ -r===l
VOO' 9.0 Vdc I
TA • 15'C
~ 1--+ VOO • 9.0 Vdc I ~

100 0 I r
1 .
;:: 100.0
i
z
, Voa c 7.2 Vdc
z
'J'l
~ 10.0 ~ 10.0 • I
!2 p. CH SOURCE CURRENT ::::::::j
I I
I I
4
VOS. DRAIN TO SOURCE VOLTAGE IVdcl
10.0 TA=250C~
I
4'
oS
•... 1.0 voa '" 9.0 Vdc or 7.2 Vdc I
~
az
~ 0.1
!2
, -- p.
I
CH SOURCE
AND
N -CH SINK
CURRENT
I
5
VOS. DRAIN TO SOURCE VOLTAGE (Vdc)
® MOTOROLA
CMOS
INTERCONNECT
• lonisation Type with On-chip FET SMOKE DETECTOR
• Piezoelectric Horn Driver On-chip
• Guard Outputs on Both Sides of Detect Input
• Input Protection Diodes on the Detect Input
• Low Battery Threshold, Internally Set, Can Be Altered via Exter-
nal Resistor
• Detect Threshold, Internally Set, Can Be Altered via External
Resistor
• Pulse Testing for Low Battery Uses LED for Battery Loading
• Comparator Outputs for Detect
• Internal Reverse Battery Protection
• Strobe Output for External Trim Resistors
• 1/0 Pin Allows up to 40 Units to be Connected for Common
Signalling
• Power-on-reset Prevents False Alarms on Battery Change P SUFFIX
PLASTIC PACKAGE
CASE 648
® MOTOROLA
ADDRESSABLE ASYNCHRONOUS
RECEIVER/TRANSMITTER
The MC14469 Addressable Asynchronous Receiver Transmitter is
constructed with MOS P-channel and N-channel enhancement de-
vices in a single monolithic structure (CMOS). The MC14469 re- ADDRESSABLE ASYNCHRONOUS
ceives one or two eleven-bit words in a serial data stream. One of the RECEIVER/TRANSMITTER
incoming words contains the addressand when the addressmatches,
II the MC14469 will then transmit its information in two eleven-bit·

word data streams. Each of the transmitted words contains eight
data bits, even parity bit, start and stop bit.
The received word contains seven address bits and the addressof
the MC14469 is set on seven pins. Thus 27 or 128 units can be 1,,'1 '!r:
. 'f) . j
interconnected in simplex or full duplex data transmission. In addi· \' ~r'j .J

\'11J" PSUFFIX
tion to the address received, seven command bits may be received
for data or control use.
~¥ J PLASTIC PACKAGE
CASE 711
The MC14469 finds application in transmitting data from remote
A·to-D converters, remote MPUs or remote digital transducers to the
master computer or MPU_
• Supply Voltage Range - 4.5 Vdc to 18 Vdc
• Low Quiescent Current - 75/lAdc maximum @ 5 Vdc
• Data Rates to 9600 Baud
• Receive - Serial to Parallel
Transmit - Parallel to Serial
• Transmit and Receive Simultaneously in Full Duplex
• Crystal or Resonator Operation for On-Chip Oscillator Ceramic Package
• See also Application Note AN-806 Plastic Package
8
Output
l.OIl'c 9
10
11
12
13
14
15
16
17
O~,~O"'."'C'~'
OK, ~ ?_ O••• ,,,.,,
18
19
20
Rec.ive D~ul
voltages or electric fields; however, it is advised
Symbol Value Unit that normal precautions be taken to avoid
DC Supply Voltage VOO -0.5 to+18 Vdc application of any voltage higher than maxi·
Vdc mum rated voltages to this high impedance
Input Voltage, All Inputs Vin -0.5 to VOO + 0.5
circuit. For proper operation it is recommended
DC Current Drain per Pin I 10 mAdc
that Vin and Vout be constrained to the range
Operating Temperature Range TA -40 to +85 °c
VSS" (V in or Voutl "VOO'
Storage T emperatu re Range Tstg -65to+150 °c Unused inputs must always be tied to an
VSS or Vool.
Tlow* 25°C Thinh*

Voo
Characteristic Symbol Vdc Min Max Min Typ Max Min Max Unit
Output Voltage "0" Level VOL 5.0 - 0.05 - 0 0.05 - 0.05 Vdc
Vin = VOO or 0 10 - 0.05 - 0 0.05 - 0.05
15 - 0.05 - 0 0.05 - 0.05
"1" Level VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vdc
Vin=OorVOO 10 9.95 - 9.95 10 - 9.95 -
15 14.95 14.95 15 - 14.95 -
Input Voltage # "0" Level Vil Vdc
(VO" 4.5 or 0.5 Vdc) 5.0 - 1.5 - 2.25 1.5 - 1.5
(VO" 9.0 or 1.0 Vdc) 10 - 3.0 - 4.50 3.0 - 3.0
(VO" 13.5 or 1.5 Vdcl 15 - 4.0 - 6.75 4.0 - 4.0
"1" Level VIH Vdc
(VO" 0.5 or 4.5 Vdcl 5.0 3.5 - 3.5 2.75 - 3.5 -
(VO" 1.0 or 9.0 Vdcl 10 7.0 - 7.0 5.50 - 7.0 -
(VO" 1.5 or 13.5 Vdcl 15 11.0 - 11.0 8.25 - 11.0 -
Output Orive Current (Except Pin 2) IOH mAdc
1VOH " 2.5 Vdcl Source 5.0 -1.0 - -0.8 -1.7 - -0.6 -
(VOH " 4.6 Vdcl 5.0 -0.2 - -0.16 -0.35 - -0.12 -
1VOH " 9.5 Vdcl 10 -0.5 - -004 -0.9 - -0.3 -
(VOH " 13.5 Vdc) 15 -1.4 - -1.2 -3.5 - -1.0 -
(VOL" 004 Vdcl Sink IOl 5.0 0.52 - 0044 0.88 - 0.36 - mAdc
(VOL" 0.5 Vdcl 10 1.3 - 1.1 2.25 - 0.9 -
(VOL" 1.5 Vdcl 15 3.6 - 3.0 8.8 - 204 -
Output Drive Current (Pin 2 Only) IOH mAdc
(VOH "2.5 Vdcl Source 5.0 -0.19 - -0.16 -0.32 - -0.13 -
(VOH "4.6 Vdc) 5.0 -0.04 - -0.035 -0.07 - -0.03 -
(VOH "9.5 Vdc) 10 -0.09 - -0.08 -0.16 - -0.06 -
(VOH " 13.5 Vdcl 15 -0.29 - -0.27 -0048 - -0.2 -
(VOL" 004 Vdcl Sink IOl 5.0 0.1 - 0.085 0.17 - 0.07 - mAdc
(VOL" 0.5 Vdcl 10 0.17 - 0.14 0.28 - 0.1 -
(VOL" 1.5 Vdc) 15 0.50 - 0042 0.84 - 0.3 -
Maximum Frequency fmax 4.5 400 - 365 550 - 310 - kHz
I nput Current lin 15 - ±0.3 - ±0.00001 ±0.3 - ±1.0 ,uAdc
Pull-Up Current (Pins 4-18) lup 15 12 120 10 50 100 8.0 85 ,uAdc
(Vin" 0)
Quiescent Current 100 5.0 - 75 - 0.010 75 - 565 ,uAdc
(Per Package) 10 - 150 - 0.020 150 - 1125
15 - 300 - 0.030 300 - 2250
upply Voltage VOO - +4.5 +18.0 +4.5 - +18.0 +4.5 +18.0 Vdc
*Tlow = -400C
Thigh" +850C
=Noise immunity specified for worst-case input combination.
Noise Margin both "1" and "0" level = 1.0 Vdc min @ VOD = 5.0 Vdc
2.0 Vdc min@VOO" 10 Vdc
2.5 Vdc min@VOO = 15 Vdc
RECEIVE DATA (RI; Pin 19)
I.... Address ••• ~ ~ Command -I

-----1. r T T T T r T T1-r---i ~5TrrTT~IT~\\]-;-p----
~ _ 1_L. L .L L..L..I" L! J 5P L::L ...L ~ ...L ..L ..L ...l "-
" Address Command
4 5 6 7 8 9 10 Identifier Identifier
39 38 37 36 35 34 33
CO Cl C2 C3 C4 C5 C6
MC6850
ACIA Pin Number 22 21 20 19 18 17 16 22 21 20 19 18 17 16
Pin Designation DO Dl 02 03 04 05 06 DO 01 02 03 04 05 06
II
TRANSMIT DATA (TRC; Pin 21)
I- I nput Data
-"I"- Status
..,. -I
rr~ T T TT
..LJ...1..L
~T
oJ. .L T~T
.L P 5P 5T L ..1. ..L
T T T '"T T 'T P' 5P
..L ..L ..L ..L J. ..•. 1
MC14469
Pin Numbers 11 12 13 ,. 15 16 17 18 29 28 27 26 25 2' 23 22
Pin Designation 100101102103104105106107 50 51 52 53 5. 55 56 57
MC6850
ACIA Pin Number 22 21 20 19 18 17 16 15 22 21 20 19 18 17 16 15
Pin Designation DO D1 D2 D3 D' D5 D6 D7 DO D1 D2 D3 D' D5 D6 D7
ST Start Bit AQ -. A6 = Address Bits 100 •...•I D7 = MC14469 Identification Code

P Parity Bit (even) co -+ C6 = Command Bits SO -+ 57" MC14469 Status Code
SP StDP Bit DO -+ 07 '" ACIA 8us Bits
M M
Address S Command 5
~B S .....--,.....·-----..,8 S
Vao SOl 2 34 5 6 7 P SOl 2 3 4 5 6 7 P
""T'"'X"X"X!XTXTXTX'"
VSS L.:..a ~:";.;A.
pnTrx'xrxTxTXTX"TX'
:.£.:~~~_~., _.;&;&;:.to.:.&::.L ~~
rp" ------------------------ Receiver Input (AI)
I
I
I
I
~:~:tddress Pulse ~~-----_-------------------------

I
I
I
Internal Valid I
Address Memory ----+l-----------------
(VALl I
I
I
I
~-----L--.J
I I
I I
I
I
n
I
I
I
I
I
IJI~ _
I
I M M
155
V I B 5 8 5
_______________ OO~5 X X X"X"'TXT"XTXTXTp"'P~5
ISLX1X~.L:.A:.A .L I,;.I_~;:>L:: X'X'XrXrxrxl'X'X"plp--
C L':.L:.a.; L. &,;. L;;I~
T01234567 T01234567
OSCILLATOR (Ose1. Ose2; Pins 1. 2) - These pins SECOND or STATUS INPUT DATA (SO-S7; Pins 22.
are the oscillator input and output. (See Figure 1.) 23.24.25.26.27.28.29) - These pins contain the
input data for the second eight bits of data to be
RESET (Reset; Pin 3) - When this pin is pulled low. transmitted.
the circuit is reset and ready for operation.
SEND (Send; Pin 30) - This pin accepts the send
ADDRESS {AO-A6; Pin 4. 5. 6. 7. 8. 9. 101 - These command after receipt of an address.
are the address setting pins whieh contain the address
match for the received signal. VALID ADDRESS PULSE (VAP; Pin 31) - This is the
output for the valid address pulse upon receipt of a
INPUT DATA (100-107; Pins 11. 12. 13. 14. 15. 16.
17. 18) - These pins contain the input data for the
first eight bits of data to be transmitted.
matched incoming address.
COMMAND STROBE (CS; Pin 32) - This is the output

for the command strobe signifying a valid set of com-
B
RECEIVEINPUT (RI; Pin 191 - This is the receive input mand data on pins 33-39.
pin.
COMMAND WORD (CO-C6; Pins 33. 34. 35. 36. 37.
NEGATIVE POWER SUPPLY (VSS; Pin 20) - This pin 38. 391 - These pins are the readout of the command
is the negative power supply connection. Normally this word which is the second word of the received signal.
pin is system ground.
POSITIVE POWER SUPPLY (Voo; Pin 401 - This pin is
TRANSMIT REGISTER OUTPUT SIGNAL (TRO; Pin the package positive power supply pin.
21) - This pin transmits the outgoing signal. Note
that it is inverted from the incoming signal. It must go
through one stage of inversion if it is to drive another
MC14469.
The receipt of a start bit on the Receive Input (R1) A positive transition on the Send input initiates the
line causes the receive clock to start at a frequency transmit sequence. Send must occur within 7 bit times
equal to that of the oscillator divided by 64. All receiv- of CS. Again the transmitted data is made up of two
ed data is strobed in at the center of a receive clock eleven-bit words, i.e .• address and command words.
period. The start bit is followed by eight data bits. The data portion of the first word is made up from in-
Seven of the bits are compared against states of the put Oata inputs (100-107). and the data for the se-
address of the particular circuit (AO-A61. Address is cond word from Second Input Oata (SO-57) inputs.
latched 31 clock cycles after the end of the start bit of The data on inputs 100-107 is latched one clock
the incoming address. The eighth bit signifies an ad- before the falling edge of the start bit. The data on in-
dress word "1" or a command word "0". Next. a puts SO-S7 is latched on the rising edge of the start
parity bit is received and checked by the internal logic bit. The transmitted signal is the inversion of the
for even parity. Finally a stop bit is received. At the received signal. which allows the use of an inverting
completion of the cycle if the address compared. a amplifier to drive the lines. TRO begins either 1/2 or
Valid Address Pulse (VAP) occurs. immediately follow- 11/2 bit times after Send. depending where Send oc-
ing the address word. a command word is received. It curs.
also contains a start bit. eight data bits. even parity bit The oscillator can be crystal controlled or ceramic
and a stop bit. The eight data bits are composed of a resonator controlled for required accuracy. Pin 1 may
seven-bit command, and a "0" which indicates a be driven from an external oscillator. See Figure 1.
command word. At the end of the command word a
Command Strobe Pulse (CS) occurs.
MC14469
Internal
Oscillator
Note: For externally

generated clock,
drive Pin 1, float Pin 2.
Note: Ceramic Resonators

307.2 kHz ± 1 kHz for 4800 Baud Rate
C1 - Cl ~ 50 pF
C2 - C2 == 200 pF
(Ceramic Resonator Suppliers:
Radio Materials Company, ChiCi:go, Illinois
Vernitron Piezoelectric Division, Bedford, Ohio)
CO
Channel
C1
Select
C2
Select
Channel,
C5
Start
Conversion
End
Send
Conversion Analog
Inputs
SO
51
52
53 Digital
54 Outputs
55
56
57
8·Channel
AID Converter
Assembly
AO,100 A1. t01
A1,101 A2, t02
A2,ID2 A3,103
A3,103 A4,104
A4, t04 CS A5.ID5 CS
A5,105 A6, t06
A6, 106 Send
Note: For Simplex operation the 107 must be tied high. S7 must be
tied low and the 77bit 10 must be set to some unused address
to prevent erroneous responses.
AI TRO
VDD
VSS
MC14469
Address
0
000000
AO Address Al
A' COOOOf A2
A2 A3
A3 A4
A4 VAP A5 VAP
AS A6
A6 Send
@MOTOROLA
The MCl4490 is constructed with complementary MOS enhance- CMOS LSI

ILOW-POWER COMPLEMENTARY MOS)
ment mode devices, and is used for the elimination of extraneous level
changes that result when interfacing with mechanical contacts. The
HEX CONTACT
digital contact bounce eliminator circuit takes an input signal from a
bouncing contact and generates a clean digital signal four clock periods BOUNCE ELIMINATOR
after the input has stabilized. The bounce eliminator circuit will remove
bounce on both the "make" and the "break" of a contact closure. The
clock for operation of the MCl4490 is derived from an internal R-C
oscillator which requires only an external capacitor to adjust for the
desired operating frequency Ibounce delay), The clock may also be
driven from an external clock source or the oscillator of another
L SUFFIX
MCl4490.
CERAMIC PACKAGE
CASE 620
• Noise Immunity=45% of VDD Typical
• Six Debouncers Per Package
• Internal Pullups on All Data Inputs
• Can Be Used as a Digital Integrator, System Synchronizer, or Delay
P SUFFIX
Line
PLASTIC PACKAGE
• Internal Oscillator IR-CI, or External Clock Source CASE 648
• TTL Compatible Data Inputs/Outputs

• Single Line Input, Debounces Both "Make" and "Break" Contacts
• Does Not Require "Form C" ISingle Pole Double Throwl Input
Signal
• Cascadable for Longer Time Delays
Denotes
• Schmill Trigger on Clock Input (Pin 7)
CeramIc Package
• Supply Voltage Range= 3.0 V to 18 V Plastic Package
Voo = Pin 16
Vss '= Pin 8
~1~ ~~
P-----o 2
Bout
~1 ! ~t
f----o 13 Cout
t 4'2t
~1
f---o4 °out
~1 ! ~2 !
P-----o 11
Eout
~lt ~2!
Fout
~6
DS9ll43
PIN ASSIGNMENT
Raling Symbol Value Unit
16
OC Supply Voltage VOO 0.5 to + 18 V
2 15
-0.510
Inpul Voltage. All Inputs V,n V
VOO+0.5 3 14
DC Current Dratn per Input PIn I 10 mA 4 13

Operating Temperature Range MC14490L -55 to +125 5 12
TA °C
MC14490P -40 to +85
6 11
10
8 9
Characteristic Symbol
Voo Tlow
. 25°C Thigh'
Unit
Vdc Min Max Min Typ Max Min Max
Output VOltage "0" Level 5.0 - 0.05 - 0 0.05 - 0.05
V,n=VOO or 0 VOL 10 - 005 - 0 005 - 0.05 V
15 - 005 - 0 005 - 0.05
"1" Level 5.0 4.95 - 4.95 5.0 - 495 -
V,n=O or VOO VOH 10 995 - 995 10 - 9.95 - V
15 14.95 - 14.95 15 - 14.95 -
Input Voltage I "0" Level
(VO=4.5 or 0.5 VI 5.0 - 1.5 - 2.25 1.5 - 1.5
VIL V
1VO=9.0 or 1.0 VI 10 - 3.0 - 4.50 30 - 3.0
1VO= 13.5 or 1.5 VI 15 - 4.0 - 6.75 4.0 - 4.0
"1" Level
1VO = 0.5 or 4.5 VI
VIH
5.0 3.5 - 3.5 2.75 - 35 - V
1VO= 1.0 or 9.0 VI 10 7.0 - 7.0 550 - 7.0 -
1VO= 1.5 or 13.5 VI 15 11.0 - 11.0 8.25 - 11.0 -
Output Drive Current
Source
OscIllator Output
1VOH=2.5 VI 5.0 -0.6 - -0.5 - 1.5 - -04 -
1VOH=4.6 VI 5.0 -0.12 - -0.1 -03 - -0.08 -
1VOH=9.5 VI 10 -0.2 - -0.2e -0.8 - -0.16 -
IOH -1.4 -1.2 -1.0 mA
1VOH = 13.5 VI 15 - -3.0 - -
Debounce Outputs
1VOH= 2.5 VI 5.0 -09 - -0.75 -2.2 - -0.6 -
1VOH =4.6 VI 50 -0.19 - -0.16 -O.4t - -0.12 -
1VOH =9.5 VI 10 -OOC - -050 - 1.2 - -0.4 -
1VOH = 13.5 VI 15 -1.8 - -1.5 -4.5 - - 1.2 -
Sink
Oscillator Output
1VOL = 0.4 VI 5.0 036 - 0.30 0.9 - 024 -
1VOL =0.5 VI 10 0.9 - 0.75 2.3 - 0.6 -
1VOL = 1.5 VI IOL 15 4.2 - 3.5 10 - 28 - mA
Debounce Outputs
1VOL =0.4 VI 50 2.6 - 2.2 4.0 - 1.8 -
(VOL =0.5 VI 10 4.0 - 3.3 9 - 2.7 -
(VOL=I.5VI 15 12 - 10 35 - 6.4 -
Input Current
Oebounce Inpuls IVIH = VOOI
IIH 15 - 2 - 0.2 2 - II ~A
Input Current Oscillator - Pin 7 I,n 15 - ±620 - ±255 ±4OO - ±25O ~A

Pullup ReSistor Source Current 5.0 210 375 140 190 255 70 130
Oebounce Inputs IlL 10 415 740 280 380 500 145 265 ~A
IVIL = VSSI 15 610 1100 415 570 750 215 400
Input Capacitance IVm-Ol em - - - - 5.0 7.5 - - pF
Quiescent Current 5.0 - 150 - 40 100 - 90
100 10 - 280 - 90 225 - 180 ~A
15 - 840 - 225 650 - 550
INoise Immunity specified tor worst case combination. ·Tlow= -55°C for L Device. _40 C for P Device.
0
NOIse margin lor both "1" and "0" level = 1.0 V min @ VOO=5.0 V Thigh = + 125°C for L Device. + 85°C for P DeVice.
2.0 V In,n @ VOO= 10 V
2.5 V m,n @ VOO= 15 V
Symbol VDD Min Typ Max Unit
Characteristic
Vdc
Output Rise Time \ 5.0 - 180 360
All Outputs tTLH 10 - 90 180 ns
15 - 65 130
Output Fall TIme
OscIllator Output 5.0 - 100 200
10 - 50 100
tTHL 15 - 40 80 ns
Debounce Outputs 50 - 50 120
10 - 30 50
15 - 20 40
Propagation Delay Time tpHL
Oscillator Input to Debounce Outputs 5.0 - 285 570
10 - 120 240
15 - 95 190 ns
tpLH 50 - 370 740
10 - 150 320
15 - 120 240
Clock Frequency 150% Duty Cycle} 50 - 2.8 1.4
1External Clockl fCI 10 - 6 3.0 MHz
15 - 9 4.5
Setup TIme (See FIgure 1) 50 100 50 -
tsu 10 80 40 - ns
f 15 60 30 -
Maximum External Clock Input 50
Rise and Fall Time tr, If 10 No Limit ns
Oscillator Input 15
Oscillator Frequency fosc_ typ 1.5
5.0
OSCout Ce" IIn ~FI
Ce" = 500 pF to 0.1 ~F 4.5
10 ----
C Iin ~F)
Hz
ext
6.5
15
Cext I,n ~FI
1000
~ 900
~
z 800
PLASTIC OR CERAMIC
PACKAGE
"
o
~ 700
iiij. I'.
~3\8
600
o~
a: u 500
~~ "'-
90%
10%
50%
If
~~
~
"
400
300
"'"
~
"
~
200
100 ""
o
2S
"
The MC14490 Hex Contact Bounce Eliminator is After some time period of N clock periods, the contact
basically a digital integrator. The circuit can integrate is opened and at N+7 a 1 is loaded into the first bit. Just
both up and down. This enables the circuit to eliminate after N+7, when the input bounces low, all bits are reset
bounce on both the leading and trailing edgesof the signal, to O. At N+8 nothing happens because the input and
shown in the timing diagram of Figure 3. output are low and all bits of the shift register are O. At
Each of the six Bounce Elim inators is composed of a time N+9 and thereafter the input signal is a high (1) clean
4Y,·bit register (the integrator) and logic to compare the signal. At N+13 the output goes high (1) as a result of
input with the contents of the shift register, as shown in four l's being shifted into the shift register.
Figure 4. The shift register requires a series of timing Assuming the input signal is long enough to be clocked
pulses in order to shift the input signal into each shift through the Bounce Eliminator, the output signal will be
register location. These timing pulses (the clock signal) no longer or shorter than the clean input signal plus or
II
are represented in the upper waveform of Figure 3. Each minus one clock period.
of the six Bounce Eliminator circuits has an internal The amount of time distortion between the input and
resistor as shown in Figure 4. A pullup resistor was incor- output signals is a function of the difference in bounce
porated rather than a pulldown resistor in order to imple· characteristics on the edges of the input signal and the
ment switched ground input signals, such as those coming clock frequency. Since most relay contacts have more
from relay contacts and push buttons. By switching bounce when making ascompared to breaking, the overall
ground, rather than a power supply lead, system faults delay, counting bounce period, will be greater on the
(such as shorts to ground on the signal input lead,; will leading edge of the input signal than on the trailing edge.
not cause excessive currents in the wiring and contacts. Thus, the output signal will be shorter than the input
Signal lead shorts to ground are much more probable than signal - if you include the leading edge bounce in the
shorts to a power supply lead. overall timing calculation.
When the relay contact is open the shift register is The only requirement on the clock frequency in order
loaded with a 1 (positive logic assumed) on each positive to obtain a bounce free output signal is that four clock
edge of the clock signal. To understand the operation, we periods do not occur while the input signal is in a false
assume all bits of the shift register are loaded with l's and state. Referring to Figure 3, a false state is seen to occur
the output is at a 1 or high level. three times at the beginning of the input signal. The input
At clock edge 1 (Figure 3) the input has gone low signal goes low three times before it finally settles down
and a 0 (low level) has been loaded into the first bit or to a valid low state. The first three low pulses are referred
storage location of the shift register. Just after the posi· to as false states.
tive edge of clock 1 the input signal has bounced back to If the user has an available clock signal of the proper
a logic 1. This causes the shift register to be reset to all frequency, it may beused by connecting it to the oscillator
l's in all four bits - thus starting the timing sequence input (pin 7). However, if an external clock is not available
over again. the user can place a small capacitor across the oscillator
During clock edges 3 to 6 the input signal has stayed input and output pins in order to start up an internal
low. Thus a logic 0 has been shifted into all four shift clock source (as shown in Figure 4). The clock signal at
register bits and, as shown, the output goes to a 0 during the oscillator output pin may then be used to clock other
the positive edge of clock pulse 6. MC14490 80unce Eliminator packages.With the use of the
It should be noted that there is a 3Y, to 4Y, clock MC14490, a large number of signals can be cleaned up,
period delay between the clean input signal and output with the requirement of only one small capacitor external
signal. In this example there is a delay of 3.8 clock periods to the Hex Bounce Eliminator packages.
from the beginning of the clean input signal.
ul
l1I1flJl p-nIUU1J
(
ut I "
"
Cont8C t C lased Contact Open
t
II
The single most important characteristic of the MCl4490 is paralleled standard gates or by the MCl4049 or MCl4050
that it works with a single signal lead as an input, making it buffers.
directly compatible with mechanical contacts I Form A and The clock input circuit (pin 7) has Schmitt trigger shaping
Bl. such that proper clocking will occur even with very slow
The circuit has a built in pullup resistor on each input. The clock edges, eliminating any need for clock preshaping. In
worst case value of the pullup resistor (determined from the addition, other MCl4490 oscillator inputs can be driven from
Electrical Characteristics tablel is used to calculate the con- a single oscillator output buffered by an MCl4050 (see
tact wetting current. If more contact current is required, an Figure 5l. Up to six MCl4490s may be driven by a single buf-
external resistor may be connected between VOO and the in- fer.
put. The MC14490 is TTL compatible on both the inputs and
Because of the built-in pull up resistors, the inputs can- the outputs. When VOO is at 4.5 V, the buffered outputs can
not be driven with a single standard CMOS gate when VOO sink 1.6 mA at 0.4 V. The inputs can be driven with TTL as a
is below 5 V. At this voltage, the input should be driven with result of the internal input pullup resistors.
In applications where different leading and trailing As shown in Figure 8, the Bounce Eliminator circuits
edge delays are required (such asa fast attack/slow release can be connected in series. In this configuration each
timer.) Clocks of different frequencies can be gated into output is delayed by four clock periods relative to its
the MC14490 as shown in Figure 6. In order to produce a respective input. This configuration may be used to gener-
slow attack/fast release circuit leads A and B should be ate multiple timing signals such as a delay line, for
interchanged. The clock out lead can then be used to programming other timing operations.
feed clock signals to the other MC14490 packages where One application of the above is shown in Figure 9,
the asymmetrical input/output timing is required. where it is required to have a single pulse output for a
single operation (make) of the push button or relay contact.
This only requires the series connection of two Bounce
Eliminator circuits, one inverter, and one NOR gate in
order to generate the signal AB as shown in Figures 9 and
10. The signal AB IS four clock periods in length. If the in-
verter is switched to the A output, the pulse AS will be
EJ
generated upon releaseor break of the contact. With the use
of a few additional parts many different pulses and
waveshapes may be generated.
The contents of the Bounce Eliminator can be latched

by using several extra gates as shown in Figure 7. If the
latch lead is high the clock will be stopped when the
output goes low. This will hold the output low even
though the input has returned to the high state. Any time
the clock is stopped the outputs will be representative of
the input signal four clock periods earlier.
7 1 9
050;" ~o5Oout
Clock
II
Input'lnn d' fU1J
A
el)
B
«)
C
"'I I
c'<)
D
e<)
II
C<
AB «
AS lI:
® MOTOROLA MC14493
MC14494
MC14495
BINARY-TO-SEVEN SEGMENT
LATCH/DECODER/DRIVERS
EJ
BINARY-TO-SEVEN SEGMENT
The MC14493, MC14494 and MC14495 are all constructed with LATCH/DECODER/DRIVERS
CMOS enhancement mode devices and NPN bipolar output drivers
on a single monolithic structure. Internal series resistors of typically
290 ohms allow the parts to interface directly with seven segment
common cathode LED displays at 5 volt supply.
Applications include MPU systems, TV displays and general purpose
displays.
• MC 14493 - binary plus one decoding for 1'h-digits
• MC 14494 - binary decoding for 1'h-digits
• MC 14495 - binary to hexadecimal decoding
L SUFFIX P SUFFIX
• VCR output activated when 1 6 or F is displayed CE RAMie PACKAGE PLASTIC PACKAGE
• High-current sourcing outputs with internal limiting resistance cAse 620 CASE 648
• Internal input level shift

• Supply voltage range 4.5 to 18 Vdc T Suffix Denote.
C L Cer.mic Peck.ge
P Pl.'tic Pack-ve
ADDRESS
DECODER
AND
SEGMENT
ARRAY
---T .-----T--~
Rating Symbol
--_._. __ __ ._----
Value
.
-----
OC Supply Voltage VOO -0.5 V to +18 Vdc
Input Voltage, all Inputs VIN -0.5 V to VOO + 0.5 Vdc
DC Current Drain per Input t 10 mA
Dissipation per Output Driver POH mW

Pins I, 2, 3,12,13,14,15 50
Pin 4 100
II Operating Temperature
Storage Temperature
Range
Range
TA
Tstg
o to +70
-65 to +150
·C
·C
strained to the range VSS ~ (Vin or Vout) ,;;;VOO'
Ch.racteristics Symbol Min. Max. Unit
OC Supply Voltage VOO 4.5 16 V
Input Voltage VIL 0.8 V
(VOO = 15 V) VIH 4 V
(VOO = 5 VI 3.5
Input Current IIN ±1 I'A
VCR, Output. open drain (VOH = VOO) IOH ±1 I'A
(VOL = 0.5 V. Voo = 5 V) IOL 0.2 mA

(VOL = 0.5 V. VOO = 15 V) 1
Outputs a.b.c,d.e.f.Q (VOH = 2.0 V. VOO = 5 VI IOH -6.0 mA

(VOH = 1.5 V. VOO = 5 V) -14.0
(VOH = 12 V, VOO = 15 V) -6.0
(VOH = 11.5 V. VOO = 15 VI -14.0
(VOL = 1 V. VOO = 5 V) IOL 0.1 mA

(VOL = 1 V, VOO = 15 V) 0.5
Output h + i (VOH = 2 V. VOO = 5 V) tOH -12.0 mA

(VOH = 1.5 V. VOO = 15 V) -28.0
(VOH = 12 V, VOO = 15 V) -12.0
(VOH = 11.5 V. VOO = 15 V) -28.0
(VOL = 1 V. VOO = 5 V) tOL 0.2 mA

(VOL = 1 V, VOO = 15 vI 1.0
VDD
Characteristic Symbol Vdc Min Typ Ma. Unit
Propagation Delay Times TpLH 5.0 - 1.20 2.50

10 - 0.45 0.90 llS
15 - 0.27 0.55
TpHL 5.0 - 750 1500

10 - 235 470 llS
15 - 135 270
Output Rise Time TTLH 5.0 - 500 1000
B
10 - 345 700 ns
15 - 250 500
Output Fall Time TTHL 5.0 - 130 260

10 - 40 80 ns
15 - 27 55
Clock Pulse Width tWH 5.0 2.4 1.2 -

10 0.70 0.35 -
15 0.55 0.27 -
SEGMENT DRIVER (a, b, c, d, e, f, g, h, i; Pins 1,2,3,

4,12,13,14,15).
The block diagram is shown on page 1. The inputs A. B.
The segment drivers are emitter·follower NPN·tran· C and D are fed to a 4·bit latch which is controlled by
sistors. To limit the output current, a resistor typically clock (CLl. Two modes of operation are available.
290 ohms is integrated internally at each output. There·
fore, external resistors are not necessary when driving an
LED at the supply voltage of VDD = 5.0 volts.
The data on the inputs A. B. C aNd D will pass through
the latch and wi II be displayed immediately when the
clock is low. In this mode of operation the circuit is
performing the function of a conventional decoder/driver.
This output is activated (goes to low) whenever the The data may be loaded into the latch when CL = low
address corresponding to program 16 is selected. Other· and will be latched with the rising edge of CL. The data
wise the output is open. See the truth table. will remain stored as long as CL is high.
14493 TRUTH TABLE 14494 TRUTH TABLE
A B C D a b c d e f 9 h+i VCR Display A B C D • b c d e f 9 h+i VCR Display
0 0 0 0 0 1 1 0 0 0 0 0 Open 1 0 0 0 0 1 0 1 1 1 1 1 1 0 16
1 0 0 0 1 1 0 1 1 0 1 0 Open 2 1 0 0 0 0 1 1 0 0 0 0 0 Open 1
0 1 0 0 1 1 1 1 0 0 1 0 Open 3 0 1 0 0 1 1 0 1 1 0 1 0 Open 2
1 1 0 0 0 1 1 0 0 1 1 0 Open 4 1 1 0 0 1 1 1 1 0 0 1 0 Open 3
0 0 1 0 1 0 1 1 0 1 1 0 Open 5 0 0 1 0 0 1 1 0 0 1 1 0 Open 4
1 0 1 0 1 0 1 1 1 1 1 0 Open 6 1 0 1 0 1 0 1 1 0 1 1 0 Open 5
0 1 1 0 1 1 1 0 0 0 0 0 Open 7 0 1 1 0 1 0 1 1 1 1 1 0 Open 6
1 1 1 0 1 1 1 1 1 1 1 0 Open 8 1 1 1 0 1 1 1 0 0 0 0 0 Open 7
0 0 0 1 1 1 1 1 0 1 1 0 Open 9 0 0 0 1 1 1 1 1 1 1 1 0 Open 8
1 0 0 1 1 1 1 1 1 1 0 1 Open 10 1 0 0 1 1 1 1 1 0 1 1 0 Open 9
0 1 0 1 0 1 1 0 0 0 0 1 Open 11 0 1 0 1 1 1 1 1 1 1 0 1 Open 10
1 1 0 1 1 1 0 1 1 0 1 1 Open 12 1 1 0 1 0 1 1 0 0 0 0 1 Open 11
0 0 1 1 1 1 1 1 0 0 1 1 Open 13 0 0 1 1 1 1 0 1 1 0 1 1 Open 12
1 0 1 1 0 1 1 0 0 1 1 1 Open 14 1 0 1 1 1 1 1 1 0 0 1 1 Open 13
0 1 1 1 1 0 1 1 0 1 1 1 Open 15 0 1 1 1 0 1 1 0 0 1 1 1 Open 14
1 1 1 1 1 0 1 1 1 1 1 1 0 16 1 1 1 1 1 0 1 1 0 1 1 1 Open 15
INPUTS OUTPUTS
, ,, ,,, ,, ,, ,
D C B A a b c d e f 9 h+i VCR DISPLAY
0
0
0
0
0
0
0
0 0
1
0
1
0
0
0 0
0 Open
Open ,
0
0 0
, ,,
1 0 0
, 0 1 0 Open 2
0
0
0
,
1
1
,
0 0, ,
1
0 ,
, ,
,
1
0
0
0
0 0
0
Open
Open
3
4
0
0 1
0 1
1 0 1
0
0,,,1
1
1
1
0 0
0
Open
Open
5
6
, , , , ,, 7 ALPHANUMERIC DISPLAY
,, ,, ,,,
0 1 1 1 1 1 1 0 0 0 0 0 Open
,
,, , ,,
0
0
0
0
0 1
, , 0 1
0
0
Open
Open
B
9 ma::fl'-:l5I~
0 0 1
, ,,,,,
0 1 1 1 Open A 0123456789101112131415
,, ,
0 1 0
,,,0
,, Open b
, ,, ,, ,,, ,,
1 0 0 0 0 1 1 0 1 Open C
1
, ,,1
0
0
0
1
, 0 0
1 0 1 Open
Open
d
E
1 1 1 0 0 0 0 F
.§.·8 8" c
b
® MOTOROLA
HEXADECIMAL-TO-SEVEN SEGMENT LATCH/

DECODER/ DRIVER HEXADECIMAL·TO·SEVEN SEGMENT
LATCH/DECODERIDRIVER
The MCl4495-1 hexadecimal-to-seven segment latch/decoder/driver

is constructed with CMOS enhancement-mode devices and NPN
bipolar output drivers in a single monolithic structure. The circuit pro-
vides the functions of a 4-bit storage latch. With a 5-volt power supply,
it can be used without resistor interface to drive seven segment LED
displays. The series output resistors of, typically, 290 ohms are internal
to the device.
Applications include MPU systems display driver, instrument display
driver, computer/calculator display driver, cockpit display driver, and L SUFFIX P SUFFIX
various clock, watch, and timer uses. CERAMIC PACKAGE PLASTIC PACKAGE
• Low Logic-Circuit Power Dissipation CASE 620 CASE 648
• High Current-Sourcing Outputs With Internal Limiting Resistors

• Latch Storage of Code
• Supply Voltage Range~ 4.5 V to 18 V MC14XXX Suffix Denotes
• CMOS Input Switching Levels ~ L 1 Ceramic Package

Pl Plastic Package
11 e -VDD 16
---'0
21 f d 15
c 14
a
31 9
41 h+ j b 13 "g
51 A a 12 ·f Ie
61 B VCR 11 d
7 LE D 10
B VSS C 9
ALPHANUMERIC DISPLAY
,_,.-. ':' :',.'C

" .. ' '.'
c
'.1
-,ooe.,_
• '-' _, , , 1.1
,-
'.
.ere]
C". I'
0 1 2 3 4 5 6 7 8 9 101112131415
INPUTS OUTPUTS
D C B A a b e d 0 f 9 h+i VCR DISPLAY
0 0 0 0 1 1 1 1 1 1 0 0 Open 0
0 0 0 1 0 1 1 0 0 0 0 0 Cpon 1
0 0 1 0 1 1 0 1 1 0 1 0 Open 2
0 0 1 1 1 1 1 1 0 0 1 0 Open 3
0 1 0 0 0 1 1 0 0 1 1 0 Open 4
0 1 0 1 1 0 1 1 0 1 1 0 Open 5
0 1 1 0 1 0 1 1 1 1 1 0 Open 6
0 1 1 1 1 1 1 0 0 0 0 0 Open 7
1 0 0 0 1 1 1 1 1 1 1 0 Open 8
1 0 0 1 1 1 1 1 0 1 1 0 Open 9
1 0 1 0 1 1 1 0 1 1 1 1 Open A
1 0 1 1 0 0 1 1 1 1 1 1 Open b
1 1 0 0 1 0 0 1 1 1 0 1 Open C
1 1 0 1 0 1 1 1 1 0 1 1 Open d
1
1 ,
1 1
1
0
1
1
1
0
0 0
0 1
0
1
1
1
1
1
1
1
1
Open
0
E
F
Rating Symbol Value Unit This device contains circuitry to protect the
DC Supply Voltage VDD -0.5 to+ 18 V inputs against damage due to high static
vOltages or electric fields; however, it is ad-
Input Voltage, All Inputs Vin -0.5 to VDD + 0.5 V
vIsed that normal precautions be taken to
DC Current Drain per Input Pin I 10 mA avoid application of any voltage higher than
Operating Temperature Range TA -40 to+85 'C maximum rated voltages to this high in~
pedance circuit. For proper operation it is
Storage Temperature Range T sto -65 to+ 150 'C
recommended that Vin and Vout be con-
Maximum Continuous Output Power POHmax* mW strained to the range VSS ~ IV in or Vout)
(Source) per Output @ 25°C .;; VDD·
Pins 1, 2, 3, 12, 13, 14, 15 50
Pin 4 100
, 25'C Thigh'
VDD Tlow
Characteristic Symbol V Min Max Min Typ Max Min Max Unit
Output Voltage - Segments VOL 5 - 0.1 - 0 005 - 005 V
Vin= VDD or VSS 10 - 0.1 - 0 0.05 - 0.05
15 - 0.1 - 0 0.05 - 005
VOH 5 4.1 - 4.1 4.65 - 4.1 - V

V,n = VSS or VDD 10 9.1 - 91 96 - 9.1 -
15 14.1 - 14.1 14.5 - 14.1 -
Input Voltage VIL V
1VO=3.8 or 0.5 VI 5 - 1.5 - 2.25 1.5 - 1.5
1VO=8.8 or 1.0 VI 10 - 3.0 - 450 3.0 - 30
IVO~ 13.8 or 1.5 VI 15 - 4.0 - 600 4.0 - 4.0
IVO~0.5 or 3.8VI VIH 5 3.5 - 35 2.75 - 3.5 - V

1VO= 1.0 or 8.8 VI 10 7.0 - 7.0 5.50 - 7.0 -
1VO= 1.5 or 138 VI 15 11.0 - 11.0 825 - 11.0 -
Output Dnve Voltage - Segments, VOH V
h+ I - L device 5
IIOH~ OmAI 40 - 4.0 4.8 - 4.0 -
1I0H= 5mAI 2.45 - 2.4 3.0 - 205 -
IIOH = 10 mAl 1.3 - 0.8 1.8 - - -
IIOH= o mAl 10 90 - 90 98 - 90 - V
IIOH~ 5 mAl 7.4 - 7.2 8.1 - 6.9 -
1I0H= 10 mAl 6.4 - 58 68 - 50 -
IIOH= 15 mAl 53 - 44 5.4 - 3.05 -
IlnH= OmAI 15 140 - 140 14.8 - 14.0 - V

1I0H= 5 mAl 12.2 - 12.0 13.1 - 11.7 -
IIOH~ 10 mAl 10.9 - 10.4 11.8 - 9.6 -
IIOH = 15 mAl 9.7 - 8.8 10.5 - 7.45 -
IIOH=20 mAl 85 - 7.2 90 - 5.25 -
IIOH=25 mAl 7.4 - 5.6 7.4 - 3.0 -
Output Dnve Voltage - Segments, VOH V
h+ i - P deVIce
1I0H= o
mAl 5 4.0 - 4.0 4.8 - 4.0 -
IIOH= 5mAI 2.45 - 2.4 3.0 - 205 -
1I0H~10 mAl 1.3 - 0.8 1.6 - - -
1I0H~ o mAl 10 9.0 - 9.0 9.8 - 90 - V

1I0H= 5 mAl 7.4 - 7.2 8.0 - 69 -
IIOH= 10 mAl 6.4 - 5.8 6.6 - 5.0 -
IIOH~ 15 mAl 5.3 - 4.4 5.2 - 305 -
1I0H= OmAI 15 14.0 - 14.0 14.8 - 14.0 - V

1I0H= 5mAI 12.2 - 12.0 130 - 11.7 -
1I0H= 10 mAl 10.9 - 10.4 11.6 - 9.6 -
1I0H= 15 mAl 9.7 - 88 10.2 - 7.45 -
1I0H~20 mAl 8.5 - 72 86 - 5.25 -
1I0H~25 mAl 74 - 56 68 - 3.0 -
Voo -40°C 25'C 85°C
Characteristic Symbol V Min Max Min Typ Max Min Max Unit
Output Sink Current- VCR output- IOL mA
L devIce
(Val ~O 4 VI 5 - 03 1.00 - -
(Val ~ 0.5 VI 10 - - -
(Val ~ 1.5 VI 15 - 0.5 1.25 - -
Output SInk Current-VCR output- IOl mA
P device
(VOl=04 VI 5 - 03 1.00 - -
(Val =0.5 VI 10 - - -
1VOl = 1.5 VI 15 - 05 1.25 - -
Input Current (L Device)
Input Current IP DevIce)
Input Capacitance
(V,n=OI
lin
lin
C,n
15
15
-
-
-
-
;;0.1
±0.3
-
-
-
-
±O.OOOOl
±O.OOOOl
50
±0.1
±0.3
75
-
-
-
±
± 1.0
1.0
-
~A
~A
pF
II
QUiescent Current IL Devlcel 100 5 - 03 - 0.08 025 - 0.2 mA
(Per Packagel 10 - 1.5 - OAO 125 - 10
15 - 30 - 085 2.50 - 2.0
QUiescent Current IP Device) 100 5 - 03 - 008 025 - 02 mA
(Per Packagel 10 - 15 - OAO 1.25 - 1.0
15 - 3.0 - 0.85 2.50 - 2.0
Total Supply Current··t IT 5 IT = l1.g #A/kHzlf + 100 #A
(Dynamic plus OUiescent, 10 IT = 13.8 #A/kHzlf + 100
Per Packagel 15 IT= 157 ~A/kHzlf+ 100
(Cl ~ 50 pF on all outputs, all
buffers sWItching)
no calculate total supply current at loads other than 50 pF· IT1Cli ~ ITI50 pFI + 3.5 x 10- 3(Cl - 501 Vaal
where: IT IS In IlA (per package), CL In pF, VOO In Vdc. and f in kHz is input frequency.
·-The formulas given are for the typical characteristIcs only at 25°C.
VDD
Characteristic Symbol V Min Typ Max Unit
Output RIse Time, Segment Outputs l Figure 1l tTLH ns
5 - 210 450
10 - 145 300
15 - 90 200
Output Fall Time. Segment Outputs (Figure 11 tTHL
5 - 1.5 3.5 ~s
10 - 1.3 2.75
15 - 1.1 2.25
Output Fall Time. VCA Output tTHL ns
(Figures 3 and 41 5 - 105 250
10 - 40 100
15 - 30 75
Propagation Delay Time, A. B, C. 0 to Segment tpLH ns
Outputs (Figure 21 5 - 935 2400
10 - 340 900
15 - 230 500
tPHL 5 - 7.0 180 #s
10 - 35 90
15 - 2.0 5.0
Prop.agatlon Delay Time. A. B. C. D to VCR tPLZ #s
Output (Figures 3 and 41 5 - 110 250
10 - 80 200
15 - 40 100
tpZL 5 - BOO 1500 ns
10 - 400 1000
15 - 200 500
Propagation Delay Time. LE to Segment tPLH - ns
Outputs (Figure 5) 5 - 1300 3000
10 - 500 1500
15 - 350 1000
IpHL 5 - 16.0 300 #s
10 - 6.0 15.0
15 - 5.0 10.0
Propagation Delay Time. LE to VCR Output tpLZ #s
(Figures 4 and 61 5 - 14.0 30
10 - 80 20
15 - 60 15
tPZL 5 - 100 25 ~s
10 - 50 15
15 - 40 10
Setup Time. A. B. C. D to LE (Figure 71 tsu 5 100 35 - ns
10 65 25 -
15 65 25 -
Hold Time. LE to A. B. C. D (Figure 71 th 5 125 45 - ns
10 75 30 -
15 75 25 -
Latch Enable Pulse Width. LE (Figure 71 tWL 5 525 210 - ns
10 200 BO -
15 140 55 I -
SEGMENT DRIVER la, b, C, d, e, f, g, h + i; PINS 12, 13, 14, INPUT DATA lA, B, C, D; PINS 5, 6, 9, 10)
15,1,2,3,4) The block diagram is shown on page 1. The inputs A, B,
The segment drivers are emitter-follower NPN-transistors. C, and D are fed to a 4-bit latch which is controlled by the
To limit the output current, a resistor typically 290 ohms is in- Latch Enable input.
tegrated internally at each output. Therefore, external
resistors are not necessary when driving an LED at the sup- LATCH ENABLE ILE; PIN 7)
ply voltage of VDD = 5.0 volts. The data on inputs A, B, C and D will pass through the
latch and will be decoded immediately when LE IS low. In this
II
OUTPUT lVCR; PIN 11) mode of operation the circuit is performing the function of a
This output is activated (goes lowl whenever inputs A, conventional decoder/driver. The data may be loaded into
B, C, and D are all set to a logic one. Otherwise the output is the latch when LE= low and will be latched with the rising
open. See the truth table. edge of LE. The data will remain stored as long as LE is high.
A'B'C'D~p_~~r- _=-~~'r-
VCR Output ~ '-
____I
Output
Under
Test
I~PF
Figure 6 Figure 7
A,B,C,D
LE
/ A,B,C,D
---tISU . '. th=t-
~~. / },,,~ LE
B VCR
Output
IPL:k
10%
90%
"~l Common
Cathode
.",-
LED
Display
'JCR ~
A through F
(Open Drain)
Indicator
-=- LED
@MOTOROLA
The MC 14497 is a PCM remote control transmitter realised in

CMOS
CMOS technology. Using a dual·single (AM/FSK) frequency biphase
modulation the transmitter is designed to work with various PCM REMOTE CONTROL
receivers. TRANSMITTER
• 500kHz reference oscillator controlled by inexpensive ceramic

resonator
• Selectable Start-Bit polarity (AM only)
• Shifted key mode available P SUFFIX

PLASTIC PACKAGE
CASE 707
Input Voltage, All Inputs Vin -0.5 to VOO+0.5 Vdc
Operating Temperature Range TA o to of 70 ·C
Storage Temperature Range Tstg - 65 to +150 ·C
strained to the range VSS ,,; (Vin or Vout) ,;;;VOO'
Unused inputs must always be tied to an appropriate logic voltage level le.g. either VSS or VOO).
Characteristics Symbol Pin VOO Min Max Units

Vdc
Supply Voltage VOO 18 - 4.0 10.0 Vdc
Supply Current 'DO 18

Idle 10 - 50 ~A
Operation 10 - 5 mA
Output Current - Signal 8

VOH~3.0V Source IOH 4 -900 - ~A
VOL ~ 0.5V Sink IOL 4 120 -
Output Current - Scanner 4,5,
VOH=3.0V Source IOH 6,7 4 -30 - ~A
VOL = 0.5V Sink IOL 4 245 -
Output Current - Oscillator 13
VOH~3.0V Source IOH 4 -300 - ~A
VOL = 0.5V Sink IOL 4 245 -
Input Current - Oscillator lin 12
Operation 10 ±2 ±80 ~A
Idle, V1L ~ 0.5V 4 30 -
Input Current - Decoder lin 1,2,3,10 ~A
VIH=9V 11,14,15 10 -15 -
VIL = 0.5V 16,17 4 - -60
Input Voltage - Decoder 1,2,3,10

V1H 11. 14, 15 10 9 - Vdc
VIL 16,17 10 - 1.2
VIH 4 3 -
V1L 4 - 1.0
The transmitter emits a 6-bit, labelled AILSB) to FIMSBI. the same time, which causes bit-F to go high, that is to
binary code giving a total of 64 possible combinations or logical "I". By interconnecting only certain address inputs
code words. All of these are user selectable, except the It is possible to make an Intermediate keyboard with be-
last two - where channel 63 is not sent while channel 62 tween 32 and 64 keys.
is automatically sent by the transmitter at the end of each
transmissions as an "End of Transmission" code. The other two switches in figure 1, FK1 and FK2, change
the modulation mode, a closure changes the modulation
In either mode, AM or FSK, the transmitted signal ISin the from FSK to AM, and the start-bit polarity, a closure
form of a biphase pulse code modulation IPCMI signal. changes the start-bit to a logical "0", respectively.
The AM coding IS shown In figure 1 .
The full range of options available is illustrated In the table
below:
Start-bit Modulation bit-F Channels

E9 - open 1 FSK 0 0-31
~ E9-A1 tFKlI 1 AM 0 0-31
FSK 0 0-31·
'0'
-:
----i-J ~'1 L
E9 - A2
E9· A3
IFK21
IFK31
0
1 FSK 1 32 - 61
I I I E9· A1 • A2 0 AM 0 0-31
AM 'I I E9 - A1 • A3 1 AM 1 32 - 61
I I I
E9 - A2 • A3 0 FSK 1 32·61·
'1' --.Jf0 :,
'I L.i-.-
E9· A1 . A2 _ A 0 AM 1 32 - 61
Where f1 is a train of pulses at the modulating frequency One of the transmitter's major features is its low power
of 31.25 kHz for a reference frequency of 500 kHz. consumption - in the order of 1O~A in the idle state. For
this reason the battery is perpetually in Circuit. It has in
In the FSK mode two modulating frequencies are used as fact been found that a light discharge current is beneficial
shown in figure 3. to battery life.
In ItS active state the transmitter efficiency ISIncreased by

the use of a low duty cycle, less than 2.5% for the
modulating pulse trains.
While no key IS pressed the circUit is in its Idle state, the

reference oscillator ISstopped and the eight address input
lines are held high through internal pull-up resistors.
'0' --.J~ '2 I 'I L
I I I
I I , As soon as a key is pressed thiS takes the appropriate
I I I address line low, signalling to the CirCUit that a key has
been selected. The oscillator is now enabled. If the key is
'I' --.J~'1 I'2 L released before the code word has been sent the circuit
returns to its idle state. To account for accidental activa-
tion of the transmitter the circuit has a built-In reaction
Where f 1 is 50 kHz and f 2 is 41 .66 kHz for a reference time of some 20ms, which also overcomes contact
frequency of 500 kHz. bounce. After this delay the code word will be sent and
repeated at 90ms intervals for as long as the key is
The keyboard can be a simple switch matric using no ex- pressed. As soon as the key is released the cirCUit
ternal diodes, connected between the four scanner out- automatically sends channel 62, the "End of Transmis-
puts, A 1 to A4, and the eight row inputs, E1 to EB. Under sion" lEOTI code. The transmitter then returns to its idle
these conditions only the first 32 code words are state.
available, bit-F is always at logical "0" However, a sim-
ple two-pole, changeover switch, in the manner of a type- The differences between the two modulation modes are
writer "shift" key Iswitch FK3 in figure 1) can be used to illustrated in figure 5. However it should be noted that:
change the polarity of bit-F to give access to the next full
set of 32 instructions. In the AM mode each transmitted word is preceded by a
burst of pulses lasting 51 2~s. This is used to set up the
An alternative method of accessing more than 32 instruc- AGC loop in the receiver's preamp. In the FSK mode the
tions IS by the use of external diodes between the address first frequency of the first bit is extended by 1 .5ms and
inputs, see figure 4. These have the effect of producing the AGC burst is suppressed. In either mode it is assumed
"phantom" address Inputs by pulling two inputs low at that the normal start-bit is present.
Row Inputs El to E8 (Pins 1, 2, 10, 11, 14, 16& 17). If required the transmitter can be used as a keyboard en-
Under idle conditions these inputs are held high, by coder for direct use with a receiver. In this case the AM
internal pull-up resistors. As soon as a key is pressed a option is selected, the output inverted and fed directly to
logical "0" on that particular line signals to the circuit the receiver's signal input pin.
that a key has been selected. After a delay of 20ms the
internal register is loaded with the code word for the key
selected.
Row Input E9 IPin 31. This is a special programming

-<r' , ,
Vss
.
slllll~, VOD
"
."
--~11
input and when connected to the appropriate scanner , , , ,
II
output, via a diode, it will modify the transmitted output , , , ,
",
according to the table in the previous section. ,
,
, ,
, ,
,
, ." ",
In that table the figures in brackets, FK1 etc. refer to the
, , , , ...
switches shown in figures 1 and 4. If only one option is
..
required the diode may be omitted. The connections
shown in the table may be made in any combination.
,
,
,
, ,
, ,
, ,
,
,
,
...
-~1S
·
Although E9 is a row input forcing this line low will not , , , , ". MCIU'1
activate the circuit. , ,I, , ----!.!

...
u
-
, , , ,
Scanner Outputs A 1 to A4 (Pins 4, 5, 6 & 71. Under idle , , , ,
condition these outputs are held low, logical "0" When
, , , , ". ""
the circuit is activated, by a key being pressed, the
oscillator will start and release the outputs.
,
,
, ,
, ,
,
,
.. "
".
Oscillator (Pins 1 2 & 131. This is designed to operate .,
., ,
with a 500kHz ceramic resonator or a tuned LC circuit.
It is important that a ceramic resonator and noe a filter

.. ·· ,
., ,
is used here as the oscillator frequency can not be

guaranteed if a ceramic filter is used.
"~
{'"
~ '"c,rDi"
" "
Signal Out (Pin 8). This output provides the modulating

signal ready to drive the modulation amplifier.
T?-- -=f'
B
I 270p
Chennel Code word Keyboard Channel Code word Keyboard

F E 0 C B A In Out F E 0 C B A In Out
0 0 0 0 0 0 0 E8 A4 32 1 0 0 0 0 0 E8a A4
2
1 0
0
0
1
1
0
El
E2
A4
A4
33
34
0
0 ,
0 1
0
E1a
E2a
A4
A4
3 0 1 1 E3 A4 35 0 1 1 E3a A4
4 1 0 0 E4 A4 36 1 0 0 E4a A4
5 1 0 1 E5 A4 37 1 0 1 E5a A4
6 1 1 0 E6 A4 38 1 1 0 E6a A4
7 1 1 1 E7 A4 39 1 1 1 E7a A4
8 0 0 1 0 0 0 E8 A1 40 1 0 1 0 0 0 E8a A1
9 0 0 1 E1 A1 41 0 0 1 E1a A1
10 0 1 0 E2 A1 42 0 1 0 E2a A1
11 0 1 1 E3 A1 43 0 1 1 E3a A1
12 1 0 0 E4 A1 44 1 0 0 E4a A1
13 1 0 1 E5 A1 45 1 0 1 E5a A1
14
15
1
1
1
1 ,
0 E6
E7
A1
A1
46
47
1
1
1
1
0
1
E6a
E7a
A1
A1
16 0 1 0 0 0 0 E8 A3 48 1 1 0 0 0 0 E8a A3
17 0 0 1 E1 A3 49 0 0 1 E1a A3
18 0 1 0 E2 A3 50 0 1 0 E2a A3
19 0 1 1 E3 A3 51 0 1 1 E3a A3
20 1 0 0 E4 A3 52 1 0 0 E4a A3
21 1 0 1 E5 A3 53 1 0 1 E5a A3
22
23
1
1
1
1
0
1
E6
E7
A3
A3
54
55
1
1
1
1 ,
0 E6a
E7a
A3
A3
24 0 1 1 0 0 0 E8 A2 56 1 1 1 0 0 0 E8a A2
25 0 0 1 E1 A2 57 0 0 1 E1a A2
26 0 1 0 E2 A2 58 0 1 0 E2a A2
27 0 1 1 E3 A2 59 0 1 1 E3a A2
28 1 0 0 E4 A2 60 1 0 0 E4a A2
29 1 0 1 E5 A2 61 1 0 1 ESa A2
30 1 1 0 E6 A2 62 (EOT) 1 1 0 E6a A2
31 0 1 1 1 1 1 E7 A2 Not transmitted 1 1 1 1 1 1 E7a A2
NOTE: Although the 'a' suffIX applies to a 'phantom' input when
using a keyboard with up to 64 keys the coding for a shifted key.
up to 32 keys, model. with F K3 closed. is identical.
® MOTOROLA
CMOS
7-5EGMENT LED DISPLAY
II DECODER/DRIVER
,...
The Me 14499 is a 7-segment alphanumeric LED decoder/driver for
use in conjunction with microprocessor (MPU) systems. It is able to
drive directly 4 digit displays.
• High current segment drivers on-ehip

•
•
•
MPU compatible input levels
Very few external components
Wide Supply Voltage Range
required lrwnVV~~~ P SUFFIX
PLASTIC PACKAGE
CASE 707
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
DC Supply Voltage VOO -0.5 to+ 7.0 Vdc mum rated voltages to this high impedance
Input Voltage, all Inputs: -0.5 to VOO+ 0.5 Vdc circuit. For proper operation it is recom-
VIN
mended that Vin and Vout be constrained
Operating Temperature Range TA o to + 70 oC to the range VSS <; (Vin or Vout) :Iii; VOD'
Storage Temperature Range TSTG ~5to+ 150 oC
QO 250 700
Characteristic Pin Symb. Unit
Min. Max. Min. Typ. Max. Min. Max.
Input Voltage '0' level 5,12, Vil 0.3xVOO - 0.45xVOO 0.3xVOO 0.3xVOO Vdc
'1' level 13 VIH 0.7xVOO 0.7xVOO 0.55xVOO - 0.7xVOO Vdc
Input Current (VIN = 0 to VOO) IIN ±0.1 ±0.001 ±0.1 ±1.0 PoA
Oscillator Input Voltage '0' level 6 VllO 0.25xVoo - 0.3xVOO 0.25xVOO 0.2xVOO Vdc
'1' level VIHO 0.75xVOO 0.75xVOO 0.7xVOO - 0.8xVOO Vdc
Oscillator Input Current VOSC=O IIOl 100 30 50 80 10 PoA
VOSC=VOO IIOH -100 -30 -50 -80 -10 PoA
Segment Driver Voltage below VOD 1-4, VOO'

IOUT=5OmA 14,15, -VSOH 1.1 - 0.9 1.0 1.1 Vdc
IOUT=lOmA 16,17 0.8 - 0.7 0.75 0.8 Vdc
Segment Driver OFF Leakage IOFF
VOUT=O 100 - 1 50 100 PoA
Digit Drivers 7,8,

Source (On) VOUT=0.8 V 10,11 IOOH 6 5.5 8 - 4 mA
Sink (Off) VOUT=0.5V IDOL -0.2 -0.2 -2 - -0.1 mA
Quiescent Current 18
VIN = 0, lOUT = 0, COSC = 15 nF 1 - 0.5 1 1 mA
Maximum Power Dissipation 500 - - 500 500 mW
PIN ASSIGNMENT
Characteristic Fig. Symbol Min. Max. Unit
Clock High time 3 2 d VOD 18

tCH Po'
Clock Low time 3 tCl 2 Po' 2 17
Clock Rise time 3 tCR 2 Po' 3 b 16
Clock Fall time 3 tCF 2 Po'
4 9 15
Enable Lead time 3 tElead 200 n.
Enable Lag time 3 tElag 200 n. 5 Data DP 14
Data Set-up time 3 tOSup 200 n. 6 Osc Cl 13
Data Hold ti me 3 tOHold 1 Po' 7 IV EN 12
Scanner Frequency· 5 l/tScan 50 300 Hz
8 III I 11
Osc/Digit Lead time 5 too 10 Po'
Ose/Segment Lead time 5 9 VSS II 10
tos 10 p.S
Digit Overlap 5 tOY 5 Po'
The circuit accepts a 20-bit input, 16-bits for the four
digit display plus 4-bits for the decimal point - these
latter four-bits are optional.
The scanner frequency is determined by an on-chip oscill-
The input sequence is the decimal point code followed by ator, which requires an external frequency determining
the four digits, as shown in figure 2. capacitor. The capacitor voltage varies between two trigger
levels at the oscillator frequency.
In order to enter data the enable input, EN, must be low,
=> O. The sample and shift are accomplished on the falling An external oscillator signal can be used, within the
clock edge, see figure 3. Data are loaded from the shift recommended operating range of 200 to 800Hz - to
register to the latches when EN goes high, = 1. While the avoid flicker and digit overlap. For test purposes this
shift register is being loaded the previous data are stored frequency can be increased up to 10kHz.
in the latches.
A divide by four counter provides four non-over lapping
If the decimal point is used the system requires 20 clock scanner waveforms corresponding to the four digits -
pulses to load data, otherwise only 16 are required. see figure 5.
If a 1111 word is loaded into the decimal point latch, the The code used in this matrix decoders is shown in
output of the shift register is switched to the d,ecimal figure 6.
point driver, see figure 4. Therefore, to cascade n four digit
display drivers a set-up is used which will firstly load
the 1111 cascading word:
EN =0
2 Load 20-bits, the first four bits being 1, with 20
clock pulses.
The segment and decimal point drivers; these are NPN
3 EN = 1, to load the latch emitter followers with no current limiting devices.
4 Repeat steps 1 to 3 (n-1) times The digit output buffers; These are short circuit
protected CMOS devices.
5 (nX20)-bits can be loaded into n circuits, with 1111
as decimal point word to continue the cascading.
co co
~ ~ ~ ~
·en ·en ·en ·en
co co co co co co
'-'" '" -''"
:2 '" -''"
:2 '" -''"
:2
~I 0 0 0 0
Digit IV Digit III Digit II Digit I Decimal Point

02 ---~ O_N _
~--~---
DIGIT SEGM
DATA DP
CLOCK MC 14499
MC 14499
EN (1) ( 2)
'00 I/lose
OSC
'SCAN
DIGIT I
DIGIT n
DIGIT m
DIGIT nz
'oV
SEGMENT
OUTPUTS
FIGURE 6 - SEGMENT CODE
‫סס‬oo 1000 n
"
L' 0
0001
, I 1001
q
,-,
00'0
2 1010
1-'
,
0011 "') 1011
::' I
,,
0100
L: 1100 ,,
0101
,-::. 1101
I ,
0110
, L'
D 1110 d.sh
0111
I
, 1111 blank
SEGMENT
---!!'.
I .
OUTPUTS
(7)
IS
~ b
,
~
MC1.4GG
.
d
cf .,
1
ill
g
I
II
Illll
~ND
R1-'
II III
DIGIT
OUTPUTS
0 n
n 0
(')
,-1.#, _.#, U.#.
#'
V
••0,
'0
J..,0' J
..,0,
I V
•.•.
0.
I I
01 ·04: Be 338 or similar
R1 . R8: 36-82f!
C: 22 nF
VOO Typ: 5-6 V

IS max.: 40-50 mA
lomax.: 81S max.
® MOTOROLA
The MC14500B Industrial Control Unit (ICU) is a single bit

CMOS processor. The ICU is designed for use in systems requiring
decisions based on successive single bit information. An external
ROM stores the control program. With a program counter (and
output latches and input multiplexers. if required) the ICU in a
system forms a stored program controller that replaces combinatorial
logic. Applications include relay logic processing. serial data mani-
pulation and control. The ICU also may control an MPU or be
controlled by an MPU.
• 16 Instructions
• DC to 1.0 MHz Operation at VDD = 5 V L SUFFIX P SUFFIX
• On Chip Clock (Oscillator) CERAMIC PACKAGE PLASTIC PACKAGE
CASE 620 CASE 648
• Executes One Instruction per Clock Cycle
• 3 V to 18 V Operation
•
•
•
Noise Immunity Typically 45% of VDD
Quiescent Current 5.0 pAdc Typical at VDO = 5 V
Capable of Driving One Low·Power Schottky Load or Two Low·
""'"~'11SUft;X L
Oenot.,
C.ramic Package
P Plastic Package
Power TTL Loads over Full Temperature Range A Extended Opet'"ating
• For additional information. see application note AN-889 and Temperatur. Ran"
C Limited Operating
handbook H8-209
TemJM'ntur. Range
Oetailed operation and applications are given in the "MC14500B

Industrial Control Unit" handbook.
1 16
2 15
3 I.
• 13
12
'0 15
6 11
AA
8
11
5
INST
AEG
Jl. 12
!-OJ""P
7
8
10
a
'2
Jl. 11
!-OATN
13 • A 10
f-() Flea0
AST~
A~FleaF
Rating Symbol Value Unit static voltages or electric fields; however.
"DC Supply Voltage VDD -0.5 to +18 Vdc it is advised that normal precautions be
Input Voltage, All Inputs -{).5to VDD + 0.5 Vdc taken to avoid application of any voltage
Vin
higher than maximum rated voltages to
DC Current Drain per Pin I 10 mAdc this high impedance circuit. For proper
Operating Temperature Range - AL Device TA -55 to +125 °c operation it is recommended that V in and
CL/CP Device -40 to +85 Vout be constrained to the range Vss "
(Vin or Vout)" VDD.
Storage Temperature Range Tsty -65 to +150 °c
VDD Tlow
. 250C Thigh"
Characteristic Symbol Vdc Min Max Min 'Typ Max Min Max Unit
Output Voltage "0" level Val 5.0 - 0.05 - 0 0.05 - 0.05 Vdc
Vin - VDD orO 10 - 0.05 - 0 0.05 - 0.05
15 - 0.05 - 0 0.05 - 0.05
"I" level VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vde
Vin = 0 or VDD 10 9.95 - 9.95 10 - 9.95 -
15 14.95 - 14.95 15 - 14.95 -
Input Voltage # "0 level" Vll Vde
RST,D,X2
(Va = 4.5 or 0.5 Vdc) 5.0 - 1.5 - 2.25 1.5 - 1.5
(Va - 9.0 or 1.0 Vdc) 10 - 3.0 - 4.50 3.0 - 3.0
(Va' 13.50r 1.5 Vdc) 15 - 4.0 - 6.75 4.0 - 4.0
"'''level VIH Vde
(Va - 0.5 or 4.5 Vde) 5.0 3.5 - 3.5 2.75 - 3.5 -
(VA - 1.0 or 9.0 Vde) 10 7.0 - 7.0 5.50 - 7.0 -
(Va. 1.5 or 13.5 Vdc) 15 11.0 - 1'1.0 8.25 - 11.0 -
Input Voltage # "0" level Vll Vdc
10, II, 12, 13
(Va - 4.5 or 0.5 Vdc) 5.0 - 0.8 - 1.1 0.8 - 0.8
(Va = 9.0 or 1.0 Vde) 10 - 1.6 - 2.2 1.6 - 1.6
(Va -13.50r 1.5 Vde) 15 - 2.4 - 3.4 2.4 - 2.4
"1"level VIH Vdc
(Va -.0.5 or 4.5 Vdc) 5.0 2.0 - 2.0 1.9 - 2.0 -
(VA = 1.0 or 9.0 Vdc) 10 6.0 - 6.0 3.1 - 6.0 -
(Va· 1.5 or 13.5 Vdc) 15 10 - 10 4.3 - 10 -
Output Drive Current Source IOH mAde
Data, Write (Al/Cl/CP Device)
(VOH - 4.6 Vde) 5.0 1.2 - -1.0 -2.0 - -0.7 -
(VOH • 9.5 Vde) 10 3.6 - ·3.0 -6.0 - -2.1 -
(VOH - 13.5 Vde) 15 7.2 - -6.0 -'2 - -4.2 -
(Val· 0.4 Vde) Sink IOl 5.0 1.9 - 1.6 3.2 - 1.1 - mAde
(Val - 0.5 Vde) 10 3.6 - 3.0 6.0 - 2.1 -
(VOL - 1.5 Vde) 15 7.2 - 6.0 12 - 4.2 -
OutpUt Drive Current Source IOH mAde
Other Outpuu (Al Devi•• )
(VOH - 2.5 Vde) 5.0 -3.0 - -2.4 -4.2 - -1.7 -
(VOH = 4.6 Vde) 5.0 -0.64 - -0.61 -0.88 - -0.36 -
(VOH - 9.5 Vdc) 10 -1.6 - -1.3 -2.25 - -0.9 -
(VOH - 13.5 Vdc) 15 -4.2 - -3.4 8.8 - -2.4 -
(Val - 0.4 Vde) Sink IOl 5:0 0.64 - 0.51 0.88 - 0.36 - mAde
(Val - 0.5 Vde)
(Val - 1.5 Vde)
10 1.6 - 1.3 2.25 - 0.9 -
15 4.2 - 3.4 8.8 - 2.4 -
OutPUt Drive Current Source IOH mAde
Other Outputs (Cl/CP Device)
(VOH - 2.5 Vde) 5.0 -2.5 - -2.1 -4.2
-0.88
- -1.7 -
(VOH - 4.6 \Ide) 5.0 -0.62 - -0.44 - -0.36 -
(VOH - 9.5 Vde) 10 -1.3 - -1.1 -2.25 - -0.9 -
(VOH - 13.5 Vde) 15 -3.6 - -3.0 -8.8 - -2.4 -
(Val - 0.4 Vde) Sink' IOl 5.0 0.62 - 0.44 0.88 - 0.36 - mAde
(Val - 0.5 Vde) 10 1.3 - 1.1 2.25 - 0.9 -
(Val· 1.6 Vde) • 15 3.6 - 3.0 8.8 - 2.4 -
VOO Tlow
. 250C Thigh-
Characteristic Symbol Vde Min Max Min Typ Max Min Max Unit
Inpu' Curren', AST (AL!CL/CP Device) lin 15 25 - - 150 - - 250 "Ade
Input Current tAL Device} lin 15 - 10.1 - 10.‫סס‬OO1 to.l - t 1.0 "Ade
Input Current (CL/CP Device) lin 15 - to.3 - to.OOOOl to.3 - 11.0 "Adc
Input Capacitance (Data) Cin - - - - 15 - - - pF
Input Capacitance (All Other Inputs) Cin - - - - 5.0 7.5 - - pF
(Vin' O)
Quiescent Current tAL Device} 100 5.0 - 5.0 - 0.005 5.0 - 150 ",Adc
IPer Package) 10 - 10 - 0.010 10 - 300
15 - 20 - 0.015 20 - 600
EI Quiescent Current (CL/CP

(Per Package)
··Total SupplV Current at an E)(ternal

Load Capacitance (el) on
All Outputs
Device) 'DO
IT
5.0
10
15
-
-
-
-
20
40
80
-
-
-
0.005
0.010
0.015
IT' 11.5 "A/kHz}
IT • 13.0 "A/kHz}
IT' 14.5 "A/kHz)
f
f
f
20
40
80
+ 100
+ 100
+ 'DO
-
-
-
150
300
600
"Adc
"Adc
• Tlow -5SoC for AL Device, -40°C for CL/CP Device.

g
Thigh'" +12SoC for AL Device. +8SoC for CL/CP Device .

•• The formulas given are for the typical characteristics only at 2SoC.
# Noise immunity specified for worst-case input combination.
VOO All Types

Characteristic Sy'mbol Vde Min Typ Mox Unit
Propagation DeilY Time Xl to AA 'PLH, 5.0 - 250 500 ns
'PHL 10 - 125 250
15 - 100 200
Xl '0 Flag F. Flag O. ATN. JMP 5.0 - 200 400 ns
10 - 100 200
15 - 85 170
Xl to Write 5.0 - 225 450 ns
10 - 125 250
15 - 100 200
Xl to Data 5.0 - 250 500 ns
10 - 120 240
15 - 100 200
AST ,oAA 5.0 - 250 500 ns
10 - 125 250
15 - 100 200
AST '0 Xl 5.0 - 450 Note 1 ns
10 - 200
15 - 150
AST '0 Flag F. Flag 0, ATN, JMP 5.0 - 400 800 n.
10 - 200 400
15 - 150 300
RST to Write, Dati 5.0 - 450 900 n.
10 - 225 450
15 - 175 350
Clock Pul.a Width. Xl 'WId} 5.0 400 200 - n.
10 200 100 -
15 180 90 -
Aa •• t Pul •• Width. AST 'WIA} 5.0 500 250 - n.
10 250 125 -
15 200 100 -
Setup Time - Instruction 'sull} 5.0 400 200 - ns
10 250 125 -
15 180 90 -
Dati 'sulO) 5.0 200 100 - ns
10 100 50 -
15 80 40 -
Hold Tim. Instruction 'hll) 5.0 100 0 - n.
10 50 0 -
15 50 0 -
Oa •• thlO) 5.0 200 100 - n.
10 100 50 -
15 100 50 -
FIGURE 1 - TYPICAL CLOCK FREQUENCY Pin No. Function Symbols
versus RESISTOR IRCI 1 Chip Reset AST
2 Write Pulse Write
3 Data Inlout Data
4 MSB Instruction Word 13
5 Bit 2 Instruction Word 12
6 Bit 1 Instruction Word 11
7 LSB Instruetion Word 10
8 Negative SupplV (Ground) VSS
9 Flag on NOP F Flag F
10 Flag on NOP 0 FlagO
11 Subroutine Return flag ATN
12 Jump Instruction Flag JMP
13 Oscillator Input X2
14 Oscillator Output Xl
15 Result Register AA
16 POSitive Supply VDD
Instruction Code Mnemonic Action

0 0000 NOPO No change In registefs. AA -. AA, Flag 0·- rt.
1 0001 LD Load result register. Data -.. RR
2 0010 LDC Load complement. Data ...• AR
3 0011 AND Logical AND. AA Data -. RA
4 0100 AN DC Logical AND complement. AA Data -- RR
5 0101 OA LogicalOR. AA + Data -. RR
6 0110 OAC Logical OR complement. RA + Data - RR
7 0111 XNOA Exclusive NOR. If AA = Da.a, AA - 1
8 1000 STO Store. RR -- Data Pin, Write -- JL
9 1001 STOC Store complement. RR •..•Data Pin, Wnte -..•.J'"'L
A 1010 IEN Input enable. Data -- IEN Register
B lOll DEN Output enable. Data - OEN Register
C 1100 JMP Jump. JMP Flag - JL.
0 1101 ATN Return, RTN Flag - JL and skip next mstruction
E 1110 SKZ Skip next instruction if RR =- 0
F 1111 NOPF No change In registers. AA - AA, Flag F -.fL
I
Additional :
I Output Devices I
L -J
MC14599B :)
a·Bit Addressable Latch a
Outputs
with Bidirectional Oata
MC14512
a·Cha"nel
Oata Selector
r---------,
I Additiona' I
: Input Devices :
I I
I I
tW(R)---ltPHL~
(RESETTOXI)
f--- 'PHL(RESETTORR)
4 Bit
In.truction ~
\
~~~--~------
r---\ r---\
1
FLAG 0
---'PLH
(DATA TO FLAG)
I
::::rl-- Jk-. ~~
j--\'--------
RST 1
RR\---~
JMP Flea ,-------\
__________________ J :===========-----'P-H-L-
RTN Fle" ~/ \ (RESET TO Jump)
~ ~I
tPHL
(Xl to Write)
NOTE 1. Valid output data.
® MOTOROLA
The MCM14505 64-bit random access memory is fully decoded

54-BIT (64 X 1) STATIC
on the chip and organized as 64 one-bit words (64 X 1). Medium
RANDOM ACCESS MEMORY
EI
speed operation and micropower supply requirements make this
device useful for scratch pad or buffer memory applications where
power must be conserved or where battery operation is required.
When used with a battery backup, the MCM 14505 can be utilized
as an alterable read-only memory, allowing the battery to retain in-
formation in the memory when the system is powered down, and
allowing the battery to charge when power is applied. The micro-
power requirements ofthis memory allow quiescent battery operation
for great lengths of time without significant discharging.
• Quiescent Current = 50 nA/package typical @ 5 Vdc

• Noise Immunity = 45% of VOO typical L SUFFIX PSUFFIX
CERA.MIC PACKAGE PLASTIC PACKAGE
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
CASE 632 CASE 6.6
• Single ReadlWrite Control Line
• Wired-OR Output Capability (3-State Output) for Memory
Expansion
• Access Time = 180 ns typical at VOO = 10 Vdc SU~f;:e::;:t::Ck."
• Write Cycle Time = 275 ns typical at VOO = 10 Vdc C P Plastic Package
A Extended Operating
• Fully Buffered Low Capacitance Inputs
• Capable of Oriving Two Low-power TTL Loads, One Low-power ~ C
Temperature
Limited
Tamperature
Range
Operating
Range
Schottky TTL Load or Two HTL Loads Over the Rated Temper-
ature Range

DC Supply Voltage Voo -0.5 to +18 Vdc
AO 1
Input Voltage, All Inputs Vi" -0.5 to VOO + 0.5 Vdc
Al 2
Addr.. A2 3
Operating Temperature Range - AL Device TA -55 to +125 °c Inputs A3 4
CLlCP Oevice -40 to +85 {
"A411
Storage Temperature Range Tstg -65 to +150 °c AS 12
Oata In 13
Strobe 5
This device contains circuitry to protect the inputs against damage due to htgh
static voltages or electric fields; however, it is advised that normal precauttons be CEl6
,eken to avoid application of any voltage higher than maximum rated volt~'1 to CE28
this high impedance circuit .. For proper operation it is recommended that Vin and RIW 9
Vout be constrained to the range Vss <; (Vi" or Vout)"'; VOO-
Unused inputs mutt always be tied to In appropriate logic volt8Q8 level (e.g ..
either Vss or VoaL
Voo Tlow
. 25PC Thi h*
Characteristic Symbol Vdc Min Ma. Min TVp Ma. Min Ma. Unit
Output Voltage "0" Level VOL 5.0 - 0.05 - 0 0.05 - 0.05 Vdc
V,n Van or 0 10 _. 0.05 - 0 0.05 - 0.05
15 - 0.05 - 0 0.05 - 0.05
"1" Level VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vdc
Vin o or Vao 10 9.95 - 9.95 10 - 9.95 -
15 14.95 - 14.95 15 - 14.95 -
Noise Immunity Ii VNL Vdc
I V out ~ 0.8 Vdcl 5.0 1.5 - 1.5 2.25 - 1.4 -
('V Out ~ 1.0 Vdd 10 3.0 - 3.0 4.50 - 2.9 -
(I\Vout ,,;; 1.5 Vdd 15 4.5 - 4.5 6.75 - 4.4 -
1·'Vou !"
0.8 Vdc) VNH 5.0 1.4 - 1.5 2.25 - 1.5 - Vdc
( .vout ~ 1.0 Vdcl 10 2.9 - 3.0 4.50 -- 3.0 -
(.'Vout"" 1.5 Vdc) 15 4.4 - 4.5 6.75 - 4.5 -
Output Drive Current lAL Device) IOH mAde
1VOH = 2.5 Vdc) Source 5.0 -1.2 - -1.0 -1.7 - -0.7 -
1VOH ~ 4.6 Vdcl 5.0 -0.25 - -0.2 -0.36 - -0.14 -
1VOH = 9.5 Vdc) 10 -0.62 - -0.5 -0.9 - -0.35 -
1VOH = 13.5 Vdcl 15 -1.8 - -1.5 -3.5 - -1.1 -
1VOL = 0.4 Vdcl Sink IOL 5.0 0.3 - 0.25 0.35 - 0.18 - mAde
1VOL = 0.5 Vdcl 10 0.9 - 0.75 1.2 - 0.50 -
(VOL = 1.5 Vdcl 15 2.2 - 1.7 4.S- - 1.2 -
Output Drive Current (CUe? Device) IOH mAde
1VOH = 2.5 Vdcl Source 5.0 -1.0 - ·-0.8 -1.7 - -0.6 -
1VOH = 4.6 Vdc) 5.0 -0.2 - -016 -0.36 - -0.12 -
1VOH = 9.5 Vdcl 10 -0.5 - -0.4 -0.9 - -0.3 --
1VOH = 13.5 Vdcl 15 -1.4 - -1.2 -3.5 - -1.0 -
1VOL = 0.4 Vdc) Sink IOL 5.0 0.2 - 0.15 0.35 - 0.1 - mAde
1VOL = 0.5 Vdcl 10 0.6 - 0.5 1.2 - 0.4 -
(VOL = 1.5 Vdcl 15 0.9 - 0.75 4.5 - 0.6 -
Input Current tAL Device) lin 15 - 10.1 _. <000001 !O.1 - ± 1.0 /JAde
Input Current (CUe? Device) lin 15 < 1.0 <000001 11.0 - ±14 /JAde
Input Capacitance Gin - - - 5.0 7.5 - - pF
(Vin ~ 0)
Quiescent Current tAL Devlcel 100 50 - 50 - 0.050 5.0 - 150 /JAde

(Per Package) 10 - 10 - 0.100 10 - 300
15 20 0150 20 - 600
QUiescent Current (CUe? DeVice) 'DO 5.0 - 50 - 0.050 50 - 375 /JAde
(Per Package) 10 - 100 - 0.100 100 - 750
15 - 200 - 0.150 200 - 1500
Total Supply Current·· t IT 5.0 IT ~11.28 "A/kHz) f + 100 ,..,.Adc
(Dynamic plus Quiescent, 10 'T = 12.56 "A/kHz) f + 100
Per Package) 15 IT = 13.85 "A/kHz) f + 100
(CL SOpF on all outputs, all
C~
buffers sWitching)
Three-State Leakage Current ITL 15 - ± 0.1 - -0.00001 ± 0.1 - ±3.0 J,JAdc
(AL Devicel
Three·State Leakage Current 'TL 15 - 11.0 - '0.00001 ± 1.0 - ± 7.S J.lAdc
(CLlCP Device)
·T!oW = -SSoC for AL Device, -40oC for CLlCP Device.

Thigh = +12SoC for AL Device. +8SoC for CLlCP Device.
#Noise immunity specified for worst-case input combination.
tTo calculate total supply current at loads other than 50 pF:
'TICL) = IT,150 pF) + 1 • 10-3 ICL -501 VOO'
where: IT is in uA (per package), CL in pF. VOO in Vdc. and f in kHz is input frequency .
• ·The formulas given are for the typical characteristics only at 2SoC.
CMr_iotic Symbol VDD Min Typ Max Unit
Output Rise Time tTLH ns
tTLH· 12.43 ns/pFI CL + 58.5 ns 5.0 - 180 360
tTLH· 11.08 ns/pFI CL + 36 ns 10 - 90 180
tTLH· 10.72 ns/pFI CL + 39 ns 15 - 75 150
OutPut Fell Time tTHL ns
tTHL· 12.16 ns/pFI CL + 52 ns 5.0 - 160 320
tTHL· 10.96 ns/pFI CL + 32 ns 10 - 80 160
tTHL· (0.69 ns/pFI CL + 33 ns 15 - 65 130
Propegation Oeley Time teeclRI ns
Rnd ACCftS Time
II
tecclRI - 11.4 ns/pFI CL + 385 ns 5.0 - 455 750
tecclRI· 110.7 ns/pFI CL + 175 ns 10 - 210 400
tecclRI - 10.5 ns/pFI CL + 105 ns 15 - 130 300
Strobe Down Time twL ns
5.0 500 100 -
10 125 50 -
15 95 75 -
Address setup Tim. to.. ns
5.0 300 -100 -
10 120 -40 -
15 90 -25 -
Dag Setup Time to..lDI ns
5.0 200 70 -
10 75 25 -
15 55 20 -
RNd setup Time tsu(RI ns
5.0 270 90 -
10 60 20 -
15 45 15 -
Write Setup Time tsuIWI ns
5.0 400 80 -
10 100 25 -
15 75 11 -
Address Rei ••• Time troHRI ns
5.0 75 15 -
10 25 10 -
15 20 5.0 -
D.g Hold Time th(DI ns
5.0 50 0 -
10 15 0 -
15 10 0 -
RNd R81e_ Tim. troHRI ns
6.0 0 -90 -
10 0 -25 -
15 0 -10 -
Write R81._ Time . ns
troHwl
6.0 0 5.0 -
10 0 10 -
16 0 30 -
Rood Cyde Tim. teyelRI ns
5.0 - 500 750
10 - 200 400
16 - 150 300
Write Cyel. Time teyeIWI ns
6.0 - 440 100
10 - 276 660
Output DINbItI Daley tells

16 - 200 4111
no
(1C1"OutPUt Chongo Into 1.0 kO Lood) 6.0 - 200 800
10 - 80 200
III - 80 160
Not.: Th. rNld/writ. input c.n b. m.int.ined .t • logic "0"
(low voltllg.) during. writ. cycle. If the r.-d/write
input is meint.ined .t e logic "0" while the strobe is
e logic ""1"" then the output dete "";'illbe diubled (high
impeclence)during the write cycle.
TA '" 25°C
!
..~
x
0
..
~
... 1.0
0
'"In
10 VDD' 5.0 Vd,
lOVd,
--- -- -- VDD' 5.DVd,
10Vd,
)( 15 Vd,
; 0.1
: 15Vd,
l;
0.01
••• -20 20 60 100 140
TA. AMBIENT TEMPERATURE fOC)

II VDD-lDS
Vlnput
0---
--l \-300 n.
10kHz
--
Notes'
1. Cvcle AIW to ground and then to VOO
prior to measurement to insure turn-
on of the device under te,t.
2. For the P-ehanne' characteristics.
VOS'" VOH - VOD-
3. For the N-channel charllCteristics.
Vos j,measur~ directly. E
4. For the drain current,IO'" 100 Amp
E.ternal External
Power Power
Supply Supply
(a) TA" -55°C

{bl T A::: 'f250C
;{ ;{
(c)TA.:::+1250C
~ -2.0 ~ 8.0
~
z
~ '"'"
B
w
-4.0 a 6.0
u
'"
z
'" ;;;
~
"
~ -6.0 10
~
~ Vdc "
~
l!: "
o fa) T A • _~~oC
"
0_8.0 ~ 2.0 (b)T A ::: + 25°C
'"
52
(clTA::: +1250C
lEI
AO ;e
.
"¥
0
A4
Al
.
~
"¥
0
0
~
A2 0
0 U
~ on
A3
0
a: ..'"- AS
'"
I-
I
I
I
I
I
I
I
I
I
I
I
I
I ~
I
I
I
IL
--1~
~~O.t.out
(3·Stat.)
~"~
In considering the operation of the MCM14505 CMOS memory. row is in the low state. and the unselected 15 rows retain their
refer to the funettonal circuit du.gram of Figure 1 and timing logic "1" level due to the row e-j»citance that exists when the row
diagrams shown in Figures 1 and 2. The basic memory cell is a decoder inhibit gates are disabled. This capacitive storege mecha·
cross-eoupled flip·flop consisting of two inverter gates and two Olsm requires 8 maximum strobe width (see Figure 3) equal to the
P-ehannel devicesfor read/write control. The push-pull cell provides junction reversebias RC time constant. When the strobe is returned
high speed as well as low power. to a logic ''0'' the rows are forced to VDO by the row decoder
During a read cycle, when the strobe Une is high the write inhibit gates (pullup devices). Similarly the column readlwrite
selection drivers are disabled and the data from the selected row is inhibit gates (pulldown devices) force the column lines to a logic
available on columns lb. 2b. 3b. and 4b. The A4 and AS address "0" state.
EI
bits are decoded to select output data from one of the four columns. Two column lines are associatedwith each memory cell in order
The output data is available on the data output pin only when the to write into the cell. The write selection drivers Ire enabled when
strobe and read/write lines are high 5imultaneously and after the the RIW line is a logic "0" and the strobe line is I logic "1". The
read accesstime, tacc(RI. has occurred (see Figure 11." Note that input data is written into the column selected by the column
the output is initially disabled and always goes to the logic "0" state decoder. For instlnce, if a "1" is to be written in the memory cell
(low voltage) before data is valid. The output is in the htgh· associated with row 1 and column 1. then row 1 would be enabled
impedance state (disabled) when the strobe line or the RM line is (logic "0") while column 1b is forced high and column 1a is forced
in the low state. The memory is strobed for reading or writing only low by the write selection drivers. If a logic "0" is to be written
when the strobe, CE1. and CE2 are high simultaneously. The RM into the cell, then column 1a is forced high and 1b is forced low.
line can be a dc voltage during a read or write cycle and need not The data that is retained in the memory cell is the data that was
be pulsed. as shown in the timing diagrams. For this casethe RM present on the data input pin at the moment the strobe goes low
line shoukt be a logic "1" (high) for reading and a logic "0" for when RM is low, or when R/W goeshigh when the strobe is high.
writing.
When the strobe line is high. the column read/write inhibit
gates and the row decoder inhibit gates are disabled. the selected
Figure 8 showsa 25&v-.ord by n·bit static RAM memory system Figures 11. 12. and 13 show methods of interfacing the
The outputs of four MCM14505 devices are tied together to form memory output to TTL logic at various memory voltages. If a
256 words by 1 bit. Additional bits are attained by paralleling the VOO of 5.0 volts is used for slow·speed. low·power applications.
inputs in groups of four. Memories of larger words can be attained one transistor and one resistor must be used (Figure 111. The
by decoding the mo$! significant bits of the address and ANOing MCM14505AL will drive one low·power TTL gate directly.
them with the strobe input. If a VOO of 10 volts is used, the output of the memory device
Fan-in and fan..aut of the memory is limited only by speed can fan out to two 10wllovver TTL gates (Figure 12a) or to a
requirements. The extremely low input and output leakagecurrent discrete transistor (F igure 12bl. The di.:rete transistor circuit
1100 nA maximum) keep the output voltage levels from changing provides higher speed and/or high fan..aut. A puUdown resistor
significantly as more outputs are tied together. With the output at the base of the transistor is not needed for fast turn-off because
levels independent of fan-out, most of the power supply range is of the push·pull output of the memory. Turn..an time of the
available 8S logic swing, regardless of the number of units wired transistor is much faster in Figure 12b since the voltage rise is only
together. As a result, high noise immunity is maintained under 0.75 volt. The low output capacitance of the MCM14505 means
all conditions. that several outputs can be wire-Q Red without significantly de-
Power dissipation is 0.1 IlW per bit at a 1.0--kHz rate for a grading performance. The read accesstime is increased by only
5.0·volt power supply, while the static power dissipation is 2.0 nW 20 ns typically for 16 outputs tied together When Figure 12b
per bit. This low power allows non-volatile information storage is used.
when the memory is powered by a small standby battery. Five low-power TT L gates can be driven from the memory
Figure 9 shows an optional standby power supply circuit for output .f a VOO of 15 volts is used (Figure 13a). Figure 13b
making a CMOS memory "non·volatile". When the usual power shows the interface if a discrete transistor is used. The 1.0 kilohm
fails, a battery is used to sustain operation or maintain stored resistor in the base is required to insure that not more than 10 mA
information. While normal power supply voltage is present, the flows through the output as listed in the maximum ratings. If a
battery is trickle-charged through a resistor which sets the charging 2.0 kilohm collector resistor is used (fan<tut '" 3), the turn<tn
rate. VB is the sustaining voltage. and V+ is the ordinary voltage time of the transistor is only slightly faster than in the circuit
from a power supply. VDO connects to the power pin on the shown in Figure 12b due to the lower output impedance when
memory. Low·leakege diodes are recommended to oonserve VOO :: 15 volts. The voltage at the memory data output has to
battery power. rise to only 1.3 yoits to insuredriving a f.,,-out of three TTLdevices.
The memory system shown in Figure 8 can be interfaced If a 510-ohm collector resistor is used. 20 TTL lo.cts may be
directly with the other devices in the McMOS family. No external driven. The reed accesstime is increased about 20 ns when four
components are required. memory outputs are tied together since the output volt. must
At the inputs to the CMOS memory, TT L devices can interllce rise to 3.7 yoits before the transistor can sink the full 10 L for a
directly if an open-eolleetor logic gate such as the MC7407 is used fan-out of 20 TTL devices. Almost any NPN transistor with a
as shown in Figure 10. Driver circuits are not required since the minimum beta of 15 can be used for the interlace shown in
input capacitance is low (4.0 to 6.0 pFL The address, dlta, and Figures 11,12and 13.
read/write tnputs do not need to be fast since they can be changed The high source current from the push-pull output stegeof the
for the duration when the strobe pulse is low, tSTL (see Figures 1 MCM14505 makes for a simpler interface circuit since alow source
and 2). For high-speedoperation. a push-pull driver should be used current memory requires a differential comperator to achieve high-
if more than five strobe inputs must be driven at one time. One speedoperation.
circuit of the type shown in Figure 10 can be used for every ten
strobe inputs.
A 1
B 2
C 3
Add'... 0 4
Line, E 11 MCM14505
F 12 64-Bit 10 >--
G 6 Rom
H B
.--- 5
-9
- 13
- 1
r;L> G
2
3
:L)H 4
11
12
MCM14505
10 r----
64·Bit
6 Rom
-=- 8
5
>- - 9
13
f--<>I
1
2
3
4
11 MCM14505
12 54-Bit lOr----
6 Rom
8
5
>- -- 9
>- 13
1
2
3
4
11 MCMI4505
64·Bit 10 I--
12
Rom
6
8
5
9
- 13
I I II II I I II
I I I III II I I
I I I III I II I
I I I III I-' I I
-=- VB
1-
•. Using low..pow. TT L G.tes
voo - 15 V
® MOTOROLA
The MC14511B BCD-to-sevensegment latch/decoder/driver is con-

structed with complementary MOS (CMOS) enhancement mode de-
vices and NPN bipolar output drivers in a single monolithic structure_
The circuit provides the functions of a 4-bit storage latch, an B421
BCD-to-sevensegment decoder, and an output drive capability_ Lamp
test (Ll'). blanking (81), and latch enable (LE) inputs are used to test BCD·TO-SEVEN SEGMENT
B
the display, to turn-off or pulse modulate the brightness of the LATCH/DECODER/DRIVER
display, and to store a BCD code, respectively_ It can be used with
seven-segmentlight emitting diodes (LED), incandescent, fluorescent,
gas discharge, or liquid crystal readouts either directly or indirectly_
Applications include instrument (e.g., counter, DVM, etc.) dis-
play driver, computer/calculator display driver, cockpit display driver,
and various clock, watch, and timer uses.

• Low Logic Circuit Power Dissipation
L SUFFIX PSUFFIX
• High-Current Sourcing Outputs (Up to 25 mAl CERAMIC PACKAGE PLASTIC PACKAGE
CASE 620 CASE 648
• Blanking Input
• Lamp Test Provision MC14XXXB ~SUtfi" Oenote.
• Readout Blanking on all Illegal Input Combinations L Cec'emicPeckege

P Plastic PKkqe
• Lamp Intensity Modulation Capability A E••tended Operating
Tempereture Range
• Time Share (Multiplexing) Facility
C Limited Opareting
• Supply Voltage Range = 3_DVdc to 18 Vdc Tempereture Renge
• Capable of Driving Two Low-power TTL Loads, One Low-power

Schottky TTL Load or Two HTL Loads Over the Rated
Temperature Range.
,. fl~b
13
12
'0, d
R.tinSi Symbol Value Unit 10 VOO - Pin 16

DC SupplV Voltage -0.5 to +18 VSS - Pin 8
Voo Vdc
Input Voltage, All Inputs Vin -0.5 to V DO + 0.5 Vdc
DISPLAY
DC Current Drain per Input Pin I 10 mAde
Operating Temperature Range - AL Device TA -55 to +125 °c
CL/CP Device --40 to +85 ~
3 4 5 8 9
Storage Temperature Range TUg -65 to +150
Maximum Output Drive C.rrent IOHmax 25 mA
(Source) per Output
Maximum Continuous Output Power
*
INPUT
LT . . ,
nUT,uT'
•
.0-·
50 mW L" 8' 0 C 8 A b d f DIsPLAY
POHmax
(Source) par Output x x 0 x x x X 1 1 I 1 1 1 1
X
0
0
1
1
.,
1
X X
0 0 0
X X
0
0
1
0
1
0
1 ,
0 0
1 ,
0 0
0 0
0
0
1
I 1
0 0 0
0 0 I
1
0
0
1
1
1
1
0
0
1 ,
0 0
0
0
1
1
2
,
·
0 1 0 0 1 I 0 0
0 1
1
,
1 0 0 , 0
1
0
1 1
1 0
f
0 1
1
1
3
This device contains circuitry to protect the inputs against damage due to high static 0 1
, 0 1 0 1 1 0 1 1 0 1 I
•
,
, ••
voltages or electric fields; however, it is advised that normal precautions be taken to 0 1 0 1 1 0 0 0 1 1 1 1 1
HYoid application of any voltage higher than maximum fated voltages to this high im-
0
0 ,,
1 I
1
0 1
1 0 0
1
0
1
1
1
1 ,
I 0
1 ,
0 0
1
0 7
pedance circuit.
'0
A destructive high current mode may occur. if Vin and Vout is not 0
0 1
,
1
,
1 0 0
1 0
,
1
0
1
0
1
0
1
0
0 0 1 1
a,_•
.0_
constrained tho range VSS "IVin or You,) •• Voo. 1 1 0 0 0 0
0
, , ,
1 0 1 0 0 0 0 0 0 0 0'-
Due to the sourcing capability of this circuit, damage can occur to the device if VOD is
applied, and the outputs are shorted to Vss and are lit a logical 1 (See Maximum
0
0
0
1
1
1
,
1
1
1
1 0
1 0
, ,,
1
0
1
0
0
0
0
0
0
0
0
0
0
0 0 0
0 0 0
0 0 0
0
0
0
.0-
a,_
a,_
Aotings). 0
1 ,
1
1
1
X X X
1
X
0 0 0 0 0 0 0
Unused inputs must alWaYs be tied to an appropriate logic voltage level (e.g., either
x- Don't Cere
Vss orVool.
-OeP4lnds upon the BCD code preYlou.ly eppUed
when LE - 0
I "DO
I Tlow " 25°C Th' h"
Chliraet"'tic Symbol Vde Min Max Min Typ Max Min Mex Unit
I;Output Voltage "0" Level VOL 5.0 - 0.05 - 0 0.05 - 0.05 Vde
Vin" VOD or 0 10 - 0.05 - 0 0.05 - 0.05

15 - 0.05 - 0 0.05 - 0.05
"I" Level VOH 5.0 4.1 - 4.1 4.57 - 4.1 - Vde

Vin-OorVOD 10 9.1 - 9.1 9.58 - 9.1 -
15 14.1 - 14.1 14.59 - 14.1 -
'Input Voltage"" "0" Leve' Vde
VIL
(VO. 3.8 or 0.5 Vdel 5.0 - 1.5 - 2.25 1.5 - 1.5
(VO a 8.80.1.0 Vde) 10 - 3.0 - 4.50 3.0 - 3.0
(VO - 13.80.1.5 Vde) 15 - 4.0 - 6.75 4.0 - 4.0
II (VO :0.5·or3.8 Vde) "1" level VIH 5.0 3.5 - 3.5 2.75 - 3.5 - Vde
(VO -1.0 or 8.8 Vde) 10 7.0 - 7.0 .5.50 - 7.0 -
(VO. 1.5 or 13.8 Vde) 15 1t.0 - 11.0 8.25 - 11.0 -
OutpUl Drive Vol" (AL Device) Vde
VOH
(I0H • 0 mAde), Source I 5.0 4.10 - 4.10 4.57 - 4.1 -
(I0H - 5.0 mAdel - - - 4.24 - - -
(I0H - 10 mAde) 3.90 - 3.90 4.12 - 3.5 -
(IOH· 15 mAde) - - - 3.94 - - -
(lOH • 20 mAde) 3.40 - 3.40 3.75 - 3.0 -
(I0H - 25 mAde) - - - 3.54 - - -
(lOH' o mAde) 10 9.10 - 9.10 9.58 - 9.1 - Vde
(I0H -. 5.0 mAde) - - - 9.26 - - -

(lOH - 10 mAdel 9.00 - !l.OO 9.17 - 8.6 -
(lOH - 15 mAde) - - - 9.04 - - -
8.60 - 8.2 -
(lOH- 20 mAde) - 8.60 8.90
(lOH - 25 mAde) - - 8.75 - -
(IOH - o
mAde) 15 14.1 - 14.1 14.59 - 14.1 - Vde
(IOH - 5.0 mAde) - - - 14.27 - - -
(lOH - 10 mAde) 14.0 - 14.0 14.18 - 13.6 -
(lOH - 15 mAde) - - - 14.07 - - -
(lOH- 20..-1 13.8 - 13.6 13.95 - 13.2 -
(lOH - 25 mAde) - - - 13.110 - - -
Outpu' Drive Voltege (CL/CP Device) Vde
VOH
(lOH· 0 mAdel1 Source 5.0 4.10 - 4.10 4.57 - 4.1 -
(IOH - 5.0 mAdel - - - 4.24 - - -
(lOH - 10 mAde) 3.60 - 3.60 4.12 - 3.3 -
(lOH - 15 mAde) - - - 3.94 - - -
(lOH- 20 mAde) 2.90 - 2.80 3.75 - 2.5 -
(lOH - 25 mAde) - - - 3.54 - - -
(IOH - 0 mAde) 10 9.10 - 9.10 9.58 - 9.1 - Vde
(lOH - 5.0 mAde) - - - 9.26 - - -
(lOH - 10 mAde) 8.75 - 8.75 9.17 - 8.45 -
(IOH· 15 mAde) - - - 9.04 - - -
(lOH • 20 mAde) 8.10 - 8.10 8.90 - 7.8 -
(I0H - 25 mAde) - - - 8.75 - - -
(lOH - o mAde) 15 14.1 - 14.1 14.59 - 14.1 - Vde
(lOH - 5.0 mAde) - - - 14.27 -
-
- -
-
(lOH - 10 mAde) 13.75 - 13.75 14.18 13.45
(lOH - 15 mAde) - - - 14.07 -
-
- -
-
(lOH' 20 mAde) 13.1 - 13.1 13.95 12.8
(lOH - 25 mAdel - - - 13.80 - - -
Oulpu' Drive Currenl (AL Device) IOL mAde
(VOL' 0.4 Vde) Sink 5.0 0.64 - 0.51 0.88 - 0.36 -
1.6 1.3
(VOL-0.5Vde) 10 - 2.25 - 0.9 -
(VOL -1.5 Vde) 15 4.2
- 3.4 8.8 - 2.4 -
Outpu' Drive Curren, (eLlCP Device) IOL mAde
(VOL -0.4 Vde) Sink 5.0 0.52 - 0.44 0.88 - 0.36 -
(VOL - 0.5 Vdel 10 1.3 - 1.1 2.25 - 0.9 -
(VOL - 1.5 Vdel 15 3.6 - 3.0 8.8 - 2.4 -
Voo TI_
. 25°C Th •••••
Characteristic Symbol Yd. Min Ma. Min Typ Ma. Min Ma. Unit
Input Current IAL OeYice~ lin 15 - to.l .0.‫סס‬oo1 to.l '1.0 ~Ad.
Input Current (CL/ep Device) lin 15 - 10.3 10.‫סס‬OO1 '0.3 11.0 ~Adc
Input Capacitance Gin - - - - 5.0 7.5 pF

(Vin' 01
Quiescent Current tAL Devk:el 100 5.0 - 5.0 - O.oos 5.0 150 ~Adc
(Pe' Packagel 10 - 10 - 0.010 10 - 300
15 - '20 - 0.016 20 - 600
QUiescent Current (CLlCP Device) 100 5.0 - 20 - 0.005 20 - 150 ~Adc
(Per Package) 10 - 40 - 0.010 40 - 300
15 - 80 - 0.015 80 - 600
Total Supply Current· • t
(Dynamic plus Quiescent,
Per Package)
(el 50 pF on all outputs,
:E
buffers switching)
all
IT 5.0
10
15
IT'
IT'
IT'
11.9 ~A/kHll
(3.8 ~A/kHll
(5.7 ~A/kHzl
f + 100
f + 100
f + 100
IlAde
II
·Tlow:;" -55°C for AL Device. -40oC for cLlep Device. tTo calculate total supply current at loads other than 50 pF:
Thigh'" .12SoC for AL Device. +8SoC for CL/CP Device. ITICL) = ITI50 pFI + 3.5 x 10-3 (CL -501 Voo'
.Noise Immunity spec;ified for worst-case input combination. where: IT is in ~A (per package). CL in pF. VOO in Vdc.
NOiseMargin for both "1" and "0" level a and f in kHz is input frequency_
1.0 Vdc min@l Voo • 5.0 Vdc ··The formulas given are for the typical
2.0 Vdc min@ Voo = 10 Vdc characteristics only at 2SoC.
2.5 Vdc min @ Voo = 15 Vdc
SWITCHING CHARACTERISTICS· (CL' 50 pF. TA· 25°C I
Voo
ChIlraeteristic Svmbol Vdc Min Typ Ma. Unit
tTLH • 11.5 ns/pF) CL + 50 ns 5.0 - 40 80
tTLH • (0.75 os/pF) CL + 37.5 ns 10 - 30 60
tTLH • 10.55 ns/pF) CL + 37.5 ns 15 - 25 50
Output Fell Time ns

tTHL -
tTHL' 11.5 ns/pFI CL + 50 ns 5.0 125 250
tTH L • (0.75 ns/pFI CL + 37.5 ns 10
- 75 150
tTHL· (0.55 nslpF) CL + 37.5 ns 15
- 65 130
Data Prop&gIItion Delay Time 'PLH ns

tpLH' (0.40 ns/pFI CL + 620 ns 5.0
- 640 1280
'PLH' (0.25 ns/pFI CL + 237.5 ns 10 - 250 600
tpLH • (0.20 nsipFI CL + 165 ns 15 - 175 350
tpHL· (1.3 ns/pFI CL
+665 ns tpHL 5.0 - 720 1440 ns
'PHL = (0.60 ns/pFI CL + 260 ns 10 - 290 580
tpHL' 10.35 ns/pFI CL + 182.5 ns 15 - 200 400
Blink Propagation Delay Time ns
tpLH' (0.30 ns/pFI CL + 305 ns
'PLH
5.0
- 600 750
- 200 300
'PLH = (0.25ns/pFI CL + 117.5 ns 10
- ISO 220
tPLH' (0.15 ns/pFI CL + 92.5 ns 15
tpHL' (0.86 ns/pFI CL + 442.5 os tpHL 5.0 - 485 970 ns
lpHL' (0.45ns/pFI CL + 177.5 ns 10 - 200 400
tpHL' (0.35 ns/pFI CL + 142.5 ns 15 - 160 320
Lamp Test Propagation Delay Time tpLH ns
tpLH' (0.45 ns/pFI CL + 290.5 ns 5.0 - 313 625
tpLH • (0.25 nsipFI CL + 112.5 ns 10 - 125 2SO
tpLH' (0.20 nsipFI CL + 80 ns 15 - 90 180
tpHL' (1.3 ns/pFI CL + 248 ns lpHL 5.0 313 625 ns
'PHL' (0.45 ns/pFI CL + 102.5 ns 10 - 125 260
lpHL' (0.35 ns/pFI CL + 72.5 ns 15 - 90 180
Setup Time tlU 5.0 180 90 - ns
10 76 38 -
15 40 20 -
.:.
Hold Time th 5.0 0 -90 ns
10
15
0 -38 -
0 -20
Latch Enoble Pulse Width tWL 5.0 520 260 - ns
10 220 110 -
15 130 86
Input LE low, WId Inputs 0, BT and [f high.
fin respect to a tv.18m dock.
All outputs connec.d to respective CL loed•.
1/1
50%outvCVCI' VOH
50%
~ --VOL
20"'~20"'
90% VOO
Input C 50,,1
10%..11 Vss
tpLH~HL--J
90% - -VOO
Output g 50%
10% VSS
I tTLH tTHL
F
t,u
----.-------VOO
, 50"
~-----------VOH
Outputg \
~.----------VOL
II
LIQUID CRYSTAL (LCDI READOUT

excltetlon
(SQuar. W • ..,••
VOD VSS to VOO)
':' Vss
.*.•.fll~nt , •• Iator I, rwcommended to reduce fll..,...nt
pre-w.,m
ttMrmel thoek and Increue the effective cold ,.'ttance of the
fllemant.
13 a
A1
12 b
I Ie
B 1
10 d
9.
'5 f
C2
14 9
06
® MOTOROLA
The MC14513B BCD-to-seven segment latch/decoder/driver is

constructed with complementary MOS (CMOS) enhancement mode
CMOS MS.
devices and NPN bipolar output drivers in a single monolithic struc-
ture .. The circuit provides the functions of a 4-bit storage latch, an
8421 BCD-to-seven segment decoder, and an output drive capability. BCD-TO-SEVEN SEGMENT
Lamp test (L n,
blanking (BI), and latch enable (LEI inputs are used
LATCH/DECODER/DRIVER
to test the di'splay, to turn-off or pulse modulate the brightness of
the display, and to store a BCD code, respectively. The Ripple WITH RIPPLE BLANKING
,,-,,-
Blanking Input (RBI) and Ripple Blanking Output (RBO) can be
used to suppress either leading or trailing zeroes. It can be used with
seven-segment light emitting diodes (LED), incandescent. fluores-
cent, gas discharge, or liquid crystal readouts either directly or
indirectly.
Applications include instrument (e.g., counter, DVM. etc.) dis-
play driver. computer/calculator display driver. cockpit display
driver, and various clock, watch, and timer uses. l SUFFIX P SUFFIX
CASE 726 CASE 707
OROERING INFORMATION
• High-current Sourcing Outputs (Up to 25 mAl
•
•
Latch Storage of Binary Input
Blanking Input
." ..... 11SUffiX Oenot ••.
L e.ramic Package
• l.amp Test Provision P Pla •.tic Package
• Readout Blanking on all Illegal Input Combinations
Temperature Range
• Lamp Intensity Modulation Capability e Limitad Operating
Temperature Range
• Time Share (Multiplexing) Capability
• Adds Ripple Blanking In, Ripple Blanking Out to MC1451 1 B
• Capable of Driving Two Low-Power TTL Loads. One Low-power
Schottky
Temperature
irTL Load
Range.
to Two HTL Loads Over the Rated
tm b
·0' d

DC SupplV Voltage VDD -0.5 to +18 Vdc
Input Voltage, All Inputs Vin -0.5 to V DO + 0.5 Vdc
DC Current Drain per Input Pin 1 10 mAde
Operating Temperature Range - AL Device TA -55 to +125 OC
CL/CP Device -40 to +85
Storage Temperature Range Tstg ~5 to +150
Maximum Continuous Output OrNe Current IOHmax 25 mA
INPUTS
·. . , , ,
OUTfl'UU
."
·
(Source) per Output 0; o c ",0
, ", , ", ,,,,
·. ,,,,,,, 01$PlAY
·· ··· ····.. .-·,

0
Maximum Continuous Output Power POHmax 50 toW , , 0 ,,,, 0 o. ,,-
(Source) per Output t , , o • , 0
, 0
, 0
0
0
0 00 , ,,,,
0 0
, 0
,
0
, 0
, , ,, 0
,
,
,
0
,
,
0 0
, 0
,, ,,
,,,,
, 0
,
,
, ,,
. ,
0 0 0 0 0 0 0
·· ···.···· ··· ··· ,··

, , 0
, 0
, 0 0
,, 0 0
,,
This device' contains circuitry to protect the inputs against damage due to high static , , , 0
, , 0
, ,,
0
,, ,
voltages or electric fields; however, it is advised that normal precautions be taken to ,
,
, ,
,
,, ,, , , ,,,
, ,,0 ,,
,
, , 0
, , 0
,,,, 0 0
,,
0 0
·
avoid application of any voltage higher than maximum rated voltages to this high imped-
ance circuit. A destructive high current mode may occur if Vin and Vout is not con· , , 0
, , , 0
,,,, ,,
, , 0
, , , 0 0 0
··· ..
strained to the range Vss ~ (Vin or Vout) ~ VOO. o ••
, , 0
, , ,, 0 0
~
0 0 0 0
· ·· .'-
· ·
,
,
,
,
,
,
, ,
,, ,
0 0 0 000 0 0 0
Oue to the sourcing capability of this circuit, damage can occur to the device if VOD is
, ,
0
, ,, ,
0
0
0
0 0
000
000
0
0
0 0
,,-
applied, and the outputs are shorted to Vss and are at a logical 1 (see Maximum o ••
Ratingo).
, , 0
, ,,,, 0
0 000
0 0 0 8_
8_
, , , ,,,, 0 0 0
Unused inputs must always be tied to an approprLcite logic voltage level (e.g., either VSS
orVOO).
Tlow " 250C Thigh"
VDD
Characteristic Symbol Vde Min Max Min Typ Max Min Max Unit
Output Voltage - Segment Outputs VOL Vde
"0" Level 5.0 - 0.05 -' 0 0.05 - 0.05
Vin '" Voo ora 10 - 0.05 - 0 0.05 - 0.05
15 - 0.05 - 0 0.05 - 0.05
"I" Leval VOH 5.0 4.1 - 4.1 5.0 - 4.1 - Vde
Vin=OorVOD 10 9.1 - 9.1 10 - 9.1 -
15 14.1 - 14.1 15 - 14.1 -
Output Voltage - ABO Output VOL Vde
"0" Leval 5.0 - 0.05 - 0 0.05 - 0.05
•
Vi" = VOD or 0 10 - 0.05 - 0 0.05 - 0.05
15 - 0.05 - 0 0.05 - 0.05
"I" Level VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vde
Vi" '" OarVOD 10 9.95 - 9.95 10 - 9.95 _.
15 14.95 - 14.95 15 - 14.95 -
Input VOltage# "0" Level VIL Vde
IVO = 3.8 or 0.5 Vdc) 5.0 - 1.5 - 2.25 1.5 - 1.5
IVO = 8.8 or 1.0 Vde) 10 - 3.0 - 4.50 3.0 - 3.0
1VO' 13.8 or 1.5 Vde! 15 - 4.0 - 6.75 4.0 - 4.0
(VO' 0.5 or 3.8 Vdel "1" Level" VIH 5.0 3.5 - 3.5 2.75 - 3.5 - Vde
(VO = 1.0 or 8.8 Vde! 10 7.0 - 7.0 5.50 - 7.0 -
1VO' 1.5 or 13.8 Vde) 15 11.0 - 11.0 8.25 - 11.0 -
Output Drive Voltage - Segments VOH Vde
(AL Device)
1I0H - OmAdc) Source: 5.0 4.10 - 4.10 4.57 - 4.1 -
1I0H = 5.0 mAde) - - - 4.24 - - -
1I0H = 10 mAde! 3.90 - 3.90 4.12 - 3.5 -
1I0H - 15 mAde! - - - 3.94 - - -
1I0H = 20 mAde) 3.40 - 3.40 3.75 - 3.0 -
1I0H - 25 mAde! - - - 3.54 - - -
1I0H =OmAdcl 10 9.10 - 9.10 9.58 - 9.1 - Vde
1I0H • 5.0 mAde! - - - 9.26 - - -
1I0H = 10 mAde) 9.00 - 9.00 9.17 - 8.6 -
1I0H' 15 mAde I - - - 9.04 - .- -
1I0H = 20 mAdel 8.60 - 8.60 8.90 - 8.2 -
1I0H • 25 mAdel - - - 8.75 - - -
1I0H 'OmAdcl 15 14.1 - 14.1 14.59 - 14.1 - Vde
II OH • 5.0 mAdel - - - 14.27 - - -
1I0H '10mAde) 14.0 - 14.0 14.18 - 13.6 -
IOH ='15 mAde) - - - 14.07 - - -
II OH = 20 mAde) 13.6 - 13.6 13.95 - 13.2 -
1I0H • 25 mAde) - - - 13.80 - - -
Output Drive Voltage - segments VOH Vde
(CL/CP Device)
1I0H 'OmAdc) Source: 5.0 4.10 - 4.10 4.57 - 4.1 .-
1I0H = 5.0 mAdel - - - 4.24 - - -
1I0H - 10 mAde) 3.60 - 3.60 4.12 - 3.3 -
1I0H = 15 mAde) - - - 3.94 - - -
1I0H = 20 mAde) 2.80 - 2.80 3.75 - 2.5 -
1I0H • 25 mAde) - - - 3.54 - - -
1I0H = 0 mAde) 10 9.10 - 9.10 9.58 .- 9.1 - Vde
1I0H • 5.0 mAdel - - - 9.26 - - -
1I0H'10mAde) 8.75 - 8.75 9.17 - 8.45 -
1I0H - 15 mAde) - - - 9.04 - - -
1I0H - 20 mAde) 8.10 - 8.10 8.90 - 7.8 -
1I0H = 25 mAde I - - - 8.75 - - -
o
1I0H = mAde) 15 14.1 - 14.1 14.59 - 14.1 - Vde
(IOH = 5.0 mAde) - - - 14.27 - - -
1I0H' 10 mAde) 13.75 - 13.75 14.18 - 13.45 -
1I0H' 15 mAde) - - - 14.07 - - -
1I0H = 20 mAde I 13.1 - 13.1 13.95 - 12.8 -
1I0H • 25 mAdel - - - 13.80 - - -
Tlow· 25°C Thi9ho
Voo
Symbol Vdc Min Mo. Min Typ Mo. Min Mo. Unit
Output Drive Current - RBO Output IOH mAd<;
(AL Device)
(VOH - 2.5 Vdc) Source 5.0 -0.40 - -0.32 -0.64 - -0.22 -
(VOH - 9.5 Vdc) 10 -0.21 - -0.17 -0.34 - -0.12 -
{VOH = 13.5 Vdcl 15 -0.81 - -0.66 -1.3 - -0.46 -
(VOL = 0.4 Vdcl Sink IOL 5.0 0.18 - 0.15 0.29 - 0.10 - mAde
(VOL' 0.5 Vdcl '10 0.47 - 0.38 0.75 - 0.26 -
(VOL - 1.5 Vdcl 15 1.8 - 1.5 2.9 - 1.0 -
Output Drive Current - RBO Output IOH mAde
(CLlCP Device)
II
(VOH = 2.5 Vdcl Source 5.0 -0.25 - -0.21 -0.64 - -0.17 -
(VOH = 9.5 Vdc) 10 -0.13 - -0.11 -0.34 - -0.092 -
(VOH' 13.5 Vdcl 15 -0.52 - -0.44 -1.3 - -0.36 -
(VOL - 0.4 Vdc) Sink IOL 5.0 0.12 - 0.098 0.29 - 0.080 - mAde
(VOL = 0.5 Vdc) 10 0.30 - 0.25 0.75 - 0.21 -
(VOL = 1.5 Vdcl 15 1.2 - 0.98 2.9 - 0.80 -
Output Drive Current - Segments IOL mAde
(AL Device)
(VOL' 0.4 Vdc) Sink 5.0 0.64 - 0.51 0.88 - 0.36 -
(VOL' 0.5 Vde) 10 1.6 - 1.3 2.25 - 0.9 -
(VOL = 1.5 Vdcl 15 4.2 - 3.4 8.a - 2.4 -
Output Drive Current - Segmentt IOL mAdc
(CL/CP Device)
(VOL - 0.4 Vdc) Sink 5.0 0.52 - 0.44 0.88 - 0.36 -
(VOL' 0.5 Vdc) 10 1.3 - 1.1 2.25 - 0.9 -
(VOL = 1.5 Vdc) 15 3.6 - 3.0 8.8 - 2.4 -
Input Current (AL Device) lin 15 ±0.1 ±O.OOOOI ±0.1 ±1.0 "Adc
Input Current (CLlCP Device) lin 15 - ±0.3 - ±O.OOOOI ±0.3 - ±1.0 "Adc
Input Capacitance Gin - - 5.0 7.5 - - pF
(Vin' 0)
Ouiescent Current IAL Device) 100 5.0 - 5.0 - 0.005 5.0 - 150 "Adc
(Pet Packagel 10 - 10 - 0.010 10 - 300
15 - 20 - 0.015 20 - 600
Quiescent Current ICLlCP Device) 100 5.0 - 20 ~ 0.005 20 - 150 ",Adc
(Pet Packagel 10 - 40 - 0.010 40 - 300
15 - 80 - 0.015 80 - 600
Total SUppt'l Current--t IT 5.0 IT = (1.9 "A/kHzl 1+100 "Adc
(Dynamic plus Quiescent, 10 IT = (3.8 "A/kHzl I + I DO
Per Packagel 15 IT' (5.7 "A/kHz) 1+100
(CL - 50 pF on all outputs, all
buffers switching)
°Tlow - -55°C lor Al Device, -4o"C lor Cl/CP Device. t To calculate total supply current at loads other than 50 pF:
Thigh'" +12SOC for AL Device, +2SoC for CL/CP Device. IT(Cl) • IT(50 pF) + 3.5. 10-3 (Cl - 501 VDDI
# Noise immunity specified for worst-case input combination. where: IT is in IlA (per packagel. CL in pF. VOD in Vdc.
and f in kHz is input frequency.
Noise Margin for both "1" and "0" level ""
•• The formulas given are for the tYPK:al characteristics
1.0 Vdc min &l VOD • 5.0 Vdc
only at 25°C.
2.0 Vdc min &l VDO - 10 Vdc
2.5 Vdc min &l VDD = 15 Vdc
Input LE and RBI low. and Inputs D. ~ and CT high.

f in respect to a system clock.
All outputs connected to respective CL loads.
tff
50"outVCVCI' VOH
50"
~ --VOL
All Types
VOO
Char.cteristic Symbol Vdc Min Typ Mox Unit
Output Rise Ti!T1e - Segment Outputs 'TLH ns
5.0 - 40 80
10 - 30 60
15 - 25 50
Output Rise Time - RBO Output 'TLH ns
5.0
_. 480 960
10 - 240 480
15 - 190 380
Output Fall Time - Segment Outputs
'THL ns
'THL : 11.5 ns/pFI CL' 50 ns 5.0 - 125 250
'THL < 10.75 ns/pFI CL' 37.5 ns 10 - 75 150
'THL : 10.55 ns/pFI CL' 37.5 ns 15 - 65 130
Output Fall Time ABO Outputs ns
'THL
'THL ~ 11.5 ns/pFI CL' 50 ns 5.0 - 270 540
'THL : 10.75 ns/pFI CL • 37.5 ns 10 - 135 270
'THL : 10.55 ns/pFI CL • 37.5 ns 15 - 110 220
Propagation Delay Time - A, B, C. 0 Inputs tPLH ns
tPLH • 10.40 ns/pFI CL' 620 ns 5.0 - 640 1280
tPLH • 10.25 ns/pFI CL • 237.5 ns 10 - 250 500
'PLH < 10.20 ns/pFI CL • 165 ns 15 - 175 350
tPHL: 11.3 ns/pFI CL' 655 ns 'PHL 5.0 - 720 1440 ns
'PHL' 10.60 ns/pFI CL' 260 ns 10 - 290 580
'pHL' 10.35 ns/pFI CL' 182.5 ns 15 - 200 400
Propagation Delay Time - RBI Input tpLH ns
'pLH • 10.30 ns/pFI CL' 305 ns 5.0 - 600 750
lPLH : 10.25 ns/pFI CL' 117.5 ns 10 - 200 300
tPLH • 10.15 ns/pFI CL • 92.5 ns 15 - 150 220
lpHL : 10.85 ns/pF I CL • 442.5 ns tPHL 5.0 - 485 970 ns
lPHL' 10.45 ns/pF) CL' 177.5 ns 10 - 200 400
tPHL' 10.35 ns/pF) CL' 142.5 ns 15 - 160 320
Propagation Delay Time Bllnput lPLH ns
lPLH " 10.3 ns/pFI CL' 305 ns 5.0 - 600 750
'PLH • 10.25 ns/pF} CL • 117.5 ns 10 - 200 300
tPLH = 10.15 ns/pFI CL' 92.5 ns 15 - 150 220
'PHL' 10.85 ns/pFI CL • 442.5 ns tpHL 5.0 - 485 970 ns
tPHL = 10.45 ns/pF I CL • 177.5 ns 10 - 200 400
tpHL = 10.35 ns/pFI CL • 142.5 ns 15 - 160 320
Propagation Delay Time LT InpOt
. lPLH ns
lpLH = 10.45 ns/pF) CL' 290.5 ns 5.0 - 313 625
tPLH 10.25 nslpF) CL + 11,2.5 os
:c: 10 - 125 250
tpLH = 10.20 ns/pFI CL • 80 ns 15 - 90 180
tPHL' 11.3 ns/pFI CL' 248 ns tPHL 5.0 - 313 625 ns
'PHL' 10.45 ns/pFI CL' 102.5 ns 10 - 125 250
lPHL' 10.35 ns/pFI CL • 72.5 ns I 15 - 90 180
Minimum Setup Time
'ou
5.0 - 90 180 ns
10 - 38 76
15 - 20 40
Minimum Hold Time
I" 5.0 - -90 0 ns
10 - -38 0
15 - -20 0
Minimum Latch Enable Pulse Width 'WLILE) 5.0 - 260 520 ns
10 - 110 220
15 - 65 130
20"1 -1
90" I
. 50".!.
Inpute 10YI
-J VSS
outP:::H~~VOH
--=fL tTLH
JtVOL
tTHL.
~-----------VOH
Output 9 \
_.-----------VOL
I I .-J 1.-.20 ns
20 nS-t ,.-. I ~I V
90"U':
50" ,
00
'0" -----VSS
tWLILE) -l ~
II
LIQUID CRYSTAL (LCI READOUT

Excitation
(Squar. Wave,
VSS to VOOI
•• A filament pr.-warm resistor is recommendttd to reduce filament

thermal shock and incr.aM the effective cold r.,i,tance of the
filament.
A7
14 b
13 c
12 d
11.
17 f
C2
16.
MC145138
o 0 0 0 o 0 0 1
(01 (11
I I
I I
II
MC145138 MC145139 MC,45138 MC14513B MC14513B MC,4513B
o 1 0 1 o 0 0 0 o 0 0 1 o 0 1 o 0 0 0 o 0 0 a
(5) (0) (I) (31 (0) (0)
® MOTOROLA
1024-BIT READ ONLY MEMORY

The MCM14524 is a complementary MOS mask programmable
Read Only Memory (ROM). This device is ordered as a factory spe-
cial with its unique pattern specified by the user.
1024-BIT
This ROM is organized in a 256 x 4-bit pattern. The contents of
(256 X 4)
a specified address « AD, A I, A2, A3, A4, A5, A6, A7 >1 will
appear at the four data outputs (BO, B I, B2, B31 following the READ ONLY MEMORY
negative going edge of the clock. When the clock goes high, the data
present at the output will be latched. The memory Enable may be
taken low asynchronously, forcing the data outputs low and reset-
ting the output latches. This device finds application wherever low
power or high noise immunity is a design consideration.
• Noise Immunity = 45% of VDD typical
• Quiescent Current - 10 nA/package typical @ 5 Vdc L SUFFIX PSUFFIX
• Single Supply Operatioh - Either Positive or Negative.
~ASE 620 CASE 648
• Memory Enable AlloYl(s Expansion
• Output Latches Provide a Useful Storage Register
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driv.ing Two Low-power TTL Loads, One Low-power ." •• "'11:;5UII;. L
Oenot ••
Ceramic Package
Schottky TIL Load to Two HTL Loads Over the Rated Temper-
P Pla,tic Package
ature Range
A Ext.nded Operating
Temperatur. Range
e limited Operating
Temperatur. Range
Memory Addr •••

Matrix Oecoder
(32.8) (' of8)
Addr •••
(32.81 Decoder
1 of 32 (' of 8)
Addre ••
Oecod ••..
Addr •••
(32.8) Oecod.
(' of 81
Add' ••
(32.81 Decoder
(. of 81
DC Supply Voltage VOO -0510·'8 Vdc
Input Vultage. All Inputs Von -0.5 to VOO + 0.5 Vdc
DC Curren I oralO per Pin I 10 mAde
Operating Temperature Range AL DeVice TA -5510+125 DC
CL!CP DeVIce -40 to +85
Storage Temperature Range T 519 -6510·'50 DC
Voo TI_
. 25°C Th •••••
CharKteristic Symbol Vdc Min Ma. Min Typ Ma. Min Ma. Unit
II Output Voltage "0" Level
''1'' Level
VOL
VOH
5.0
10
15
5.0
10
15
-
-
-
4.99
9.99
14.99
om
om
0.01
-
-
-
-
-
-
4.99
9.99
14.99
0
0
0
5.0
10
15
0.01
0.01
0.01
-
-
-
-
-
4.95
9.95
14.95
0.05
0.05
0.05
-
-
-
Vdc
Vdc
Noise Immunity 11- VNL Vdc

I Vout .0.8 Vdc) 50 1.5 - 1.5 2.25 - 1.4 -
( ·V out ~. 1.0 Vdcl 10 3.0 - 3.0 4.50 - 2.9 -
(Naut •...1.5 Vdcl 15 3.15 - 3.15 6.15 - 3.15 -
f Vout •• 0.8 Vdc) VNH 5.0 1.4
_.
1.5 2.25 1.5 - Vdc
I VOU! •.•1.0 Vdcl 10 2.9 3.0 4.50 - 3.0 -
('Vout •...1.5 Vdcl 15 3.65 - 3.15 6.75 - 3.15 -
OutPut Drive Current IAL Devicel 'OH mAde
{VOH • 2.5 Vdcl Source 5.0 -1.2 .. ··1.0 -1.7 - -0.7 -
(VOH • 4.6 Vdel 5.0 -0.25 - -0.2 -0.36 -0.14 -
{VOH • 9.5 Vdcl 10 -0.62 - -0.5 -0.9 - -0.35 -
(VOH' 13.5 Vde) 15 -1.8 - -1.5 -3.5 - -1.1 -
(VOL' 0.4 Vdel Sink 'OL 5.0 0.64 - 0.51 0.88 0.36 - mAde-
IVOL • 0.5 Vdel 10 1.6 - 1.3 2.25 - 0.9 -
(VOL ·1.5Vdel 15 4.2 - 3.4 8.8 - 2.4 -
Output Drive Current (ClICP Device) 'OH mAde
(VOH • 2.5 Vdel Source 5.0 -1.0 - -0.8 -1.7 -0.6 -
IVOH' 4.6 Vdel 5.0 -0.2 - -0.16 -0.36 - -0.12 -
IVOH • 9.5 Vdel 10 -0.5 - -0.4 -0.9 - -0.3 -
(VOH' 13.5 Vde) 15 -1.. - -1.2 -3.5 - -1.0 -
(VOL' 0.4 Vdel Sink 'OL 5.0 0.52 - 0.44 0.88 - 0.36 - mAde
{VOL' 0.5 Vdel 10 1.3 - 1.1 2.25 - 0.9 -
{VOL' 1.5 Vdcl 15 3.6 - 3.0 8.8 - 2.4 -
Input Current IAl OevK:el lin 15 - -0.1 - '0.‫סס‬OO1 '0.1 .- ".0 IlAdc
Input Current (CL/CP Oev;cel lin 15 - '1.0 - '0.‫סס‬OO1 '1.0 - t100 ".Adc
Input Capacitance C.n - - - - 5.0 - - - pF
(Vin·OI
Quiescent Current (AL Device)
'DO 5.0 - 5.0 - 0.010 5.0 - ISO ~Adc
(Per Package) 10 - 10 - 0.020 10 - 300
15 - 20 - 0.030 20 - 600
Quiescenl Currenl (CLlCP Devicel 100 5.0 - 50 - 0.010 SO - 315 ~Adc
(Per Packaget 10 - 100 - 0.020 100 - 1SO
15 - 200 - 0.030 200 - 1500
Total Supply Current- - t IT 5.0 'T' (1.6 ~A/kHzl' + 'DO ~Ade
(Dyn-"ic plus Quiescent, 10 IT' (32 ~A/kHzl' + 100
Per Packagel 15 IT' 14.8 ~A/kHzI I + 100
tCL = 50 pF on all outputs, all
buffers switchingl -
-Tlow• -55°C for AL Device, "'OoC for CLlCP Device.
Thigh· +12SoC for AL DeYice. +8SoC for CL/CP Device.
~oise immunity specified for worst-case input combination.
tTo c"culate total supply current at loads other than SO pF:
IT'CL) = ITI50 pFI + 1 • 10-3 {CL -SOl VOO'
where: IT is in ~A (per pack." CL in pF. VOO in Vdc. and f in kHz is input frequency.
--The formulas gi•••n are for the typicall cheracteristics only at 25°C.
a..-iItlc Symbol VDD Min Typ Mox Unit
OutPUt Rile Time tTLH no
tTLH. tTHL • 13.0 nl/pFI CL + 30 no 6.0 - 180 380
tTLH.tTHL· (1.6 nl/pFI CL + 16 no 10 - 90 180
tTLH. tTHL· (1.1 nilpFI CL+ 10 nl 16 - 66 130
Output Fall Time tTHL nl
tTLH.tTHL· (1.6 nl/pFI CL + 26 nl 6.0 - 100 200
tTLH. tTHL· (0.76 nilpFI CL + 12.6 nl 10 - 50 100
tTLH tTHL· (0.56 nl/pF) CL + 9.6 nl 16 - 40 80
Clock Read Access Oeley Time 'oc:cC nl
toc:cC· (1.7 nilpFI CL + 1266 nl 6.0 - 1360 4000
toc:cC· (0.66 nllpF) CL + 517 no 10 - 660 1600
toc:c" • (0.6 nslpFI CL + 325 nl t 16 - 360 1200
Enoble Access Oeley Time tecCEn nl
'OC:CEn-11.7 nllpF) CL + 160 nl 6.0 - 245 616
'OC:CEn- 10.66 nllpF) CL + 77 nl 10 - 110 265
tOC:CEn• (0.6 nl/pFI CL + 60 nl 16 - 76 190
Clock Pulse Wid'ht 'WH 6.0 460 160 - ns
10 166 56 -
16 126 35 -
'WL 6.0 3600 1200 ns
10 1426 476 -
16 1070 300 -
Moximum Low Clock Pulse Width # 'WL 6.0 2.0 10 - ml
10 0.9 3.0 -
16 0.1 0.3 -
Address Setup-Time 'su(A) 6.0 0 0 - nl
10 0 0 -
15 0 0 -
Add, ••• Hold Time 'MAl 6.0 0 0 - nl
10 0 0 -
16 0 0 -
Clock '0 Enoble Se'up Time 'sulell 6.0 4276 1426 - nl
10 1726 675 -
16 1296 400 -
Clock '0 Enoble Hold Time 'h(ell 6.0 160 0 - nl
10 76 0 -
16 66 0 -
The formulae given are for typical characteristics only.
t The clock can remain high indefinitely with the date remaining latched .
• If clock stays low too long, the dynamically stored data will leak off and will have to be recalled.
Not •• :
Not.:
1. Source current, add' ••• ROM to obtain. "1"
Addr ••• ROM to obtain lavel change when
on all four outputs (80 thru 931.
clocking any ona -cf4' •• lin •.
2. Sink curr."t, addr ••• ROM to obtain a "0"
on all four outputs (SO thr •.•83).
., u••••Clock to
RoodM_y
Addr ••
Input
.~=_~
·Oao Outputl atwav. go to the logic ." •• stat. b.tor. the data I, ..,elk!
betwMn .cc ••• lng .uc:c••• iva "0'."
•• OutPuts forced to "0" by Enable.
A'~::t" A_d_d_'_._"_V_._'_id ~
AddreSllnputs:
Words .e' numbered 0 thrbugh 255 and ••• ddreued using
_quanti.1 -sdreuing of Address lead, AO through A 7 with AO
as the lent lignifiC'M'lt di git.
Logic "0" i. dofin.d ••• "'ow" Addr ••• input IV,L).
Logic 'T' i. defined ••• "high" Addre •• input IVIHI.
~
WORD A7 A6 A5 A4 A3 A2 Al AO
Word 0 0 0 0 0 0 0 0 0
Wo~ 1 0 0 0 0 0 0 0 1
Word 2 0 0 0 0 0 0 1 0
Word 3 0 0 0 0 0 0 1 1
_d 255 1 1 1 1 1 1 1 1
Voo ~ vss
vss~ voo BINARY TO HEXA·

DECIMAL CON·
X
VERSION TABLE
BINARY
WORD CARD
ESIRED CHARACTER
o 000 0
o 0 0 1 1
o 0 1 0
o 0 , , 2
J
o 10 0 4
o , o , 5
o , 1 0 6
o , 1 1 7
A binary coded decimal equivalent of each desired output may
be punched in stendard computer cards (four c.ds are requtred ,
1 o 0 0
o 0 1
8
9
for all 256 words) in numerical lword number) order. 64 words 1 o 1 0 A
per card are punched in columns 12 thru 75 using the Binary to 1 o 1 1 8
Hex~ecjm81 conversion table. Columns 77 and 78 are used 1 1 o 0 C
1 1 o ,
,,,,
0
to number the cards. which must be in numerical order. Please 1 , 0 E
use characters as shown in the table when punching computer c.d •. 1 F
SAMPLE WORD
ADDRESS INPUTS OUTPUTS
WORD CARD
NUMBER A7 A6 A5 A4 A3 A2 Al AO B3 B2 Bl BO CHARACTER
0
, 0
0
0
0
0
0
0
0
0
0 0
0 0
0
0
1
0
0
0
0
0
1
0
1
0
J
Shown in column.
12 - 150n urd
2 0 0 0 0 0 0 1 0 0 0 1 1 J
} below
J 0 0 0 0 0 0 1 1 0 0 0 0 0
255 1 1 1 1 1 1 1 1 1 0 1 0 A
c.nI
WORD NUMBER No.-,
• I 1 ) 4 'I 1 • t It II 11 U '4 I~ •• 11 II " l't 11 11 n 14 1S no lJ 11 " • ], n u ,.. » ]I ]1 )I JS ••• u u u u ., u ., u " •• il U U '" \\ YO" ••••••• 51 53 "
•••• , ••• ' •• 1'01111111111111111111111111111111111111111111111111111111111111'10'1

I .1.11 1".lllIIIM"~ltMn."DnM"."ft".nRUMD.U ••• UQU¥ •• " •• Wi'U~MUY"MH.~UU"UU"M._llnnNnN"n".
11111111111111111111111111111111111111111111111111111111111111111111111111111111
22222222222222222222222222222222222222222222222222222222222222222222222222222222
33333333333311333333333333333333333333333333333333333333333333333333333333333333
44444444444444444444444444444444444444444444444444444444444444444444444444444444
55555555555555555555555555555555555555555555555555555555555555555555555555555555
•• I.i ••• IIIII.111111111111111111111111161111111111111611111111116111111111111111
7177717711171 71 7 71 71 711 71 7 71 711 71 71717 71 7 711 7 7171171 71 711 71 7 71 7 71 71 711 7 11 7 7 71 7 1 7
••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 1••• 1.11.
""""""""""""""""""."""""""","""""""""""""
I .J.""tMlllIIINB"I'M".llun~nMJI.8.JlgQW.~"
G&..c.ENO.1 STAND&IIO
,OMIt $0.'
••• 'IUU.U.U.~.SINUWU.UWHM~~""QM":ln"~nnN~~.II.~.
For customers who do not have Ieee•• to punch e-rd •• Motaroll
will accept Truth T.blel. When filling out the table, use the 0 to F
hexidecinwl character in column "C".
WOflD C WORD C WORD C WORD C WORD C
II
0 51 102 153 204
1 52 103 154 205
2 53 104 155 206
3 54 105 156 207
4 55 106 157 208
5 56 107 158 209
6 57 108 159 210
7 58 109 160 211
8 59 110 161 212
9 60 111 162 213
10 61 112 163 214
11 62 113 164 215
12 63 114 165 216
13 64 115 166 217
14 65 116 167 218
15 66 117 168 219
16 67 118 169 220
17 68 119 170 221
18 69 120 171 222
19 70 121 172 223
20 71 122 173 224
21 72 123 174 225
22 73 124 175 226
23 74 125 176 227
24 75 126 177 228
25 76 127 178 229
26 77 128 179 230
27 78 129 180 231
28 79 130 181 232
29 80 131 182 233
30 81 132 183 234
31 82 133 184 235
32 83 134 185 236
33 84 135 186 237
34 85 136 187 238
35 86 137 188 239
36 87 138 189 240
37 88 139 190 241
38 89 140 191 242
39 90 141 192 243
40 91 142 193 244
41 92 143 194 245
42 93 144 195 246
43 94 145 196 247
44 95 146 197 248
45 96 147 198 249
46 97 148 199 250
47 98 149 200 251
48 99 150 201 252
49 100 151 202 263
50 101 152 203 254
255
® MOTOROLA
The MCM 14537 is a static random accessmemory (RAM) organ-

ized in a 256 x l·bit pattern and constructed with MOS P-channel
and N-channel enhancement mode devices in a single monolithic
structure. The circuit ·consists of eight address inputs (AnI, one data 256-BIT (256 X 1) STATIC
input (Din), one write enable input (WEI, one strobe input (ST). two
II
chip enable inputs (CEn). and one data output (Dout).
Using both chip enable inputs as extensions of the address inputs,
a lO-bit address scheme may be employed. Four MCM14537 devices
may be used to comprise a 1024-bit memory without additional
address decoding. The CE and ST inputs are dissimilary designed to
enable usage of the memory in a variety of applications. An output
latch is provided on the chip for storing the data read or written into
memory, making a data-out storage register unnecessary. The CE
inputs control the data output for third·state (high output imped-
ance) or active operation which makes the memory very useful in a
L SUFFIX P SUFFIX
bus oriented system. When CE2 is high the chip is fully disabled.
When CE 1 is high the output is in the third state but data can be
CASE 620 CASE 648
written into the output latch during a read cycle. This enables the
use of the memory for fast reading by using the CE 1 input to enable
the latch. The memory is also designed SO that dc signals can operate
the memory with no maximum pulse width required on the CE and SuffiX Oenot ••
ST lines.
Medium speed operation and micropower operation make the L Co,om,c Pock •••
device useful in scratch pad and buffer applications where micro·
Extended Operating
power or battery operation and high noise immunity are required.
Temperatur. Range
• Quiescent Current = 0.5 /lA/package typical @ 5 Vdc ~ : Limited Operating
Temperetur. Range
• 3·state Output Capability for Memory Expansion
• Output Data Latch Eliminates Need for Storage Buffer
• Access Time = 700 ns typical @VDD = 10 Vdc
• Fully Decoded and Buffered
• Supply Voltage Range = 3.0 Vdc to lB Vdc
• Capable of Drivirlll Two Low·power TTL Loads, One Low-power
Schottky TTL Load or Two HTL Loads Over the Rated Temper·
ature Range
MAXIMUM RA TI NGS (Voltages referenced to Vss I

Rating Symbol Value Unit This device contains circuitry to protect
OC Supply Voltage VOO -0.5 to +18 Vdc voltages or electric fields; hOMver. it is
Input Voltage, All Inputs Vi" -0.5 to VOO + 0.5 Vdc advised that normal precautions be taken
DC Current Drain per Pin I 10 mAde to avoid application of any voltage higher
than maximum rated Yoltages to this high
Operating Temperature Range - AL Device TA -55 to +125 °c impedance circuit. For proper operation it
CL/CP Oevice -40 to +85 is recommended that Vin and Vout be
Storage Temperature Range Tstg -65 to +150 °c constrained to the range VSS <; (Vin or
Voutl <; VOO'
Unuse~ inputs mutt always be tied to an
appropriate logic yoltage level (e.g., either
Vssor VOOI.
Voo TI_
. 2SoC Th·•••••
Characteristic Symbol Yd. Min Ma. Min Typ Ma. Min Ma. Unit
Ou tpu I Vol tage "0" Level VOL 5.0 - 0.05

_. 0 0.05 0.05 Yd.
Vin-VODorO 10 - 0.05 - 0 0.05 - 0.05
15 - 0.05 - 0 0.05 - 0.05
"I" Level VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vd.
vin ., 0 or VOO 10 9.95 - 9.95 10 - 9.95 -
15 14.95 - 14.95 15 - 14.95 -
Noise Immunity It VNL Vd.
IWou'" 0.8 Vd.) 5.0 1.5 - 1.5 2.25 - 1.4 -
(!..Vout " 1.0 Vdcl 10 3.0 - 3.0 4.50 - 2.9 -
(I\Vout " 1.5 Vdd 15 4.5 - 4.5 6.75 - 4.4 -
I·Wou' " 0.8 Vdcl VNH 5.0 1.4. - 1.5 2.25 - 1.5 - Vd.
('Vout" 1.0Vdcl 10 2.9 - 3.0 4.50 - 3.0 -
(.\Vout ••. 1.5 Vdcl 15 4.4 - 4.5 6.7~ - 4.5 -
Output Drive Current IAL Device) 10H mAde
1VOH = 2.5 Vdcl Source 5.0 -1.2 - -1.0 -1.7 - -0.7 -
1VOH = 4.6 Vdcl 5.0 -0.25 - -0.2 -0.36 - -0.14 -
1VOH = 9.5 Vdcl 10 -0.62 - -0.5 -0.9 - -0.35 -
(VOH = 13.5 Vd.1 15 -1.8 - -1.5 -3.5 - -1.1 -
1VOL = 0.4 Vdcl Sink 10L 5.0 0.64 - 0.51 0.88 - 0.36 - mAde
(VOL = 0.5 Vdcl 10 1.6 - 1.3 2.25 - 0.9 -
(VOL = 1.5 Vdc) 15 4.2 - 3.4 8.8 - 2.4 -
Output Drive Current (CLlCP Device) 10H mAde
1VOH • 2.5 Vdcl Source 5.0 -1.0 - -0.8 -1.7 - -0.6 -
1VOH • 4.6 Vdcl 5.0 -0.2 - -0.16 -0.36 - -0.12 -
1VOH • 9.5 Vdcl 10 -0.5 - -0.4 -0.9 - -0.3 -
(VOH' 13.5 Vdcl 15 -1.4 - -1.2 -3.5 - -1.0 -
(VOL' 0.4 Vdc) Sink 10L 5.0 0.52 - 0.44 0.88 - 0.36 - mAde
1VOL = 0.5 Vdc) 10 1.3 - 1.1 2.25 - 0.9 -
(VOL' 1.5 Vdc) 15 3.6 - 3.0 8.8 - 2.4 -
Input Current IAL Device) lin 15 - '0.1 - '0.‫סס‬OO1 '0.1 - ± 1.0 IolAdc
Input Current fCLlCP Device) 'in 15 - ,1.0 '- '0.‫סס‬OO1 '1.0 - ,14 ~Adc
(Vin' 0)
Quiescent Current IAL DevK:et 100 5.0 - 100 - 0.5 100 - 1800 "Adc
(Per Package) 10 - 200 - 1.0 200 - 3600
15 .. 400 - 1.5 400 - 7200
QUiescent Current (CLlCP DevICe) 100 5.0 - 100 - 0.5 100 - 1800 ,..Adc
IPer Package) 10 - 200 - 1.0 200 - 3800
15 - 400 ~ 1.5 400 - 7200
Total SupplV Current· • t IT 5.0 IT = 11.46 uA/kHz) " 100 ,..Adc
(Dynamic plus Ouiescent, 10 IT = 12.91 uA/kHz) I • 100
Per Package) 15 IT = 14.37 uA/kHz) I • 100
teL = 50 pF on all outputs. all
buffers SWitching)
Three-State Leakage Current ITL 15 - '0.1 - -0.‫סס‬oo1 ±O.l - ,3.0 uAdc
(AL Devicel
Three·State Leakage Current ITL 15 - '1.0 - -0.‫סס‬oo1 , 1.0 - , 7.5 ,.Adc
ICLlCP Oev;ce)
·Tlow ,.. -5SoC fOr AL Device. -40oC for CL/CP Device.

Thigh .12SoC for AL Device. +8SoC for Cl/CP Device.
:II:
-Noise Immunity specified for worst-case input combination.

No;se Margin lor bo.h "I" and "0" level • 1.0 Vdc min@lVOO '5.0 Vdc
2.0 Vdc min i> VOO • 10 Vdc
2.5 Vdc m;n @ VOO • 15 Vdc
tTo calculate total supply current at loeds other than SO pF:
ITICL) = ITI50 pFI • 1 • 10-3 leL -SOl VOO'
where: 'T is in,.A «per package), Cl in pF. VOO in Vdc. and f in kHz is input frequency.
··The formul. given are for the typical ch.,ac::teristic:s only·at 2SoC.
Charecteristic Figur •... Symbol VOO Min Typ MIl" Unit
Output Rile Time 3 'TLH n.
tTLH· 13.0n.!pFI CL + 30 n. 5.0 - 180 360
'TLH· (1.5 n.!pFI CL + 15 n. 10 - 90 180
tTLH· 11.1n.!pFI CL + 10 n. 15 - 65 130
Output Fall Time 3 tTHL n.
,THL· 11.5n.!pFI CL + 25 n. 5.0 - 100 200
tTHL· 10.75n.!pFI CL + 12.5 n. 10 - 50 100
tTHL· 10.55 n.!pFI CL + 9.5 n. 15 - 40 80
Read Acce" Time from ST or CE2 4,5 'ecclAI n.
'eee· (1.4 n.!pF) CL + 2480 n. 5.0 400 2500 6000
'aCe· (0.7 n.!pF) CL + 690 n. 10 150 700 2000
'eee • 10.5n.!pF I CL + 393 n. 15 115 400 1500
Ou,pu' Enlble DIllY from CEI or CE2 5,6 'ecclcrnl 5.0 70 300 900 n.
10 25 100 300
15 20 70 225
Setup Time from An to ST or CE2 4.5,6,7 '.uIA) 5.0 1800 600 - n.
10 600 200 -
15 450 140 -
Hold Time from An to ST or CE2 4.5,6.7 'hlAI 5.0 600 200 - ns
10 240 80 -
15 180 55 -
Data Hold Time 7 'hlol 5.0 1400 480 - n.
10 500 160 -
15 375 110 -
Data Setup Time 7 '.u(o) 5.0 3600 1200 - n.
10 1800 600 -
15 1350 420 -
Write Enable Hold Time 7 'hlWE) 5.0 150 50 n.
10 60 20 -
15 45 15 -
Write Enable Setup Time 7 '.u(WEI 5.0 720 240 n.
10 240 80 -
15 180 55 -
Write Enable to 00ut Disable" 4 'WE 5.0 720 240 - n.
10 240 80 -
1.5 180 55 -
strObe or CE2 Pulse Width When Reeding 4.5.6 'WLIAI 5.0 '350 450 - ns
10 450 150 -
15 340 100 -
Strobe, eEl or CE2 Pulse Width When Writing 7 'WLIW) 5.0 2400 1200 - ns
10 1260 600 -
15 945 420 -
Write Recovery Time 4 'AIW) n.
'W· (1.4 ns!pF) CL + 219 ns 5.0 70 240 720
'W· (0.7 n./pF) CL + 70 n. 10 25 80 240
'W - 10.5n.!pF) CL + 47.5 ns '5 20 55 180
eEl or CE2 to 00ut Disable Delay·· 6 'CEn 5.0 70 300 900 ns
10 25 100 300
15 20 70 225
Read Setup Time 4.5 "uiAI 5.0 0 -100 - n.
10 0 -40 -
15 0 -30 -
Read,Hold Time 4.5 'hlRI 5.0 540 180 - n.
10 240 60 -
15 180 45 -
Read Cycle Time 4,5 'eyclRI 5.0 - 2500 6000 n.
10 - 700 2100
15 - 500 1575
Write Cycle Time 7 'cycIW) 5.0 - 1400 4800 n.
10 - 700 2100
15 - 500 1575
Voo
AO
Al
A2
A3
A4
Output Source Output Sink
AS Input Characteristics Characteristics
AS Cout
WE Pulse Once Pulse Once
A7
Din SW1 in Position 1 SW1 in Position 2
ST
D
VGS -VOO VOO
WE
VOS Vout - VOO Vout
CEI
VOO 01
CE2
SWI Din
VSS 02
Al
Pulse
Generator
1
(~
\_--
A2
Pulse
A3
Generator
A4 2
AS
AS Dout
Output IOout) -------\~ ~I
A7
ST
WE
CEI
CE2
Ojn
VSS
« VOO
AO
Al
A2
Pul •• A3
Gener.tor
1 A4
AS
AS Dout
P.G.2
P.G.3
P.G.•
A7
ST
WE
CEI
to,
P.G.5 CE2
P.G.S Din
ivss
Address
Inputs
(An)
NOTES: , High impedance output state occurs when WE is mamtained as a logical

"0" (low level).
The output momentarily displays data from the previous state.
For read operation, WE may be maintained at a logical "'" (high level)
during the complete cycle.
4 CE' and CE2 are maintained at a logical "0" state (low level).
5 All input rise and fan times are 20 ns.
~~~~~:s yO% ~--------VDD
lAn' _ ~------t'-U-IA-)
----------t-h-IA-'=J "---------VSS
~
tWL(All
,1-'"''' ,--------VDD
~%
---------- VSS
NOTES: , High Impedance output state occurs when CE' or CE2 is maintained
in the logical "'" state (high level).
The output momentarily displays data from .the previous state.
For read operation, WE may be maintained at a logical "'" (high level)
during the complete cycle.
4 All input' ise and fall times are 20 ns.
5 tWL(Al.~tacc(A)max
VOO
2f
Address
...,~~
Inputs
(Ani
VSS
,
tWL(R2)
VOO
CE2 lID
VSS
CEl
Idelav{CE21
I -- VOO
NOTES: 1 High impedance output state occurs when eEl or CE2 is maintained
in the logical "'" state (high level).
2 WE is maintained at the logical "'" state for this example.
3 All input rise and fall times are 20 os
4 'delav(CE2) minimum assuares that only data presently addressed
will appear at the output.
tdelay(CE21 min." taceR max. - tacclCE1) min.
5 tWl1R2) ~td.tay (CE21 min t tace (CEn) me.
Addre" ~~.o-,,---------voo
Inputs
IAn)
---------------------~/I"~--------
',utA)]
~ ••:-----t-W-L-(W-I--tcv~IWI thlAI_1 "I VSS
Strobe or
eEl or CE2
(ST, CEl, CE2)
NOTES: 1 The Strobe, eEl and CE2 may be utilized to control a write cycl.,
however, during changes of address either Strobe or CE2 must
be in the logical ."" .tat. (high 1...,.1).
2 Data input logic levell, don't cln during the indicated interval,.
3 Data Input logic lawl must ramain fixed.
• Wr.ita Enabla may be maintained a' a logical "0" during the write cycle.
S All Input ri. and fell tim •• are 20 ns.
16 x 16 x 1
Memory
Array
I
I
I
I
I
I
I I
L _ _ __ J
FUNCTION CE, CE2 ST WE Din Dout COMMENTS
Address changing
X X
, X X AlA
O...iW.J: will be acti~e_if CE 1 ~nd
CE2 = "0" and WE" "1".
valid CE2" "1", fully disables internal
X 1 X X X A
logic and output.
Address changIng Changing address in this mode

X 0 0 X X AlA
not valid may result in altered data.
CE 1 = "1" disables write cycle

00ut disabled in 1 X X X X A
and Cout'
high resistance state
X 1 X X X A The chip is fully disabled.
WE r "0" enables writing into

X X X 0 X A memory if CE 1, CE2, and
S'f = "0".
If ST '"' "''', the-output stores

00ut enabled in
0 0 X 1 X A and reads the previous data
active state
from or written into memory.
The output reads the pre.nt
0 0 0 1 X A
contents that are addressed.
Aead addresMd
The addressed location is read
memory location
1 0 0 1 X A into output latch with output in
into output latch.
OiMble reading X , X X X A
the "A" state.
Address changing can take

from memory X X 1 X X AlA place in this condition.
Din is written into memory

Write into memory 0 0 0 0 A A
Write disabled , X X X X A
and into the output latch
WE'" "'" is a read enable.

X 1 X X X A WE: s "0" is. write enabla.
X X 1 X X AlA
X X X 1 X AlA
A = High resistance state at 00ut

A'" An active level of either vSs·or VOO
AlA" An A or A condition depending on the don't care condition
X" Oon't care condition (must be in thu "'" or "0" state)
1 = A high level at VOO
0= A low level ilt VSS
® MOTOROLA
BCD-TO-SEVEN SEGMENT LATCH/DECODER/DRIVER

for LIQUID CRYSTALS
BCD-TO-SEVEN SEGMENT
The MC 14543B BCD-to-seven segment latch/decoder/driver is for
designed for use with liquid crystal readouts, and is constructed with LIQUID CRYSTALS
complementary MOS (CMOS) enhancement mode devices. The cir-
cuit provides the functions of a 4·bit storage latch and an 8421 BCD·
to-seven segme~t decoder and driver. The device has the capability
to invert the logic levels of the output combination. The phase (Ph),
blanking (BI), and latch disable (LD) inputs are used to reverse the
truth table phase, blank the display, and store a 8CD code, respec-
tively. For liquid crystal (LC) readouts, a square wave is applied to
the Ph input of the circuit and the electrically common backplane
of the display. the outputs of the circuit are connected directly to
the segments of the LC readout. For other types of readouts, such
as light-emitting diode (LED), incandescent, gas discharge, and
fluorescent readouts, connection diagrams are given on this data
sheet. L SUFFIX P SUFFIX
Applications include instrument (e.g., counter, DVM etc.) display CERAMIC PACKAGE PLASTIC PACKAGE
driver, computer/calculator display driver, cockpit display driver, CASE 620 CASE 64e
and various clock, watch, and timer uses.
• Logic
5 Vdc
Circuit Quiescent Current 5.0nA/package typical @
MC14XXXB~SU~fiXC.::i:t::Ck .. e

LP Pla,tic Package
• Blank ing Input Temperatur. Range
• Readout Blanking on All Illegal Input Combinatiohs e Limited Operating
Temperatur. Range
• Direct LED (Common Anode or Cathode) Driving Capability
• Capable of Driving Two Low-power TTL Loads, One Low·power
.
Schottky TTL Load or Two HTL Loads Over the Rated Temper- INPUTS OUTPUTS
ature Range ,
• Pin-for-Pin Replacement for CD4056A (with Pin 7 Tied to VSSI.
LO 8' Ph' D C 8 A. b d f
• Oi~.v
,
X
, 0 X X X X 0
,, , ,,
0 0 0 0 0 0 BI.nII.
, 0 0 0 0 0
,
0
, , 1 0 0
, 0 0 0 0
,
0 0
, , , , 0 0 0 0 1
,
,,
0
0
0
0
0
0
0
,
0 t ,
0
1 , ,
,
0
,
, ,
I
I
0
0
0
2
3
0 0 0
,, 0
,
0 0
, , ,
1 0 0
••
0 0 0 0 1
,,, ,,,
0 I 0
•
,,, ,
I 0 0 0
,, 1 0 0 I 1
0 0 0
, , ,, , ,
I 0 0 0 0 1
Symbol V.lue Unit

0 0
, 0 0 0
,,
1
, I 8
•
R.ting
, 0 0
, , 0 0 I 1 I 0 t
OC SupplV Voltage VOO -0.5 to +18 Vdc

,
1
0
0
0
0
, ,
1
,
0
0 ,
0 0
0
0
0
0 0
0 0
0
0
0
0
0
0
Blenk
Blenk
Input Voltage. All Inputs Vin -0.5 to VOO +0.5 Vdc , 0 0

, , 0 0 0 0 0 0 0 0 0 Blenk
, 0 0
, , 0 1 0 0 0 0 0 0 0 8lenk

, 0 0
,, ,I
,
0 0 0 0 0 0 0 0 Blenk
Operating Temperature Range - AL Device TA -55 to +t25 °c 0

0
0
0
0 X X X X
0 0 0 0
.. 0 0 0
..
Blenk
..•...
CL/CP Oevice -40 to +85
1 1 I , Inv.rse of OutPut Displ.v
Storage Temperature Rance Tstg -65 to +150 °c Combinetions
A••••
Maximum Continuous Output Drive Current IOHm,x 10 mAde
(Source or Sjnk~ per Output IOLmax X· Don't cer.
t • AboYt>Combine dons
Maximum Continuous Output Power· POHmax 70 mW •• For liquid crystel rudouts, IPPtv • IQUW• ...-ve to· Ph.
(Source or Sink) per Output For common cethode LED rudouts. "eet Ph • o.
POLmax
For common .node LED f'NdOutt. select Ph • 1.
'POHmax B IOH (VOH - VOO) end POLmax = IOL (VOL - VSS) ••• Depends upon the BCD code pr••••touav epplied when LD • 1
Voo Tlow· 25°C Thi h·
Characteristic Symbol Vdc Min M•• Min Typ MI' Min MI' Unit
Output Voltage "0" Level VOL 5.0 - 0.05 - 0 0.05 - 0.05 Vde
Vin = VOO or 0 10 - 0.05 - 0 0.05 - 0.05
15 - 0.05 - 0 0.05 - 0.05
"". Level VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vde
Vin = 0 or VOO 10 9.95 - 9.95 10 - 9.95 -
15 14.95 - 14.95 15 - 14.95 -
Input Voltage" "0" Level V,L Vdc
(VO" 4.5 or 0.5 Vdcl 5.0 - 1.5 - 2.25 1.5 - 1.5
1VO " 9.0 or 1.0 Vdcl 10 - 3.0 - 4.50 3.0 - 3.0
(VO = 13.5 or 1.5 Vdel 15 - 4.0 - 6.75 4.0 - 4.0
"'" Level V,H
1VO = 0.5 or 4.5 Vdel 5.0 3.5 - 3.5 2.75 .. 3.5 - Vdc
1VO = 1.0 or 9.0 Vdel 10 7.0 - 7.0 5.50 - 7.0 -
(VO = 1.1; or 13.5 Vdel 15 11.0 - 11.0 8.25 - 11.0 -
Output Drive Current (AL De••••
ice) 10H mAde
1VOH = 2.5 Vdcl Source 5.0 -3.0 - -2.4 -4.2 - -1.7 -
(VOH • 4.6 Vdcl 5.0 -0.64 - -0.51 -0.88 - -0.36 -
1VOH = 0.5 Vdel 10 - - - -10.1 - - -
1VOH = 9.5 Vdcl 10 -1.6 - -1.3 -2.25 - -0.9 -
1VOH =.13.5 Vdcl 15 -4.2 - -3.4 -8.8 - -2.4 -
(VOL = 0.4 Vdel Sink 10L 5.0 0.64 - 0.51 0.88 - 0.36 - mAde
(VOL = 0.5 Vdel 10 1.6 - 1.3 2.25 - 0.9 -
(VOL = 9.5 Vdcl 10 - - - 10.1 - - -
(VOL = 1.5 Vdel 15 4.2 - 3.4 8.8 - 2.4 -
Output Drive Current (CL/CP Devjce~ IOH mAde
(VOH = 2.5 Vde) Source 5.0 -2.5 - -2.1 4.2 - -1.7 -
(VOH = 4.6 Vdcl 5.0 -0.52 - -0.44 0.88 - -0.36 -
1VOH = 0.5 Vdc) 10 - - - 10.1 - - -
(VOH = 9.5 Vdcl 10 -1.3 - -1.1 2.25 - -0.9 -
1VOH = 13.5 Vdel 15 -3.6 - -3.0 8.8 - -2.4 -
(VOL = 0.4 Vdcl Sink 10L 5.0 0.52 - 0.44 0.88 - 0.36 - mAde
(VOL' 0.5 Vdcl 10 1.3 - 1.1 2.25 - 0.9 -
(VOL = 9.5 Vde) 10 - - - 10.1 - - -
(VOL = 1.5 Vdel 15 3.6 - 3.0 8.8 - 2.4 -
Input Current tAL Device) I,n 15 - ,01 '000001 '01 • 10 J,l.Adt:
Inpul Current ICLlCP Device) Ion 15 '03 '000001 '03 , 1.0 ~Adc
Input Capacitance C,n - 50 7.5 pF
(V1n 01
QUiescent Current IAl Device) 100 50 50 0.005 50 150 J,lAr1c
(Per Package! 10 10 0.010 10 - 300
15 20 0.015 20 600
OUlescenl Current (CLlCP Device) 'DO 50 - 20 0.005 20 150 IJAdc
(Per Packagel 10 - 40 - 0.010 40 300
15 - 80 - 0.015 80 - 600
Total Supply Current·· t IT 50 (1.6 f • ,..Adt:
'T ,uA/kHl) 100
IOyn.mlc plus QUiescent, 10 IT (3.1 ,lJA/kHz) I" 100
Per Package) 15 'T 14.7 lolA/kHz) I. 100
ICL - 50 pF on all outputs, all
buffers sWitching)
-Tlow'- -55°C for Al Device. -40oC for CLlCP Device.

Thigh:; +12SoC for Al DeVIce. +8SoC for CLlCP Device.
• Noise Immunity specified for worst·case input combination.
NOIseMargin for both "1" and "0"level ::: 1.0 Vdc min@VOD :" 5.0 Vdc
2.0 Vdc min@ VDD .• 10 Vdc
2.5 Vde min @ VOO 15 Vde 0

'T(eL' • IT(50 pFI' 3.5 x 10-3 ICL -SOl VOO'
where: IT is in J,JA(per packagel. CL in pF. VDD in Vdc. and f in kHz is input frequency.
··The formulas given are fOr the typical characteristiCS only at 25°C
fields: however. it is advised that normal precautions be taken to avoid application of any voltage higher
Vin and Vout be constrained to the range VSS '" (Vin or Vout) .:;;VDD'
Unused inputs must always be tied to an appropriate logic voltage level (e.g. either VSS or VDD)'
ChM••• oristic Symbol VOO Min Typ Mo. Unit
Output Rise Time ITLH ns
ITLH· 13.0 ns/pF) CL + 30 ns 5.0 - 100 200
ITLH = 11.5 ns/pF) CL + 15 ns 10 - 50 100
ITLH = ILl ns/pF) CL + 10 ns 15 - 40 80
Output Fall Time ITHL ns
ITHL· (1.5 ns/pFI CL +25ns 5.0 - 100 200
ITHL = (0.75 ns/pF) CL + 12.5 ns 10 - 50 lOa
tTHL = 10.55 ns/pF) CL + 12.5 ns 15 - 40 80
furn:-Off Delay Time IPLH ns
IpLH = 11.7 ns/pF) CL + 520 ns 5.0 - 605 1210
IPLH = 10.66 ns/pF) CL + 217 ns 10 - 250 500
II
IPLH = 10.5 ns/pF) CL + 160 ns 15 - 185 370
Turn·On Delay Time IPHL ns
IPHL = 11.7 ns/pFI CL + 420 ns 5.0 - 505 1650
IPHL = (0.66 ns/pFI CL + 172 ns 10 - 205 660
IpHL = (0.5 n./pFi CL + 130 ns 15 - 155 495
Setup Time Isu 5.0 0 -40 - ns
10 0 -15 -
15 0 -10 -
Hold Time Ih 5.0 80 40 - ns
10 30 15 -
15 20 10 -
Latch Disable Pulse Width (Strobing Data) twH 5.0 250 125 - ns
10 100 50 -
15 80 40 -
1-
•...
6.0
~
a -t2
oc
w
u
.OC
::>
~:i. -18
EI P
-24
-16 -12 -8.0 -4.0
IVoH -VOO). SOURCE DEVICE VOLTAGE (We)
0
o
o 4.0 aD
POLmax
I
VSS~oVdc
I
z:
12
(VOL - VSSI.SINK DEVICE VOLTAGE (Vdc)
70 mWdc
Vss
VOH
Inputs 81 and Ph low. and Inputs 0 and LO high.
f in respect to a system clock. _____ '0%_ VOL
tTLH :::oJ
~
All outputs connected to respective CL loads.
20n.~on. VOO
A. B. and C 90% 50%
10% 1/1 --- VSS
50% Duty Cyela
VOH
Any Output
~ ---VOL
,y---x VDD
-----~-w~~ L-J ''-------VSS

MC14543B
Output
Ph
PIN ASSIGNMENT
16
2 15
3 14
4 13
12
6 11
10
B 9
0
® MOTOROLA
BCD·TO-5EVEN SEGMENT LATCH/DECODER/DRIVER

for L1aUID CRYSTALS
The MC14544B BCD-to-seven segment latch/decoder/driver is

designed for use with Iiqu id crystal readouts, and is constructed with BCD-TO-SEVEN SEGMENT
II
complementary MOS (CMOS) enhancement mode devices. The cir-
cuit provides the functions of a 4-bit storage latch and an 8421 BCD- WITH RIPPLE BLANKING
-
to-seven segment decoder and driver. The device has the capability
to invert the logic levels of the output combination. The phase (PhI.
blanking (BII. and latch disable (LD) inputs are used to reverse the
truth table phase, blank the display, and store a BCD code. respec-
tively. For liquid crystal (LC) readouts, a square wave is applied to
the Ph input of the circuit and the· electrically common backplane
of the display. The outputs of the circuit are connected directly to
..~1i~UU
~
L SUFFIX
.. 1
P SUFFIX
the segments of the LC readout. The Ripple Blanking Input (RBI) CERAMIC PACKAGE PLASTIC PACKAGE
and the Ripple Blanking Output (RBO) can be used to suppress CASE 126 CASE 101
either leading or trailing zeroes. OROERING INFORMATION
For other types of readouts. such as light-emitting diode (LEDI.
incandescent, gas discharge, and fluorescent readouts, connection
diagrams are given on this data sheet.
."""'1tSUffiX l
OonotO,
Ceramic Package
Applications include instrument (e.g.• counter, DVM etc.) display P Pla,tic Package
driver, computer/calculator display driver. cockpit display driver, A Extended Operating
Temperature Range
and various clock, watch. and timer uses. e Limited Operating
Temperature R.nge
• Logic Circuit Quiescent Current = 5.0nA/package typical @
5Vdc
• Blanking Input
• Readout Blanking on All Illegal Input Combinations
• Direct LED (Common Anode or Cathode) Driving Capability
• Capability for Suppression of Non-significant zero
• Capable of Driving Two Low·power TTL Loads, One Low-power
ature Range
Rating Symbol Value Unit This device contains circuitry to protect

the inputs ag.inst damage due to high
OC Supply Voltage VOO -0.5 to +18 Vde
static voltages or electric fields; however.
Input Voltage. All Inputs Vin -0.5 to VOO + 0.5 Vde it is advised that normal precautions be
taken to avoid application of any voltage
higher. then maximum rated voltages to
Operating Temperature Range - AL Device TA -55 to +125 °c this high impedance circuit. For proper
CLlCP Device -40 to +85 operation it is recommended that V in and
Storage Temperature Rance -6510 +150 °c Vout be constrained to the range Vss <;
T,tg
(Vin or Vou" <; VOO'
Maximum Continuous Output Drive Current 'OHmax 10 mAde Unused inputs must always be ·tied to an
(Source or Sink) per Output IOLmax appropriate logic voltage level te.g., either
Maximum Continuous Output Pamr· POHmax 10 mW VssorVOOI.
(Source or Sink) per Output POLmax
'POHmax = IOH (VOH - Voo'and POLmax = IOL (VOL' VSS)
VDD TI_
. 25°C Th· ••••
Chat'lCteriltic Symbol Vd. Min M•• Mi" Typ M•• Mi" M•• Unit
Output Volt. "0" Level VOL 5.0 - 0.05 - 0 0.05 - 0.05 Vd.
Vjn"'VooorO 10 - 0.05 - 0 0.05 - 0.05
15 - 0.05 - 0 0.05 - 0.05
"1" L•••••
' VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vdc
VinsOorVoo 10 9.95 - 9.95 10 - 9.95 -
15 14.95 - 14.95 15 - 14.95 -
Input Volt.- "0" Llv,l VIL Vdc
1VO : 4.5 or 0.5 Vclc) 5.0 - 1.5 - 2.25 1.5 - 1.5
(VO : 9.0 or 1.0 Vclc) 10 - 3.0 - 4.50 3.0 - 3.0
(VO' 13.5 Of' 1.5 Vclc) 15 - 4.0 - 6.75 4.0 - 4.0
"'" Level VIH
(VO' 0.5 Of' 4.5 Vdcl 5.0 3.5 - 3.5 2.75 - 3.5 - Vdc
1VO' 1.0 or 9.0 Vclc) 10 7.0 - 7.0 5.50 - 7.0 -
(VO' 1.5 or 13.5 Vd.1 15 11.0 - 11.0 8.25 - 11.0 -
Output Drive Current tAL Device) 10H mAde
(VOH • 2.5 Vclc) Source 5.0 -3.0 - -2.4 -4.2 - -1.7 -
(VOH • 4.6 Vd.) 5.0 -0.64 - -0.51 -0.88 - -0.36 -
(VOH • 0.5 Vdcl 10 - - - -10.1 - - -
(VOH • 9.5 Vd.) 10 -1.6 - -1.3 -2.25 - -0.9 -
(VOH - 13.5 Vdcl 15 -4.2 - -3.4 -8.8 - -2.4 -
(VOL' 0.4 Vdcl Sink 10L 5.0 0.64 - 0.51 0.88 - 0.36 - mAde
(VOL' 0.5 Vd.) 10 1.6 - 1.3 2.25 - 0.9 -
(VOL' 9.5 Vd.) 10 - - - 10.1 - - -
(VOL' 1.5 Vdc) 15 4.2 - 3.4 8.8 - 2.4 -
OUtput Ori •• Current ICL/CP Device' 10H mAde
(VOH • 2.5 Vd.) Source 5.0 -2.5 - -2.1 4.2 - -1.7 -
(VOH • 4.6 Vdc) 5.0 -0.52 - -0.44 0.88 - -0.36 -
(VOH • 0.5 Vdc) 10 - - - 10.1 - - -
(VOH • 9.5 Vdc) 10 -1.3 - -1.1 2.25 - -0.9 -
(VOH' 13.5 Vdc) 15 -3.6 - -3.0 8.8 - -2.4 -
(VOL' 0.4 Vdc) Sink 10L 5.0 0.52 - 0.44 0.88 - 0.36 - mAde
(VOL' 0.5 Vdcl 10 1.3 - 1.1 2.25 - 0.9 -
(VOL - 9.5 Vdc) 10 - - - 10.1 - - -
(VOL' 1.5 Vdc) 15 3.6 - 3.0 8.8 - 2.4 -
Input Current IAL DeviceI lin 15 - to.l - to 00001 to,' - ! 1.0 ~Adc
Input Current (CUep Device I lin 15 - t 0.3 - '0.00001 to.3 - 11.0 ~Adc
Input Capacitance Cin - - - 5.0 7.5 - - pF
(Vin' 01
Quiescent Current tAL Devtee' 100 5.0 5.0 - 0.005 5.0 - 150 .wAde
CPer Package) 10 - 10 - 0.010 10 - 300
15 - 20 - 0.015 20 - 600
QUiescent Current tCLlep OIYte.) 100 5.0 - 20 - 0.005 20 - 150 .wAde
(Pe' Pockogel 10 - 40 - 0.010 40 - 300
15 - 80 - 0.Q15 80 - 600
Tot.1 Supply Current·· t IT 5.0 IT' 11.6 .A/kHzl f + 100 IoIAdc
(OynlfTlic plus Quiescent, 10 IT' 13.1 .A/kHzl I + 100
Per P.:kage) 15 IT' 14.7 .A/kHzl I + 100
ICl .,.SO pF on all outputs, all
buffers switching)
·Tlow :: -5SoC for AL Cevic., -400C for eLlep Device.

Thigh' +1250C for AL Device. +850C for CL/CP Oovic•.
~oi •• immunity specified for worst-cue input combination.
Noise Margin for both "1" and "0" level =: 1.0 Vdc min @ VOO '"'5.0 Vdc
2.0 Vclc min (jjlVOO • 10 Vdc
2.5 Vd. min (jjlVOO : 15 Vdc
fTo calculat. total supply current at loeds other than 50 pF:
IT(CL) • IT(50 pFI + 3.5. 10-3 (CL -SO) VOO'
where: IT is in IAA (per pKkegeJ. Cl in pF;Voo in Vd«:. and f in kHz is input frequency.
--The formul. given are for the tYpical charKterilticl only at 25°C.
Ch.raeteristic Symbol VOO Min Typ Max Unit
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 - 100 200
tTLH = 11.5 ns/pF) CL + 15 ns 10 - 50 100
tTLH· 11.1 ns/pF) CL + 10 nl 15 - 40 80
'THL' (1.5 ns/pF) CL + 25 ns 5.0 - 100 200
tTHL· (0.75 ns/pF) CL + 12.5 ns 10 - 50 100
tTHL· (0.55 ns/pFI CL + 12.5 ns 15 - 40 80
Turn-Off Delay Time tPLH ns
tpLH· 11.7 ns/pF) CL + 520 ns 5.0 - 605 1210
tpLH =
10.66 ns/pF) CL + 217 ns 10 - 250 500
tPLH • 10.5 ns/pF) CL + 160 ns 15 - 185 370
Turn-On Delay Time tpHL ns
tPHL' 11.7 ns/pF) CL +420ns 5.0 - 505 1650
tPHL· 10.66 ns/pF) CL + 172 ns 10 - 205 660
tPHL· 10.5 ns/pF) CL + 130 ns 15 - 155 495
Setup Time tsu 5.0 0 -40 ns
10 0 -15 -
15 0 -10 -
Hold Time th 5.0 80 40 - ns
10 30 15 -
15 20 10 -
Latch Disable Pulse Width IStrobing Datal tWH 5.0 250 125 - ns
10 100 50 -
15 80 40 -
FIGURE 2 - TYPICAL OUTPUT SINK
CHARACTERISTICS
:i 18
.s
...
~
~ 12
::>
<.>
'"zin
-24
-16 -12 -3.0 -4.0 0
oo . 4.0 8.0 12 16
(VaN -Vaal. SOURCE DEVICE VOLTAGE (Vdc) (Val - VSS). SINK DEVICE VOLTAGE (Vd,)
90%
10% ~S
Inputs Blind Ph low. and Inputs 0 and LO high. tPHL!lO%~5O% k=VOH

. IO%~ VOL
f in respect to I system clock.
tTHL tTLH :::J
All outputs connected to respecti:-,eCL loads.
20 •••~on. VOO
VOO
A. B. and CIO% 90% 50%
1/1 ---VSS VSS
50% DutY Cyela VOO
VOH
Any OUlI><ll VSS
~ ---VOL
'\.. VOH
"---- VOL
----~~-w~D'------::
II
MC14544B MC14544B MC14544B MC14544B MC14544B MC14544B
o. 0 0 0 o 0 0 0 o 0 1 o 0 0 0 o 0 0 1 o 0 1
(01 (0) (51 (0) (1) (31
TRAILING EDGE ZERO SUPPRESSION
Oisp'.ys
1 I I I 1
1 I I I _I
MC14544B MC14544B MC14544B MC14544B MC14544B MC14544B

o 1 0 1 o 0 0 0 o 0 0 1 o 0 1 1 o 0 0 0 o 0 0 0
(51 (01 (11 (31 (01 (01
MC145448
Output
Ph
RBr LO BI
INPUTS
""
0 C B A
., .
RBO b , d .,.
OUTPUTS
DISPLAY
x = Don't Care
t = Above Combinations
, ,,
X X 1 0 X X X X 0 0
,,,,
0 0 0 0 0 81,nk • = For liquid crystal readouts, apply a square wave to Ph. For
0 0 0 0 0 0
,
0 0 0 0 0
,
0 0 Blink
common cathode LEO readouts, select Ph = O. For com-
0
,, 0 0 0 0 0
, 0 0
,, 0 0
, mon anode LED readouts. select Ph =
1.
, ,
,, , ,, , ,
X 0 0 0 0 0 0 0 0 0 0 0
Depends upon the BCD Code previously applied when
X 0 0 0 0
,, 0 0
, 0 0
, 2 =
X 1 0 0 0 0
, 0
,, 0
,,
0 3
•
LD ~ 1.
X
,
1 0
0
0 0
0
0
0, , 0 0
0 ,
0
0 ,, 0 0
0 ,, •
X 0
, , , , ,
X
X ,
1 0
0
0
0
0
0 , ,, 0 0
0 1
0
1
,,
,
1
0 0
1
,
0
1
0
6
7
X
,
1 0 0
,
1 0
,
0 0 0 1 1 1
,, 1 B
X 0 0
, 0
,
0 0 1 1 1 1 0 9
X
X ,
1 0
0
0
0
,,
1
0
0 ,,0 0
0
0 0 0
0 0 0 0 0 0 0
0 0 0 0 BLink
81.,-.k
X
X ,
1 0
0
0
0 ,, ,
0
0 , 0 0
0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
Blank
Blank
.
X 1 0 0 1 1 0 0 0 0 0 0 0 0 0 Blank
X 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Blank
--
X 0 0 0 X X X X
t t t 1 t t
1•••••• 01 o..lput
C_ ••• t__ ~"'~
@MOTOROLA
HIGH CURRENT
The MC14547 BCD-to-seven segment decoder/driver is constructed
BCDTO·SEVEN SEGMENT
with complementary MOS ICMOS) enhancement mode devices and
NPN bipolar output drivers in a single monolithic structure. The circuit DECODER/DRIVER
provides the functions of an 8421 BCD-to-seven segment decoder with
high output drive capability. Blanking !B1l, can be used to turn off or
pulse modulate the brightness of the display. The MC14547 can drive
seven-segment light-emitting diodes I LED), incandescent. fluorescent
or gas discharge readouts either directly or indirectly.
Applications include instrument le.g., counter, DVM, etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.
",,,,!fIlJ ".
L SUFFIX P SUFFIX
CASE 620 CASE 648
• High Current Sourcing Outputs IUp to 65 mAl

• Supply Voltage Range = + 3.0 V to + 18 V MC'.XXXB~SU~f':e::;:t::'k.ge
• Blanking Input L. P PlastIc Package
• Readout Blanking on All Illegal Combinations A Extended opera.ting

Temperature Range
• Lamp Intensity Modulation Capability C Limited Operating
Temperature Ran~
• Multiplexing Capability
• Capable of Driving Two Low-Power TTL Loads,
One Low-Power Schottky TTL Load or
Two HTL Loads over the Rated Temperature Range '6
• Use MC14511 B for Applications Requiring Data Latches 's
,.
• '3 '/7'/b
t2 eC/'
6 11 d
'0
9
MAXIMUM RATINGS IVoltage referenced to VSS, Pin 8)
DISPLAY
DC Supply Voltage VDD + 18 to -0.5 Vdc
Input Voltage, All Inputs Vin VDD to -0.5 Vdc
Operating Temperature Range MC14547BAL TA -55to+125 °c 0
MC14547BCLlCP -40 to +85
Maximum Continuous Output Drive Current IOHmax 65 mA TRUTH TABLE
(Source) per Output
INPUTS OUTPUT
Maximum Continuous Power Dissipation POHmax 1200' mW
BI D B A a b c d e f DISPLAY
·See power derating curve (Figure 1). ,,

0 X
C
X X X
, 0 0 0
, 0 0
,
0
9
0 Blank
,, t, ,, ,,, ,
0 0 0 0 1 1 1 0 0
t
,
0
0
0
0
0
0
0 1
,
, ,
0
0 0
1
0
0
0
1 2
This device contains circuitry to protect the inputs against damage due to high static ,, 0
0 , , ,
0
0 0 0 , , 0,, ,t0
0
0 1 3
•
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated voltages to this high im- , , 0
0
1 0
, , t ,
1 1 0
1
0
0
0
1
1 , t , ,0 5
6
pedance circuit. A destructive high current mode may occure if Vin and Vout is not
constrained to the range VSS ~ (Vin or Voutl ~ VOO' ,, ,,, , , ,,
0 1
0 0 0 ,, , , ,,
1 0 0 0 0
1
7
B
0 0 1 1 0 t 0 9
Oue to the sourcing capability of this circuit, damage can occur to the device if VOO is ,
1
, ,
0 0 0 0 0 0 0 0 0 Blank
Blank
applied, and the outputs are shorted to Vss and are at a logical 1 (See Maximum
Ratings). 1 , ,,
1 0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Blank
, ,, , , ,
1 1 0 1 0 0 0 0 0 0 0 Blank
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either 1 0 0 0 0 0 0 0 0 Blank
1 1 0 0 0 0 0 0 0 Blank
Vss or VDD)'
> 25°C Thigh>
Symbol Voo Tlow Unit
Characteristic
Vde Min Max Min Typ Max Min Max
Output Voltage "0" Level 5.0 - 0.05 - 0 0.05 - 0.05
Vin = VOD or 0 VOL 10 - 0.05 - 0 0.05 - 0.05 Vde
15 - 0.05 - 0 005 - 0.05
"1" Level 5.0 4.1 - 4.4 4.6 - 4.3 -
Vin = 0 or VDD VOH 10 9.1 - 9.4 9.6 - 9.3 - Vde
15 14.1 - 14.4 14.6 - 14.4 -
Input Voltage' "0" Level
(VO = 3.8 or 0.5 Vdcl 5.0 - 15 - 2.25 1.5 - 15
Vde
VIL
(VO = 8.8 or 1.0 Vde) 10 - 30 - 4.50 3.0 - 30
(VO = 13.8 or 1.5 Vdcl 15 - 4.0 - 6.75 4.0 - 4.0
(VO = 0.5 or 3.8 Vdcl "1" Level 5.0 3.5 - 3.5 2.75 - 3.5 -
1VO = 1.0 or 8.8 Vdcl VIH 10 7.0 - 7.0 5.50 - 7.0 - Vde
(VO = 1.5 or 13.8 Vde! 15 11.0 - 11.0 8.25 - 11.0 -
Output Drive Voltage tAL DeVice)
"0H = 5.0 mAdcl Source 4.0 - 4.2 43 - 43 -
"0H = 10 mAdcl
5.0
- - 4.1 43 - - - Vde
"0H = 20 mAdcl 38 - 3.9 4.2 - 4.0 -
(IOH = 40 mAdcl - - 3.7 4.0 - - -
(IOH ~ 65 mAde! 3.1 - 32 37 - 30 -
"0H ~ 5.0 mAdcl 9.1 - 9.2 9.3 - 9.3 -
(IOH =
10 mAdcl VOH - - 9.1 9.3 - - -
"0H =
20 mAdel 10 8.8 - 9.0 9.2 - 92 - Vde
"0H =
40 mAdcl - - 8.9 9.0 - - -
"0H =
65 mAde) 8.4 - 85 8.8 - 8.1 -
"0H = 5.0 mAde! 14.0 - 14.2 14.3 - 14.4 -
"0H = 10 mAdcl - - 14.1 14.3 - - -
"0H = 20 mAde) 13.8 - 14.0 14.2 - 14.2 -
"0H ~ 40 mAdcl 15 - - 13.8 14.0 - - - Vde
"0H = 65 mAde! 13.5 - 13.5 13.7 - 13.3 -
Output Drive VOltage (CL/CP Devleel
"0H =
5.0 mAdcl Source 39 - 4.1 4.3 - 4.2 -
IIOH =
10 mAde! - - 40 4.3 - - -
5.0 Vde
"0H ~ 20 mAde! 36 - 38 4.2 - 3.9 -
IIOH =
40 mAde! - - 35 4.0 - - -
IIOH =
65 mAdcl 30 - 30 37 - 29 -
(IOH = 5.0 mAdel 8.9 - 9.1 93 - 9.2 -
"0H = 10 mAde! VOH - - 90 9.3 - - -
"0H = 20 mAdcl 10 86 - 88 9.2 - 9.0 - Vde
"0H = 40 mAdcl - - 8.5 90 - - -
(IOH = 65 mAdcl 80 - 8.1 88 - 8.0 -
(IOH = 5.0 mAdel 13.9 - 14.1 14.3 - 14.2 -
(IOH = 10 mAde! - - -14.0 14.3 - - -
"0H = 20 mAdcl 15 13.6 - 13.8 14.2 - 14.0 - Vde
(IOH = 40 mAde! - - 13.5 14.0 - - -
"0H = 65 mAdcl 13.0 - 13.0 13.7 - 13.0 -
Output Dnve Current tAL DeVice)
(VOL =
0.4 Vdcl Sink 5.0 032 - 0.26 0.44 - 0.18 -
mAde
10L
(VOL =
0.5 Vde! 10 0.80 - 065 1.13 - 0.45 -
(VOL =
1.5 Vdcl 15 2.10 - 1.7 4.4 - 12 -
OutPUt Drive Current ICL/CP Devieel
= 0.44 - 0.18 -
(VOL 0.4 Vdcl Sink 5.0 0.26 - 0.22
mAde
(VOL =
0.5 Vdcl IOL 10 0.65 - 055 1.13 - 0.45 -
(VOL =
1.5 Vde! 15 18 - 1.5 4.4 - 1.2 -
Symbol VDD Tlow' 25°C Thi h' Unit
Characteristic
Vdc Min Max Min Typ Max Min Max
Input Current IAL Devicel 'in 15 - ±0.1 - ±0.axxJ1 ±01 - ± 10 ~Adc
Input Current lCLlCP DevIce) Iln 15 - ±03 ±0.axxJ1 ±03 ± 10 ~Adc
Input Capacitance (V In - m Cin - - - - 5.0 7.5 - - pF
QUIescent Current IAL DevIce) 50 5.0 0005 50 150
I Per Packagel IDD 10 - 10 - 0.010 10 - 300 ~Adc
15 - 20 - 0015 20 - 600
QUIescent Current lCL/CP Devlcel 50 - 20 - 0.005 20 - 150
(Per Package 1 IDD 10 - 40 - 0.010 40 - 300 ~Adc
15 - 80 - 0.015 80 - 600
Total Supply Current" t 50 iT = (19 ~AlkHzl I + IDD
(DynamiC plus Quiescent, 10 IT = (38 ~AlkHzl I + IDD
Per Package) IT 15 IT = 15.7 ~AlkHzl f + IDD ~Adc
(CL ~ 50 pF on all outputs, all
buffers SWItching)
• Tlow = - 55°C lor AL Device, -40°C for CL/CP Device t To calculate total supply current at loads other than 50 pF:
Thigh = + 125°C for AL DeVice, +85°C for CL/CP Device IT (CLI =
IT 150 pFI + 3.5 x 10-3 (CL - 501 VDDf
I Noise immunity specified for worst-case input combination. where: IT is in ~A (per packagel, CL in pF, VDD in Vdc,
Noise Margin for both "'" and "0" level = and f in kHz is input frequency.
1.0 Vdc min @ VDD = 5.0 Vdc •• The formulas given are for the typical
2.0 Vdc min @ VDD = 10 Vdc characteristics only at 25°C.
2.5 Vdc min @ VDD = 15 Vdc
Symbol VDD
Characteristic Min Typ Max Unit
Vdc
50 - 40 80
Output Rise TIme tTLH 10 - 40 80 ns
15 - 40 80
5.0 - 125 250
Output Fall Time tTHL 10 - 75 150 ns
15 - 70 140
5.0 - 750 1500
IpLH 10 - 300 600 ns
15 - 200 400
Data Propagation Delay Time
5.0 - 750 1500
tPHL 10 - 300 600 ns
15 - 200 400
50 - 750 1500
tPLH 10 - 300 600 ns
Blank Propagation Delay Time 15 - 200 400
5.0 - 500 1000
tPHL 10 - 250 500 ns
15 - 170 340
A 7
13 a
12 b
B 1
" c
10 d
C 2
9 e
15 f
D 6
14 9
"'"
"""-
.......... """-
"'" """-
I'-.. "'" ~CL DEVICE
I'>.. x.....
CP DEVICE """- AL DEVICE
'<.
"':'"Vss
•• A filament pre-warm resistor is recommended to reduce filament • VZD should be set at VDD - '.3 V - VLED. Wattage of zener
thermal shock and increase the effective cold resistance of the diode must be calculated for number of segments and worst·case
filament. condltlons.
® MOTOROLA MC14549B
MC14559B
SUCCESSIVE APPROXIMATION
The MC14549B and MC14559B successiveapproximation regis- REGISTERS
ters are 8-bit registers providing all the digital control and storage
necessary for successiveapproximation analog-ta-digital conversion
systems. These parts differ in only one control input. The Master
Reset {MRI on the MC14549B is required in the cascaded mode
when greater than 8 bits are desired. The Feed Forward (FF) of the
MC14559B is used for register shortening where End-of-Conversion
(EOC) is required after less than eight cycles_
Applications for the MC14549B and MC14559B include analog-
L SUFFIX P SUFFIX
to-digital conversion, with serial and parallel outputs.
CASE 620 CASE 648

• Totally Synchronous Operation
• All Outputs Buffered
• Single Supply Operation
• Serial Output ."""" 11SUffiX Denotes
L CeramIC Package
• Rctriggerable
P PlastiC Package
• Compatible with a Variety of Digital and Analog Systems such as A E Jlftended Operating
the MC1408 8-Bit D/A Converter Temperature Range
• All Control Inputs Positive-Edge Triggered e Limited Operating

Temperature Range
ature Range

Input Voltage, All Inputs Von ~.5 to VOO + 0.5 Vdc
DC Current Drain per Pm I 10 mAde
OperatIng Temperature Range - A l Device TA -55 to +125 °e
Storage Temperature Range Tug -65 to +150 °e
se se(I_11 MR MRll_ll Clock Action se Se(I_11 EOe Clock Action

X
X
X
X
X
1
X
X ---
-'
None
Reset
X
1
X
0
X
0
"L-
-r-
-r-
None
Start
ConverSion This device contains circuitry to protect
1 0 0 0 -' Start
Conversion
X 1 0 Continue
Conv.fslon
voltages or electric fields; however, it is
1 X 0 1
...r- Start 0 0 0
....r Continue
advised that normal precautions be taken
Conversion Conversion to avoid application of any voltage higher
1 1 0 0
...r Continue 0 X 1
...r Retain
Conwrsion Conversion
impedance cirCUit. For proper operation it
Result is recommended that Vin and Vout be
0 X 0 X ...r- Continue 1 X 1 -r- Start

constrained to the range VSS ~ (Vin or
Previous Conversion Vou,I';;VOO·
Operation Unused inputs must always be tied to an
Vssor Vool.
Voo Tlow
. 2SoC Thiah·
Ch.rKteristic Symbol Vd. Min MI' Min Typ MI, Mi" MI' Unit
Output Voltage "0" Level VOL 5.0 - 0.05 - 0 0.05 - 0.05 Vd.
Vin~VDOorO 10 - 0.05 - 0 0.05 - 0.05
15 - 0.05 - 0 0.05 - 0.05
."" Level VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vdc
Vin"OarVOD 10 9.95 - 9.95 10 - 9.95 -
15 14.95 - 14.95 15 - 14.95 -
Input VoltageI' "0" Level VIL Vdc
(VO • 4.5 or 0.5 Vdc! 5.0 - 1.5 - 2.25 1.5 - 1.5
1VO = 9.0 or i.o Vdcl 10 .- 3.0 - 4.50 3.0 - 3.0
1VO = 13.5 or 1.5 Vdcl 15 - 4.0 - 6.75 4.0 - 4.0
"'" Level VIH
(VO " 0.5 or 4.5 Vdc! 5.0 3.5 - 3.5 2.75 - 3.5 - Vdc
1VO ~ 1.0 or 9.0 Vdc! 10 7.0 - 7.0 5.50 - 7.0 -
(VO = 1.5 or 13.5 Vdc! 15 11.0 - 11.0 8.25 - 11.0 -
Output Drive Current IAL Device) 10H mAde
(VOH • 2.5 Vdc! Source 5.0 -1.2 - ··1.0 -1.7 - -0.7 -
(VOH • 4.6 Vdc! 5.0 -0.25 - -0.2 -0.36 - -0.14 -
1VOH • 9.5 Vdc! 10 -0.62 - -0.5 -0.9 - -0.'35 -
1VOH = 13.5 Vdcl 15 -1.8 - -1.5 -3.5 - -1.1 -
(VOL' 0.4 Vdc) Sink IOL 5.0 1.28 - 1.02 1.76 - 0.72 - mAde
(VOL = 0.5 Velcl a Outputs 10 3.2 - 2.6 4.5 - 1.8 -
(VOL = 1.5 Vdcl 15 8.4 - 6.8 17.6 - 4.8 -
1VOL = 0.4 Vdc! Sink 5.0 0.64 - 0.51 0.88 - 0.36 -
(VOL = 0.5 Vdcl Pin 5. 11 only 5.0 1.6 - 1.3 2.25 - 0.9 -
(VOL = 1.5 Vdcl 10 4.2 - 3.4 8.8 - 2.4 -
Output Drive Current (CLlep Devicel 10H mAde
(VOH =
2.5 Vdcl Source 5.0 -1.0 - -0.8 -1.7 - -0.6 -
(VOH = 4.6
Vdc! 5.0 -0.2 - -0.16 -0.36 - -0.12 -
1VOH • 9.5 Vdc! 10 -0.5 - -0.4 -0.9 - -0.3 -
(VOH' 13.5 Vdcl 15 -1.4 - -1.2 -3.5 - -1.0 -
(VOL =
0.4 Vdcl Sink 10L 5.0 1.04 - 0.88 1.76 - 0.72 mAde
1VOL • 0.5 Vdcl a Outputs 10 2.6 - 2.2 4.5 - 1.8 -
(VOL' 1.5 Vdc) 15 7.2 - 6.0 17.6 - 4.8 -
(VOL = 0.4 Vdcl Sink 5.0 0.52 - 0.44 0.88 - 0.36 -
(VOL' 0.5 Vdc! Pin 5. 11 only 10 1.3 - 1.1 2.25 - 0.9 -
(VOL' 1.5 Vdc! 15 3.6 - 3.0 8.8 - 2.4 -
Input Current (Al DeVice) lin 15 - '01 - '000001 to.l - t 1.0 ~Adc
Input Current (CL/ep Device) I,n 15 - , 0.3 - :0.00001 '0.3 - ".0 ,.,Adc
Input Capacitance CIn - - - 50 7.5 - - pF
(Vi" '" 01
Quiescent Current (AL Device) 100 5.0 - 5.0 - 0.005 5.0 - 150 ~Adc
(Per Package) 10 - 10 - 0.010 10 - 300
(Clock = V!i!i 15 - 20 - 0.015 20 - 600
Quiescent Current (CLlCP Device) 100 5.0 - 20 - 0.005 20 - 150 ~Adc
(Per Packagel 10 - 40 - 0.010 40 - 300
(Clock = V!i!i 15 - 80 - 0.015 80 - 600
Total Supply Current· • t IT 5.0 IT - (0.8 .A/kHz! f • 100 ,.,Adc
IOynamlc plus Quiescent. 10 IT = (1.6 .A/kHzl , • 100
Per Packanel 15 IT' (2.4 .A/kHz! f t 100
ICL = 50 pF on all outputs, all
huffers sWitching'
"Ttow = -SSoC lOr AL DeVice, -40oC for CLlCP DeVice.
Thigh = +12SoC IOf AL Of'vice, +8SoC for CLlCP Device.
.••Nolse Immunity Sp~c.;tfledfor worst-case input combination
NOise Margin for uoth "1" and "0" level = 1.0Vdc min@ VDD = 5.0 Vdc
2.0 Vdc min@l VOO 10Vdc
2.5 Vdc min Ci.' VOO = 15 Vdc
fTo calculate 10lal supply current at loads other than 50 pF.
'r(CL! Ir(50 pF' t 2.10-3 ICL -501 VOO'
where: IT 1$ In ~A {per packagel, CL in pF. VOO in Vdc. and f In kHz is input frequency .
• "The formulas gIven are for the tYPical characteristics only at 2SoC.
Ch.racteristic Symbol VDD Min Typ Mox Unit
tTLH = (3.0 ns/pFI CL + 30 ns 5.0 - 180 360
tTLH • 0.5 ns/pF) CL + 15 ns 10 - 90 180
tTLH ~ (1.1 ns/pFI CL + 10 ns 15 - 65 130
tTHL = 0.5 ns/pF) CL + 25 ns 5.0 - 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 - 50 100
tTHL· (0.55 ns/pF) CL + 9.5 ns 15 - 40 80
Propagation Delay Time tPLH, ns
Clock to a tpHL
tPLH. tpHL = (1.7 ns/pFI CL + 415 ns 5.0 - 500 1000
tPLH, tpHL = (0.66 ns/pF) CL + 177 ns 10 - 210 420
tPLH. tPHL • (0.5 ns/pF) CL + 130 ns 15 - 155 310
Clock to Sout
tpLH. tpHL = (1.7 ns/pF) CL + 665 n, 5.0 - 750 1500
tpLH. tpHL • (0.66 ns/pFI CL + 277 ns
tPLH. tPHL = (0.5 ns/pF) CL + 195 ns
10
15
-- 310
220
620
440
Clock to EOC
tPLH. tpHL' 0.7 ns/pF) CL + 215 ns 5.0 - 300 600
tPLH. tPHL • (0.66 nsl pFI CL + 97 ns 10 - 130 260
tPLH. tPHL = 10.5 ns/pF) CL + 75 ns 15 - 100 200
SC. D. FF or MA Setup Time tsu 5.0 250 125 - ns
10 100 50 -
15 80 40 -
Clock Pulse Width !WH(el) 5.0 700 350 - ns
10 270 135 -
15 200 100 -
Puis. Width - 0, SC, FF or MA tWH 5.0 500 250 - ns
10 200 100 -
15 160 80 -
Clock Rise and Fall Time tTLH. 5.0 - - 15 IlS
tTHL 10 - - 5.0
15 - - 4.0
Clock Pulse Frequency lei 5.0 - 1.5 0.8 MHz
10 - 3.0 1.5
15 - 4.0 2.0
07
06
C
05
A"
Programmable SC
Q3
Pulse
Genarator 02
FF(MR)
01
00
0
~ - Don't t::are condition

I nh - Indicate. S.rial Out ,. jnhibi~d low .
• - 08 i. ninth-bit of serial information available from 8-bit register.
Note: Pin 10· VSS

Both the MC 1 4549B and MC 14559B can be operated for a 6-bit conversion, tie 01 to FF; the part will respond
in either the "free run" or "strobed operation" mode for as shown in the timing diagram less two bit times. Note
conversion schemes with any number of bits. Reliable that Oland 00 will still operate and must be disregarded.
cascading and/or recirculating operation can be achieved For 8-bit operation, FF is tied to VSS.
if the End of Convert IEOC) output is used as the controll- For applications with more than 8 but less than 16 bits,
ing function, since with EOC = 0 land with SC = 1 for use the basic connections shown in Figure 1 The FF
MC14549B but either 1 or 0 for MC14559B) no stable input of the MC14559B IS used to shorten the setup.
state exists under continual clocked operation. The Tying FF directly to the least significant bit used In the
MC14559B will automatically recirculate after EOC = 1 MC14559B allows EOC to provide the cascading Signal,
during externally strobed operation, provided SC = 1. and results In smooth transition of serial information from
All data and control inputs for these devices are trig- the MC14559B to the MC14549B. The Serial Out ISout!
gered into the circuit on the positive edge of the clock inhibit structure of the MC14559B remains Inactive one
pulse. cycle after EOC goes high, while SoUl of the MC14549B
Operation of the various terminals is as follows: remains Inhibited until the second clock cycle of Its opera-
C = Clock - A positive-going transition of the Clock is tion.
required for data on any input to be strobed into the cir- On = Data Outputs - After a conversion IS Initiated
cuit. the O's on succeeding cycles go high and are then condi-
SC = Start Convert - A conversion sequence is in- tionally reset dependent upon the state of the 0 input.
itiated on the positive-going transition of the SC input on Once conditionally reset they remain In the proper state
succeeding clock cycles. until the circuit IS either reset or reinltlated.
D = Data In - Data on this input lusually from a com- EOC = End of Convert - ThiS output goes high on the
parator in AID applications) is entered into the circuit on a negative-going transition of the clock follOWing FF = 1
positive-going transition of the clock. This input is Schmitt lIor the MC14559B) or the conditional reset of 00. ThiS
triggered and synchronized to allow fast response and allows settling of the digital circuitry prior to the End of
guaranteed quality of serial and parallel data. Conversion indication. Therefore either level or edge trig-
MR = Master Reset (MC14549B only) - Resets all gering can indicate complete converSion.
output to 0 on positive-gOing transitions of the clock. If Sout = Serial Out - Transmits conversion In serial
removed while SC = 0, the circuit will remain reset until fashion. Serial data occurs during the clock period when
SC = 1. This allows easy cascading of circuits. the corresponding parallel data bit is conditionally reset.
FF = Feed Forward (MC14559B only) - Provides Serial Out is inhibited on the Initial period of a cycle,
register shortening by removing unwanted bits from a when the circuit IS reset, and on the second cycle after
system. EOC goes high. This provides efficient operation when
For operation with less than 8 bits, tie the output cascaded.
following the least significant bit of the circuit to FF.E.g.,
Serial Out
(Continual
update every
13 clock cycles)
fCompletion of conver.ion
automatically,e-initiat ••
cycle in fr •• run mode.
·F Fallows EOC to activate

•• if in 4-stage register .
• ·Cascading using EOC guerantMd;
no stabl. unfunctional state.
Externally Controlled 6-Bit ADC (Figure 2) Continuously Cycling 12-Bit ADC (Figure 4)
Several features are shown in this application: Because each successive approximation register (SAR)
• Shortening of the register to six bits by feeding the has a capability of handling only an eight-bit word, two
seventh output bit into the FF input. must be cascaded to make an ADC with more than eight
• Continuous conversion, if a continuous signal is bits.
applied to SC. When it is necessary to cascade two SAR's, the second
• Externally controlled updating (the start pulse must SAR must have a stable resetlable state to remain in while
be shorter than the conversion cycle). awaiting a subsequent start signal. However, the first stage
• The EGC output indicating that the parallel data are must not have a stable resetlable state while recycling,
valid and that the serial output is complete. because during switch-on or due to outSide influences,
the first stage has entered a reset state, the entire ADC
Continuously Cycling 8-Bit ADC (Figure 3) will remain in a stable non-functional condition.
This ADC is running continuously because the EGC This 1 2-bit ADC is continuously recycling. The serial
signal is fed back to the SC Input, Immediately Initiating a as well as the parallel outputs are updated every thirteenth
new cycle on the next clock pulse. clock pulse. The EGC pulse indicates the completion of
Additional Motorola Parts for Successive
Approximation ADC
the 12·bit conversion cycle, the end of the serial output Monoliltlic digital-to-analog corwerters - The MC1408/
word, and the validity of the parallel data output. 1508 converter has eight-bit resolution and is available
with 6. 7. and B-bit accuracy. The amplifier-comp.ator
block - The MC140711507 contains a hilt> speed oper-
ational amplifier and a high speed comparator with ad·
Externally Controlled 12·8it ADC (Figure 5) justable window.
In this circuit the external pulse starts the first SAR With these two linear parts it is possible to construct
and simultaneously resets the cascaded second SAR. When SA·ADCs with an 8C'Curacy of up to eight bits. using as the
Q4 of the first SAR goes hilt>. the second SAR starts register one MC14549B or one MC14559B. An additional
conversion, and the first one stops conversion. EOC indi- CMOS block will be necessary to generate the clock fre-
cates that the parallel data are valid and that the serial quency.
output is complete. Updating the output data is started Additional information on successive approximation
with every external control pulse. ADC is found in Motorola Application Note AN-716.
@ MOTOROLA
The MCM 14552 is a static random accessmemory (RAM) organ·

ized in a 64 x 4 bit pattern. The three chip enable inputs can be used
256·BIT (64 X 4) STATIC
as extensions of the six address inputs, creating 9·bit addressscheme.
Eight MCM 14552 devices may be used to comprise a 2048·bit memo
ory (512 x 4) without additional addressdecoding.
The mode control (M) is used to change the control logic charac·
teristic of the circuit. For example, with M high, the 3·state input
(T) fully controls the 3·state characteristic of the output. With M
low, the output 3·state characteristic is controlled by chip enable
inputs (CEI. write enable input (WE) and T.
The memory is designed so that dc signals may operate the memo
ory, with no maximum pulse width restrictions.
Medium speed, micropower operation, and control flexibility
J~ 1
make the device useful in scratch pad or buffer applications where
battery operation or high noise immunity are required.
L SUFFIX
• Quiescent Current = 50 !lA/package typical @ 5 Vdc CERAMIC PACKAGE
CASE 623
• 3·state Output Capability for Memory Expansion
• Output Data Latch Eliminates Need for Storage Buffer
• Access Time = 700 ns typical @ VDD = 10 Vdc
• Fully Decoded and Buffered
• Supply Voltage Range = 3.0 Vdc to 18 Vdc P SUFFIX
• Capable of Driving Two Low·power TTL Loads, One Low·power PLASTIC PACKAGE
CASe 709
ature Range
Note: Strobe Must be Inactive (High) during Address Changes .,., «•• I1SUffiX Denote,
L Ceramic Package
Note: Pin 20(LE) must be connected to Vss
P Pl •• tic Package
Temperature Range
e Limited Operating
Temperature Range
R~ting Symbol Valu. Unit

OC Supply Voltage VOO -0.5 to +'8 Vdc
Input Voltage, All Inputs Yon -0.5 to VOO + 0.5 Vdc
24
Operating Temperature Range - Al DeVIce TA -55 to +125 °c
CL/CP DeVice -40 to +85 23
3 22
4 21
5 20
6 19
This device contains circuitry to protect the inputs against damage due to high 18
static voltages or electric fields..: t'lowever. It IS advised that normal precautions be 8 17
taken to avoid application of any voltage higher than maximum rated voltages
9 16
to this high impedance circuit. For proper operation it is recommended that
10 15
Vin and Vout be constrained to the renge VSS ~ (Vin or Vout' ~ VOO-
11 14
Unused inpuu must always be tied to an appropriate logic voltage level (e.g .• either
12 13
VSS or VOO'
Voo Tlow
. 25°C Thi h-
Characteristic Symbol Vdc Min Max Min Typ Ma. Mi" Ma. Unit
Output Voltage "0" Level VOL 5.0 - 0.05 - a 0.05 0.05 Vdc
Vin Vao or 0 10 - 0.05 .. a 0.05 - 0.05
15 - 0.05 .. a 0.05 - 0.05
"'" Level VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vdc

Vin o or Vao 10 9.95 - 9.95 10 - 9.95 -
15 14.95 - 14.95 15 - 14.95 -
Input Volt8ge# "0" level V'l Vdc
(VO 4.5 or 0.5 Vdcl 5.0 - 1.5 - 2.25 1.5 - 1.5
(VO " 9.0 or 1.0 Vdcl 10 _. 3.0 - 4.50 3.0 - 3.0
(VO" 13.5 or 1.5 Vdcl 15 - 4.0 6.75 4.0 - 4.0
••," Level VIH
(VO" 0.5 or 4.5 Vdcl 5.0 3.5 - 3.5 2.75 - 3.5 - Vdc
(VO" 1.0 or 9.0 Vdcl 10 7.0 - 7.0 550 - 7.0 -
1VO' 1.5 or 13.5 Vdcl 15 11.0 - 11.0 8.25 - 11.0 -
Output Drive Current IAL Device) 'OH mAde
1VOH ". 2.5 Vdcl Source 5.0 -1.2 - -1.0 -1.7 - -0.7 -
{VOH - 4.6 Vdcl 5.0 -0.25 - -0.2 -0.36 - -0.14 -
(VOH ' 9.5 Vdcl 10 -0.62 .- -0.5 -0.9 .. -0.35' -
1VOH ' 13.5Vdcl 15 -1.8 - -1.5 -3.5 - -1.1 -
1VOl = 0.4 Vdcl Sink IOl 5.0 0.64 - 0.51 0.88 - 0.36 - mAde
(VOL = 0.5 Vdc) 10 1.6 - 1.3 2.25 - 0.9 -
IVOl = 1.5 Vdcl 15 4.2 - 3.4 8.8 - 2.4 -
Output Drive Current ICL/CP Device) IOH mAde
(VOH = 2.5 Vdcl Source 5.0 -1.0 - -0.8 -1.7 - -0.6 -
1VOH = 4.6 Vdcl 5.0 -0.2 - ·0.16 -0.36 - -0.12 -
{VOH = 9.5 Vdcl 10 -0.5 - ·0.4 -0.9 - ·0.3 -
1VOH = 13.5 Vdcl 15 -1.4 - -1.2 -3.5 - ·1.0 -
1VOl = 0.4 Vdcl Sink IOl 5.0 0.52 - 0.44 0.88 - 0.36 - mAde
(VOL = 0.5 Vdc) 10 1.3 - 1.1 2.25 - 0.9 -
(VOL = 1.5 Vdcl 15 3.6 - 3.0 8.8 - 2.4 -
Input Current IAL Device) lin 15 - '0.1 - '0.00001 :to.' :t 1.0 ~Adc
Input Current ICLlCP Device) lin 15 - ,1.0 .- '0.00001 ,1.0 - "4.0 jJ.Adc
(Vin '" Q)
Quiescent Current (AL Devicel

'DO 5.0 - 5.0 - 0.050 5.0 - 150 ,uAde
(Per Packagel 10 -
_.
10 - 0.100 10 - 300
15 20 - 0.150 20 - 600
QUIescent Current (CUCP Device) 100 5.0 - 50 - 0.050 50 - 375 jJ.Adc
(Per Package) 10 - 100 - 0100 100 - 7SO
15 - 200 - 0.150 200 - 1500
Total Supply Current--t IT 5.0 IT' 11.98 ~A/kHzl I + 'DO ""Adc
(Dynamic plus Quiescent, 10 IT = (3.96 ~A/kHzl f + 100
Per Package) 15 IT" 15.86 ~A/kHzl f + 100
(CL -- 50 pF on all outputs, aU
buffers switching)
Three-State Leakage Cunent ITl 15 •. to.l - -0.00001 t 0.1 - 13.0 IlAdc
(AL Device)
Three-State Leakage Current ITl 15 .. il.o - -0.00001 11.0 - t 7.5 ~Adc
(CLlCP DeVice)
-Tlow '" -55°C for AL Device, -400C for CL/CP Device.

Thigh'" +1250C for AL Device. +8SoC for CL/CP Device.
#Noise immunity spet:ified for worst-case input combination.
Noise Margin for both "1" and "0" level = 1.0 Vdc min @ VOD "" 5.0 Vdc
2.0 Vdc min@ VOO "10 Vdc
2.5 Vdc min@ VOO ' 15 Vdc
3
IT1Cl) = 'T150 pFI +4 x 10. (Cl -SOl VOO'
where: IT is in IlA (per package). CL in pF. VOD in Vdc, and f in kHz is input frequency.
--The formulas given are for the typical characteristics only at 2SoC.
Chw_istlc Figure Symbol VOO Min Typ Mex Unit
Output Rise Time 1 'TLH n.
'TLH· 13.0 n./pFI CL + 30 n. 5.0 - 180 360
'TLH = 11.5 n./pFI CL + 25 n. 10 - 90 180
'TLH· (1.1 n./pFI CL + 10 no 15 - 65 130
Output Fall Time 1 'THL n.
'THL· (1.5 n./pF) CL + 25 n. 5.0 - 100 200
'THL - (0.75 n./pF) CL + 12.5 n. 10 - 50 100
'THL - (0.55 n./pFI CL + 9.5 n. 15 - 40 80
Read Cycle Time 1,2 'cyc(R) 5.0 2000 6000 n.
10 - 750 2200
15 - 500 1650
Write Cycle Time 3,4 'cyc(WI 5.0 - 1200 3600 n.
10 - 750 2200
15 - 500 1650
Address to ~ Setup Time 1,3 '.u(A-S'!'1 5.0 1500 500 - n.
10 450 150 -
15 350 120 -
Strobe to Address 'Hold Time 1,3' 'hIST·A) 5.0 150 50 - n.
10 .100 0 -
15 75 0 -
Address to Chip Enable Serup Time 2,4 'su(A-eEI 5.0 1800 600 - n.
10 600 200 -
15 450 150 -
Chip Enable to Address Hold Time 2,4 'h(CE-A) 5.0 450 150 n.
10 300 100 -
15 225 75 -
Strobe or Chip Enable Pulse Width When Reading 1,2 'WL(RI 5.0 1800 450 n.
10 450 150 -
15 350 100 -
~ or Chip Enable Pulse Width When Writing 3,4 'WL(WI 5.0 3600 1200 n.
10 1800 600 -
15 1350 400 -
Read Setup Time 1 "uIR) 5.0 0 -100 - n.
10 0 -40 -
15 0 -30 -
Read Hold Time 1 'h(RI 5.0 540 180 - n.
10 240 60 -
15 180 45 -
0lt8 Setup Time 3,4 "u(DI 5.0 1800 600 - n.
10 600 200 - .
15 450 150 -
Data Hold Time 3,4 'hlDI 5.0 600 200 n.
10 150 50 -
15 120 30 -
I Figure I
I I
Symbol VOO
~g ~=~ TVp
240
Max
-
Unit
n,
I
3.4 t,u(WEI 80 ..
i I 15 180 55 -
.,,-'- "~,,- I ,.. '<."
'
50 - I ns
I" ,~ 20 -
=-_."m.'..m'".~ j"I ~·"".t-iH~

+- =
15
2000
700
350
6000
2100
1600
-
n,
n,
1
Read Access TIme from Chip Enable I -2 tacC(R'CEJ-~ 2100 6300
Ou!!!.ut Enable/Disable
Wrote Enable
Delay from Ch." ;; ••
;;abl.
~.;~~J,._
or I -hi~jl.-~
.",,,. 'R (WE) I 10 -
750
400
400''-~-
200
2250-t~
1700
600
n,
I fhieO-S.ate Enable/Di,able Du.p~t Del-;;~---'-- - 2-- -~(Yl--t-~_· _.-:--

150
-'400 .-
~.---j
',2.00 I ;;-, i
. I - 4
Din Din Din Din

o 2 3
4 6 8 10
Q Q Q
CE123
CE2 22
CE3 21
3 toa
DO 00 3 00ut 0
Decoder 64 x 4
01 01 5 DOUl1
Memory
Latch ••
02 Q2 7 °out2
Array
3 toB
03 03 9 Dout 3
O-..oder
Voa = Pin 24
VSS = Pin 12
j
tcvc(A)
VOO
Addr •••
VSS
t,u
B Strobe
IA·ST)
tWL(R)
50"
VOO
VSS
Voo
Write Enable
Vss
t,u(A)
Latch Enable
OaU Out
tcyc(A) ~ ~
__ ~*50"
Note,: 1 - Unused a.~. M and 'f .re low and 'WI is high.
2 - High impedance output stata occurs when any n i, high
and M is low, or when'" i, high.
3 - The output display. data from the previous Itat •.
4 - tWL(R) > t.cc(A.CElmax·
tcyc(W)
VOO
*
Address
VSS
thIA-!rf)
II
VOO
Strobe
Vss
Voo
Write Enable
VSS
VOO
Oata In
Data Out
tacc(R-n)
3 4 E=~:: VOL
Not •• : 1 - CE', CE2, CE3 and T are maintained at the logical "0" level.
2 - M is maintained at the logical "'" level.
3 - Tha output displeys the contents of the previous state.
4 - The output displays the contents of the presently addressed location as in a
read modify write cycle.
S- The output displays the data that was wrinen into addressed location.
tCYC(W) 1.
Add,", --*50%
th (A-Cll~ -----------
'ouIA-~) ~
Voo
VSS
Voo
50%
------VSS
Not •• : 1 - High Impedance output "ate OCCurl when ~ il high or whan W'E
II low, for M and T ~int.lned In the low stete.
2 - Unu..s ~'I, 'JT. M and T .re maintained at the logical "0" level.
Funetion CEI CE 2 CE3 T lE M ST WE Din 0_.
R/.
Com_ta
,f
Addreu X X X X X X I X X DOUt WIll be ICt'~ ~I
CNrllWog X X I X X X X X X R/. CE· 0, T· 0 and WE· 1

V.lid X I X X X X X X X R/A OfttM-landT-a
1 X X X X X ·X X X R/A
Address Ch.ng,ng 0 0 0 X X X 0 X X R/. 00ut wilt be Kt'~ if T • 0
Not Valid ~dWI·lor,fM·t
and fo. 0
001,11 Q,Ybled
hn hrgh lesrst'l'ICl Ilalel X X I X X 0 X X X R D'Mbl" wrIte Clrcu'try
X I X X X 0 X X X R
1 X X X X 0 X X X R
X X X 1 X X X X X R T • 1 ,lwavs d,sables 001,11
X X X X X 0 X 0 X R M • 0 and write operatIon
d,1oabIes 001,11
DOU1 Er~bled 0 0 0 0 X X X 1 X A Reed OPeratIon. 001.11KlIve
II
(In Ktlvell'tel X X X 0 X I X X X A Reed Of •••••.
,te. 0nutIC1'VI
Re.td Addressed 0 0 0 X 0 X 0 X X R/A If WI •. O. D,n· 000.11

Memorv LocatIon
InlO Oulput latch
Disable Rncllng X X I X X X X X X R/A
FromM,mo.y X I X X X X X X X R/.
I X X X X X X X X R/.
X X X X X X 1 X X RIA
X X X X X X X 0 X R/A
Wrrte Into Memorv 0 0 0 X X X 0 0 A R/.
Wrtte D,sabled X X I X X X X X X R/A
X I X X X X X X X R/.
I X X X X X X X X R/.
X X X X X X I X X R/.
X X X X X X X I X R/A
Output lilCh Enabled 0 0 0 X 0 X 0 X X R/A
Output latch D,sabled X X 1 X X X X X X R/A
X 1 X X X X X X X R/A
X X R/A
i
I X X X X X X
X X X X I X X X X R/.
X X X X X X I X X R/A
R • Hogh reS,stance JI.te ., Dou1 x • Don', care cond'llon Imu" be In the .",. 0, "0" sta,el
A a An ICItYelevel 01 ."her Voa 0_ VSS 1 - A hogh level al Voa
AlA· An A Ot A conrl'hon depend,ng on Ihe c10n', el'e cond,llon o A low level a, VSS
)' )' )' )'

U3
U2
Ul
AS
A4
A3
A2
Al
AD
---< ST
---< T
All M .nd U :..,J"'14

inputs .,
grounded
• I 32 pi
I
CE3
U2
Ul
---< AS
- ---< A4
A3
A2
Al
AD
---< 5T
T
~~ ~~
® MOTOROLA
The MC145588 decodes 4-bit binary coded decimal data depen-

dent on the state of auxiliary inputs, Enable and RBI, and provides an
BCD-TO-SEVEN
active high seven-segmentoutput for a display driver.
An auxiliary input truth table is shown, in addition to the BCD SEGMENT DECODER
to seven-segmenttruth table, to indicate the functions available with
the two auxiliary inputs.
Leading Zero blanking is easily obtained with an external flip-flop
in time division multiplexed systems displaying most significant
decade first.
• Quiescent Current = 5.0 nA/package typical @ 5 Vdc L SUFFIX P SUFFIX

CASE 620 CASE 648
• Segment Blanking for All Illegal Input Combinations
• Lamp Test Function
• Capability for Suppression of Non-Significant Zeros
•
•
Lamp Intensity Function
Capable of Driving Two Low-power TTL Loads, One Low-power
MC14XXXB ~SU~f;:.::,:t::Ck'..
ature Range L P PlastiC Package
Temperature Range
e Limited Operating
Temperature Range

DC Supply Voltage VDD -05to+18 Vdc
Input Voltage. All Inputs V,n -0.5 10 VDD + 0.5 Vdc
DC Current Drain per Pm I 10 mAde
Operating Temperature Range .- AL Device TA -55 to +125 °c
Storage Temperature Range

CLlCP Device
T stg
-40 to +85
-65 to +150 °c
2
3
4 ·C/c
f'Z,b
5 d
6
7
8
BCD
Enable RBI Input RBD
Pin 3 Pin 5 Code Pin 4 Function Performed
0 o. x 0 Lamp Test
0 1 X 1 Blank Segments
1 1 0 1 Display Z.ro
1 0 0 0 Blank Segmen ts
1 X 1·9 1 1·9 0 isplaYed
X::: Don't Car.

RBI - Ripple Blanking Input
RBO = Ripple Blanking Output
Voo T10w . 25°C Thi h·
Charuteristic Symbol Vdc Min Max Min Typ Max Min Max Unit
Output Voilage ··0" Level VOL 5.0 - 0.05 - 0 0.05 - 0.05 Vdc
V,n VOO or 0 10 - 0.05 - 0 0.05 - 0.05
15 - 005 - 0 0.05 - 0.05
"1" Level VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vdc
V,n o or Vao 10 9.95 - 9.95 10 - 9.95 -
15 14.95 - 14.95 15 - 14.95 -
Input VoltageU "0" Level VIL Vdc
(VO 4.5 or 0.5 Vdcl 5.0 - 1.5 - 2.25 1.5 - 1.5
(VO a
9 or 1.0 Vdcl 10 - 3.0 - 4.50 3.0 - 3.0
(VO 135 Or 1.5 Vdcl 15 - 4.0 - 675 4.0 - 4.0
II
.,," Level V,H
(VO· 0.5 or 4.5 Vc1cl 50 3.5 - 3.5 2.75 - 3.5 - Vdc
(VO 1.0 or 9.0 Vdc) 10 7.0 - 7.0 5.50 - 7.0 -
(VO - 1 50< 13.5 Vdcl 15 11.0 - 11.0 8.25 - 11.0 -
Output Olive Current (AL DeVice) 'OH mAde
(VOH 2.5 Vdcl Source 50 -3.0 - -2.4 -4.2 - -1.7 -
1VOH 4.6 Vdcl 5.0 -0.64 - -0.51 -0.88 - -0.36 -
(VOH "9.5 Vdcl 10 -1.6 - -1.3 -2.25 - -0.9 -
(VOH • 13.5 Vdcl 15 -4.2 - -3.4 -8.8 - -2.4 -
1VOL - 0.4 Vdc) Sink 'OL 5.0 0.64 - 051 0.88 - 0.36 - mAde
(VOL: 0.5 Vdcl 10 16 - 1.3 2.25 - 0.9 -
(VOL" 1.5 Vdcl 15 4.2 - 3.4 8.8 - 2.4 -
Output Drive Current (CL/CP Device) 'OH mAde
{VOH • 2.5 Vdcl Source 5.0 -2.5 - -2.1 -4.2 -1.7 -
IVOH - 4.6 Vdcl 5.0 -0.52 - -0.44 -0.88 - -0.36 -
1VOH - 9.5 Vdcl 10 -1.3 - -1.1 -2.25 - -0.9 -
1VOH - 13.5 Vdcl 15 -3.6 ..
-3.0 -8.8 - -2.4 -
(VOL" 0.4 Vdcl Sink 'OL 5.0 0.52 - 0.44 0.88 - 0.36 - mAde
IVOL " 0.5 Vdcl 10 1.3 - 1.1 2.25 - 0.9 -
{VOL' 1 5 Vdcl 15 3.6 - 3.0 8.8 - 24 -
Input Current tAL Devlcel 'on 15 - ,01 - ,000001 ,01 - .!. 1.0 /-lAde
Inpul Current (CLlCP DeVice) ',n 15· - '03 - ~O.OOOOl '03 - , 1.0 /-lAde
Input Capacitance C,n - - - - 50 7.5 - - pF

(V1n 01
QUIescent Current (AL DeVice) 100 50 5.0 - 0.005 5.0 - 150 /-lAde
{Per Packagel 10 - 10 - 0.010 10 - 300
15 - 20 - 0.Q15 20 - 600
QUiescent Current IClfCP Devlcel 100 5.0 - 20 - 0.005 20 - 150 ",Adc
(Per Pac;kaqel 10 - 40 - 0.010 40 - 300
15 .. 80 - 0.015 80 - 600
TOlal Supply CUHent·· t IT 50 IT" 11.2 "A/kHZ) I + 100 .uAde
(DynamiC plus OUlescent, 10 'T; 12.4 "A/kHz) I + 100
Per Packaqel 15 IT" 13.6 "A/kHz) f + 100
(CL 50 pF on all outputs, all
buffers SWItching)
·T1ow -55°C for AL DeVice, -40°C for CL/CP DeVice.

Thigh - .1250C for AL DeVice, -+850C for CL/CP DeVice.
.:.:NolseImmunlly spt:c.:d'edfOl worst·case Input combination
NOiseMiHQln fOI both "1" and "0" level 1.0 Vdc min @ VOO ~ 5.0 Vdc
20 Vdc min @ VOD . 10 Vdc
2.5 Vdc min @ VOO 15 Vdc
tTo calculate total supply current at loads olher than 50 pF
ITICl' 'T(50 pF) + 4 x 1O-31Cl -501 VOO'
where IT's In ~A (per packagel. CL in pF, Vaa In Vdc. and f In kHz ISinput frequency .
•• The formulas given are for the typical characteflsllcs only at 25°C.
This device 'contains circuitry to protect the inputs against damage due to high static voltagesor electric fields; however. it is ad·
vised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high im-
pedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS " (Vin or Voutl
" VOO
Unused inputs must always be tied to an appropriate logic voltage level le.g., either Vss or Vaal.
Characteristic Symbol VOO Min Typ Mo. Unit
Output Rise Time 'TLH n.
'TLH = 13.0 n./pFI CL + 30 n. 5.0 - '00 200
'TLH' 11.5 n./pFI CL +'5 ns ,0 - 50 '00
'TLH' (,., ns/pF) CL +'0 ns 15 - 40 80
Output Fall Time 'THL n.
'THL = ('.5 ns/pFI CL + 25 ns 5.0 - '00 200
,
'THL = (0.75 ns/pF) CL + 12.5 ns '0 - 50 '00
'THL = 10.55 ns/pFI CL + 9.5 ns '5 - 40 80
ProPagation Delay Time tpLH n.
=
tpLH (1.7 ns/pFI CL + 495 ns 5.0 - 580 1160
tPLH = (0.66 ns/pF) CL + '87 ns '0 - 220 440
tPLH = (0.5 ns/pF I CL + 120 ns '5 - ,45 230
ProPagation Delay Time tPHL n.
=
tPHL (1.7 ns/pFI CL + 695 n. 5.0 - 780 '560
tpHL' (0.66 ns/pFI CL + 242 ns '0 - 275 550
=
tPHL (0.5 ns/pFI C, + '60 ns '5 - ,85 370
En
Pm 3
RBI
Pin 5
D
Pin 6
INPUTS
C
Pin 2
B
Pin 1
A
Pin 7
.
Pin 13
b
Pin 12
c
Pin 11
d
Pin 10
OUTPUTS'
e
Pin 9
f
Pin 15
9
Pin 14
RBO
Pin 4 DISPLAV
1 1 0 0 0 0 1 1 1 1 1 1 0 1
n
U
1
• 0 0 0 1 0 0 0 0 1 1 0 1
I
I
1
• 0 0 1 0 1 1 0 1 1 0 1 1
2
1
• 0 0 1 1 1 1 1 1 0 0 1 1
3
1
• 0 1 0 0 0 1 1 0 0 1 t 1 '-I
1
• 0 t 0 t t 0 t t 0 t 1 1
5
1
• 0 1 t 0 0 0 1 t t 1 1 1
b..,
1
• 0 1 1 t t t 1 0 0 0 0 1
I
1 X t 0 0 0 1 1 1 t 1 1 1 1
B
t
• t 0 0 t t 1 t 0 0 1 1 1 q
t 0 0 0 0 0 0 0 0 0 0 0 0 0 BI.nk
0 0
• • • • t , t t t 1 t 0 B
0 1
• • • • 0 0 0 0 0 0 0 1 BI8nk
II
t'l
~ Ol U 0
i
c
w
® MOTOROLA
SUCCESSIVE APPROXIMATION
The MC14549B and MC14559B successiveapproximation regis-
REGISTERS
ters are B-bit registers providing all the digital control and storage
necessary for successiveapproximation analog-ta-digital conversion
systems. These parts differ in only one control input. The Master
Reset (MRI on the MC14549B is required in the cascaded mode
when greater than B bits are desired. The Feed Forward (FF I of the
MC14559B is used for register shortening where End·of·Conversion
(EOC) is required after lessthan eight cycles.
Applications for the MCI4549B and MC14559B include analog-
L SUFFIX P SUFFIX
to-digital conversion, with serial and parallel outputs.
CASE 620 CASE 648

• Totally Synchronous Operation
• All Outputs Buffered
•
•
Single Supply Operation
Serial Output .<,.m'1l;sUffiX L
Denotes
Ceramic Package
• Retriggerable
P PlastIC Package
• Compatible with a Variety of Digital and Analog Systems such as A EJo:tended Operating
the MC140B B-Bit D/A Converter Temperature Range
C limited Operating
• All Control Inputs Positive-Edge Triggered
Temperature Range
• Supply Voltage Range = 3.0 Vdc to lB Vdc
ature Range

DC Supply Voltage VOO -05 to +18 Vdc
Input Voltage, All Inputs V,n -0.5 to VOO • 0.5 Vdc
DC Current Drain per Pm I to mAde
Storage Temperature Range TSt9 -65 to +150 °c
SC SCIl-tl
X X
MA MAI._II
X X
Clod<
-----,....
Action
None
SC SCI._II
X X
EOC
X
.....
Clock Action
None
X X 1 X -r Aewt 1 0 0 .J"" Start
ConverSion This device contains circuitry to protect
1 0 0 0
...r- 5ta,t X 1 0
...r Continue the inputs aglinst damage due to high static
Conyer,ion ConverSion volt.s or electric fields; however, it is
1 X 0 1
...r- Start 0 0 0
...r Continue
Conver,ion Conv.lion to avoid appliClition of any voltage higher
1 I 0 0
...r- Continue 0 X 1
...r Retain
impedance cirCUit. For proper operation it
Com".nion Conversion
Result is recommended that Vin and Vout be
0 X 0 X ...r- Continue 1 X 1 ...r 5ta,t

constrained to the range VSS ::s;;; «Vin or
Previous Conversion Vou') ';;VOO·
Operation Unused inputs must always be tied to an
Vssor Vool.
® MOTOROLA
PHASE COMPARATOR AND

PROGRAMMABLE COUNTERS
The MC14568B consists of a phasecomparator, a divide-by-4, 16,
64 or 100 counter and a programmable divide-by-N 4-bit binary PHASE COMPARATOR
counter (all positive-edge triggered) constructed with MaS P-charinel AND PROGRAMMABLE
and N-channel enhancement mode devices (complementary MaS) in
COUNTERS
a single monol ithic structure.
The MC14568B has been designed for use in conjunction with a
programmable divide-by-f'J counter for frequency synthesizers and
phase-locked loop applications requiring low power dissipation and/
-
or high noise immunity.
--
t. ·t· -,
This device can be used with both counters cascaded and the
output of the second counter connected to the phase comparator
(CTL high). or used separateof the programmable divide-by-N coun-
I
,
ter, for example cascadedwith MC14569B (CTL lowl, MC14522B or
MC14526B. L SUFFIX P SUFFIX
• Quiescent Current = 5.0 nA typ/pkg @ 5 Vdc
CASE 648
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 620
• Capable of Driving Two Low-Power TTL Loads, One Low-Power

Schottky TTL Load or Two HTL Loads Over the Rated Tempera-
ture Range.
MC14XXXB ~SU~f;.c.::,:t::Ck...
L. P Plastic Package
A Ex.tended Operating
Temperature Range
DC Supply Voltage VDD -0.510+18 Vdc e Limited Operating
Input Voltage, All Inputs -05 to VDD + 0.5 Vdc Temperature Range
V,"
Storage Temperature Range T stg -65 to +150 °c F G Division R.tio
Pin 10 Pin '1 of Counter 01
0 0 4
BLOCK DIAGRAM 0 1 16
r----------, 1 0 64
I I 1 1 lOO
13 peout
12 pePoul
CTL HIGH
PCOllt
llG
C1
p.C.
10 ,:: PC;~
CTL 15 PCP out
C1
01
"0"
, QlIC2
PE
"O"~
~-Q1'iC2
"0"
VOO Pin 16
5 6
Pin 8
Dp2 Dp1
VSS
VOO Tlow· 25°C Thi h·
Characteristic Symbol Vdc Min Ma. Mi" TVp Max Min Ma. Unit
Output Voltage "0" Level VOL 5.0 - 0.05 - 0 0.05 - 005 Vdc
Vi" VOO or 0 10 - 0.05 ..
0 0.05 - 0.05
15 .. 0.05 .- 0 0.05 - 0.05
"1" Level VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vdc
Vi" o or VOD 10 9.95 - 9.95 10 - 9.95 ..
15 14.95 - 14.95 15 - 14.95 ..
Input Voltage # t "0" Level V,L Vdc

(VO - 4.50,0.5 Vdc) 5.0 - 1.5 - 2.25 1.5 - 1.5
IVO 9.0 or 1.0 Vdcl 10 - 3.0 - 4.50 3.0 -- 3.0
(VO - 13.50,1.5 Vdcl 15 - 40 - 6.75 4.0 - 40
II Output
IVO
(VO'
0.5 or 4.5 Vdcl
1.00,9.0
IVO ~ 1.5 or 13.5 Vdc)
DrIve Current
Vdc)
(AL
"1" Level
DeVice)
V,H
'OH
5.0
10
15
35
7.0
11.0
-
-
-
3.5
7.0
11.0
2.75
5.50
8.25
.-
-
-
3.5
7.0
11.0
-
-
-
Vdc
mAde
(VOH - 2.5 Vdcl Source 5.0 -1.2 - -1.0 -1.7 - -0.7 -
(VOH " 4.6 Vdc) 5.0 -0.25 - -0.2 -0.36 - -0.14 -
IVOH • 9.5 Vdcl 10 -0.62 - -0.5 -0.9 - -0.35 -
IVOH' 13.5 Vdc) 15 -1.8 - -1.5 -3.5 - -1.1 -
IVOL • 0.4 Vdc) Sink tOL 5.0 0.64 - 0.51 0.88 - 036 - mAde
(VOL' 0.5 Vdc) 10 1.6 - 1.3 2.25 - 0.9 -
IVOL' 1.5 Vdcl 15 4.2 - 3.4 8.8 - 2.4 -
Output Drive Current (CLlCP Device) IOH mAde
IVOH • 2.5 Vdcl Source 5.0 -1.0 .. -0.8 -1.7 .. -06 -
(VOH • 4.6 Vdcl 5.0 -0.2 - -016 -036 - -0.12 -
(VOH • 9.5 Vdcl 10 -0.5 .. -0.4 -0.9 - -03 -
IVOH' 13.5 Vdcl 15 -1.4 - -1.2 -3.5 - -1.0 -
(VOL' 0.4 Vdcl Sink 'OL 5.0 '0.52 - 0.44 0.88 - 0.36 - mAde
(VOL' 0.5 Vdc) 10 13 - 1.1 2.25 - 0.9 -
(VOL' 1.5 Vdc) 15 3.6 .. 3.0 8.8 - 2.4 -
Input Current (AL DeVice) lin 15 '01 - ,000001 '01 ! 1.0 JJAdc
I"pul Current (CLlCP Device) lin 15 - '03 - to.OOOOl , 0.3 - , 1.0 ,..Adc
Input Capacitance C,n .. -- 50 7.5 - pF
(Vi" = 01
QUiescent Current (AL Device) 5.0 .- 5.0 0.005 5.0 ..
150 /JAde
100
(Per Package) 10 - 10 - 0.010 10 300
15 20 - 0-015 20 - 600
QUiescent Current ICLlCP DeVIce) 'DO 50 - 20 - 0.005 20 - 150 pAde
(Per Package) 10 - 40 - 0.010 40 - 300
15 - 80 - 0-015 80 - 600
Total Supply Current-· t IT 5.0 'T • 10.2 "A/kHz) I ~ 100 IJAdc
(Dynamic plus Quiescent. 10 IT • 10.4 "A/kHz) I + 100
Per Package) 15 IT' 10.9 "A/kHz) 1+100
eel" 50 pF on all outputS, all
buffers switching)
Three-State Leakage Current, Pins 1, 13 ITL 15 - .0.1 - .0.‫סס‬oo1 .0.1 - ,3.0 I-lAdc
(AL Device)
Three-State Leakage Current, Pins 1, 13 ITL 15 - ± 1.0 - .0.00001 ,1.0 - , 7.5 J.lAdc
(CL/CP Devices)
·Tlow .".-5SoC for AL Device. -40oC for CL/CP Device.
Thigh '" +12SoC for AL Devtce. +850C for CLlCP Device .
•.Noise immunity 5Pe'l:ified for worst·case input combination.
Noise Margin for both "1" and "0" level'" 1.0 Vdc min @ v.OO :" 5.0 Vdc
2.0 Vdc min @ VOO ..; 10 Vdc 16
2.S Vdc min@ VOO '" 15 Vdc
fTo calculate tOlal supply current at loads other than 50 pF. 2 15
ITICL' • 'T(50 pF) + 1 • 10-3 (CL -SOl VOOI 3 14
where: IT is in JlA (per package). CL in pF. VOD in Vdc. and f in kHz is Input frequency.
4 13
·-The formulas given are for the typical characteristics only at 2SoC.
tPin 15 is connected to Vss or VOO for input voltage test.

._---
Symbol VOO Min Typ Mox Unit
Characteristic
Vd.
Output Rise Time tTLH 5.0 - 180 360 ns
10 - 90 180
15 - 65 130
i--=----- ------------- ..-------
Output Fall Time tTHL 5.0 - 100 200 ns
10 - 50 100
15 - 40 80
1----=-c---------
-
f------------ -
Minimum Pulse Width, Cl, Ql/C2, or PCin Input tWH 5.0 125 250 ns
10 - 60 120
15 - 45 90
Maximum Clock Rise and Fall Time, tTLH. 5.0 15 - -
."
Cl, Ql/C2, or PCin Input
L- _____
...,-----,-----------
Input Resistance
Input Sensitivity, DC Coupled
_._- I
tTHL
Rin
-
10
15
5.0 to 15
5.0 to 15
'-----
15
15
- I
-
-
106
-
-
-
See Input Voltage
Mn
II
Turn-Off Delay Time, tPHL 5.0 550 1100 ns
PCout and PCPout Outputs 10
15
-
-
195
120
I 390
240
Turn-On Delay Time, tPHL 5.0 - 675 1350 ns
PCout and PCPout Outputs 10 - 300 600
L.-
I
15 - 190 380
DIVIDE-BY-4, 16,64 OR 100 COUNTER (D1)
I Maximum Clock Pulse Frequency
lei
MHz
ion Ratio::: 4, 64 or 100 5.0 3.0 6.0 -
I
~ DIVIS
10 8.0 16 -
15 10 22 -
ion Ratio = 16 5.0 1.0 2.5 - MHz
I 10
I 3_0 6.3 -
L- I 15 5.0 9.7 -
,
Propagat ion Delay Time, Ql/C2 Output I tpLH. ~ ns
I DIvis ion Ratio::: 4, 64 or 100

I tPHL 5.0
10
-
-
450
190
900
380
I 15 - 130 260
LV'S ion Ratio:. 16 5.0

10
15
-
-
-
720
300
200
1440
600
400
ns
Maximum Clock Pulse Frequency lei I 5.0
I (Figure 3al I 10
15
I Turn-On Delay Time, "0" Output tpLH 5.0
: (Figure 3a) 10
15
tPHL 5.0
10
15
tWH(PEI 5.0
10
'15
strained to the range VSS ,,; (Vin or Vout) ,,; VOO'
SWITCHING TIME TEST CIRCUITS AND WAVEFORMS
FIGURE 1 - PHASE COMPARATOR
~
2 "O"out REF
II
20n~tWIC1)
I,n ' .•,a.
tpHL
Ql/£2
1('"
"0" ::L~~"
~~
'";j
tTHL--ft=
_
~_O'3PCOUt
Voo'" Pin 16
VSS = Pin 8
Typical Maximum Frequency Divider 01 Typical Maximum Frequency Divider 01
Division ratios: 4,64 or 100 (Cl = 50 pF) Division ratio: 16 (Cl = 50 pF)
6~
"- '"
II 1
......
""
~
"'"
",-VoD,'5V
"'" "I'
"-
~
"'"
~ Voo' 10 V
""'-- ....
Typical Maximum Frequency Divider 02

DiVisionratio: 2 (Cl = 50 pF)
-. -- -- -- -
- Voo' 5 V
The MC14568B contains a phase comparator, a fixed If the input signals have different frequencies, the out·
divider (0- 4, 0- 16, 0- 64, 0- 100) and a programmable put signal will be high when signal B hasa lower frequency
divide·by·N 4·bit counter. than signal A, and low otherwise.
Under the sameconditions of frequency difference, the
output will vary between VOH (or Val) and some inter·
The phase comparator is a positive edge controlled mediate value until the frequencies of both signals are
logic circuit. It essentially consists of four flip·flops and equal and their phase difference equal to zero, i.e. until
an output pair of MaS transistors. Only one of its inputs locked condition is obtained.
(PCin, pin 14) is accessible externally. The second is Capture and lock rangewill be determined by the VCO
connected to the output of one of the two counters D 1 frequency range. The comparator is provided with a lock
or D2 (seeblock diagram). indicator output, which will stay at logic 1 in locked
II
Duty cycles of both input signals(at A and B) need not conditions.
be taken into consideration since the comparator responds The state diagram (Figure 5) depicts the internal state
to leading edgesonly. transitions. It assumesthat only one transition on either
If both input signals have identical frequencies but signal occurs at any time. It shows that a change of the
different phases,with signal A (pin 14) leading signal B output state is always associatedwith a positive transition
(Ref.), the comparator output will be high for the time of either signal. For a negativetransition, the output does
equal to the phasedifference. not change state. A positive transition may not causethe
If signal A lags signal B, the output will be low for the output to change; this happens when the signals have
same time. In between, the output will be in a three·state different frequencies.
condition and the voltage on the capacitor of an RC filter
normally connected at this point will have some inter· DIVIDE BY 4,16,64 OR 100 COUNTER (011
mediate value (see Figure 41.When used in a phaselocked This counter is able to work at an input frequency of
loop, this value will adjust the Voltage Controlled ascii· 5 MHz for a VDD value of 10 volts ovet the standard
lator frequency by reducing the phasedifference between temperature range when dividing by 4, 64 and 100. Pro·
the reference signal and the divided VCO frequency to gramming is accomplished by use of inputs F and G (pins
zero. 10 and 111 according to the truth table shown. Connect·
ing the Control input (CTl, pin 15) to VOO allows cas·
FIGURE 4 - PHASE COMPARATOR WAVEFORMS cading this counter with the programmable divide-by-N
A (PCinl---4
n
I _~
n-
'--
VOO
VSS
counter provided in the same package. Independent
operation is obtained when the Control input is con-
nected to VSS.
IRefl---lrL---Jh=
,. ~::
l~l/f~ll
The different division ratios have been chosen to gen-
erate the reference frequences corresponding to the chan-
B
nel spacings normally required in frequency synthesizer
PCP out -U I I
U
II
,
V
VOL
OH
applications. For example, with the division ratio 100
and a 5 MHz crystal stabilized source a reference fre-
quency of 50 kHz is supplied to the comparator. The
PCout --.Y u. ;_--- VOH lower division ratios permit operation with low frequency
,---- VOL crystals.
If used in cascade with the programmable divide·by·N DP3 (pins 7 ... 4). The Preset Enable input enables the
counter, practically all usual reference frequencies, or parallel preset inputs DpQ ... DP3. The "0" output must
channel spacings of 25, 20. 12.5, 10, 6.25 kHz, etc. are be externally connected to the PE input for single stage
easily achievable. applications. Since there is not a cascade feedback input,
this counter. when cascaded, must be used as the most
PROGRAMMABLE OIVIOE·BY·N significant digit. Because of this, it can be cascaded with
4·BIT COUNTER (021 binary counters as well as with BCD counters IMC14569B,
MC14522B, MC14526B).
CF CF
C Me 145228 Q4 C Me 145228 04
0' 0'
MC14526B MC14526B
"0"
C Mixer
I
L_ _ _ .JI 2k
II
Nl N2 N3
(0-5) (0-9) (0,4,8,12)
(625 kHz steps) (62.5 kHz steps) (6.25 kHz steps)
Example: Figures shown in parenthesis

fout = Nl (MHz) + N2 (xl00 kHz) + N3 (x25 kHz) refer to example.
Frequency range = 5 MHz
Channel spacing = 25 kHz
Reference frequency = 6.25 kHz
.91-1.20 C2.55) MHz
N - 91-120 (255) MHz
NOTE,
1. 10 kHz Channa' speclng
2. expandable to 165 Channel,
(Expanded frequency range
shown In par.nth •••• )
To Tr.nlfTlitter
26.965-27.255
C28.605) MHz
® MOTOROLA MC14573
MC14574
MC14575
QUAD PROGRAMMABLE OPERATIONAL AMPLIFIER

QUAD PROGRAMMABLE COMPARATOR QUAD PROGRAMMABLE
DUAL/DUAL PROGRAMMABLE OPERATIONAL AMPLIFIER
AMPLIFIER-COMPARATOR QUAD PROGRAMMABLE
COMPARATOR
The MC14573, MC14574, and MC14575 are a family of Quad opera- DUAL/DUAL PROGRAMMABLE
tional low power amplifiers and comparators using the complementary OPERATIONAL
P-channel and N-channel enhancement MOS devices in a single
AMPLIFIER-COMPARATOR
monolithic structure. The operating current is externally programmed
with a resistor to provide a choice in the tradeoff of power dissipation
and slew rates. The operational amplifiers are internally compensated.
These low cost units are excellent building blocks in consumer, in-
dustrial, automotive and instrument applications. Active filters, voltage
reference, function generators, oscillators, li""t set alarms, TTL-to-
CMOS or CMOS-to-CMOS up converters, A-to-D converters and zero
crossing detectors are some applications. These units are useful in both
battery operated and line operated systems.
• Low Cost Quads

• Power Supply - Single 3.0 to 15 Vdc L SUFFIX P SUFFIX
Dual ± 1.5 to ± 7.5 Vdc CASE 62(l CASE 648
• Wide Input Voltage Range
I1
• Common Mode Range 0.0 to VDD - 2.0 Vdc for Single Supply
• Externally Programmable Power Consumption with One or Two
Resistors
• Internally Compensated Operational Amplifiers MC14XXX Denotes
SUffoK
• High Input Impedance
~ l Ceramic Package
• Comparators - JEDEC B-Series Compatible P PlasticPackage
C limited Operating
Temperature Range
PIN ASSIGNMENT
Output A Output 0
MCl4673
Quad Op Amplifier
Inputs A { } Inputs 0
MCl4674 '!D~ VSS

Quad Comparator
Inputs B { } Inputs C
MCl4675
Dual Op Amplifier IA & Bl plus Output B Output C
Dual Comparator IC & Dl
ISet A, B ISet C, 0
DS9ll34
2-199
Rating Symbol Valua Unit This device contains circuitry to protect the inputs
DC Supply Voltage -0.5 to + 18 Vdc against damage due to high static voltages or elec-
VOO
tric fiMjs; however. it is advised that normal precau·
Input Voltage, All Inputs Vin - 0.5 to VOO + 0.5 Vdc tK>ns be taken to avoid application of any voltage
DC Current Drain per Pin I 10 mAdc higher than maximum rated voltages to thiS high im-
pedance circuit. For proper operation it is recom-
Programming Current Range ISet 2 mA
mended that Vin and Vout be constrained to the
Operating Temperature Range TA -40 to +85 'C range VSS :s (Vin or Vout) :S Voo
Storage Temperature Range Tstg -85 to + 150 'C
Package Power Dissipation· Pn 800 mW

DC Supply Voltage VOO to VSS +3.0 to + 15 Vdc
Programming Current VOO = 3V ISet 2 to 50 pA
5V<VOO<15V 2 to 750
VOO Unit
Characteristic Symbol Min Typ Max
Vdc
Input Common Mode Voltage Range VICR 3 0 - 1.5 Vdc
5 0 - 3.5
10 0 - 85
15 0 - 13.5
Output Voltage Range YOR 3 0.05 - 2.95 Vdc
RL = 1 MO to VSS 5 0.05 - 4.95
10 0.05 - 9.95
15 0.05 - 14.90
Input Offset Voltage V\O 3 - ±5 ±30 mVdc
MCl4573, MCl4575 5 - ±8 ±30
10 - ±10 ±30
15 - ± 10 ±30
Average Temperature Coefficient of VIO 4VI0/4T - - 15 - pV/'C
Input Capacitance Cin - - 5 10 pF
Input Bias Current IIR - - 1 50 pA
Input Bias Current TA = -40'C to +85°C 118 - - - 1 nA
Input Offset Current 110 - - - 100 pA
Open Loop Voltage Gain Vo = 1 V pop AVOL 3 2 8 - V/mV
Vo = 3 V pop 5 8 10 -
Vo = 6Vp-p 10 8 12 -
Vo = 9Vp-p 15 8 12 -
Power Supply Rejection Ratio PSRR 3 45 57 - dB
MC14573, MCl4575 5 54 67 -
10 54 67
15 54 67 -
Common Mode Rejection Ratio CMRR 3 45 70 - d8
MC14573, MC14575 5 50 73 -
10 54 75 -
15 54 75 -
Output Source Current 10H - 55 80 - pA
VOH = VOO -0.6 V
Output Sink Current VOL = 0.4 V 10L 3 2.1 4.2 - mA
Vin+ =VOO/2+0.5 VOL = 0.4 V 5 2.5 5.0 - -
Vin- =VOO/2-0.5 VOL = 0.5 V 10 5.5 11.0 -
VOL = 1.5V 15 15 30 -
Slew Rate SR - 0.6 0.8 - Vips
Unity Gain Bandwidth GBW 5 05 1 - MHz
Phase Margin </1M - - 45 - Degrees
Channel Separation - - - 80 - dB
Supply Current Per Pa" lRL = go} , 100 - - 260 340 pA
VOO
Characteristic Symbol
Vdc Min Typ Ma. Unit
Input Common Mode Voltage Range VICR 5 0 - 3 Vdc

10 0 - 8
15 0 - 13
Output Voltage Range VOR 5 0.1 - 4.8
RL = lOOK to VSS 10 0.1 - 98
15 0.1 - 14.8 Vdc
Input Offset VoltaQe VIO 5 - ±8 ±3O mVdc
MC14573, MC14575 10 - ±10 ±3O
15 - ± 12 ±3O
Average Temperature Coefficient of VIO ~VIO/~T - - 20 - I'V/·C
Input Capacitance
Input Bias Current
Input Bias Current
Input Offset Current
Open Loop Voltage Gain
TA - -40·C
Vo
to
=
+ 85·C
3Vp-p
Cin
liB
liB
110
-
-
-
-
5
-
-
-
-
t
5
1
-
-
2
10
50
1
100
-
pF
pA
nA
pA
V/mV
EJ
AVOL
Vo = 6Vp-p 10 1 3 -
Vo = 9VP-P 15 1 4 -
Power Supply Rejection Ratio P3RR 5 45 54 - dB
MC14573, MC14575 10 54 67 -
15 54 67 -
Common Mode Rejection Ratio CMRR 5 40 56 - dB
MC14573, MC14575 10 50 67 -
15 50 70 -
Output Source Current VOH = Vaa - 1.5V 10H - 550 800 - jiA
Output Sink Current VOH-O.4V 10L 5 2.2 4.2 - mA
VOH = 0.5 V 10 5.0 10.0 -
VOH = 1.5 V 15 15 30 -
Slew Rate SR - 5 7 - VII's
Unity Gain Bandwidth GBW 5 1.5 3 - MHz
Phase Margin q,M 4B Degrees
Supply Current Per Pair IRL = 001 100 - - 2.6 3.4 mA
Voo
Characteristic Symbol Min Typ Max Unit
Vdc
Input Common Mode Voltage Range VICR 3 0 - 1.5 Vdc
5 0 - 3.5
10 0 - 8.5
15 0 - 13.5
Output Voltage Range VOL 3 - 0 0.05 Vdc
"0" Level 5 - 0 0.05
10 - 0 0.05
15 - 0 0.05
Output Voltage Range VOH 3 295 3 - Vdc
"1" Level 5 4.95 5 -
II
10 9.95 10 -
15 14.95 15 -
Input Offset Voltage VIO 3 - ±8 ±3O mVdc
MC14574, MC14575 5 - ±8 ±3O
to - ±10 ±3O
15 - ±10 ±3O
Average Temperature Coefficient of VIO ~VIO/~T - - 15 - ~V/oC
Input Bias Current 118 - - 1 50 pA
Input Bias Current TA = -40°C to +85°C 118 - - - 1 nA
Open Loop Voltage Gain VOL 3 1 20 - V/mV
5 1 to -
10 1 6 -
15 1 6 -
Power Supply Rejection Ratio PSRR 3 45 57 - d8
MC14574, MC14575 5 54 67 -
10 54 67 -
15 54 67 -
Common Mode Rejection Ratio CMRR 3 45 55 - d8
MC14575, MC14575 5 50 65 -
10 54 67 -
15 54 67 -
Output Source Current VOH = 2.6 V 10H 3 -0.35 -0.65 - mA
VOH = 2.5 V 5 -25 -5.0 -
VOH = 4.6 V 5 -000 - 1.1 -
VOH = 9.5 V 10 -1.3 -2.5 -
VOH = 13.5 V 15 -5.0 -9.5 - I
Output Sink Current VOL = 0.4 V 10L 3 13 2.6 - mA
VOL = 0.4 V 5 19 38 -
VOL = 0.5 V 10 3.5 65 -
VOL=I.5V 15 14 25 -
Output Rise and Fall Time. 100 mV Overdrive tTLH, 3 - 140 250 ns
tTHL 5 - 100 180
10 - 120 200
15 - 140 250
Propagation Delay Time. 5 mV Overdrive td 3 - 15 30 ~s
5 - 10 20
to - 12 24
15 - 15 30
Propagation Delay Time, 100 mV Overdrive 1<1 3 - 4 8 ~s
5 - 2 4
10 - 3 6
15 - 4 8
Channel Separation - - - 80 - d8
Supply Current, Per Pair IDD - - 180 250 ~A
VOO
Characteristic Symbol Min Typ Max Unit
Vdc
Input Common Mode Voltage Range VICR 5 0 - 3 Vdc
10 0 - 8
15 0 - 13
Output Voltage Range VOL 5 - 0 0.05 Vdc
"0" Level 10 - 0 005
15 - 0 005
Output Voltage Range VOH 5 4.95 5 - Vdc
"1" Level 10 9.95 10 -
15 14.95 15 -
Input Offset Voltage VIO 5 - ±10 ±30 mVdc
MC14574, MC14575 10 - ±13 ±30
15 - ±15 ±30
Average Temperature Coefficient of VIO - 40°C to + 85°C Jl.VIO/Jl.T - - 20 - ~V/oC
Input Bias Current IF8 - - 1 50 pA
Input Bias Current - 40°C to + 85°C liB - - - 1 nA
Open Loop Voltage Gain AVOL 5 2 7 - V/mV
10 1 4 -
15 1 4 -
Power Supply RejectIon Ratio PSRR 5 45 67 - dB
MC14574, MC14575 10 54 67 -
15 54 67 -
Common Mode Rejection Ratio CMRR 5 40 65 - dB
MC14574, MC14575 10 50 67 -
15 50 67 -
Output Source Current VOH = 2.5 V 10H 3 -2.5 -5.0 - mA
VOH = 4.6 V 5 -0.60 -1.1 -
VOH = 9.5 V 10 -13 -2.5 -
VOH = 13.5 V 15 -5.0 -9.5 -
Output Sink Current VOL = 0.4 V 10L 5 1.9 3.8 - mA
VOL = 0.5 V 10 3.5 6.5 -
VOL=1.5V 15 14 25 -
Output RIse and Fall Time. 100 mV Overdrive tTLH, 5 - 75 150 ns
tTHL 10 - 50 100
15 - 45 90
Propagation Delay Time. 5 mV Overdrive td 5 - 2.5 50 ~s
10 - 35 7
15 - 5 10
Propagation Delay Time, 100 mV Overdrive l(j 5 - 0.6 1.2 ~s
10 - 0.75 1.5
15 - 0.75 1.5
Supply Current, Per Pair 100 - - 1.8 2.5 mA
Voo
~tB
~
ISetCircuit~. ldJ
EI Non-Inverting
Input 1+)..
Inverting,
j
-
~
-
Input 1- I I I---- ---.;
IT: I 11]________._
T
VSS
Voo
ISetCircuit~. ~dj ;dl

Non-Inverting
Inputl+) ••
j
-
~
-
Inverting,
Inputl-J II-- ~
-1] ,1] 1] VSS

The programming current ISet is fixed by an external If a pair of op amps is not used, the ISet pin for that pair
resistor RSet connected between V SS and either one or may be tied to VDD for minimum power consumption. To
both of the ISet pins 18and 9l. When two external program- minimize power consumption in an unused pair of com-
ming resistors are used, the set currents for each op amp pair parators this is not effective. The comparators should use a
or comparator are given by: high value set resistor and the inputs should be set to a
voltage that will force the output to VDD Ii.e .• + in = VDD,
VDD-VSS-l.5
I Set I"AI - ------- -in=Vssl.
RSet IMOI It should be noted that increasing ISet for comparators will
Pins 8 and 9 may be tied together for use with a single pro- decrease propagation delay for that comparator.
gramming resistor. The set currents for each op amp pair or For operational amplifiers, the maximum obtainable out-
comparator pair are then given by: put voltage 1VOHI for a given load resistor connected to
VSS is given by:
VDD-VSS-l.5
ISet A, 8 = ISet C, D {"AI - ------ VOH=4x ISetx RL -0.05 V, RL in 0, ISet in A
2 RSet IMOI
The total device current is typically 13 times ISet per pair if
the outputs are in the low state, and 5 times ISet per pair if
the outputs are in the high state. For op amps with an output Typical op amp slew rates are given by:
in the linear region the device current will be between the
values of 5 times and 13 times ISet. SR = 004 ISet IV/"sl. ISet in "A
SET CURRENT versus VDD
•••...
3 I
RS•• -l0 kfl
i
B
100 RSet-l00kfl~
'":i
z
~
ffio 10 RSet~lMfl~
lE I
I I
6 a 10 12 14 16
VOO, SUPPLY VOLTAGEIVOlTSI
OPEN LOOP VOLTAGE GAIN versus ISet GAIN-BANDWIDTH PRODUCT versus ISet
35712351123571 23571 35712
..
o
>
z
15
10 V
••
~100
~ 5 V
~ ~ ~
i 90 """""
p:::
<>. /~~
9 80
~
z
~ 70
~ ~...•...
o
.•••... 15 V ~ ~?
-.....::~rll ~
lOOI'A lOOI'A 11'A
ISet, PROGRAMMINGCURRENT ISet, PROGRAMMINGCURRENT
COMPARATOR PROPAGATION DELAY V8fSUslSet
SLEW RATE V8fSUS ISet I ± 50 mV OVERDRIVE)
~ 35712357123571 357123571
II II
357
f-
. I. I 111111
r- ~~":~~4'~~5 V
\
60 r-
~ 50
f- VOO-15V -
\ 1\
\
~
a<
40 r-
\
\\ \
!
oj 3D
J
20
V", VIOrl-l~ V
10
/ V
V
10pA 100pA
IIII 10pA 100pA
lset. PROGRAMMING CURRENT 'Set. PROGRAMMING CURRENT
70 70
60 60
~ I
..•
i£ 50 z
~
50
'" 40 40
30 30
20
10 10
0 0
10 100 1 k 10 k 100 k 10 lk 10k lOOk
fREDUENCY 1Hz) fREDUENCY 1Hz)
1 k 10 k tOO k 1 M 10 M 10k lOOk

fREDUENCY 1Hz) fREQUENCY IHzI
SMALL SIGNAL TRANSIENT RESPONSE LARGE SIGNAL TRANSIENT RESPONSE
VOO = 10 V NON· INVERTING UNITY GAIN VOO = 10 V NON· INVERTING UNITY GAIN
ISel=2OO ~A Vin AVERAGE = 5 V ISet = 200 ~A Vin AVERAGE = 5 V
(' I "
/
SMALL SIGNAL TRANSIENT RESPONSE LARGE SIGNAL TRANSIENT RESPONSE

VOO= 10 V NON·INVERTING UNITY GAIN VOO ~ 10 V NON· INVERTING UNITY GAIN
ISel=1O ~A Vin AVERAGE = 5 V ISel=1O ~A Vin AVERAGE = 5 V
(\
/ \
" \
J-
-
EQUIVALENT INPUT NOISE VOLTAGE IENI versus FREQUENCY
2000
1000_
1400
100
1200
C
~> .!>
.:;
~
1000
....'"
III
10
'"i5z 800 ~
...
0-
::>
0.,-
0-
1i' 600 i!!O

~
400
200
10 100 1k 10k -20 20 40 60 80 100

FREQUENCY IHd TEMPERATURE I"CI
"A 10 mVo,erdrivo is. signll on DIllinput
ISet-20 ~A of • _.tor thlt r_ from 10 mV
-
loss thin tho othor input to 10 mV mar.
thlll th. other input.
I
1'1..
"-
II ..... ISET-200 ~A
~
0.1
o 10 20 30 40 50 60 70 80 90 100
OVERDRIVE
(mV)
® MOTOROLA
4 x 4 MUl TIPORT REGISTER

The MC145808 is a 4 by 4 multiport register useful in small
scratch pad memories, arithmetic operations when coupled with an
adder, and other data storage applications. It allows independent
reading of any two words (or the same word at both outputs) while
writing into anyone of four words. .
Address changing and data entry occur on the rising edge of the
clock. When the write enable input is low, the contents of any word
may be accessed but not altered.
• Logic Swing Independent of Fanout
• No Restrictions on Clock Input Rise or Fall Times
• 3·State Outputs
• Single Phase Clocking
• Ouiescent Current = 10 nA/package typical @ 5 Vdc
• Capable of Driving Two Low·power TTL Loads, One Low·power L SUFFIX
CERAMIC PACKAGE
CASE 623
ature Range.
• Pin Compatible with CD401 08

DC Supply Voltage VOO -0.5'0+18 Vdc P SUFFIX
PLASTIC PACKAGE
Input Voltage, All Inputs Vin -0.5 to VOO + 0.5 Vdc CASE 709
Operating Temperature Range - AL Device TA -55 '0 +' 25 °c
C LlCP Device -40 to +85
.",,"" 11:;SUffiX Denotes
Storage Temperature Range Tstg -65 to +150 °c L Ceramic Package
P Plastic Package
Temperature Range
e Limited Operating
Temperatur. Range
Clock
WE
DO
01
Data {
Input 02
03
Voo Tlow
. 25°C Thi h·
Characteristic Symbol Vdc Min Ma. Min Typ Ma. Min Max Unit
OUlPUI Voltage "0" Level VOL 5.0 - 0.05 - 0 0.05 - 0.05 Vdc
V,n VOO or 0 10 - 0.05 - 0 0.05 - 0.05
15 - 0.05 - 0 0.05 - 0.05
"1'· Level VOH 5.0 4.95 - 4.95 5.0 - 4.95 - Vdc
V,n oor VOO 10 9.95 - 9.95 10 - 9.95 -
15 14.95 - 14.95 15 - 14.95 -
Input VoltageU "0" Level VIL Vdc
(VO 4.5 or 0.5 Vdc) 5.0 - 1.5 - 2.25 1.5 - 1.5
(VO 9.0 or 1.0 Vdcl 10 - 3.0 - 4.50 3.0 - 3.0
(VO" 13.5 or 1.5 Vdc) 15 - 4.0 - 6.75 4.0 - 4.0
"'" Level VIH
(VO" 0.5 or 4.5 Vdcl 5.0 3.5 - 3.5 2.15 - 3.5 - Vdc
(VO" 1.0 or 9.0 Vdc) 10 1.0 - 1.0 5.50 - 1.0 -
(VO" 1.5 or 13.5 Vdc) 15 11.0 - 11.0 8.25 - 11.0 -
Output Drive Current IAL DeVice) IOH mAde
(VOH : 2.5 Vdc) Source 5.0 -3.0 - -2.4 -4.2 - -1. 7 -
(VOH " 4.6 Vdc) 5.0 . -0.64 - -0.51 -0.88 - -0.36 -
(VOH • 9.5 Vdc) 10 -1.6 - -1.3 -2.25 - -0.9 -
(VOH = 13.5 Vdcl 15 -4.2 - -3.4 -8.8 - -2.4 -
(VOL: 0.4 Vdcl Sink IOl 5.0 0.64 - 0.51 0.88 - 0.36 - mAde
(VOL = 0.5 Vdc) 10 1.6 - 1.3 2.25 - 0.9 -
(VOL: 1.5 Vdcl 15 4.2 - 3.4 8.8 - 2.4 -
Output
(VOH
Drive Current
= 2.5 Vdcl
(CLJCP Device)
Source
IOH
5.0 -2.5 - -2.1 -4.2
. - -1.7 -
mAde
(VOH = 4_6 Vdcl 5.0 -0.52 - -0.44 -0.88 - -0.36 -

(VOH = 9.5 Vdc) 10 -1.3 - -1.1 -2.25 - -0.9 -
(VOH = 13.5 Vdc) 15 -3.6 - -3.0 -8.8 - -2.4 -
(VOL = 0.4 Vdcl Sink IOL 5.0 0.52 - 0.44 0.88 - 0.36 - mAde
(VOL = 0_5 Vdcl 10 1.3 - 1.1 2.25 - 0.9 -
(VOL = 1.5 Vdcl 15 3.6 - 3.0 8.8 - 2.4 -
InpUt Current IAL Devicel lin 15 '01 - '0.00001 '01 - ! 1.0 #lAde
Input Currenl (CL/CP Device) 'in 15 - '03 - '0.00001 '0.3 - '1.0 #lAde
(Vin = 01
Ouiescent Current IAL Devicel 100 5.0 - 50 - 0.010 5.0 - 150 }.lAde
(Per Package) 10 - 10 - 0.020 10 - 300
15 20 - 0.030 20 - 600
QUiescent Current ICL/CP DeVice) 100 5.0 - 50 - 0.010 50 - 375 IJAdc
(Pel Package) 10 - 100 - 0.020 100 - 150
15 - 200 - 0.030 200 - 1500
Total Supply Current-· t IT 5.0 IT - (1.18 ~A/kHl) f • 100 jJAdc
(DynamiC plus Quiescent, 10 IT = (1.91 .~A/kHl) I • 100
Per Package~ 15 IT = (2.61 ~AlkHl) I • 100
(el " 50 pF on all outpulS, all
buffers switching)
Three-State Leakage Current 'TL 15 ! 0 1 - -000001 1:0.1 - 1:3.0 IJAdc
IAL Device)
Three-State Leakage Current ITL 15 - ±10 -. -0.00001 1:1.0 - ± 7.5 IJAdc
(CLlCP Dev;cel
-Tlow ..:-55°C lor AL Devtce, -400C for CLlCP Device. This device contains circuitry to protect
Thigh'" +12SoC for AL DeVICe, +SSoC for CL/CP Device. the inputs ~inll damage due to high
.z:Noise immunity specified for worst-case input combination. static voltages or electric fields: however,
it is advised that norlT\lll precautions be
NOise Margin for both "1" and "0" level'" 1.0 Vdc min@l VDD ~ 5.0 Vdc
taken to avo'd application of any voltage
2.0 Vdc min@ VOO "10 Vdc higher than IT\Ilkimum r.tld voltages to
2_5 Vdc min@ VOO "15 Vdc this high impedance circuit. For proper
tTo calculate total supply current at loads other than 50 pF: operation it is recommendtd that Vin.nd
IT(Cl) = IT(50 pF) + 4. 10-3 (Cl -501 VOOf Vout be constr.ined to the range Vss "
(Vin or Vout) " VOO·
where: IT is in IJA (per package). CL in pF, VDD in Vdc. and f in kHz is input frequency.
Unused inputs must always be t~ to an
--The formulas given are for the typical characteristics only at 25°C.
appropriate logic voltage level (e.g., eith.-
Vssor VOOL
Symbol
Output Rise Time lTLH
lTLH· 13.0 ns/pFI CL + 30 ns
Output Fall Time
lTHL· 11.5 ns/pF) CL + 25 ns
lTHL· 10.75 ns/pFI CL + 12.5 ns
lTHL· 10.55 ns/pF) CL + 9.5 ns
Propagation Delay Time. Clock to Output lPLH.
lpHL lpLH· 11 7 ns/pFI CL + 1415 ns lPHL 1500 4500
l
I lPHL: lPLH· 1066 ns/pF) CL + 467 ns 500 1500
I
B
lPHL. lPLH· 105 ns/pFI CL + 325 ns 350 1125
Wrtte Enable Setup Time lsulWEI 800 2000
300 750
180 550
~---- - - lsulWEI -300 +150
-100 +75
!
-60 +55
-800 -200
-300 -75
·180 -45
150 450
70 210
50 160
160 480
65 195
50 150
lPHZ. lPLZ. 355 900
lPZH.lPZL 140 350
85 250
1000 3000
350 1050
200 800
400 1200
85 255
60 200
Sink Current Source Current

Position of $1 2 1
VGS '"' Voo -vOO
VOS = Vout Vout- Voo

P.G.,- __ ~I L
P.G, 2 J'LAJl..JL..J
P.G.3~
r----\
Output -"
OnA .B L....J '---J,-
Voo
VSS
Voo
VSS
Clock WE Wrtte 1 Write 0 Read lA f'ead 0A Aead 1B Read Os 3·SWteA 3·State B Dn QnA QnB
--r- 1 0 1 0 1 0 1 1 1 1 1 1
-r 1 0 1 1 1 0 0
l.- X X X
0
X
1
X
0
X
1
X 1 1 X No °
No
Change Change
X X X X X X X X 0 0 X A A
0 X X X X X X X 1 1 X No No
Change Change
1 X X X X X X X 1 1 X No No
Change Change
-r 1 0 0 0 1 1 0 1 1 On to Contents Contents
ward 0 of word 1 of word 2
displayed displayed
-r ° 0 0 0 1 1 0 1 1 Word 0 Contents Contents
not of word 1 of word 2
altered dlsolayed displaved
R implies high resistance - 1 09 ohms.

X = Don't care.
® MOTOROLA
CMOS MSI
(lOW-POWER COMPLEMENTARY MOS)
The MC144100 is a 32-bit serial data input to 32-segment LED DUPLEX MODE
II driver realised in CMOS technology. designed for use in AC mains

powered applications. The use of the 50/60Hz mains to provide
the two phase multiplexing ensures minimal radio frequency
interference (RFII.
32-SEGMENT LED DRIVER
P SUFFIX
PLASTIC PACKAGE
CASE 709
This device contains circuitry to protect the inputs
against damage due to high static voltages or elec-
tric fields: however, it is advised that normal
Rating Symbol Value Unit precautions be taken to avoid application of any

voltage higher than maximum rated voltages to
this high impedance circuit. For proper operation it
OC Supply Voltage --05 to 6S V DC is recommended that Vin and Vout be constrained

VDD
to the range VSS (Vin or Voutl VOO'
Input Voltage, All Inputs VIN -0.5 to VDO + 0.5 V DC Unused inputs must always be tied to an ap-
propriate logic voltage level (e.g. either VSS or
DC Current Drain per Input Pin I 10 mA
Voal.
DC Current Drain per Output Pin I 50 mA
Output Voltage, Segment Output VSOFF VSS -6 to VDD ' 0.5 V DC
Operating Temperature Range TA o to 70 C
Storage Temperature Range TSTG -65 to 150 C
Characteristic Pin Condition Symbol Min Max Unit
Supply
Supply
Voltage
Current
12,24 VIN=O,IOUT=O VDD
IDD
. 30
-
6.0
1.0
V DC
mA
Input Voltage High 15.13 VIN -0, IOUT-O VIH 0.7 X VDD - V DC
Input Voltage Low 14,11 Vil - 0.3 X VDD V DC
Input Current VIN=oOtoVDD IIN - 1 "A

Input Voltage High 10 VIHS VDD- OS V DC
Input Voltage Low VllS - VDD - 2 V DC
Input Current VIN'OtoVDD IINS - 10 "A

Output Drive Capability 9 VOL' 0.5V IOl 200 -
"A
VOH' VDD - 0.5V IOH -200 - "A
Voltage Dror 1 to 8 lOUT' 30mA, VDD 5V VDD - VSOH - 1.2 V DC
16 to 23 IOUT'10mA VDD - VSOH - 0.75 V DC
Leakage Current VOUT' 0 IOFF - 0.1 mA
Power Dissipation PMAX - 500 mW
(on-ehip)
Characteristic Figure Symbol Min Max Unit
Clock High Time 2,3 tCH 2 - "s

Clock Low Time 2,3 tCl 2 -
Clock Rise Time 2,3 tCR - 2
"'
"s
Clock Fall Time 2,3 tCF - 2 "s
Enable Lead Time 2,3 tE Lead 200 - ns
Enable Lag Time 2,3 tELag 200 - ns
Data Set-up Time 2,3 tDSup 200 - ns
Data Hold Time 2,3 tDHold 1 - "s

<;erial Data Out Delay
TDOUT 1 "S
Multiplexer Lead Time 4 tMLead - 10 "s
Multiplexer Lag Time 4 tMLag - 10 "s
The circuit operation can be followed by reference to Multiplexing is controlled by the SYNC input whose
the block diagram Figure 1 switching threshold occurs just before the LED segments
Data are fed serially into the circuit via the data input are turned on. A current limiting resistor is necessary for
pin DIN, which is controlled by the CLOCK and chip this inputif the control signal swings outside the limits of
enable, EN, pins-this latter enables the circuit when it is VDD t 0.5V to VSS - 0.5V.
low i.e. at logical '0'. When EN goes high, to logical '1', The relationship hetween the SYNC input and the
the clock idle state is stored in a latch; thus permitting the displayed word is shown in the table below:
use of a positive or negative going clock.
II Four B-bit words are loaded into a 32-bit shift register,

made up of four B-bit registers, when EN is low. At the
next rising edge of EN the data in the shift register are
loaded into latches.
The shift In the register takes place on the falling edge
Segments
SAl - SAB
SAl - SAB
SYNC
low
high
Word
1
2
of the clock when the clock control input, CLCONTR, is SSl - SSB low 3
low, logical '0'. Conversely, when CLCONTR is high, SSl - SSB high 4
logical '1', the shift takes place on the clock's rising edge.
See Figures 2 and 3.
Word number 1 is the first shifted and number 4 the Because decodmg is a function of an external circuit,
last. for example the microprocessor In a radio synthesizer
The outPut DOUT servesas a cascading output. application, there is no decoding circuitry in this device.
wilen low, logical '0'. When high it causes the clock

idle state, at the time of the positive going transition, to
DOUT - (pin 9) This is the cascading output. If desired be stored In a latch.
this pin can be tied directly to the DIN pin (pin 15) of a
further MC1441 00 for cascading purposes. SYNC - (pin 10) The status of this input determines
which of the four input words are displayed. See Table 1.
CLOCK (pin 131 ThIS is the clock input and is able If the control signal applied to this pin goes more positive
to accept a clock frequency of up to 250k Hz. than VDD t 0.5V or more negative than VSS - 0.5V an
external current limiting resistor will be necessary.
CLCONTR - (pin 14) The state of this pin determines
whether ihe data are shifted on the rising edge, CLCONTR OUTPUT DRIVERS - (pins 1 to B & 16 to 23) These
= logical '1', or an the falling edge, CLCONTR = logical are on-chip NPN emitter followers each requiring an
'0', of the clock signal. external current limiting resistor. In the off state they are
protected against voltages down to VSS - 6V.
FIGURE 2 - TIMING DIAGRAM - CL CDNTR HIGH
aJ POSITIVE CLOCK/RISING EDGE SHIFT (CL CONTR = HI/ FALLING EDGE DOUT
FIGURE 3 - TIMING DIAGRAM - CL CONTR LOW
al POSITIVE CLOCK/FALLING EDGE SHIFT /CL CONTR = LJ RISING EDGE DOUT
bl NEGATIVE CLOCK/FALLING EDGE SHIFT ICL CONTR = lI/ RISING EDGE DOUT
EN
c,
tel tCH
==~~- __
\=x:::=
II
A A t
------~----~- --- VDD
----V-----V--
-~----~---- __ --- VDD
~---~------
•... -,
/
/ ""
/ \
.DO
S.'
•
·
••
1
DIN $A'
.
Cl
!Ii 0
0
POUT
SYNC
i:
....
SI"
..
""
t1
EJ
50"
'55
® MOTOROLA
The MCM144102 is a 16-bit/16-word CMOS static RAM designed

for consumer applications in conjunction with dedicated or MPU TUNING MEMORY SYSTEM
based systems. The chip consists of three control lines, one I/O pin, MEMORY CIRCUIT
one chip enable pin and a single clock input.
P SUFFIX
PLASTIC PACKAGE
CASE 626
16x16 CONTROl
MEMORY
III
III
w
D:
C
~
CE/PF Voo CLOCK C1

voltages or electric fields; however. it is
Rating Symbol Value Unit advised that normal precautions be taken
DC Supply Voltage Range VDD 7 to -- 0.5 Vde than maximum rated voltages to this high
impedance circuit. For proper operation it
Vde is recommended that V in and Vout be
Input Voltage, All Inputs Vin VDD +0.5 to
constrained to the range VSS" (Vin or
-0.5
Vout)" VDD·
Operating Temperature Range TA -40 to +70 ·C
-65to +150 ·C
II
Storage Temperature Range TUg
-40·C 25°C +70·C

VDO
Vdc
Min Max Min Typ Max Min Max
Output Voltage
VIN = VDD or DV "0" Level VOL 5V - 0.05 - 0 0.05 - 0.05 Vde
V1N ~ VDD or OV "1" Level VOH 5V 4.95 - 4.95 5 - 4.95 - Vde
Input Voltage "0" Level VIL Vde
(VO = 4.0V or 0.5V) 4.5V - 1.35V - - 1.35V - 1.35V
(VO ~ 4.5V or 0.5V) 5.0V - 1.5V - - 1.5V - 1.5V
(VO = 6.0V or 0.5V) 6.5V - 1.95V - - 1.95V 1.95V
"1" Level VIH Vde

(VO = 0.5V or 4.0V) 4.5V 3.15 - 3.15 - - 3.15 -
(VO = 0.5V or 4.5V) 5.0V 3.50 - 3.50 - - 3.50 -
(VO = 0.5V or 6.0V) 6.5V 4.55 - 4.55 - - 4.55 -
Input Current lall inputs)
Low VIN = OV IlL 6.5V - -1 - - -1 - -1 /lAde
High IIH 6.5V - 1 - - 1 - 1 /lAde
Output Current.
(Data 110)
VOH = VDD - 0.8V Source 10H - -2 - -1.4 - - -1 - mAde
VOL ~ 0.8V Sink 10L - 2 - 1.4 - - 1 - mAde
Tri-state output
(Data 1/0 Leakage Current)
VOT = VDD 'TH - - 1 - - 1 - 1 /lAde
VOT = OV ITL - - -1 - - -1 - -1 /lAde
Quiescent Current
Operating IDDOP 5V - 50 - - 50 - 350 IJAde
Standby 'DDST8 1.2V - 10 - - 10 - 80 /lAde

Parametlr Pin Symbol Min Typ Max Unit
3 (1) kHz
Clock Frequency (fCL = 1/'CL' fCL 100
Clock Hold Time High 'CLH 4 20 jJ.S
Low 'CLL 4 "s

Clock Rise ~nd Fall Time 'CLF 1 "s
Write Time (per word) 'WRITE 1 clock

cycle
Read Time (per word) 'READ 1 clock

cycle
Data Out Delay 8(3) ,,(2) 50n 3 "s

Data In Set Up Time 2 "s
'2
Instruction Set up Lead 4,5,6(1 2
'3 "s
Lag '4 50 ns
NOTES;
I The maximum pin capacitance is lOpF to VSS for: C1• C2, C3 and clock
2 tl applies only during data transition as the data format is NRZ
3 The output exter"al loading capacitance wttf be lOpF (max)
READ - The memory can store up 16, 16·bit words, with STANDBY - When this instruction is received the memory
all functions controlled by a 3-bit parallel instruction goes in to a Quiescent state, when only a 1.2V battery
bus and an applied clock, which may be free running. is necessary to supply the device's modest power
requiremen~s.
A READ instruction, presented for one clock period
moves data from memory and parallel loads it in to the INSTRUCTION SEQUENCES - The READ and WRITE
sh ift register. instructions need to be presented for one clock cycle only.
All instructions, except SERIAL DATA OUT, force the
A SERIAL DATA OUT instruction, presented for 16
output data driver to a high impedance state_
clock pulses, causes the data to be moved out of the chip
on the I/O bus_ During this time the data are internally
recirculated to allow further read out without accessing
the memory array.
WRITE - This is basically the inverse of READ. The

address can be changed and data serially loaded in to the
chip over 16 clock cycles. The WRITE instruction, MIN MAX
presented for one clock period, shifts the data in to the
selected address in the memory array. . , , 1 Standby 0 tookHz
0 O. 1 No operation
CLOCK - This is active high. In all modes, other than
WRITE, the memory array remains undisturbed
presence, or absence, of signals on the clock line.
by the
0
0 ,
1 0
1
Write
Serial Data Out
0
0
100kHz
100kHz
0 0 0 No Operation
POWER FAIL/CHIP ENABLE - Only when this dual 1 0 0 Serial Address In 0 100kHz
purpose pin is high, = 1, is the chip selected. At all 1 0 1 Serial Data In 0 100kHz
other times, including low power conditions, the memory 1 1 0 Read 0 100kHz
is disabled thus avoiding erroneous data transfer and
excessive drain on the standby battery due to intermediate 1 = high 0=10'1
levels on the inputs.
VIH
--- Vil
,
I I' /1-.. L
I ' I /~I L
~
: 'I
=:tX: READ:
C',C2,C3
13 i, r.C:ir
114,
13
'I
:!-=--=-==
--SE-R-IA-L-DA-,-:t.-DUT--('-I-Cl.DC--KS-)----I/j==x~-
:
II II I! __ ,It ~ I It
I I II -W
-'-~G~~PE~N~ ~-,-DA-,-A-B-'
-X--DA-'-:t.-B-2-q/~( -D-AT-A-B'-'--i~---
I II
/~
I
_'_.'_5 X DATA 816 X~ _
WRITE; I _;
i,
-'----------...-~>C' '
I
® MOTOROLA
CMOS
HIGH PERFORMANCE REMOTE

CONTROL TRANSMITTER
HIGH PERFORMANCE INFRARED REMOTE
CONTROL TRANSMITTER
• Delta Modulated FSK Coding

• Error Protected Codes
• 1 2-Bit Data Word plus Parity Bit
• 1024 Commands (64 x 16)
• Option Pin for Expansion to 4096 Commands (64 x 64)
• Simple Infrared LED Driving Circuit
• Local Data out Pin
• Very Low Duty Cycle (typ 0.33%)
• 4-10 V Supply
• Ideal Transmitter for MC144124 Receiver
• Protected against Multiple Key Operation Malfunction P SUFFIX
PLASTIC PACKAGE
CASE 709
OSC
RO CB
R1 CC
R2 CD
Keyboard R3 CE Scanner
Inputs Outputs
R4 CF
R5 CG
R6 CH
R7
Signal
Address [DR 1
ADR 2 Data Out
Inputs
OPT
TEST
VDD VSS
® MOTOROLA
CMOS
INFRARED REMOTE
II •
•
•
Biphase AM Coding
9-Bit Data Word
B Pages of 64 Commands
CONTROL TRANSMITTER
• EOT Word Sent before and after Each Command

• Protected against Multiple Key Operation Malfunction
• LC or Ceramic Oscillator
• Low Standby Current
• Low Duty Cycle
• 4-10 V Supply
• Ideal Transmitter for MC144122 Receiver
• Simple Infrared LED Driving CKT
P SUFFIX
PLASTIC PACKAGE
CASE 738
PIN ASSIGNMENT
Signal VDD
R5 OSC
R2 CD
R7 CF
R1 CG
Row Column
Inputs Outputs
CC
CB
CE
R3 CH
VSS Page Input

® MOTOROLA
CMOS
QUAD & HEX
D/A CONVERTERS
The MC 144110 and MC 144111 are hex and quad static, O/A
converters realised in CMOS technology. Each converter, featuring
6-bit resolution, consists of a 6-bit shift register, 6-bit latch and a
static 0/ A converter .
• 4/6 direct R-2R network outputs
-
• 4/6 emitter follower outputs
• MPU compatible input levels MC144110
P SUFFIX
• Serial data input PLASTIC PACKAGE
• Data cascade output

• Wide operating voltage range of 4.5 to 15 Vdc
CASE 707
.. MC144111
P SUFFIX
PLASTIC PACKAGE
CASE 646
MC144110 MC144111
DIN VDD DIN VDD
E F1 DOUT E F1 DOUT
RN1 RN6 RN1 RN4
EF2 EF6 EF2 EF4
RN2 RN5 RN2 RN3
EF3 EF5 EN EF3
RN3 RN4 VSS CL
EN EF4
VSS CL
OC Supply Voltage VOO + 18 to- 0.5 Vdc
Input Voltage, All Inputs Vin 0.5 to VOO +0.5 Vdc
Input Current, All Inputs lin 10 mAde
Operating Temperature Range TA o to +85 'c

Storage Temperature Range Tstg -65 to + 150 'c
This device contains circuitry to protect the inputs against damage due to high static voltages or
electric fields; however, it is advised that normal precautions be taken to avoid application of any
voltage higher than maximum rated voltages to this high impedance circuit. For proper operation
it is recommended that Vi" and Vout be constrained to the range VSS ~ (Vin or V out' ~ VOO·
Characteristics Conditions Symbol Min Typ Max Unit
Clock high time VOO=5V tCH 2 0.2 ~s

VOO= 10V 1.5 ~s
VOO= 15V 1 0.1 ~s
Clock low time VOO= 5V tCl 5 1.5 ~s

Voo = 10V 3.5 ~s
Voo= 15V 2 0.5 ~s
Enable lead time VOO =5V tElead 5 1.5 ~s

VOO = 10V 3.5 ~s
VOO= 15V 2 0.5 ~s
Enable lag time VOO= 5V 5 1.5 ~s
tElag
VOO= 10V 3.5 ~s
VOO= 15V 2 0.5 ~s
Data Set-up time VOO= 5V tOsup 1 0.1 ~s

VOO = 10V 0.75 ~s
VOO= 15V 0.5 0 ~s
Data Hold time VOO=5V 5 1.5 ~s
tOhold
VOO= 10V 3.5 ~s
VOO = 15V 2 0.5 ~s
Clock rise time tCrise 2 ~s

Clock fall time tCtall 2 ~s
Characteristic Pint Symbol Min Typ Max Unit
DC Supply Voltage 18 VDD 4.5 15 V DC
DC Supply Current MC 144110 (14) IDD 12 mADC

MC 144111 8 mA DC
Input low level 1,8,10 DIN 0.8 V
High level VDD=5V (1,6,8) CL 3.0 V
VDD= 10V m 3.5 V
VDD= 15V 4.0 V
Current VIN= VDD IIN 1 j.lA
Output Sink VOL =0.5V 17 IOL 200 j.lA
Source VOH=VDD-0.5V (13) IOH -200 'j.lA
01A Characteristics
Network Resistance A 7 10 15 kn ,
Precision 3,5,7,12
(w.c. at VAN = VDD/2) VDD=5V 14,16 VNONL2 20 100 mV
VDD= 10V 13,5,10, 200 mV
VDD= 15V 12) 120 300 mV
Step Size 3 -75% VDD/64 +75 %
MC 144110
NPN Emitter Follower Current Gain
IE = 0.1 -lOmA at 25°C 2,4,6, hIe 40 100
Emitter leakage Current V R N = OV 11,13 10 .j.lA
VSE at IE = lmA VSE 0.4 0.7 V
Max Dissipation 15
per output TAmax=85°C PE 10 mW

all 6 outputs PEtot 25 mW
o
per output TAmax =70 C PE 30 mW
Me 144111
NPN Emitter Follower Current Gain 2,4,9,
IE = 0.1-10mA at 250C 11 hIe 40 100
Emitter Leakage Current VRN = OV 10 j.lA
VSE at IE = lmA VSE 0.4 0.7 V

Max Dissipation
per output TAmax=8SoC PE 20 mW

per output TAmax = 70°C PE 50 mW
1 Pin numbers in brackets (t refer to MC 144111

2 See Figure 4
3 See Figure 5
°2 ----==><__
II
O_N _
_O_N __ X _
fFn RNn
r
I
L-1, I
I I
I I
I I
I I
1 I
I I
I I
I I
I I
I I
1 I
I I
- - -~ t----- "ouT
I I
L__ -l
LINEARITY ERROR (integral linearity). A measure of
how straight a device's transfer function is, it indicates the
worst-case deviation of straightness of the actual transfer
function from the ideal straight line. It is normally speci-
fied in parts of an LSB.
Step size = VOO ± 0.75 VOO

64 64
@MOTOROLA
2-DIGIT/16-SEGMENT
II
The MC144115 is a CMOS, cascadable, 2-digit/ 16-segment LCD
driver with an on-chip oscillator. Data are clocked serially into and
LCD DRIVER
out of the circuit.
• Input level translators

• Direct drive (not multiplexed)
• On-chip oscillator
• Cascadable
• Internal 16-bit latch
• Wide power supply range, 3 to 18 V DC
CP SUFFIX
PLASTIC PACKAGE
CASE 709
IT
PUlS(
Cl
" SHAPfR
IT
DIN •• 11
DOUT
iN
, IT
ZJ
DSC
~
" VSS
§ .BY'
" VOD
OK'
Rating Symbol Value Unit the inputs against damage due to high static
OC Supply Voltage Range 18 to -0.5 Vdc voltages or electric fields; ho~ver, it is
VOO
Input Voltage, All Inputs Vin VOO + 0.5 to Vdc than maximum rated voltages to this high
VSS -0.5 impedance circuit. for proper operation it
is recommended that Vin and Vout be
Input Current, All Pins lin 10 mAde
constrained to the range VSS " (Vin or
Operating Temperature Range TA -40 to +85 °c Vout) "VOO'
Unused inputs must always be tied to an
Storage Temperature Range

,. Tstg -65 to +150 °c
appropriate logic voltage level le.g., either
VSS or VOOI.
-40·C 25·C 85·C

VDD
CharllC1.ristic Symbol Unit
Vde
Min Max Min Max Min Max
Segment OutpUt Drive Current

(pin. 3.4 .. 10. 15. 16 •.•. 22)
Source VOH =4.6Vdc loH 5 220 - 160 - 120 - ,u.Adc
VOH = 9.5Vdc 10 525 - 370 - 280 -
VOH = 13.5Vdc 15 1900 - 1300 - 1000 -
Sink VOL = 0.4Vdc 10L 5 330 - 240 - 190 -
VOL = 0.5Vdc 10 880 - 600 - 470 -
VOL= 1.5Vdc 15 3100 - 2100 - 1600 -
Source Current pin 1
VOH =4.6 Vdc 10H 5 690 - 500 - 390 - "Adc

VOH- = 9.5Vdc 10 1620 - 1140 - 870 -
VOH = 1.3Vdc 15 5880 - 4000 - 3100 -
Source Current pin 11
Chip Enabled VOH =4.6Vde 10H 5 29 - 21 - 16 - "Adc

(Slave chip VOH = 9.5Vde 10 70 - 40 - 30 -
only) VOH = 13.5Vdc 15 250 - 175 - 135 -
VOH =OVdc 15 - 3100 - 2160 - 1670
Chip disabled VOH=OVdc 10H 5 6 4.5 - 3.8 "Adc
10 28 - 20 - 16 -
~, 15 58 - 40 - 31 -
Sink Current for pins
1 and 11 VOL = OAV 10L 5 590 - 430 - 340 - "Adc

VOL= 0.5V 10 1570 - 1100 - 840 -
VOL= 1.5V 15 5550 - 3850 - 2900 -
Pin 23 Input Current
(Marter chip only) lin 5 3.4 15 2.6 11 2.1 9 "Adc
Sink (Vi" = VOOl or 10 22 70 15 50 12 40
Source (V in = VSS) 15 50 150 35 110 25 85
Input Voltage VIL 5 to 15 - 0.8 - 0.8 - 0.8 Vdc
pin. 2. 13, 14 VIH 5 3 - 3 - 3 -
10 3.5 - 3.5 - 3.5 -
15 4.0 4.0 4.0 -
Quiscent current 155 5 - 150 - 20 - 150 "Adc
10 - 300 - 40 - 300
15 - 600 - 80 - 600
Tristate Output
Leakage Current
pin.11.23
In 15 - ± 1.6.
- ± 1.6 - ± 12 "Ade
Input Current
.
Except pins 11 and 23
lin 15 - ± 0.3 - ± 0.3 - ± 1.0 "Adc
Input Capacitance
(Vin-Ol
Cin - - - - 7.5 - - pF
Characteristic Condition Symbol Min Max Unit
Clock High Time VOO: 5V lCh 5 - I'S

VOO= 10V 4 - I'S
VOO: 15V 2 - "S
Clock Low Time VOO: 5V lCI 5 I'S
Voo: 10V 4 - I'S
voo = 15V 2 - "s
Enable Lead Time VOO= 5V lElead 2 - I'S
VOO= 10V 1 - I'S
VOO = 15V 500 - ns
Enable Lag Time VOO- 5V lElag 500 - ns
VOO= 10V 300 - ns
VOO = 15V 200 - ns
Data 5et-up Time VOO= 5V tOsup 500 - ns
VOO: 10V 300 - ns
VOO = 15V 200 - ns
Data Hold Time VOO = 5V IOhold 2 - I'S
VOO= 10V 1 - I'S
VOO = 15V 500 - ns
Clock Rise Time 10%1090% tCrise - 2 I'S
Clock Fall Time ofVOO lCfall - 2 I'S
Min. EN High TIme, CL = 5()pP 51015V lEnh 50 - I'S
Dl ---===x D_" _
_ DN_X _
The circuit operation can be followed by referring to
the block diagram, Figure 1.
Data are entered serially into the circuit's 16·bit shift
register via the 0 IN pin. The data transfer rate is controlled
by the clock input, CL, either positive or negative clock When MC144115s are cascaded, that which controls
pulses may be used, see Figure 2. the backplane frequency, called the master, is the last
The CL input is enabled only when the EN input is in circuit in the shift register chain, see Figure 3.
the low state, logical '0'. On the positive going edge of EN The master's BKP output is connected directly to the
data in the shift register are latched and transferred to the slaves' OSC inputs. The slaves' oscillator circuits are
display drivers. bypassed and their backplane frequency is controlled by
If more than two digits are to be displayed two, or the OSC input.
more, circuits can be simply cascaded, as shown in Figure DOUT acts an input/output. When EN is high it acts as
3. an input and when EN is low DOUT acts as an output.
Level translators are provided on inputs CL, DIN and While the chip is disabled, EN at logical '1', an internal
EN to allow the circuit to interlace directly with a 5V resistive pull·up pulls the slaves' DOUT pin high, to logical
powered controller, regardless of the circuit's own power '1'. A falling edge on EN latches·in the logic state of
supply voltage-which can lie anywhere in the range 3 V to DOUT which defines the master/slave status of each IC.
laV. During the EN low time DOUT acts as an output; the
internal pull-up is inactive and an output buffer is enabled
(standard push-pull buffer in the slave mode, open drain
N channel buffer in the master mode).
AC drive for the LCDs is provided by an on-ehip, 50% It is recommended that in a cascaded configuration
dutY cycle oscillator whose frequency is determined by a the EN input is held high during power·up to avoid any
single external capacitor, see Figure 4. chance of the circuit whose DOUT pin is grouncJed
A segment output is in phase with the backplane when trying to act as a slave and drawing current through its P
the corresponding data bit in the shift register is low, channel buffer transistor. This transistor is designed to
logical '0'. The segment is in anti-phase when the corres- limit the short circuit current to 3mA with a 15V supply.
the circuit.
In a master configuration the pin is tied to ground
thus enabling the oscillator and disabling the push·pull
data output buffer. In the slave configuration DOUT is
EN (pin 2) This is the chip enable pin and is active tied to DIN of the following device, the oscillator is by·
when low, logical '0'. On its positive going edge it causes passed and the output buffer is enabled.
the contents of the shift register to be loaded into the
latches and transferred to the display drivers. When it is OSC - (pin 23) This pin, in the master role, needs an
high it causes DOUT to act as an input and when low as external frequency determining capacitor to ground, see
an output. Figure 3. In the slave role the oscillator circuitry is by-
passed and the pin serves as the input for the backplane
frequency.
B1 to B16 - (pins 3 to 10 and 15 to 22) These are the

segment output drivers.
C (nFI
" \.
-
\ -
-
15V
10V
~5V
=
-
-
-
""\\. -
f-.-
-
f-.-
f-.-
Typical Backplane frequency Typical Backplane Frequency

PIN ASSIGNMENT as a Function of capacitor Value
as a Function of Temperature
(10nF capacitor) (lS'C)
BKP vDD
EN DSC
B' BB
BlO B7
Bll B6
B12 BS
B13 B4
B14 B3
B15 B2
B15 Bl
Dour CL
vss DIN
® MOTOROLA
4-DIGIT DUPLEX
The MC144117 is a CMOS 4 digit duplex LCD decoder/driver with LCD DECODER/DRIVER
on-chip oscillator. Data is entered serially. latched and decoded for
LCD front and back planes.
• On-chip oscillator
• On-chip analog reference voltages
• Compatible with MC 14499 LED driver
• Supply voltage range 3V to 6V DC
• MPU compatible CP SUFFIX
PLASTIC PACKAGE
CASE 709
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
DC Supply Voltage Range VDD 6 to - 0.5 Vdc
Input Voltage, all Inputs Vin VDD+ 0.5 to Vdc
mum rated voltages to this high impedance
VSS-0.5
circuit. For proper operation it is recom-
I 10 mAdc mended that Vin and Vout be constrained
DC Current Drain per Pin
to the range VSS <: (V in or Vout) "- VDD.
Operating Temperature Range TA --40 to+85 °C
Storage Temperature Range Tstg -65 to+150 °C
TA =--400C TA=250C TA =850C
Characteristic Pin Symbol VDD Min. Max. Min. Typ Max. Min. Max. Unit
DC Supply Voltage 24 VDD - 3 6 3 6 3 6 Vdc
Input Voltages
'0' Level 18.21 VIL 3 0.9 0.9 0.9 Vdc
22 6 1.8 1.8 1.8
'I'Level VIH 3 2.1 2.1 2.1

6 4.2 4.2 4.2
Quiescent Current 24 IDD 6 100 ~A
Input Current 18.21.22 IFN 6 ±1 ~A

(Vin = 0 to VDD) 23 IFN 6 ±50
Analog Output Levels

Segment Drivers 1-11.13-17 +Vd 3 2.562 Vdc
+Vd 6 5.124
1-11.13-17 -Vd 3 0.438
-Vd 6 0.876
Backplane Drivers 19.20 Vc 3 1.500
6 3.000
Characteristic Symbol Min. Typ Max. Unit
Clock high time tCH 2 ~s

Clock low time tCL 2 ~s
Clock rise time tCR 2 ~s
Clock fall time tCF 2 ~s
Enable lead time tElead 200 ns

Enable lag time tEleg 200 ns
Data set-up time

Data hold time
Oscillator frequency 1
tDsup
tDhold
lose
1
200
125
~.
ns
Hz
The circuit accepts a 20-bit input, 16 bits for the 4-digit The backplane drive signals from BPA and BPB are ortho-
display plus 4 bits for the decimal point. These latter 4 bits gonal 3-level amplitude signals, as shown in fig. 4. Only one
are optional. backplane can be at VDD or VSS when the other back-
The input sequence is the decimal point followed by the plane is at VDD/2. In this way, a segment driver (front
4 digits, as shown in figure 2. In order to enter the data plane) wh ich is connected to two segments - one on each
the enable, EN must be low (=0). The sample and the shift backplane - can be arranged to select only one (or any
are accomplished on the falling clock edge, see fig. 1. Data combination) of the segments attached to the driver.
is loaded from the shift register to the latches when EN Each segment driver has a square wave output centered
goes high (=1 I. While the shift register is being loaded, the about 0.5 VDD. Since each driver has two segments asso-
previous data is stored in the latch. Figure 5 shows the de- ciated with it (one for backplane A and one for backplane
coding used by the device. If the decimal point is used, Bl, there are 4 possible operating conditions, as follows:
the system requires 20 clock pulses to load data, otherwise
only 16 are required. Inputs CL, DIN and EN will allow
the circuit to interface directly with a 5V powered con-
troller, regardless of the circuits own power supply voltage SEG.A SEG. B
which can lie anywhere in the range 3V to 6V. on on
on off
off on
off off
The device pinout has been organised to ease the intercon- These conditions are obtained by changing the phase
nection to the LCD display. The LCD digit organisation is relationship between the segment driver and backplane
given in fig. 3. drivers, as shown in the figures 6 to 9.
____
-.-r-
----~
=====x ON
III III III III III III

••••••..••
:< :< ..••
••• ••• ••• ..••
:< •••
I I I
FIGURE 5 - SEGMENT CODE
0000 n 1000 n
1-
0001
,,
'_I
1001
_I
,--'I
DOlO I:' 1010 n

n
00 II :1 1011 I
I
-'
0100 U II 00 I I
I I ,
C I ,
OlD' II 0 I
-' U
0110 .-0 1110
01 II
-,, 1111 BLANK
0
,v'D 0 0 0 U 0 0
BPA
VDD U 0
-2-VDD-
OJO 0 n n n
BPB
0 U 0 0 L
BPA un .n n ~ 0
VDD--t/ U 0 ~ 0
-Y-vxDD-n 0 ~ n 0
BPB:oJ 0 ~O 0 L
+Vd
VSX~VC
VDD/2 -Vd
o CL~ n .n
v~D 0 00 0
-VDD...-
2~_rl nOD ~
~D 0 DOL
VDD
VSX -2-
Don n n
v~D 00 00
~VDD--n DODD
BPS:] DODO L
D1SGl - D1SG4 (Pins 1 to 4) - Front Plane Drivers for
Digit 1, Segment Groups 1 to 4
D2SGI - D2SG4 (Pins 5 to 8) - Front Plane Drivers for

Digit 2, Segment Groups 1 to 4
D3SGI - D3SG4 (Pins 9-10, 13) - Front Plane Drivers

for Digit 3, Segment Groups 1 to 4
D1SGl
D1SG2 D4SG 1 - D4SG4 (Pins 14 to 17) - Front Plane Drivers
B
for Digit 4, Segment Groups 1 to 4
D1SG3
D1SG4
D2SGl
D2SG2
D2SG3
D2SG4 D4SG4
D3SGl D4SG3
D3SG2 D4SG2
D3SG3 D4SGl EN (Pin 22) - Chip Enable Pin, when low, logical '0' CL
Input is active on the positive going edge.
VSS D3SG4
The contents of the shift register are loaded into the
latches and transferred to the display drivers.
OSC (Pin 23) - The oscillator pin requires an external

frequency determining capacitor to VSS.
,-,
VSS
BPA
BPB o. ".
o
® MOTOROL.A
CMOS
INFRARED REMOTE
II CONTROL RECEIVER
• Preamp/Detector for AM Infrared Signals

• Digital Signal Output
• Coil-less Input Circuit for High Noise Immunity
• Programmable On-chip Bandpass Filtering
• Minimal External Components
• Single 10 V Supply
P SUFFIX
PLASTIC PACKAGE
CASE 648
AGND
Signal Data
AZ
]
AO Intermediate
Gain Set BO Signal
Filter Outputs
CO
OSC OPA
Test OPB
VDD VSS
® MOTOROLA
CMOS
HIGH PERFORMANCE REMOTE
•
•
Preamp/Detector for FSK Infrared Signals
Coil-less Input Circuit for High Noise Immunity
CONTROL RECEIVER
II
• On-chip Bandpass Filtering
• Fl/F2 Detection Using Pulse Counting Technique
• Data Validation imd Address Recognition
• 2 Programmable Address Bits
• MPU Data Bus Interface
• Additional Serial Data Output
• Wake-up Logic
• Supply Relay Switch
• 5 mA Current Loop for Standby Indicator
• Uses 4 MHz Crystal
P SUFFIX
• Clock Output
PLASTIC PACKAGE
• 10 V Supply CASE 709
• Minimum External Components needed
Clock
Out
Signal EN
] Serial
Delay CL Data
Bus
Gain Set Data
AZ AUX Data Out
Filter
Reset
ACA
ACB
] Address
Inputs
Relay
On/Standby
GO
GI
] Current
Loop
Test
VDD VSS AGND

CMOS
(LOW·POWER COMPLEMENTARY MOS)
II •
•
Decodes Baseband Dual Carrier Signals
Pilot Tone Demodulation and Identification
• Signal De-emphasis
• Volume, Treble and Bass Control
• Stereo base Facility
• Pseudo Stereo Facility
• Dual Muting Facility
• Loudspeaker and Headphone Outputs
• VCR Input/Output
• Hi-Fi Output
• All Functions Digitally Controlled
• Minimal External Components
• 5 V Supply P SUFFIX
PLASTIC PACKAGE
CASE 710
K1
K2
L
R
] Loudspeakers
Serial
Data Bus
[SDA L
] Headphones
SCL R
MC144130
L
R
] VCR Input
AGND Decoupling L
R
] VCR Output
J
OSC L
Hi-Fi Output
Test R
® MOTOROLA
MC145000
MC145001
MULTIPLEXED LCD DRIVERS

MASTER AND SLAVE
MULTIPLEXED LCD DRIVERS

The MC145(XX) (Masterl LCD Driver and the MCl45001 (Slave) LCD MASTER AND SLAVE
Driver are CMOS devices designed to drive liquid crystal displays in a
multiplexed-by-four configuration. The Master unit generates both
frontplane and backplane waveforms, and is capable of independent
operation. The Slave unit generates only frontplane waveforms, and is
synchronized with the backplanes from the Master unit. Several Slave
units may be cascaded from the Master unit to increase the number of
LCD segments driven in the system. The maximum number of front-
planes is dependent upon the capacitive loading on the backplane
drivers and the drive frequency. The devices use data from a
microprocessor or other serial data and clock source to drive one LCD
segment per bit.
L SUFFIX P SUFFIX
• Microprocessor Compatibility CERAMIC PACKAGE PLASTIC PACKAGE
• Serial Data, Externally Clocked CASE 623 CASE 709
• Multiplexing-By-Four
• Net de Drive Component Less Than 50 mV
• Master Drives 4B LCD Segments
• Slave Provides Frontplane Drive for 44 LCD Segments
• Drives Segments Up to one Square Centimeter (0.155 Square
Inches)
• Display Operating Frequency = 250 Hz Maximum L SUFFIX P SUFFIX
• Supply Voltage Range = 3 V to 6 V
CASE 726 CASE 707
• Latch Storage of Input Data
• Low Power Dissipation
• Logic Input Voltage Can Exceed VDD
• Accomodates External Temperature Compensation
• 24-Pin DIP Configuration Master
• 1B-Pin DIP Configuration - Slave MC14XXXB
1 TL Suffix Denotes
L Ceramic Package
P Plastic Package
C Limited Operating
Temperature Range
VDD
oSCin
Frame-Sync. In inputs against damage due to high static
Data Out voltages or electric fields; however. it is ad-
Data Clock vised that normal precautions be taken to
Data In avoid application of any voltage higher than
FP11 maximum rated voltages to this high im-
pedance circuit. For proper operation it is
FP10
recommended that Vin and Vout be con-
Fpg
strained to the ranges VSssVoutSVDD
and VSSSVinS 15 V
Unused inputs must always be tied to an ap-
propriate logic voltage level.
Characteristic Symbol Value Unit
OC Supply Voltage VOO -0.5 to +6.5 V

Input Voltage, Oata In and Oata Clock, Vin 0.5 \0 15 V
Input Voltage, Pin 22 of Master
DC Current Drain per Pin
. Vin osc
I
0.5 to VOO + 0.5
10
V
mA
Operating Temperature Range TA -40 to +85 'C
Storage Temperature Range Tstg -65to +150 'C
VOO -40'C 25'C 85'C

V Min Max Min Typ Max Min Max
II
RMS Voltage Across a Segment "ON" 3.0 - - - 1.73 - - - V
YON
18Pi-FPjl Segment 60 - - - 3.46 - - -
"OFF" 30 - - - 1.00 - - - V
VOFF
Segment 6.0 - - - 200 - - -
Average OC Offset Voltage 3.0 - 30 - 10 30 - 30
Vdc mV
6.0 - 50 - 20 50 - 50
Input Voltage "0" Level 3.0 - 0.90 - 135 090 - 0.90
VIL V
6.0 - 1.80 - 2.70 1.80 - 1.80
"1" Level 3.0 2.10 - 2.10 1.65 - 2.10 - V
VIH
6.0 4.20 - 4.20 3.30 - 4.20 -
Output Drive Current - Backplanes
High-Current State"
VO~2.85V 150 - 75 190 - 35 -
ISH 3.0 pA
VO=l.65V 220 - 110 200 - 55 -
VO= 1.15 V 160 - 80 200 - 40 -
VO=0.15V 400 - 200 300 - 100 -
VO=5.65 V 500 - 250 300 - 125 -
VO=3.85 V
6.0
1000 - 500 500 - 250 - pA
ISH -
VO=2.15 V 800 - 400 500 - 200
VO~0.15V 500 - 250 300 - 125 -
Low-Current State"
VO=2.85 V 140 - 70 80 - 35 -
VO~1.85V ISL 3.0 2.4 - 1.2 2.8 - 06 - pA
VO~1.15V 2.2 - 1.1 2.5 - 0.5 -
VO=0.15 V 400 - 200 330 - 100 -
VO=5.85 V 190 - 95 105 - 45 -
VO=3.85 V 15 - 7.5 10 - 3.7 -
ISL 6.0 pA
VO=2.15V 13 - 6.5 9 - 3.2 -
VO=0.15V 850 - 425 570 - 210 -
Output Drive Current - Frontplanes
High-Current State"
VO=285 V 80 - 40 60 - 20 -
IFH 3.0 pA
VO=l.85V 140 - 70 120 - 35 -
VO=1.15V 180 - 60 100 - 30 -
VO=0.15 V 100 - 50 95 - 25 -
VO=5.85 V 140 - 70 90 - 35 -
VO=3.85 V 360 - 180 250 - 90 -
IFH 6.0 pA
VO=2.15 V 400 - 200 240 - 100 -
VO=015V 100 - 50 120 - 25 -
Low-Current State"
VO=2.85 V 60 - 30 40 - 15 -
VO=1.85V IFL 3.0 2.8 - 1.4 2.8 - 0.7 - pA
VO~1.15V 22 - 1.1 2.5 - 0.5 -
VO=0.15 V 100 - 50 100 - 25 -
VO=5.85 V 100 - 50 60 - 25 -
VO=3.85 V 16 - 8.0 10 - 4.0 -
IFL 6.0 pA
VO=215 V 13 - 6.5 9 - 3.2 -
VO=O. 15 V 200 - 100 175 - 50 -
Input Current lin 6.0 - ±0.1 .- ±O.OOOOl ±0.1 - ±1.0 pA
Input Capacitance (Vin = Q) Gin - - - - 5.0 7.5 - - pF
Quiescent Current (Per Package) 3.0 - 10 - 25 15 - 20
pA
100 - - -
6.0 185 50 175 130
•.For a time (t= 2.56/osc. freq.) after the backplane or frontplane waveform changes to a new voltage level. the circuit is maintained in the high·
current state to allow the load capacitances to charge quickly. Then the circuit is returned to the low-current state until the next VOltage level
change occurs.
Characteristic Symbol VDD Min Typ Max Unit
Data Clock Frequency 3.0 - 12.5 7.5
MHz
lei
60 - 24 12.5
Rise and Fall Times - Data clock 30 - - 125
tr.tf - ~s
6.0 - 10
Setup Time 3.0 48 - -
tsu ns
Data In to Data Clock 6.0 16 - -
Hold T,me 30 -5 - -
th ns
Data In to Data Clock 6.0 0 - -
PulseWidth 3.0 65 - -
tWH 40 - - ns
Data Clock 60
The Slave unit (Figure 2) consists of the same circuitry as

the Master unit. with two exceptions: it has no backplane
drive circuitry. and its shift register and latch hold 44 bits.
Figure 1 shows a block diagram of the Master unit. The Eleven frontplane and no backplane drivers are available
unit is composed of two independent circuits: the data input from the Slave unit.
circuit with its associated data clock. and the LCD drive cir-
cuit with its associated system clock. LCD DRIVER SYSTEM CONFIGURATIONS
Forty-eight bits of data are serially clocked into the shift Figure 4 shows a basic LCD Driver system configuration,
register on the rising edges of the external data clock. Data in with one Master and several Slave units. The maximum
the shift register is latched into the 48-bit latch at the be- number of slave units in a system is dictated by the max-
ginning of each frame period. (As shown in Figure 3. the imum backplane drive capability of the device and by the
frame period, tframe. is the time during which all the LCD system daw update rate. Data is serially shifted first into
segments are set to the desired "ON" or "OFF" states. I the Master unit and then into the following Slave units on
The binary data present in the latch determines the ap- the rising edge of the common data clock. The oscillator is
propriate waveform signal to be generated by the frontplane common to the Master unit and each of the Slave units. At
drive circuits, whereas the backplane waveforms are in- the beginning of each frame period, tframe, the Master unit
variant. The frontplane and backplane waveform~. FPn and generates a frame-sync pulse (Figure 3) which is received by
BPn. are generated using the system clock (which is the the Slave units. The pulse is to ensure that all Slave unit
oscillator divided by 256) and voltages from the V/3 frontplane drive circuits are synchronized to the Master
generator circuit (which divides VDD into one-third in- unit's backplane drive circuits.
crementsl. As shown in Figure 3, the frontplane and A single multiplexed-by-four, 7-segment (plus decimal
backplane waveforms and the "ON" and "OFF" segment point I LCD and possible frontplane and backplane connec-
waveforms have periods equal to tframe and frequencies tions are shown in Figure 5. When several such displays are
equal to the system clock divided by four. used in a system, the four backplanes generated by the
Twelve frontplane and four backplane drivers are available Master unit are common to all the LCD digits in the system.
from the Master unit. The latching of the data at the beginn- The twelve frontplanes of the Master unit are capable of con-
ing of each frame period and the carefully balanced voltage- trolling forty-eight LCD segments (6 LCD digits), and the
generation circuitry minimize the generation of a net de com- eleven frontplanes of each Slave unit are capable of controll-
ponent across any LCD segment. ing forty-four LCD segments (5 Y, LCD digits).
FIGURE 1 - BLOCK OIAGRAM OF THE MC145000 (MASTER) LCD DRIVER
Data Out
20
FP1
FP2
FP3
., FP4
·5
~ ~
.", .r:;
~ U
FPS
'"
a:
~ '"> FP6
EI :'"c
V>
i:ii
~
i:ii
~
;§
Ci
.t
.•'"
c:
E
0
9
10
FP7
FP8
FPS
FP10
11
FP11
13
FP12
19-
Data
Clock
Back-
-Pins 18 and 19 can plane
be driven to voltages Drive
greater than VDD.
22 23 21 Circuit
OSCin OSCout Frame~ync
Out
FIGURE 2 - BLOCK DIAGRAM OF THE MC146001 (SLAVE) LCD DRIVER

Data Out
1S
:;;
.,
·5
;; ~
.", .r:;
u
'"
a: 1ii
...J
'">
'"
:c
V> ~ ;§
i:ii
:of '"
~
:of Ci
E
~
14-
Data
Clock
-Pins 13 and 14 can be

driven to voltages
greater than VDD.
16
Frame-Svnc
In
VO:~J__ l
VOO -
2/3 (VOOI -
1/3 (VOOI -
0-
VOO-
2/3(VOOI-
1/3(VOOI-
0-
Voo -
2/3(VOOI-
1I3(VOOI-
0-
VOO-
2/31VOOI -
1/3 (VOOI -
0-
Example: One segment ON.

Frontplane wave-
VOO-
t
form IFPII for segment
e to be "ON" and 2/31VOOI -
1/31VOOI-
f. g. h to be
"OFF" (Figure 51
0-
I
VOO-
2/3 (VOO) -
ON segment
1/31VOOI -
voltage waveform Frame RMS Voltage= VOO/../3
0-
across segment e - 1/3 (VOO)- Frame OC Offset Voltage< 50 mV
(BP1-FPlI -2/3IVOOI -
-Voo -
Example: All segments OFF.

Frontplane wave-
form IFP21 for segments { VOO_
a. b. c and d to 2/3 (Vool -
1/3 1VOOI _ -'
r-."
'-l '-l
r-. " r1 " r-. r-.
L.J L.J L.J L.J
r-
L.J L...I
be "OFF"
(Figure 51. 0-
I
Voo-
2/3 (Vool -
OFF segment
1/3 (Voo)-
voltage waveform
0-
across segment b. -1/3 (Vool -
IBP2-FP21 -2/3IVool-
-Voo -
FIGURE4 - BASIC SYSTEM CONFIGURATION
Frame Sync.
Rext
{Optionall
--JVV\r-
MC145000 MC145001 MC145001

Master LCD Slave LCD Slave LCD
Driver Driver Driver
FIGURE5 - FRONTPLANEAND BACKPLANE CONNECTIONSTO A MULTIPLEXED-BY-FOUR

7-SEGMENT(PLUS DECIMAL POINTI LCD DISPLAY
FPl FP2
'''1 '"
a
",lJ-,,,
FPl FP2
BPl e a
BP2 f b
BP3 9 c
BP4 h d
-Because there IS no standard for back-
BP31---~1 c d BP3 plane and front plane connections on
multiplexed displays, this truth table may
BP4 a-BP4 be used only for this example.
FRONTPLANE DRIVE OUTPUTS DATA CLOCK (Master: Pin 19)

(Master: FP1-FP12; Pins 1-11 and 13) (Slave: Pin 14)
(Slave: FP1-FPll; Pins 1-8 and 10-12) The input pin for the external data clock, which controls
The frontplane drive waveforms for the LCD displays. the shift registers. This pin can be driven to 15 volts
regardless of the value of VDD.
DATA OUT (Master: Pin 20)

BACKPLANE DRIVE OUTPUTS (Slave: Pin 15)
(Master: BP1-BP4; Pins 14-17)
The serial data output pin.
The backplane drive waveforms for the LCD displays.
FRAME-SYNC OUT (Master: Pin 21)
The output pin for the frame-sync pulse, which is
DATA IN (Master: Pin 18) generated by the Master unit at the beginning of each frame
(Slave: Pin 13) period, tframe.
The serial data input pin. Data is clocked into the shift
register on the rising edge of the data clock. A high logic FRAME-SYNC IN (Slave: Pin 16)
level will cause the corresponding LCD segment to be turn- The input pin for the frame-sync pulse from the Master
ed on, and a low logic level will cause the segment to be unit. The frame-sync pulse synchronizes the Slave front-
turned off. This pin can be driven to 15 volts regardless of plane drive waveforms to the Master backplane drive
the value of VDD, thus permitting optimum display drive waveforms.
voltage.
OSCin (Master: Pin 22) Voo (Master: Pin 24)
(Slave: Pin 17) (Slave: Pin 18)
The input pin to the system clock circuit. The oscillator The positive supply voltage.
frequency is either obtained from an external oscillator or
generated in the Master unit by connecting an external VSS (Master: Pin 12)
resistor between the oSCin pin and the oSCout pin (Pin 23l. (Slave: Pin 9)
Figure 6 shows the relationship between resistor value and The negative supply lor ground) voltage and logic zero in-
frequency. put pin.
OSCout (Master: Pin 23)

The output pin of the system clock circuit. This pin is con-
nected to the oSCin input (Pin 17) of each Slave unit.
E
.r;
c; 1M
::>
;;;
>
*'"
.~
~ 100 k
E
~
w
The following examples are presented to give the user fur- first bit to be entered has been shifted into bit-location one,
ther insight into the operation and organization of the Master the second bit into bit-location two, and so on. Table 1
and Slave LCD Drivers. shows the bit location in the latch that controls the cor-
An LCD segment is turned either on or off depending responding frontplane-backplane intersection. For example,
upon the RMS value of the voltage across it. This voltage is the information stored in the 26th-bit location of the
equal to the backplane voltage waveform minus the front- latch controls the LCD segment at the intersection of FP7
plane voltage waveform. As previously stated, the backplane and BP3. The voltage waveform across that segment is equal
waveforms are invariant Isee Figure 3). Figure 10 shows one to IBP3 minus FP7l. The same table, but with the column for
period of every possible frontplane waveform. FP12 deleted, describes the operation of the Slave unit.
For a detailed explanation of the operation of liquid crystal In applications of this type, all the necessary data to com-
materials and multiplexed displays, refer to a brochure entitl- pletely update the display are serially shifted into the Master
ed "Multiplexed Liquid Crystal Displays," by Gregory A. and succeeding Slave units within a frame period. Typically,
Zaker, General Electric Company, Liquid XTAL Displays a microprocessor is used to accomplish this.
Operation, 24500 Highpoint Road, Cleveland, Ohio 44122.
Example 2: Many keyboard-entry applications, such as
Example 1: Many applications le.g., meters, gasoline calculators, require that the most significant digit be entered
pumps, pinball machines, and automobile dashboard and displayed first. Then as each succeeding digit is entered,
displays) require that, for each display update, an entirely the previously entered digits must shift to the left. It is,
new set of data must be Shifted into the Master and cascad- therefore, neither necessary nor desirable to enter a com-
ed Slave units. The correspondence between the frontplane- pletely new set of data for each display change. Figure 7
backplane intersections at the LCD segments and the data shows a representation of a system consisting of one Master
bit locations in the 48-bit latch of the Master lor 44-bit latch and three Slave units and displaying 20 LCD digits. If each
of the Slave) is necessary information to the system digit has the frontplane-backplane configuration shown in
designer. In Figure 1, it is shown that data is serially shifted Figure 5, the relationship between front planes, backplanes,
first into the 48th-bit location of the shift register of the and LCD segments in the display is shown in Table 2.
Master. Thus, after 48 data bits have been shifted in, the
Digits (or alphanumeric characters) are entered, most- through h of digit 1, and the previously entered eight bits
significant digit first, by using a keyboard and a decoder ex- now control segments a through h of digit 2. Thus the two
ternal to the MC145000. Data is entered into the Master digits are displayed in the proper locations.
and cascaded Slave units according to the following format: 4) Entering the remaining 18 digits from the keyboard fills
1) Initially, all registers and latches must be cleared by the 2G-digit display. Entering an extra digii will cause the first
entering 160 zero data bits. This turns off all 160 segments of digit entered to be shifted off the display.
the display.
2) Entering the most-significant digit from the keyboard Example 3: In addition to controlling 7-segment (plus
causes the appropriate eight bits to be serially shifted into decimal point) digital displays, the MC145000 and MC145001
the Master unit. These eight bits control LCD segments a may be used to control displays using 5 x 7 dot matrices. A
through h of digit 1, and cause the desired digit to be Master and three Slave units can drive 180 LCD segments,
displayed in the least-significant digit location. and therefore are capable of controlling five 5 x 7 dot
matrices 1175 segmentsl. Two control schemes are
3) Entering the second-most-significant digit from the
presented in Figures 8 and 9; one using a single Master unit,
keyboard causes eight more bits to be serially shifted into the
and one using two Master units.
Master unit. These eight bits now control LCD segments a
FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FPS FP10 FPll FP12
BP1 4 8 12 16 20 24 28 32 36 40 44 48
BP2 3 7 11 15 lS 23 27 31 35 39 43 47
BP3 2 6 10 14 18 22 26 30 34 38 42 48
BP4 1 5 S 13 17 21 25 29 33 37 41 45
Note that only six

of the 11 front-
planes are used
FP11 FP2 FP10 FP1 FP11 FP2 FP10 FP12
I l I
FJlO I FP1 FPS
1 1
FP11
I
FP2 FJlO FP1 F!S Fp '1
BP1
FP12
a1
FPll
01
FP10
a2
FP9
02
... FP2
a6
FPl
e6
FPll
a7
FP10
07
... FP1
a12
FPll
012
FP10
a13
FP9
013
... FP2
a17
FPl
017
FPll
alB
FPlO
olB
... FP7
a20
FP6
020
BP2 bl f1 b2 12 b6 16 b7 17 b12 f12 b13 113 b17 117 b1B f1B b20 120
BP3 e1 91 e2 92 e7 g6 e7 97 e12 912 e13 913 e17 917 elB 91B e20 920
BP4 dl hl d2 h2 d6 h6 d7 h7 d12 h12 d13 h13 d17 h17 dlS hlB d20 h20
1 digit 1
I digit 2
I· • ·1 digit 6
I digit 7 •• -I digit 12
I digit 13 •• -I digit 17
I digit 18 I· .• digit 20
I
I
I
Master
Slave " Slave 12 Slave '3 J
I
FPll FP9 FP2 FPll FP4 FP2 FP4 FP8 FP6
Ff6
FP12 I 1
FP10 1 FP8
1
FP3
I
I FPl
I
1
I FPlO
I
FP5
I
I
I FP3 I FPl
I
I
I
FP7 I FP5
1
1
I FP3 FP9
I
I FP7
I
I FP5
I
I 1 1 I I
I I I
I
I
I
I I I I I I I I I
-~
r ~
~
/:~I
/: ~
~
/.~.I
/. :'S--.l
-I II
TI
I
I I
I
I
I
I
I
I
liT /, I'T
I 1 I I
1 I I ! I
I 1
I I I
FP7 1 FP5
I
FP9 I
I
I
FP7 FP11
I I
I FP9
I
FP4 I FP2
FP6 FP8 FP10 FP3
Master A Slave A
FP11 FPS FP6 FP4 FPl FP10 FP7 FP5
FP12 ~ FP10 ~ FP8 FP7 ~ FP5 ~ FP3 FP2 ~ FP11 tFPS FP8 ~ FP6 ~ FP4
A I A I A A I A I A A I A I A A I A I A
I I I I I I I I I I I I I I I I I I I I
I I I I I I I I I I I I I I I I I I 1 I
I I I I I I I 1 I I I I I 1 I I I I 1 I
I I I I I 1 I I I I I I I I I I I I I 1
8Pl A
8P2 A
8P3 A
8P4 A
8P18
Master 81 8P28
8P38
I I I I I I I I I I I I I I I I I
I 1 I 1 I I I I I I I I I I I I I
I I I I I I I I I I I I I I I I I
I I
FP12 1 FP10 1 FP8
I I I
FI>7 i F~5 i Fb FI>2 i F~11 I ~P9 I1 F~4
8 FPl 1 8 FP9 8 B FP6 B FP4 B B FPl B FPlO B Fr5 B
8 B B B B B B
I-"'---lframe--_~_I 1-..•---- tframe--~~-I
,o:]_~ ":]--~ I
I
I
I VDD I
I
FPl for e, f. g, h I 2VDD/3
II off 2VDD/3tL-rillnl VDD/3

FP2 for a, b, C, d
off VDD/3 o
I
I
VDD I VDD
2VDD/3 I 2VDD/3
I
VDD/3 VDD/3
o o
VDD VDD
2VDD/3 FPl for g, h on 2VDD/3
VDD/3 FP2 for C, d on VDD/3
o o
VDD VDD
2VDD/3 FPl for e, f, 9 on 2VDD/3
VDD/3 FP2 for a, b, C on VDD/3
o o
VDD VDD
2VDD/3 FPl for e, f, h on2VDD/3
VDD/3 FP2 for a, b, d on VDD/3
o o
VDD VDD
2VDD/3 FPl for e, g, h on 2VDD/3
FP2 for a, c, d on
VDD/3 VDD/3
o o
VDD VDD
2VDD/3 FPl for f, g, h on 2VDD/3
FP2 for b, c, d on VDD/3
VDD/3
o o
VDD VDD
2VDD/3 FPl for e, f, g, h on2VDD/3
VDD/3 FP2 for a, b, c, d on VDD/3
o o
® MOTOROLA MC145026
MC145027
MC145028
MC145029
The MC145026 will encode nine bits of information and serially

transmit this information upon receipt of a transmit enable, n,
(ac- REMOTE CONTROL
tive low) signal. Nine inputs may be encoded with trinary data 10,1, ENCODER/DECODER PAIRS
open) to allow 39119,683) different codes.
Three decoders are presently available and they use the same
transmitter - the MC145026. The decoders will receive the 9-bit
word and will interpret some of the bits as address codes and some
as data. The MC145027 will interpret the f11Stfive transmitted bits as
address and the last four bits as data. The MC145029 will interpret
the first four transmitted bits as address and the last five bits as data.
The MC145028 will treat all nine bits as address. If no errors are L SUFFIX
received, the MC145027 will output four data bits, and the CERAMIC PACKAGE
CASE 620
MC145029 will output five data bits, when the transmitter sends ad-
dress codes that match that of the receiver. A valid transmission out-
put will go high on the decoders when they recognize an address
that matches that of the decoder. Other receivers can be produced
with different address/data ratios.
• May be Addressed in either 8inary or Trinary P SUFFIX

PLASTIC PACKAGE
• Trinary Addressing Maximizes Number of Codes
CASE 648
• Interfaces with RF, Ultrasonic, or Infrared Transmission Medias
• 4.5 V to 18 V Operation
• On-Chip R IC Oscillator; No Crystal Required
• High External Component Tolerance; Can use 5% Components MC14XXXX Suffix Denotes
• Standard 8-Senes Input and Output Charactenstics
~ L Ceramic Package
P Plastic Package
.. PIN ASSIGNMENTS
AI/DI
A2/D2
t. 16 VDD
15 Data Out
Al
A2
1. Al
A2
1.
2
t6
15 A6
VDD
A2
Al 1.
2
16 VDD
15 06
A3/D3 14 TE A3 07 A3 14 A7 A3 14 D7
A4/D4 4 13 RTC A4 08 A4 4 13 A8 A4 4 13 D8
A5/D5 12 CTC A5 D9 A5 5 12 A9 05 12 D9
A6/D6 11 RS Rl 11 VT RI 6 II VT RI 6 11 VT
A7ID7 10 A~/D9 Cl 7 10 R2/C2 CI 7 10 R2/C2 C, 10 R2/C2
VSS 9 A8/D8 VSS 8 9 Data In VSS 8 9 Data In VSS 8 9 Data In
MC145026 MC145027 MC145028 MC145029

Encoder Decoder Decoder Decoder
DC Supply Voltage VDD -0.5 to + 18 V
Input Voltage, All Inputs Vin 0.5 to VDD + 0.5 V
DC Current Drain Per Pin I 10 mA
OperatIng Temperature Range TA -40 to +85 °C
Storage Temperature Range Tstn -65to+150 'C
VDD -40'C 25'C +85°C

V Min Max Min Typ Max Min Max
II
Output Voltage "0" Level 5.0 - 0.05 - 0 0.05 - 0.05
V1n=VOD or 0 VOL 10 - 0.05 - 0 0.05 - 0.05 V
15 - 0.05 - 0 0.05 - 0.05
"'" Level 5.0 4.95 - 495 5.0 - 4.95 -

V,n=O or VDD VOH 10 995 - 995 10 - 9.95 - V
15 14.95 - 14.95 15 - 14.95 -
Input Voltage "0" Level
1VO=4.5 or 0.5 VI 5.0 - 1.5 - 2.25 1.5 - 1.5
VIL V
1VO=9.0 or 1.0 VI 10 - 30 - 4.50 3.0 - 3.0
IVO~ 13.5 or 1.5 VI 15 - 4.0 - 6.25 4.0 - 4.0
"1" Level
1VO=0.5 or 4.5 VI
VIH
50 3.5 - 35 2.75 - 3.5 - V
{VO~ 1.0 or 9.0 VI 10 7.0 - 7.0 5.50 - 7.0 -
1VO ~ 1.5 or 13.5 VI 15 11.0 - 11.0 8.25 - 11.0 -
Output Dflve Current Source
1VOH=2.5 VI 5.0 -2.5 - -2.1 -4.2 - -1.7 -
1VOH=46 VI 10H 5.0 -0.52 - -044 -088 - -0.36 - mA
1VOH=9.5 VI 10 - 1.3 - -1.1 -225 - -09 -
1VOH ~ 13.5 VI 15 -36 - -30 -88 - -2.4 -
1VOL =0.4 VI Sink 5.0 0.52 0.44 0.88 0.36
1VOL =0.5 VI 10L 10 1.3 - 1.1 2.25 - 0.9 - mA
1VOL = 1.5 VI 15 3.6 - 3.0 8.8 - 2.4 -
Input Current - TE IMC145026, Pullup Devlcel 5.0 - - 30 4.0 7.0 - -
lin 10 - - 16 20 26 - - ~A
15 - - 35 45 55 - -
Input Current
AS IMC1450261 lin 15 - ±0.3 - ± O.CXXXJ1 ±0.3 - ± 1.0 ~A
Data In tMCl 45027, MC145028, MC1450291
Input Current
A1/D1-A9/D9IMC1450261
Al·A5IMC1450271
A1·A91MC1450281
A 1·A4 IMC1450291
} 110
5.0
10
15
-
-
-
-
-
-
-
-
-
±55
±3OO
±650
±80
±340
±725
-
-
-
-
-
-
~A
Input Capacitance (Vin - OJ C,n 5.0 7.5 pF

QUiescent Current MC145026 5.0 0.0050 0.10
100 10 - - - 0.0100 0.20 - - ~A
15 - - - 0.0150 0.30 - -
OUlescent Current-MCI 45027,MC I 45028,MC145029 5.0 - - - 30 50 - -
100 10 - - - 60 100 - - ~A
15 - - - 90 150 - -
Total Supply Current MC145026Ifc-20 kHzl 5.0 - - - 100 200 - -
IT 10 - - - 200 400 - - ~A
15 - - - 300 600 - -
Total Supply Currenl-MC145027, MC145028, 5.0 - - - 200 400 - -
MCI 45029 IIc = 20 kHzl IT 10 - - - 400 800 - - ~A
15 - - - 600 1200 - -
than maximum rated voltages to this high impedance circuit, For proper operation it is recommended that
Vin and Vout be constrained to the range VSS ~(Vin or Vout) ;:;VOO'
Unused inputs must always be tied to an appropriate logic voltage level (e,g. either VSS or VOO)·
Characteristic Symbol VDD Min Typ Max Unit
Output RIse and Fall Time 5.0 - 100 200
tTLH
tTHL
10 - 50 100 ns
15 - 40 80
Data In Rise and Fall Time IMC145027, MC145028, MC1450291

tTLH
50 - - 15
10 - - 15 ~s
tTHL
15 - - 15
Encoder Clock Frequency 50 0 - 2

lei 10 0 - !i MHz
15 0 - 10
Maximum Decoder Frequency 50 - - 240
(Referenced to Encoder Clock) iSee Figure 91 lei 10 - - 410 kHz
15 - - 450
TE Pulse Width 5.0 65 - -
tWL 10 30 - - ns
15 20 - -
System Propagation Delay Clock
- - - 182 -
(IT to Valid Transmission) Cycles
Tolerance on Timing Components
IARTC+ACTC+ARl +ACll - - - - ± 25 %
IAR2+AC21 - - - ±25
assumes the first four bits are address. These address bits
must be encoded to match the address inputs at the
The encoder will serially transmit nine bits of trinary data
receiver. If the address bits match, the next Idata) bits are
as defined by the state of the A 11D1-A9/D9 input pins.
stored and compared to the last valid data stored. If this
These pins can be in either of three states 10, 1, open)
data matches, the VT pin will go high on the 2nd rising
allowing 39 = 19,683 possible codes. The transmit se-
edge of the 9th bit of the first word. Between the two data
quence will be initiated by a low level of the IT input pin.
words no signal is sent for three data bit times. As the se-
Each time the IT input is forced low the encoder will output
cond encoded word is received, the address must again
two identical data words. This redundant information IS
match, and if it does, the data bits are checked against the
used by the receiver to reduce errors. If the IT input is kept
previously stored data bits. If the two words of data match,
low, the encoder will continuously transmit the data words,
the data is transferred to the output data latches and will re-
The transmitted words are self-completing Itwo words will
main until new data replaces it. At the same time, the Valid
be transmitted for each IT pulse!.
Transmission output pin is brought high and will remain
Each transmitted data bit is encoded into two data
high until an error is received or until no input signal is
pulses. A logic zero will be encoded as two consecutive
received for four data bit times,
short pulses, a logic one by two consecutive long pulses,
Although the address information is encoded in trinary
and an open as a long pulse followed by a short pulse. The
fashion, the data information must be either a one or a zero,
input state is determined by using a weak output device to
A trinary lopen) will be decoded as a logic one.
try to force each input first low, then high. If only a high
stata results from the two tests, the input is assumed to be
hard wired to VDD. If only a low state is obtained, the input
is assumed to be hard wired to VSS. If both a high and a This receiver operates in the same manner as the
low can be forced at an Input, it is assumed to be open and MC145027/MC145029 except that nine address bits are
is encoded as such. used and no data output is available. The Valid Transmis-
The transmit sequence is enabled by a logic zero on the sion output is used to indicate that a valid signal has been
IT input. This input has an internal pullup device so that a received.
simple switch may be used to force the input low. While IT Although address information normally is encoded in
is high the encoder is completely disabled, the oscillator is trinary, the designer should be aware that, for the
inhibited and the current drain is reduced to quiescent cur- MC145028, the ninth address bit IA9) must be either a
rant. When IT is brought low, the oscillator is started, and one or a zero. This part, therefore, can accept only 2 x 38
an internal reset is generated to initialize the transmit se- = 13,1 22 different codes. A trinary lopen I A9 will be in-
quence, Each input is then sequentially selected and a terpreted as a logic 1 , However if the transmitter sends a
determination is made as to input logic state. This informa- trinary lor logic 1) and the receiver address is a logic 1 lor
tion is serially transmitted via the Data Out output pin, trinary) respectively, the valid transmission output will be
shortened to the R1 xC 1 time constant.
The decoder will receive the serial data from the en-
coder, check it for errors and output data if valid. The Although the encoder sends two words for error check-
transmitted data consisting of two identical data words is ing, a decoder does not necessarily wait for two trans-
examined bit by bit as it is received. The MC145027 mitted words to be received before issuing a valid transmis-
assumes the first five bits are address and the MC145029 sion output. Refer to the flowcharts in Figures 8 and 9.
MC145026Encoder R1. C1 - These pins accept a resistor and capacitor that
A1/D1-A9/D9 - These inputs will be encoded and the are used to determine whether a narrow pulse or a wide
data serially output from the encoder. pulse has been encoded. The time constant Rl x Cl should
be set to 1.72 transmit clock periods. R,Cl =3.95 RTCCTC
VSS - The most negative supply lusually ground!.
R2/C2 - This pin accepts a resistor to VSS and a
RS. CTC. RTC - These pins are part of the oscillator sec-
tion of the encoder. If an external signal source is used in- capacitor to VSS that are used to detect both the end of an
encoded word and the end of transmission. The time cons-
stead of the internal oscillator It should be connected to the
RS input and the RTC and CTC pins should be left open. tant R2 x C2 should be 33.5 transmit clock periods Ifour data
bit periods). This time constant is used to determine that the
TE - This Transmit-Enable lactive low) input will initiate Data In input has remained low for four data bit times lend of
transmission when forced low. An Internal pull up device
transmission!. A separate comparator looks at a voltage
will keep this input high normally.
equivalent two data bit times lOA R2C2) to detect the dead
Data Out - This is the output of the encoder that will pre- time between transmitted words. R2C2 = 77 RTCCTC.
sent the serially encoded signals.
Valid Transmission. VT - This output will go high when
VDD - The most positive supply. the following conditions are satisfied:
MC145027. MC145028. MC145029 DECODERS 1. the transmitted address matches the receiver address.
A1-A5 (MC1450271. A1-A9 (MC145028). A1-A4 and
(MC145029) - These are the address inputs that must 2. the transmitted data matches the last valid data
match the corresponding encoder inputs in order for the received.
decoder to output data. VT will remain high until el\her a mismatch is received. or no
06-09 (MC145027). 05-09 (MC145029) - These input signal is received for four data bit times.
outputs will give the information that is presented to the VDD - The most positive supply.
corresponding encoder inputs. Note: only binary data will VSS - The most negative supply lusually ground!.
be acknowledged; a trinary open will be decoded as a logic
one.
3-Pm
Data Select
OscIllator
and
and
Buffer
Enable
~VDD
~VSS
Sequencer
Circuit
3
9 Data
In
LGJVDD
fa; 11Hz)
23 ATC CTC'
for 1 kHz:sf:s400 kHz

where: CTC'=CTC+Clayout+ 12 pF
AS-2ATC
AS;': 20 k
ATC;': 10 k
4OOpF<CTC<15pF
The value for AS should be chosen to be about 2 times RTC. This

range will ensure that current through AS IS Inslgnlftcant compared
to current through RTC. The upper limit for AS must ensure that
RS x 5 pF (input capacitance) is small compared to ATe x ere
For freQuencies outside the indicated range. the formula will be
less ac~urate. The actual oscillation range of this circuit is from less
than 1 Hz to over 1 MHz.
FIGURE 6 - ENCODER/DECODER TIMING DIAGRAM
I+--l PWmin MC14li026 ENCODER

IT~ :- . COn~in~~~~ i;:~:~:=:~~
_NM¢U')(O ~~~~~~~~ ~oo~~~::B~?6~~ ~::'~~~~~~N~
EncoderOscilla~ ~JU1mUUUUlJlJU1Jl, ~
(Pin 121
14-1s1 BII-+I 1+-9th BII--+i I+-ls1 Bit-+! t+-91h BIt--l
DataOulIPin1_51 ~1 ~~~lJlJ4 'ULlL-

i4-- One ---+l+- Tnnary---+!-- Zero -+l I
I_ 1stWord _I ••----2nd '-Nord
Encoder
OSCIllator
(P,n 121
u
Data
Out
IPin 151
Ln__ ~n~ __ ~
Ul _
Disable VT
on the 1st
Address Mismatch
and Ignore the
Rest of This Word
Store
the
4-B,t/5-Blt
Data
Disable VT
on the 1st
Data Mismatch
Latch Data
Onto Output
Pins and
ActIvate VT
Serially Shill the
Address '''''' = ··TT
No IntO Ihe Storage
Heglster up Untli
{I.e .• Excludlngl the
ls1 Mismatch
No ShIft In
an Extra
·T·
FIGURE 10 - MC145027/MC145028/MC145029
fmax vs Clayout
400
~
0
U
~ <0
N
X
8
J U" 300
:;;
200
Clavou, (pFI on Pins 1-5 IMC1450271; PinS 1-5 and 12-15 IMC1450281
P,ns 1-4 IMC145029J
CTC' = CTC + Clayau! + 12 pF
100 pF:s CTC:S 15"F
=
RTC>: 10 k; RS 2 RTC
R1 >: 10 k
VOO
IT Cl>:400pF
-.L R2>: 100 k
IO.1"F C2>: 700 pF
I 14 16
5 15
Tnnary
Addresses 5
MC145027 Trinary
MC145026 Addresses
R1
RTC
13 15
C1 06
I 14
12 CTC 07
4-8i\ { 13
Binary 08
11 10 12
Data 09
RS '1
VT
C2
R2
1
f -
asc - 2.3 RTCCTC'
R 1C1 ~ 395 RTCCTC

R2C2 ~ 77 RTCCTC
Exemple R/C Values

IAII Resistors and Capacitors are i 5% I
ICTC' = CTC + 20 pFI
fose 1kHz) RTC CTC' RS R1 C1 R2 C2
362 10 k 120 pF 20 k 10 k 470 pF 100 k 910 pF
181 10 k 240 pF 20 k 10k 910 pF 100 k 1800 pF
88.7 10 k 490 pF 20 k 10 k 2000 pF 100 k 3900 pF
42.6 10 k 1020 pF 20 k 10 k 3900 pF 100 k 7500 pF
21.5 10k 2020 pF 20 k 10 k 8200 pF 100 k 0.Q15 "F
8.53 10k 5100 pF 20 k 10 k 0.02 "F 200 k 0.02 "F
1.71 50k 5100 pF 100 k 50k 0.02 "F 200 k 0.01 "F
® MOTOROLA
CMOS
SERIAL AID CONVERTER

The MC145040 and MC145041 are B-bit A/D converters with built-in
(SAD)
serial I/O ports. The A/D section is composed of an all capacitor, charge re-
distribution D/A converter, a chopper stabilised comparator, and a suc-
cessive approximation register. It performs a single conversion in 321-lsec
150 I'sec including the serial data transfer of the result) and includes an
on-chip 11 channel analog multiplexer. The conversion is ratiometric with
respect to an externally supplied reference voltage. Analog input range
'",_I
extends from VSS to VDD. All digital interfacing - chip select. serial data LSUFFIX
clock. serial data input and serial data output - is handled via a 4-wire "'* CERAMIC PACKAGE
serial I/O port. ~Ir --,., CASE 732
_
P SUFFIX
PLASTIC PACKAGE 20
CASE 738 1
E
ANO
AN1
AN2
AN3
AN'
AN5
~
AN.
AN7 3
ANa
AN'
AN10
VREF
VAG NOle 1 : ThIS Ime ,s open c,rcu,t

13 on (he Me 145040
NOle 2 This Ime.s open Clfcuit
on theMC145041
® MOTOROLA MC145104
MC145106
MC145107
MC145109
MC145112
The MC145104. MC145106, MC145107. MC145109. and

MC145112 are phase locked loop (PLL) frequency synthesizer parts
constructed with CMOS devices on a single monolithic structure.
These synthesizers find applications in such areas as CB and FM
transceivers. The device contains an oscillator/amplifier. a 210 or
211 divider chain for that oscillator signal. a programmable divider
PLL
chain for the input signal and a phase detector. The MC145104/
FREQUENCY SYNTHESIZERS
5106/5112 have circuitry for a 10.24 MHz oscillator or may operate
with an external signal. The MC145107/5109 require the external
reference signal. Several of the circuits provide a 5.12 MHz output
signal, which can be used for frequency tripling. A 29 (MCI45106/
5109/5112) or 28 (MCI45104/5107) programmable divider divides
the input signal frequency for channel selection. The inputs to the
programmable divider are standard ground-to-supply binary signals.
Pull-down resistors on these inputs normally set these inputs to
ground enabling these programmable inputs to be controlled from
a mechanical switch or electronic circuitry. PSUFFIX
PLASTIC PACKAGE
The phase detector may control a VCO and yields a high level CASE 648
signal when input frequency is low. and a low level signal when input
frequency is high. An out of lock signal is provided from the on-chip
lock detector with a "0" level for the out of lock condition.
The MC145106 is the full pinout version of this family of parts
and has the capability of all parts in the family. The MC145104/
-5107/5109/5112 are limited pinout versions. See block diagrams
for details. P SUFFIX
PLASTIC PACKAGE
CASE 707
• Single Power Supply
• Wide Supply Range: 4.5 to 12 Vdc
• 16 or 18 Pin Plastic Packages
• 10.24 MHz Oscillator on Chip
• 5.12 MHz Output Pin-for- Pin Replacements for:
MC145104 for SM5104, MM55104, MM55114
• Programmable Division 8inary Input Selects up to 29
MC145106 for MM55106. MM55116
• On·Chip Pull Down Resistors on Programmable Divider Inputs MC145107 for SM5107
MC145109 for SM5109
• Selectable Reference Divider, 210 or 211
MC145112 for SM5106
• Three-State Phase Detector
voltages or electric fields; however, it is
DC Supply Voltage VOO -0.5 to + 12 Vdc advised that normal precautions be taken
Input Voltage, All Inputs Vin -{l.5 to VOO + 0.5 Vdc to avoid application of any voltage higher
DC Current Drain per Pin I 10 mAdc
impedance circuit. For proper operation it
Operating Temperature Range TA -40 to +85 °c is recommended that V in and Vout be
Storage Temperature Range Tstg -65 to +150 °c constrained to the range Vss ~ (Vin or
V , .;;; VOO'
ou
Voo All Types

Characteristic Symbol Vdc Min Typ Max Unit
Supply Current 10 5.0 - 6 10 mAdc
10 - 20 35
. 12 - 28 50
Input Voltage "0" Level VIL 5.0 - - 1.5 Vdc
10
12
-
-
-
-
3.0
3.6
"1" Level VIH 5.0 3.5 - - Vde
10 7.0 - -
12 8.4 - -
Input Current IFS) "0" Level lin 5.0 -5.0 -20 -50 ,uAdc
IPull-up Resistod 10 -15 ~O -150
12 -20 -ao -200
(PO to P81 5.0 - - -{l.3
10 - - -{l.3
12 - - -{l.3
IFSI "1" Level 5.0 - - 0.3 "Ade

10 - - 0.3
12 - - 0.3
IPO to P8) 5.0 7.5 30 75
(Pull-down Resistod 10 22.5 90 225
12 30 120 300
(Oscin. fin) "0" Level 5.0 -2.0 ~.O -15 "Ade
10 ~.O -25 ~2
12 -9.0 -37 -92
10SCin. fin) "1" Level 5.0 2.0 6.0 15
10 6.0 25 62
12 9.0 37 92
Output Drive Current 10H mAdc
(VO: 4.5 Vdel Source 5.0 -{l.7 -1.4 -
(VO: 9.5 Vdc) 10 -1.1 -2.2 -
(VO: 11.5 Vde) 12 -1.5 -3.0 -
1VO = 0.5 Vdel Sink 10L 5.0 0.9 1.8 - mAde
(VO: 0.5 Vde) 10 1.4 2.8 -
(VO: 0.5 Vde) 12 2.0 4.0 -
Input Amplitude - Vp-p
(fin @4.0 MHz) - 1.0 0.2 - Sine
(Oscin @ 10.24 MHz) - 1.5 0.3
Input Resistance Rin Mil
(OSCin.fin) 5.0 - 1.G -
10 - 0.5 -
12 - - -
Input Capacitance Cin pF
(Oscin. fin) - - 6.0
Three State Leakage Current , ITL "Ade
(~ Detout) 5.0 - - 1.0
10 - - 1.0
12 - - 1.0
Input Frequency ,. fin 4.5 4.0 - - MHz
(-400C to +850C) 12 4.0 - -
Oscillator Frequency OSCin 4.5 - 10.24 MHz
(_40°C to +850C) 12 - 10.24
PO P1 P2 P3 P4 P5 P6 P7
MC145107
N.C. '" Pin 8

VOO'" Pin 1
VSS'" Pin 18
25 25
! 20 20
>- :g
--- -- - ~
~
~ 15
+2SoC
--
w
..•'" 15
+2S0C
~ I II :;
:i' +8SoC '">
J -40°C
--- - ~ +8SoC -40°C
II
> 10 - 1--- 10
"~ / /, - ~
:/": ,/ ci /. V
g 5.0 ...• ~
~ 5.0
>
Selection
P8 P7 P6 P5 P4 P3 P2 P1 PO Divide By N
0 0 0 0 0 0 0 0 0 2 (Note 1)
0 0 0 0 0 0 0 0 1 3 (Note 11
PO - P8 - Programmable divider inputs (binary)
0 0 0 0 0 0 0 1 0 2
fin - Frequency input to programmable divider (derived
0 0 0 0 0 0 0 1 1 3
from VeO)
0 0 0 0 0 0 1 0 0 4
Oscin - Oscillator/amplifier input terminal
OSCout - Oscillator/amplifier output terminal
-, LD - Lock detector, low when out of lock
0 1 1 1 1 1 1 1 1 255 <P Oetout - Signal for control of external VCO. output high
when fjo/N is less than the reference frequency; output
low when fin/N is greater than the reference frequency.
1 1 1 1 1 1 1 1 1 511 Reference frequency is the divided down oscillator -
input frequency typically 5.0 or 10kHz.
FS - Reference Oscillator Frequency Division Select. When
using 10.24 MHz Osc frequency, this control selects
10 kHz, a "0" selects 5.0 kHz.
-:-2out - Reference Osc frequency divided by 2 output; when
Note 1: The binary setting of 00000000 and 00000001 on using 10.24 MHz Osc frequency, this output is 5.12
P8 to PO result$ in a 2 and 3 division which is not MHz for frequency tripling applications.
in the 2N-l sequence. When pin is not connected V DD - Positive power supply
(or is not listed as for the MC145104 and VSS - Ground
MC145107). the logic signal on that pin can be
treated as a "0".
The MC145104, MC145106, MC145107, MC145109, mixer #1. When these signals are provided with crystal
MC145112 ICs are well suited for Applications in CB oscillators, the result is a three crystal, 360 channel,
radios becauseof the channelized frequency requirements. 50 kHz step synthesizer. When using the offset loop
A typical 40 channel CB transceiver synthesizer using a (bottom) in Figure 5 to provide the indicated injection
single crystal reference is shown in Figure 3 for receiver frequencies for mixer #1 (two for transmit and two for
IF values of 10.695 MHz and 455 kHz. receive) 360 additional channels are possible. This results
In addition to applications in CB radios, the MC145104· in a 720 channel, 25 kHz step synthe.sizer which requires
12 ICscan be usedasa synthesizer for severalother systems. only two crystals and provides RfT offset capability. The
Various frequency spectrums can be achieved through the receive offset value is determined by the 11.31 MHz
use of proper offset, prescaling and loop programming crystal frequency and is 10.7 MHz for the example.
techniques. In general, 300-400 channels can be syn· The VH F marine synthesizer in Figure 4 depicts a
thesized using a single loop, with many additional single loop approach for FM transceivers. The VCO
channels available when multiple loop approaches are operates on-frequency during tr.ansmit and is offset down-
employed. Figures 4 and 5 are examples of some ward during receive. The offset corresponds to the
possibilities. receiver IF (10.7 MHz) for channels having identical
In the aircraft syntheizer of Figure 5, the VHF loop receive/transmit frequencies (simplex), and is (10.7 -
(top) will provide a 50 kHz 360 channel system with 10.7 4.6 = 6.1) MHz for duplex channels. Carrier modulation
MHz RfT offset when only the 11.0500 MHz (transmit) is introduced in the loop during transmit.
and 12.1200 MHz (receive) frequencies are provided to
26.965 - 27.405
MHz: (transmit)
26.510 - 26.950
MHz (receive)
Transmit Ranoe
156.025 - 157.425 MHz
·'57.4
Receiver L.a. Range
145.5.,5 - 152.575 MHz
-151.3
II
Transmit
Modulation
Programmable Inputs Circuit
N = 97 to 153
·'52
Transmit
NOTES, • Values in Parentheses are
for a 5.0 kHz Reference
• Receiver IF == 10.7 MHz
• Low Side Injection
Frequency ~UPle)(
• Duplex Offset = 4.6 MHz • Example Frequencies for
14.75#
• Step Size"" 25 kHz
Channel
#Ca"
28 Shown
be eliminated
by •
by adding
c::::J (29.50)
• Frequencies in 11Hz unless
noted 184 to';'N for Duplex Channels.
TRANSMIT
118.000 - 135.975 MHz
(25 kHz Steps)
RECEIVE
128.700 - 146.675 MHz
VHF Loop
Programming
750 kHz - 2545 kHz
TRANSMIT
11.0500 MHz
11.0525 MHz
RECEIVE
12.1200 MHz
12.1225 MHz
RECEIVE
".31 MHz
810 kHz - 812.5 kHz
(Select Frequency to Give
N· 324 - 325 Desired A/T Offset I •
® MOTOROLA
PLL FREQUENCY SYNTHESIZER

The MC 145143 is a phase locked loop building block variation
of the MC1451 06/MC145112 family. The device contains the PLL
oscillator circuitry required to operate with fundamental mode FREQUENCY SYNTHESIZERS
crystals to 10.24 MHz. The oscillator circuitry is connected to the
phase detector through a divide-by-16 and a 29-1 divide-by-N
counter. The reference oscillator can be divided in steps of 16
between 32 and 8176 before interfacing with the phase detector.
The external input to the phase detector requires a VSS to VOO
B
signal and forces the phase-detector output high if higher in
frequency than the output of the divide-by-N counter. An out-of-Iock
signal is provided from the on-chip lock detector with a "0" level for
an out-of-Iock condition.
• Operation to 25 MHz
• 4.5 V to 12 V Operation
• Programmable Reference Divisions from 32 to 8176 (16X2 to P SUFFIX
16X511) PLASTIC PACKAGE
CASE 648
• Three·State Phase Detection
• On-Chip Lock Detection
15 14 13 12 11 10 8
o
PO P1 P2 P3 P4 PS P6 P7 P8
MAXIMUM RATINGS (Voltages referenced to VSSI

OC Supply Voltage VOO -0.5 to + 12 V inputs against damage due to high static
Input Voltage, All Inputs -0.5 to VOO + 0.5 V voltages or electric fields; however, it is
Vin
Operating Temperature Range TA -40 to +85 °c than maximum rated voltages to this high
Storage Temperature Range Tstg -65 to +150 °c impedance circuit. For proper operation it is
recommended that Vin and Vout be
constrained to the range V$S ~ (Vin or
Voutl OSVOO·
Characteristics Symbol Min Typ Max Units
Supply Current (OSCin = 12 MHZ) 10 - 3.5 12 mA
Input Voltage "0" Level VIL - - 1.5 V
Input Voltage "1" Level VIH 3.5 - - V
Input Current (Excluding Pin 3) lin - ±0.OOO01 ±0.1 jJA
Output Voltage 110 = 0.8 mAl VOL - - 0.5 V

Output Voltage 110 - -0.6 mAl VOH 4.5 - - V
Oscillator Frequency OSCin 25.0 - - MHz
Oscillator Input Resistance Rin - 1 - MO
Oscillator Input Capacitance Cin - 8 - pF
Three-State Leakage I4>Detoutl ITL - ±0.OO5 ±100 nA
Phase Detector Input Pulse Width - Positive Or Negative </JDetin 0.15 - - jJs
25
20
~
w
+2S0C
'"
"" t5
~
0
> +8SoC -40oC
~ 10
~ /.
g 5.0 /
>
Selection
PO - pa - Programmable divider inputs (binary)
P8 P7 P6 P5 P4 P3 P2 P1 PO Divide By N fin - Frequency input to programmable divider (derived
0 0 0 0 0 0 0 0 0 2 (Note 1) from VCOI
0 0 0 0 0 0 0 0 1 3 INote 1I Oscin - Oscillator/amplifier input terminal
0 0 0 0 0 0 0 1 0 2 OSCout - Oscillator/amplifier output terminal
0 0 0 0 0 0 0 1 1 3 LD - Lock detector, low when out of lock
0 0 0 0 0 0 1 0 0 4 <P Detout - Signal for control of external VCO. output high
when fin is greater than \the reference frequency; output
low when fin is lessthan the reference frequency.
0 1 1 1 1 1 1 1 1 255 Reference frequency is the divided down oscillator.
input frequency tYpically 5.0 or 10 kHz.
VOO - Positive power supply
1 1 1 1 1 1 1 1 1 511 VSS - Ground
Note 1: The binary setting of 00000000 and 00000001 on

pa to PO results in a 2 and 3 division which is not
in the 2N-1 sequence.
® MOTOROLA
The MC145144 is one of a family of LSI PLL frequency synthesizer

parts from Motorola CMOS. The family includes devices having serial, 4-BIT DATA BUS INPUT PLL
parallel and 4-bit data bus programmable inputs. Options include single-
FREQUENCY SYNTHESIZER
or dual-modulus capability, transmit/receive offsets, choice of phase
detector types and choice of reference divider integer values.
The MC145144 is programmed by a 4-bit input, with strobe and ad-
dress lines. The device features consist of a reference oscillator, pro-
grammable reference divider, digital-phase detector, programmable
divide-by-N counter and the necessary latch circuitry for accepting the
4-bit input data. When combined with a loop filter and VCO, the
MC145144 can provide all the remaining functions for a PLL frequency
synthesizer operating up to the device's frequency limit. For higher VCO
frequency operation, a down mixer or a fixed divide prescaler can be us-
ed between the VCO and MC145144.
• Tailored for TV Tuning Applications L SUFFIX P SUFFIX

• Low Power Drain CASE 620 CASE 648
• 3.0 to 9.0 Vdc Supply Range

• >30 MHz Typical Input Capability @5Vdc
• Programmable Reference Divider for Values Between 3584 and 3839
• On- or Off-Chip Reference Oscillator Operation
VDO 16 Vss
• Single Modulus 4-Bit Data Bus Programming
OSCin 2 15 fm
• + N Range =4 to 4092 in Steps of Eight OSCout 3 '4 DO
AD • 13 01
• "Linearized" Digital Phase Detector Enhances Transfer Function
Linearity
Al 12 02
A2 6 11 03
• Pin-for-Pin Compatible with the MN6044
ST to Test
9 PDout
DC Supply Voltage VOO - 0.5 to + 10 Vde
Input Voltage. All Inputs Vin - 0.5 to VOO + 0.5 Vde
DC Current Drain VOO or VSS Pins I 30 mA
Operating Temperature Range TA -40to +85 °C
Storage Temperature Range ~ Tstg -65to +150 °C
II Power Supply Voltage

Characteristic
Range
Symbol
VOO
VDD
-
Min
3
TLow
Max
9
Min
3
25°C
Typ
-
Max
9
Min
3
TH· h
Max
9
Units
Vde
Output Voltage o Level 3 - 0.05 - 0 005 - 005
Vin = VOO or 0
VOL 5 - 0.05 - 0 0.05 - 0.05
9 - 0.05 - 0 0.05 - 0.05
Vde
3 2.95 - 295 3 - 2.95 -
Vin = OorVOD 1 Level VOH 5 495 - 4.95 5 - 495 -
9 8.95 - 8.95 9 - 895 -
Input Voltage o Level
Vo = 2.5 or 0.5 3 - 0.9 - 1.35 0.9 - 0.9
VIL
Vo = 4.5 or 0.5 5 - 1.5 - 2.75 1.5 - 1.5
Vo = 8.5 or 1.5 9 - 2.7 - 4.05 2.7 - 2.7 Vde
Vo ~ 0.50r2.5 1 Level 3 2.10 - 2.10 1.65 - 2.10 -
Vo =
0.5 or 4.5 VIH 5 35 - 3.5 2.75 - 3.5 -
Vo =
1.5 or 8.5 9 6.3 - 6.3 4.95 - 63 --
Output Current Source
VOH ~ 2.7 3 -0.44 - -0.35 -0.66 - -0.22 -
IOH
VOH = 4.6 5 -0.64 - -0.51 -0.88 - -036 -
VOH = 85 9 -1.3 - -1.0 -1.3 - -07 - mAde
VOL = 03 Sink 3 0.44 - 0.35 066 - 0.22 -
VOL = 0.4 IOL 5 064 - 0.51 0.88 - 0.36 -
VOL = 0.5 9 1.3 - 1.0 1.3 - 07 -
Input Current Other Inputs IlL 9 - ±0.3 - ±OOOOOl ±0.1 - ± 1.0
fin. OSCin 9 - ± 15 - ±5 ±10 - ±8 ~Ade
fin. OSCin 9 - ± 15 - ±5 ±10 - ±8
IIH
Other Inputs 9 - ±03 - ±O.OOOOl ±0.1 - ± 1.0
Input Capacitance Gin 3-9 - 10 - 6 10 - 10 pF
Output Capacitance Co." 3-9 - 10 - 6 10 - 10 pF
Quiescent Current 3 - 800 - 200 800 - 1600
100 5 - 1200 - 300 1200 - 2400 ~Ade
9 - 1600 - 400 1600 - 3200
3-5tate Leakage Current PDout IlL 9 - ±0.1 - ±0.OOO1 ±0.1 - ±3.0 ~Ade
NOTE: Tlow = - 40°C

Thigh = 85°C
This device contains circuitry to protect the inputs against damage due to high static voltages or electric ftelds; however, it is advised that nor-
mal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper
operation It is recommended that Vin and Vout be constrained to the range VSS:s (Vin or Voutl::S VOO.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VOOL
Characteristic Symbol VDD Min Typ Max Units
3 - 100 200
Output Rise Time tTLH 5 - 50 100 ns
9 - 40 00
3 - 100 200
9 - 40 00
Setup Times
3 - - -
Data to ST
Isu 5 - - - ns
9 - - -
3 - - -
Address to ST tsu 5 - - - ns
9 - - -
Hold Time
3 - - -
th 5 - - - ns
Data. Address 10 ST
9 - - -
3 - - 5
Input Rise And Fall Ttmes tTLH
tTHL
5 - - 4 ~s
OSCin. fin 9 - - 2
3 40 30 -
Input Pulse Width
oSCin. fin. Strobe
tw 5 35 20 - ns
9 25 15 -
T\ow 25°C Thi h

Characteristic Symbol VDD Units
Operating Frequency 3 - 17 - 27 14 - 12
OSC,n Input = SO Wave VDD - VSS 'max 5 - 33 - 55 27 - 21 MHz
9 - 35 - 65 35 - 33
Input = Sin Wave 500 mVp-p 3 - 11 - 21 10 - 9
fmax 5 - 20 - 34 17 - IS MHz
9 - 17 - 34 17 - 15
Operating Frequency 3 - 9 - IS 8 - 7
fin Input = SO Wave VDD - VSS 'max 5 - 19 - 30 15 - 15 MHz
9 - 31 - 52 26 - 22
Input = Sin Wave 500 mVp-p 3 - 10 - IS 7 - 6
fmax 5 - 18 - 31 15 - 15 MHz
9 - 21 - 31 15 - 15
Tlow = -40°C
Thigh = 85°C
ST (Pin 7) - When high, this input will enter the data that
appears at the DO, 01, 02 and 03 inputs, and when low, will
OSCin, OSCout (Pins 2 and 3) - These pins form an on- latch that Information. When high, any changes in the data
chip reference oscillator when connected to terminals of an information will be transferred into the latches.
external parallel resonant crystal. Frequency setting
capacitors of appropriate value must be connected from + 5 (Pin 8) - The + 5 output is one fifth the reference fre-
OSCin to ground and OSCout to ground. OSCin may also quency, fR, that IS derived by dividing the OSCin signal by
serve as input for an externally-generated reference signal. the reference divider.
This signal will typically be AC coupled 10 OSCin, but for
larger amplitude signals (standard CMOS-logic levels) DC POout (Pin 9) - Three-state output of phase detector for
coupling may also be used. In the external reference mode, use as loop error signal. Note that output is of opposite
no connection is required to OSCout. polarity of the other PLL synthesizers in this family.
Frequency fv> fR or fV Leading: Positive Pulses.
ADDRESS INPUTS (pins 4, 5, 61 - AO, A 1and A2 are us- Frequency fV< fR or fV Lagging: Negative Pulses.
ed 10 define which latch receives the information on the data Frequency fV = fR and Phase Coincidence: High-
input lines. The addresses refer to the following latches: Impedance State.
(NOTE: Bit Zero is LSBI
TEST (Pin 10) - This input is used during manufacturing
and should be left open or tied 10 VSS during normal opera-
A2 Al AO Selected Function DO 01 02 03 tion.
0 0 0 Latch 0 Reference- Bits 0 1 2 3
DATA INPUTS (Pins 11, 12, 13, 14) - Information at
0 0 1 Latch 1 Reference-Bits 4 5 6 7
these inputs is transferred 10 the internal latches when the
0 1 0 Latch 2 +N Bits 3 4 5 6
ST Input is in the high state. Pin 11 (03) is most significant.
0 1 1 Latch 3 + N Bits 7 8 9 10
1 0 0 Latch 4 +N Bit 11 fin (Pin 151 - Input to + N portion of synthesizer. fin is
1 0 1 typically derived from loop VCO and is AC coupled into Pin
15. For larger amplitude signals (standard CMOS-logic
1 1 0
levels) DC coupling may be used.
1 1 1
PDout~Veo
Al ~-L
e
I
1
Fls) = ----
AleS + 1
DEFINITIONS: N = Total Division Aatio in feedback loop

Kq,= VDD/4 •• for PDout
Kveo = 2dfveo
t.vveo
for a typical design wN == (21[11 OJ fr (at phase detector input)
r " I
fV
Feedback
(f,n + NI
fR
Reference
_n_n---------..n_n_
lOse + RI
~n-_n-u--~
NOTE· The Po output state is equal to either VOO or VSS when active. When not active. the output IS high impedance ~nd the voltage at that
pin IS determined by the low pass filter capacitor.
Part Number Format Prescale Phase Detector

MC145144 4-811 Data Single Modulus 3 State
MC145145 Bus Input Single Modulus 3 5 tatel2 Output
MC145146 Format Dual Modulus 3 Statef2 Output
MC145151 Parallel Input Single Modulus 3 state/2 Output
MC145152 Format Dual Modulus 2 Output
MC145155 Senallnput Single Modulus 3 statel2 Output
MC145156 Format Dual Modulus 3 statel2 Output
MC145157 SIngle Modulus 3 statel2 Output
MC145156 Dual Modulus 3 statel2 Output
MC145159 Oual Modulus 3 statel Analog
FIGURE 2 FIGURE 3
TYPICAL fin MAXIMUM FREQUENCY vs VOO TYPICAL OSCin MAXIMUM FREQUENCY VI VOO
INPUT = 500 mV p-p INPUT = 500 mV POp
MHt
50
-40·C
40 40·C-
25·C
~ 25·C ~ 85·e-
30
20
f?- 85·C
V
'/
II 10
FIGURE 4 FIGURE 5
TYPICAL fin MAXIMUM FREQUENCY vs VOO TYPICAL OSCin MAXIMUM FREQUENCY vs VOO
INPUT= SQ WAVE VOO-VSS INPUT= SQ WAVE VOO-VSS
FIGURE 6
TYPICAL 'DO vs FREQUENCY
10010 100 10
mA 9 mA 9
8 8
30 MHt
'II
NOTE: To compute total 100 add component due to fin with that due to aSCin.
I I
I
I
I
I I
I I
I I
I I
I
I
I
I
I
I
I
"
1/6 14069/'
I
I
I
I
I I
I
L
+V _ I
_______ J
® MOTOROLA

parts from Motorola CMOS. The family includes devices having serial,
parallel and 4-bit data bus programmable inputs. Options include single- 4-BIT DATA BUS INPUT PLL
II detector types and choice of reference divider integer values.

The MCl45145 is programmed by a 4-bit input, with strobe and ad-
dress lines. The device features consist of a reference oscillator, 12-bit
programmable reference divider, digital-phase detector, 14-bit program-
mable divide-by-N counter and the necessary latch circuitry for accept-
-,-
ing the 4-bit input data. When combined with a loop filter and VCO, the
MC145145 can provide all the remaining functions for a PLL frequency
synthesizer operating up to the device's frequency limit. For higher VCO
frequency operation, a down mixer or a fixed divide prescaler can be us-
ed between the VCO and MC145145.
• General Purpose Applications L SUFFIX
CATV TV Tuning CERAMIC PACKAGE P SUFFIX
AM/FM Radios Scanning Receivers CASE 726 PLASTIC PACKAGE
Two Way Radios Amateur Radio CASE 707
• Low Power Orain

• >30 MHz Typical Input Capability @5Vdc D1 D2
• Programmable Reference Divider for Values Between 3 and 4095 DO D3
fin REFout
• Single Modulus 4-Bit Data Bus Programming
• + N Range=3 to 16383 VSS ~R
• "Linearized" Digital Phase Detector Enhances Transfer Function VDD ~V

Linearity OSCin LD
• Two Error Signal Options - OSCout 12 PDout
Single Ended (Three Statel
Double Ended AO 11 ST
Al 9 10 A2
OSCin
OSCout
DO 2
D1 1
D2018
D3 17
A2
A1
AO
ST
OC Supply Voltage VOO -0.5 to + 10 Vde
Input Voltage. All Inputs Vin - 0.5 to VOO + 0.5 Vde
DC Current Drain VDD or VSS Pins I 30 mA
Operating Temperature Range TA 40 to +85 ·C
Storage Temperature Range Tstg 65 to +150 ·C
Tlow 25·C Th' h

Characteristic Symbol VOO Units
Min Mox Min Typ Mox Min Mox
Power Supply Voltage Range VOO - 3 9 3 - 9 3 9 Vde
Output Voltage o Level

3 - 005 - 0 0.05 - 005
Vin=VOO or 0
VOL 5 - 0.05 - 0 0.05 - 0.05
9 - 0.05 - 0 0.05 - 0.05
Vde
3 2.95 - 2.95 3 - 2.95 -
Vin=OorVOO 1 Level VOH 5 495 - 4.95 5 - 4.95 -
9 895 - 8.95 9 - 8.95 -
Vo = 2.5 or 0.5
VIL
3 - 0.9 - 1.35 0.9 - 0.9
Vo = 4.5 or 0.5 5 - 15 - 2.75 1.5 - 1.5
VO=8.5 or 1.5 9 - 2.7 - 4.05 2.7 - 2.7 Vde
Vo ~ 0.5 or 2.5 1 Level 3 2.10 - 2.10 1.65 - 2.10 -
Vo = 0.5 or 4.5 VIH 5 3.5 - 3.5 2.75 - 3.5 -
VO= 1.5 or 8.5 9 63 - 6.3 4.95 - 6.3 -
VOH=27 3 -0.44 - -0.35 -066 - -0.22 -
VOH~4.6
IOH
5 -0.64 - -0.51 -0.88 - -0.36 -
VOH=8.5 9 -1.3 - -1.0 -1.3 - -0.7 - mAde
VOL=0.3 Sink 3 0.44 - 0.35 0.88 - 0.22 -
VOL =0.4 IOL 5 0.64 - 0.51 0.88 - 0.36 -
VOL=0.5 9 1.3 - 1.0 1.3 - 0.7 -
Input Current Other Inputs 9 - ±0.3 - ±O.OOOOl ±0.1 - ±1.0
IlL
fin.OSCin 9 - ±15 - ±5 ±10 - ±8 !LAde
fin.OSCin 9 - ±15 - ±5 ±10 - ±8
IIH
Other Inputs 9 - ±0.3 - ±O.OOOOl ±0.1 - ±1.0
Input Capacitance Cin 3-9 - 10 - 6 10 - 10 pF
Output Capacitance Cout 3-9 - 10 - 6 10 - 10 pF
Quiescent Current 3 - BOO - 200 BOO - 1600
100 5 - 1200 - 300 1200 - 2400 !LAde
9 - 1600 - 400 1600 - 3200
3-State Leakage Current POout IlL 9 - ±0.1 - ±O.OOOl to.1 - ±3.0 !LAde
NOTE: Tlow= -4Q·C

Thigh = B5·C
This device contains Circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that nor-
mal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper
operation it is recommended that Vin and Vout be constrained to the range VSSS(Vin or Vout)SVDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g .. either VSS or VDDI.
Characteristic Symbol VDD Min Typ Max Units
3 100 200
9 - 40 80
3 - 100 200
9 - 40 80
Setup Times
3 - - -
Data to ST
tsu 5 - - - ns
9 - - -
3 - - -
Address to ST tsu 5 - - - ns
9 - - -
Hold Time
3 - - -
Data, Address to ST th 5 - - - ns
9 - - -
Output Pulse Width 3 70 120 170
~R, ~V with fR in tWHI~J 5 50 100 150 ns
Phase With IV L 9 30 80 130
3 5
Input Rise and Fall Times tTLH
aSCin. fin
5 - - 4 ps
tTHL
9 - - 2
Input Pulse Width

3 40 30 -
tw 5 35 20 - ns
OSCin, fin, Strobe
9 25 15 -
Tiow 25'C Th'llh

OSCin Input = SO Wave VDD - VSS fmax 5 - 33 - 55 27 - 21 MHz
9 - 35 - 65 35 - 33
Input = Sin Wave 5(X)'mVp.p 3 - 11 - 21 10 - 9
fmax 5 - 20 - 34 17 - 15 MHz
9 - 17 - 34 17 - 15
fin Input = SO Wave VDD - VSS fmax 5 - 19 - 30 15 - 15 MHz
9 - 31 - 52 26 - 22
Input = Sin Wave 5(X) mV p-p 3 - 10 - 15 7 - 6
fmax 5 - 18 - 31 15 - 15 MHz
9 - 21 - 31 15 - 15
Tlow = -4O'C
Thigh =
85'C
OATA INPUTS (Pins 2, 1, 18. 17) - Information at these ST (Pin 111 - When high, this input will enter the data
inputs is transferred to the internal latches when the ST in- that appears at the 00,01,02 and 03 inputs, and when low,
put is in the high state. Pin 17 103) is most significant. will latch that information. When high, any changes in the
data information will be transferred into the latches.
fin (Pin 3) - Input to + N portion of synthesizer. fin is
typically derived from loop VCO and is AC coupled into Pin
3. For larger amplitude signals (standard CMOS-logic levels I POout (Pin 12) - Three-state output of phase detector for
OC coupling may be used. use as loop error signal.
Frequency fV> fR or fV Leading: Negative Pulses.
Frequency fV < fR or fV Lagging: Positive Pulses.
Frequency fV = fR and Phase Coincidence: High-
Impedance State.
OSCin. OSCout (Pins 6 and 7) - These pins form an on-

chip reference oscillator when connected to terminals of an LO IPin 13) - Lock detector signal. High level when loop
external parallel resonant crystal. Frequency setting is locked (fR, fV of same phase and frequency). Pulses low
capacitors of appropriate value must be connected from when loop is out of lock.
OSCin to ground and OSCout to ground. OSCin may also
serve as input for an externally-generated reference signal.
This signal will typically be AC coupled to OSCin, but for <l>v.<l>R(Pins 14 and 15) - These phase detector outputs
larger amplitude signals (standard CMOS-logic levels) DC can be combined externally for a loop error signal. A single-
coupling may also be used. In the external reference mode, ended output is' also available for this purpose (see POout).
no connection is required to OSCout. If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by <l>v pulsing
AODRESS INPUTS (Pins 8. 9,10) - AO, A1 and A2 are low. <l>Rremains essentially high.
used to define which latch receives the information on the If the frquency fV is less than fR or if the phase of fV is lag-
data input lines. The addresses refer to the following latches: ging, then error information is provided by <l>Rpulsing low.
A2 Al AO Selected Function DO 01 02 03 <l>vremains essentially high.
If the frequency of fV = fR and both are in phase, then
0 0 0 Latch 0 +N Bits 0 1 2 3
both <l>vand <l>Rremain high except for a small minimum
0 0 1 Latch 1 +N Bits 4 5 6 7 time period when both pulse low in phase.
0 0 Latch 2 +N Bits B 9 10 11
0 1 1 Latch 3 +N Bits 12 13
1 0 0 Latch 4 Reference Bits 0 1 2 3 REFout (Pin 161 - Buffered output of on-chip reference
1 0 1 Latch 5 Reference Bits 4 5 6 7 oscillator or externally provided reference-input signal.
1 1 0 Latch 6 Reference Bits B 9 10 11
1 1 1
PDout~VCO
Rl _...L
<PRC>-- C
<PVC>--
I
1
A1CS + I
Bl PDout VCO
Al
<PAC>--
A2
<PVC>--
C
NOTE: Sometimes A 1 is split into two series resistors each A 1 + 2. A capacitor Cc IS then placed from the midpoint to ground to further filter tPV and
~R. The value for Cc should be such that the corner frequency of this network does not significantly affect WN·
DEFINITIONS: N = Total DivIsion Ratio in feedback loop

K<p = VDD/4 •. for PDou!
K<p= VDD/2 •. for <PVand <PA
KVCO = 2•.~fVCO
~VVCO
FIGUAE 1
PHASE DETECTOR OUTPUT WAVEFORMS
fA
Reference
lOse ~ AI
h~1
n n n n
Feedback
din ..•. Nl
11 n
I
PD Oul
u
4>A
U ~ I I
4>V
I I ~ I
NOTE The Po ou"tput

LD
state is equal
U
to either YOO Of VSS when
~
active When
~
not active, the output IS high

I
Impedance and the voltage at that
pin is determined by the low pass filter capaCItor.

MC145144 4-Bit Data Single Modulus 3 Stale
MC145145 Bus Input Single Modulus 3 Statel2 Output
MC145146 Format Dual Modulus 3 State12 Outpul
MC145151 Parallel Input Single Modulus 3 Slatel2 OulPUI
MC145155 Serial Input Single Modulus 3 Slatel2 Output
MC145156 Format Dual Modulus 3 Statel2 OUlput
MC145157 Single Modulus 3 Statel2 Output
MC145156 Dual Modulus 3 Statel2 Output
MC145159 Dual Modulus 3 Statel Analog
FIGURE 2 FIGURE 3
TYPICAL lin MAXIMUM FREQUENCY vs VOO TYPICAL OSCin MAXIMUM FREQUENCY YO VOO
INPUT = 500 mV p+p INPUT = 500 mV p. p
-40'C
-40'C-
2S'C
~ 2S'C ~ 8S'C-
8S'C
fi'/
V
V
FIGURE 4 FIGURE 5
TYPICAL fin MAXIMUM FREQUENCY vs VOO TYPICAL OSCin MAXIMUM FREQUENCY vs VOO
INPUT = SQ WAVE (VOO-VSS) INPUT=SQ WAVE 1VOO-VSS)
FIGURE 6
TYPICAL 100 vs FREQUENCY
100
mA
10
30 MHz
t••
NOTE: To compute total 100 add component due to fin with that due to aSCin_
small changes in this value, fine tuning is accomplished. Bet-
ter tuning resolution is achievable with this method than by
The features of the MC145145 permit bus operation with a changing the + N, due to the use of the large fixed prescal-
dedicated wire needed only for the strobe input. In a ing value of + 256 provided by the MC12071.
microprocessor controlled system this strobe input is ac- The two loop synthesizer, in Figure 8, takes advantage of
cessed when the phase lock loop is addressed. The remain- these features to control the phase locked loop with a
ing data and address inputs will directly interface to the minimum of dedicated lines while preserving optimal loop
microprocessor's data and address buses. performance. 80th 25 Hz and 100 Hz steps are provided
The + R programmability is used to advantage in Figure 7. while the relatively large reference frequencies of 10 kHz or
Here, the nominal + R value is 3667; but by programming 10.1 kHz are maintained.
UHFI
VHF
Tuner
Or
CATV
Front
End
10.1000 CJ
MHz T 7.9996 to 32.0184 MHz 1.9999 to 8.0046 MHz
'= 16 13 1100 Hz Stepsl 125 Hz Steps)
OSCout REFout LD
12
OSCin
DO
PDout , ...
D1
" Loop 1
+4
YC01
Filter
9
D2
D3
AO
MC145145
Loop 1
¢y
¢R
15
14 }/
A1 3.9996 to 4.9995 MHz
10
and
fin 1
16,0085 to 17,0084 MHz
110.1 kHz Stepsl
I\)
Choice of
N Detector
<0
I\) Error
Signals
6 OSCout
20SCin
REFout
13
LD
PDout
12 j " ...•..
DO Loop 2 YC02
}/
D1 Filter
18 15
D2 ¢R
17 MC145145 14
D3 Loop 2 ¢y
4.000 to 15.0100 MHz
8
AO 110 kHz Steps 1
9
A1
10
NOTES: 1. Table 1 provides program sequence for the + N1 ILoop 11 and + N21Loop 21 Counters.
Address & Data ChiPsel"/
2. + R1 = 1000, fR1 = 10.1 kHz; + R2= 1010, fR2= 10 kHz.
"'----- V 3. fyC01 = N11fRli + N21fR21= N1IfR2+Llfi + N2lfR21 where Llf= 100 Hz.
To Controller 4. Other fRl and fR2 values may be used with appropriate + Nl and + N2 changes.
+N1 t,n1IMHz) +N2 !vC02 (MHz) !vC01 IMHz)
,,1.,
l
396
397
+
495
,J.
1
3.9996
4r
7
49995
400
399
,
301
4.‫סס‬OO
39900
,
3.0100
79996
79997
+
80095
"A"
t
.~ "J"1
401
400
t
302
,
4.0100
4.‫סס‬OO
30200
,
8.0096
80097
8.0195
"A"
t
"J" "C" ,
402
401
303
"0"
40200
4.0100
30300+
,
80196
80197
80295
Increasing
11
T
15.‫סס‬OO
In 100 Hz Steps
+
19.9995
1600 16‫סס‬oo 199996
"8"
1599 15.9900 199997
' 1' l +
1501 +
15.0100 +
20.0095
Tr 1585
1586
1684
"t"1
16.0085
16.0186
17.0084
200085
20.0086
+
20.0184
"E"
t ,J
j "C" "0"
,
20.0185
20.0186
20.0284
Increasing
In 100 Hz Steps
~ +
32.0084
32.0085
32.0086
' 1' ' 1' 320t84
@MOTOROLA

parts from Motorola CMOS. The family includes devices having serial.
or dual-modulus capabilitY, transmit/receive offsets, choice of phase 4-BIT DATA BUS INPUT PLL
detector tYpes and choice of reference divider integer values. FREQUENCY SYNTHESIZER
The MC145146 is programmed by a 4-bit input, with strobe and ad-
dress lines. The device features consist of a reference oscillator, 12-bit
programmable reference divider, digital-phase detector, 1G-bit program-
mable divide-by-N counter, 7-bit divide-by-A counter and the necessary
latch circuitry for accepting the 4-bit input data. When combined with a
loop filter and VCO, the MC145146 can provide all the remaining func-
tions for a PLL frequency synthesizer operating up to the device's fre-
quency limit. For higher VCO frequency operation, a down mixer or a
dual modulus prescaler can be used between the VCO and the
MC145146
• General Purpose Applications
CATV
AM/FM Radios
Two Way Radios
• Low Power Drain
TV Tuning
Scanning Receivers
Amateur Radio
~- L SUFFIX
CERAMIC PACKAGE
CASE 732
PIN ASSIGNMENT
1
P SUFFIX
PLASTIC PACKAGE
CASE 738
D1 1 • 20 D2
• >30 MHz Typical Input Capability @5 Vdc
19 D3
• Programmable Reference Divider for Values Between 3 and 4095
• On- or Off-Chip Reference Oscillator Operation 18 tR
• Dual Modulus 4-Bit Data Bus Programming 17 <PR

• + N Range=3 tol 023, + A Range= 0 to 127 16 <pv
• "Linearized" Digital Phase Detector Enhances Transfer Function VDD 6 15 tv
Linearity
OSCin 7 14 Modulus Control
• Two Error Signal Options -
Single Ended (Three State) OSCout 8 13 LD
Double Ended AO 9 12 ST
A1 10 11 A2
aSCin 7 12.Blt .•. R Counter 18 fA
OSCout 8
.--.§.ovoo
...-iovss
1S tv
16 .V
17 .R
DC Supply Voltage Voo -0.5 to + 10 Vde
Input Voltage. All Inputs Vin -0.5 to VDD+0.5 Vde
Operating Temperature Range TA 40 to +85 °C
Tiow 25°C Th' h

Power Supply Voltage Range VDD - 3 9 3 - 9 3 9 Vde
Dutput Voltage o Level 3 - 0.05 - 0 005 - 0.05
Vin=VDD or 0
VOL 5 - 0.05 - 0 0.05 - 0.05
9 - 0.05 - 0 0.05 - 0.05
Vde
3 2.95 - 2.95 3 - 2.95 -
Vin= orVDD 1 Level VOH 5 4.95 - 4.95 5 - 4.95 -
9 8.95 - 895 9 - 8.95 -
VO= 2.5 or 0.5 3 - 09 - 1.35 0.9 - 0.9
VIL - 1.5 - 1.5
VO=4.5 or 0.5 5 2.75 1.5 -
VO=8.5 or 1.5 9 - 2.7 - 4.05 2.7 - 2.7 Vde
Vo = 0.5 or 2.5 1 Level 3 2.10 - 2.10 1.65 - 210 -
VO=0.5 or 4.5 VIH 5 3.5 - 3.5 2.75 - 3.5 -
Vo = 1.5 or 8.5 9 6.3 - 6.3 4.95 - 6.3 -
VOH=2.7 3 -0.44 - -035 -0.66 - -0.22 -
VOH=4.6 5 -0.64 - -0.51 -0.88 - -036 -
IOH -1.3
VOH=8.5 9 - -10 -1.3 - -0.7 - mAde
VOL =0.3 Sink 3 0.44 - 0.35 0.66 - 0.22 -
VOL=O.4 IOL 5 0.65 - 0.51 0.88 - 0.36 -
VOL =0.5 9 1.3 - 1.0 13 - 0.7 -
Output Current Modulus Control Source
VOH=2.7 3 0.15 - 0.25 0.5 - 0.08 -
IOH mAde
VOH=4.6 5 0.45 - 0.75 1.5 - 0.23 -
VOH=8.5 9 0.75 - 1.25 2.5 - 0.38 -
VOL =0.3 Sink 3 0.48 - 0.8 1.6 - 0.24 - mA
VOL=O.4 IOL 5 0.90 - 1.5 3 - 0.45 -
VOl =0.5 9 2.10 - 3.5 7 - 1.05 -
Input Current Other Inputs 9 - ±0.3 - ±OOOOl ±0.1 - ±1.0
IlL
fin.OSCin 9 - ±15 - ±5 ±10 - ±8
pAde
fin.OSCin 9 - ±15 - ±5 ±10 - ±8
IIH
Input Capacitance Cin 3-9 - 10 - 6 10 - 10 of
3 - 800 - 200 800 - 1600
Quiescent Current IDD 5 - 1200 - 300 1200 - 2400 pAde
9 - 1600 - 400 1600 - 3200
3-5tate Leakage Current PDout IlL 9 - ±0.1 - ±O.OOOOl ±0.1 - ±3.0 pAde
NOTE: Tlow= -40°C

Thigh = 85°C
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however. it is advised that nor-
mal precautions be taken to avoid application of any voltage higher than maximum fated voltages to this high-impedance circuit. For proper
operation it is recommended that Vin and Vout be constrained to the range VSS:s:IVin or Vout):sVOO.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VOOL
Characteristic Symbol VOO Min Typ Max Units
3 - 100 200
9 - 40 80
3 - 100 200
Output Fan Time tTHL 5 - 50 100 ns
9 - 40 80
3 - 80 180
IPLH 5 - 50 100 ns
Propagation Delay Time 9 - 30 80
Clock to Modulus Control 3 - 80 160
5 - 50 100 ns
II
TpHL
9 - 30 60
Setup Times
3 10 0 -
Isu 5 10 0 - ns
Dala 10 ST
9 10 0 -
3 80 60 -
Address to ST Isu 5 50 30 - ns
9 30 18 -
t 3 35 15 -
Hold Time
th 5 25 10 - ns
Data. Address to ST
9 20 10 -
</lA. </lV with fA in tWHI</l1 5 50 100 150 ns
Phase with fV 9 30 80 130
Input Rise and Fall Times tTLH 3 - - 5

5 - - 4 pS
aSCin. fin tTHL
! 9 - - 2
Inpul Pulse Width

3 40 30 -
OSCin. fin. Slrobe
tw 5 35 20 - nS
9 25 15 -
Tlow 25'C Thi h

OSCin Input~SO WaveVDD-VsS fmax 5 - 33 - 55 27 - 21 MHz
9 - 35 - 65 35 - 33
Input= Sin Wave 500 mV pIP 3 - 11 - 21 10 - 9
fmax 5 - 20 - 34 17 - 15 MHz
9 - 17 - 34 17 - 15
Operating FreQuency 3 - 9 - 15 8 - 7
fin Input= SO Wave VDD- VSS fmax 5 - 19 - 30 15 - 15 MHz
9 - 31 - 52 26 - 22
Input = Sin Wave 500 mV ptp 3 - 10 - 15 7 - 6
fmax 5 - 18 - 31 15 - 15 MHz
9 - 21 - 31 15 - 15
Tlow= -4O'C
Thigh=85'C
DATA INPUTS (Pins 2,1,20,19) - Information at these
inputs is transferred to the internal latches when the ST in-
put is in the high state. Pin 19 1031 is most significant.
LD (Pin 13) - LDCk detector signal. High level when loop
fin (Pin 3) - Input to + N portion of synthesizer. fin is is locked (fR, fy of same phase and frequency). Pulses low
typically derived from loop YCO and is AC coupled into Pin when loop is out of lock.
3. For larger amplitude signals (standard CMOS-IDgic levels),
DC coupling may be used.
MODULUS CONTROL (Pin 14) - Signal generated by the
on-chip control logic circuitry for controlling an exter;lal dual
mDdulus prescaler. The modulus control level will be low at
the beginning of a count cycle and will remain low until the
PDDut (Pin 5) - Three-state Dutput Df phase detector for
+ A counter has counted down from its programmed value.
use as 10DPerrDr signal.
At this time, modulus control goes high and remains high
II
Frequency fy> fR Dr fy Leading: Negative Pulses. until the + N counter has counted the rest of the way down
Frequency fy < fR Dr fy Lagging: PDsitive Pulses. from its programmed value (N-A additional countS since
Frequency fy = fR and Phase CDincidence: Hlgh- both + Nand + A are counting dDwn during the first portion
Impedance State. of the cycle). Modulus cDntrol is then set back low, the
counters preset tD their respective programmed values, and
the above sequence repeated. This provides for a total pro-
grammable divide value (NT)=Nep+A where P and P+1
OSCin, OSCout (Pins 7 and 8) - These pins fDrm an Dn- represent the dual modulus prescaler divide values respec-
chip reference DscillatDr when cDnnected tD terminals Df an tively for high and low modulus control levels; N the number
external parallel reSDnant crystal. Frequency setting programmed into the + N counter and A the number pro-
capacitDrs Df apprDpriate value must be cDnnected frDm grammed into the + A counter.
OSCin tD ground and OSCDut to grDund. OSCin may alsD
This signal will typically be AC cDupled tD OSCin, but fDr tv (Pin 151 - This is the output of the + N counter that is
larger amplitude signals (standard CMOS-IDgic levels 1 DC internally cDnnected tD the phase detector input. With this
coupling may alsD be used. In the external reference mode, output available, the + N counter can be used independent-
nD connection is required tD OSCDut. ly.
ADDRESS INPUTS (Pins 9, 10, 11) - AO, A 1 and A2 are 4>v, 4>R(Pins 16 and 17) - These phase detector outputs
used tD define which latch receives the infDrmatiDn on the can be combined externally for a IDOPerror signal. A single-
data input lines. The addresses refer tD the fDllDwing latches: ended output is also available for this purpose (see PDoutl.
If frequency fy is greater than fR or if the phase of fy is
A2 A1 AO Selected Function DO D1 D2 D3 leading, then error information is provided by 4>y pulsing
0 0 0 Latch 0 +A Bits 0 1 2 3 low. 4>Rremains essentially high.
0 0 1 Latch 1 +A Bits 4 5 6 If the frquency fy is less than fR or if the phase of fy is lag-
0 1 0 Latch 2 + N Bits 0 1 2 3 ging, then error information is provided by 4>Rpulsing low.
0 1 1 Latch 3 + N Bits 4 5 6 7 4>y remains essentially high.
1 0 0 Latch 4 +N Bits B 9 If the frequency of fy = fR and both are in phase, then
1 0 1 Latch 5 Reference Bits 0 1 2 3 both 4>y and 4>Rremain high except for a small minimum
1 1 0 Latch 6 Reference Bits 4 5 6 7 time period when both pulse low in phase.
1 1 1 Latch 7 Reference Bits B 9 10 11
fR (Pin 18) - This is the DUtPUt of the + R counter that is
internally connected to the phase detector input. With this
ST (Pin 12) - When high, this input will enter the data output available, the + R counter can be used independent-
that appears at the DO, 01, 02 and 03 inputs, and when IDW, ly.
PDoUl~veD
RI _-1.-
"R<>-- e
"V0--
I
Fls) = __ 1_
RleS + 1
81 PDout veo
RI
"Ro-- R2
I
"V 0--
e
"'N V K"Kveo
rK:IRl + R21
e
I
NOTE· Sometimes A 1 is split into two senes resistors each A 1 -+- 2. A capacitor Cc IS then placed from the mIdpoint to ground to further filter tbV and
.R. The value for Cc should be such that the corner frequency of this network does not signiflcanu\ affect wN·
DEFINITIONS: N = Total D,vIsion Ratio in feeaback loop

K•• = VDD/4r for PDout
K•• = VDD/2r for "V and "R
Kveo = 2ra1veo
I1Vveo
MC145144 4-8it Data Single Modulus 3 State
MC145145 Bus Input Single Modulus 3 statel2 Output
MC145151 Parallel Input Single Modulus 3 statel2 Output
MC145155 Serial Input Single Modulus 3 statel2 Output
MC145157 Single Modulus 3 statel2 Output
MC145156 Dual Modulus 3 5 tatel2 Output
MC145159 Dual Modulus 3 statel Anal09
FIGURE 2 FIGURE 3
TYPICAL fin MAXIMUM FREQUENCY YS VOO TYPICAL aSCin MAXIMUM FREQUENCY YS VOO
INPUT = 500 mV pIp INPUT = 500 mV pIp
-40"C
2S"C
~ 8S"e-
FIGURE 4 FIGURE 5
TYPICAL fin MAXIMUM FREQUENCY YS VOO TYPICAL aSCin MAXIMUM FREQUENCY YS VOO
INPUT= SQ WAVE 1VOO-VSSI INPUT= SQ WAVE (VOO-VSSI
BV-
/"
/"
V
/"
------ --
---
/" SV
V
./
/" ---- - 3V
30 MHz
fin
--
1
NOTE: To compute total 100 add component due to fin with that due to OSCm.
The features of the MC145146 permit bus operation with a selection of + R values permits a high degree of flexibility in
dedicated wire needed only for the strobe input. In a choosing the reference oscillator frequency. As a result the
microprocessor controlled system this strobe input is access- reference oscillator can frequently be chosen to serve multi-
ed when the phase lock loop is addressed. The remaining ple system functions such as a second local oscillator in a
data and address inputs will directly interface to the receiver design or a microprocessor system clock. Typical
microprocessor's data and address buses. applications that takes advantage of these MC145146
The device architecture allows the user to establish any in- features including the dual modulus capability are shown in
teger reference divide value between 3 and4096. The wide Figures 7, 8 and 9.
c:J4.0 MHz 8 18 15 13
Optional
7 aSCOUl fA fV LD
Loop Error
aSC,n PDou!
Signal
16
<PV Control Voltage
To FM anej AM
Mod 14 Oscillators
6 VDD
Control
4
fin 3
NOTES: 1) For FM: Channel spacing = fA =15 kHz, + A= 160.

For AM: Channel spacing = fA = 1 kHz, -+- R = «xXl.
2) Various channel spacings and reference oscillator frequencies can be chosen since any -+- R value from 3 to 4096 can be established.
31 Data and address lines are inactive and high impedance when pin 12 is low. Their interface with the controller may therefore be
shared with other system functions if desired.
~- - - - -
1:----·
-.}
I
Choice of
I
Ref. Osc.
I
Frequency Receiver
lan-Chip Osc. L.a.
Optionall 443.325- 443.950
MHz
125 kHz Steps 1
Transmitter
Transmitter Signal
Modulation
...• 459.025 - 459.650 MHz
and 15.7 MHz
125 kHz stepsl
Offset
V
+64/65 or + 128/129
V Dual Modulus Prescaler
To Shared
Controller Bus
NOTES: 11 Receiver I.F. = 10.7 MHz. low stde InleCtlon.
2) Duplex operation with 5 MHz receive/transmit separation.
3) fA = 25 kHz, + A chosen to correspond with desired reference oSCillator frequency.
41 Ntotal= 17733 to 17758=NoP+A; N=277, A=5to 30 for P=64.
Receiver
2nd. L.O.
For Use With 33.300 MHz
Aef.Ose. - - - - • External
11.100 MHz 1- - -. ) Phase Detector
IOn-Chip Ose. r (Optionall
Optionall I Receiver First L.O.
825.030-844.980 MHz
130 kHz Steps)
TransmItter Signal
825.030- 844.980 MHz
130 kHz Steps)
V
To Shared
Controller 8us
v-------I
.•. 32/ .•. 33 Dual Modulus Prescaler
NOTES: 1) Aeceiver 1st. I.F. =45 MHz, low side injection; Aeceiver 2nd. I.F. =
11.7 MHz, low side injection.
21 Duplex operation with 45 MHz receive!transmit sepiration.
3) fA = 7.5 kHz, + A .1480.
4) Ntotal= = =
No32 + A 27501 to 28166: N = 859 to 880: A 0 to 31.
5) Only one implementation is shown. Various other configurations and dual modulus prescaling values to + 128/ .•. 129 are possible.
® MOTOROLA

parts from Motorola CMOS. The family includes devices having serial, PARALLEL INPUT PLL
parallel and 4-bit data bus programmable inputs. Options include single- FREQUENCY SYNTHESIZER
The MC145151 is programmed by 14 parallel input-data lines. The
device features consist of a reference oscillator, selectable-reference
divider, digital-phase detector and 14-bit programmable divide-by-N
counter. When combined with a loop f,lter and VCO, the MC145151 can
provide all the remaining functions for a PLL frequency synthesizer
operating up to the device's frequency limit. For higher VCO frequency
operation, a down mixer or a fixed divide prescaler can be used between
the VCO and MC145151.
L SUFFIX P SUFFIX
• General Purpose Applications - CERAMIC PACKAGE PLASTIC PACKAGE
CATV TV Tuning CASE 733 CASE 710
AM/ FM Radios Scanning Receivers
Two-Way Radios Amateur Radio
• Low Power Orain
• > 30 MHz Typical Input Capability @ 5 Vdc
• 8 User Selectable Reference Divider Values - 8, 128, 256, 512
1024, 2048, 2410, 8192
• Lock Detect Signal
• + N Counter Output Available
• Single Modulus/Parallel Programming

• + N Range = 3 to 16383
Linearity
Single Ended !Three-Statel
Double Ended
Note: NO through N13 inputs and inputs

RAO, RA 1 and RA2 have pullup resistors
not shown.
DC Supply Voltage VOO -0.5 to + 10 Vde
Input VOltage. All Inputs Vin -0.5 to VOO +0.5 Vde
DC Current Drain VOO or VSS Pins I 30 mA
Storage Temperature Range Tstg -65 to +150 °C
Tlow 25°C THigh

Charaetaristic Symbol VOO Units
Power Supply Voltage Range VOO - 3 9 3 - 9 3 9 Vde
Output Voltage o Level 3 - 005 - 0 0.05 - 0.05
Vin = VOO or 0 VOL 5 - 0.05 - 0 0.05 - 0.05
9 - 0.05 - 0 0.05 - 0.05
Vde
3 295 - 2.95 3 - 2.95 -
Vin = 0 or VOO 1 Level VOH 5 4.95 - 495 5 - 4.95 -
9 8.95 - 8.95 9 - 8.95 -
Input Voltage o level
Vo = 2.5 or 0.5 3 - 0.9 - 1.35 0.9 - 0.9
Vil
Vo = 4.5 or 0.5 5 - 1.5 - 2.75 1.5 - 1.5
Vo = 8.5 or 1.5 9 - 2.7 - 4.05 2.7 - 2.7 Vde
Vo = 0.5 or 2.5 1 Level 3 2.10 - 2.10 1.65 - 2.10 -
Vo = 0.5 or 4.5 VIH 5 3.5 - 35 2.75 - 3.5 -
Vo = 1.5 or 8.5 9 6.3 - 6.3 4.95 - 6.3 -
VOH = 2.7 3 -0.44 - -0.35 -066 - -0.22 -
VOH = 4.6 IOH 5 -0.64 - -0.51 -0.66 - -0.36 -
VOH = 8.5 9 -1.3 - -10 -13 - -07 - mAde
VOL = 0.3 Sink 3 0.44 - 0.35 0.66 - 0.22 -
VOL = 0.4 IOl 5 0.64 - 051 0.88 - 0.36 -
VOL = 0.5 9 1.3 - 1.0 1.3 - 0.7 -
Input Current Other Inputs
IlL
9 - -60 - -25 -50 - -35
fin.OSCm 9 - ± 15 - ±5 ±1O - ±8 ~Ade
f,n.OSCin 9 - ±15 - ±5 ± 10 - ±8
IIH 9 - - ±O.OOCOl ±0.1 - ± 1.0
Other Inputs ±0.3
Input Capacitance Gm 3-9 - 10 - 6 10 - 10 pF
Quiescent Current 3 - 800 ~ 200 800 - 1600
100 5 - 1200 - 300 1200 - 2400 ~Ade
9 - 1600 - 400 1600 - 3200
Three-State Leakage Current POout Il 9 - ±0.1 - ±00<Xl1 ±0.1 - ±3.0 ~Ade
Thi9h = 85°C
ThiS deVice contains cIrcuitry to protect the inputs agamst damage due to high static VOltages or electrtc fields; however. It IS adVised that normal
precautions be taken to avoid application of any voltage higher than maximum rated voltages to thiS high Impedance circuit. For proper operation It
IS recommended that Vln and Vout be constrained to the range VSS ::s (Vln or Voutl :s voo.
Unused Inputs must always be tied to an appropriate logiC voltage level le.g., either VSS or VOOJ.
Characteristic Symbol Vnn Min Typ Max Units
3 TOO 200
9 - 40 80
3 - 100 200
9 - 40 80
4>R. 4>v with IR in tWH(4)1 5 50 100 150 ns
Phase with tv 9 30 80 130
3 T
Input Rise and Fall Times tTLH 5 - - 4 ~s
OSCin. fin tTHL
EI
9 - - 2
3 40 30 -
Input Pulse Width
tw 5 35 20 - ns
OSCin.1in 9 25 15 -
Tlow 25'C Th;"h

Min Max Min Typ Ma. Min Max
OSCin Input= SO Wave VOO- VSS fmax 5 - 33 - 55 27 - 21 MHz
9 - 35 - 65 35 - 33
Input = Sin Wave 5CX)mV ptp 3 - 11 - 21 10 - 9
fmax 5 - 20 - 34 17 - 15 MHz
9 - 17 - 34 17 - 15
fin Input=Sa Wave VOO-VSS fmax 5 - 19 - 30 15 - 15 MHz
9 - 31 - 52 26 - 22
Input= Sin Wave 500 mV ptp 3 - 10 - 15 7 - 6
fmax 5 - 18 - 31 15 - 15 MHz
9 - 21 - 31 15 - 15
fin (Pin 1) - Input to + N portion of synthesizer. fin is If the frequency fy is less than fR or if the phase of fy is
typically derived from loop YCO and is AC coupled into Pin lagging, then error information is provided by q,R pulsing
9. For larger amplitude signals (standard CMOS Logic levels) low. q,y remains essentially high.
DC coupling may be used. If the frequency of fy = fR and both are in phase, then
both q,y and q,R remain high except for a small minimum
YSS (Pin 2) - Circuit Ground. time period when both pulse low in phase.
YDD (Pin 3) - Positive power supply. tv (Pin 10) - This is the output of the + N counter that is
internally connected to the phase detector input. With this
PDout (Pin 4) - Three-state output of phase detector for output 'available, the + N counter can be used independent-
use as loop error signal. Double-ended outputs are also ly.
available for this purpose (eee q,y and q,RI.
N Inputs (Pins 11 to 20 and 22 to 25) - These inputs pro-
Frequency fy> fR or fy Leading: Negative Pulses
vide the data that is preset into the + N counter when it
Frequency fy < fR or fy Lagging: Positive Pulses
Frequency fy = fR and Phase Coincidence: High- reaches the count of zero. NO is least significant and N13 is
Impedance State. most significant. Pullup resistors ensure that inputs left open
remain at a logic one and require only a SPST switch to alter
RAO, RA 1, RA2 (Pins 5, 6, and 7) - These three inputs data to the zero state.
establish a code defining one of eight possible divide values
for the total reference divider, as defined by the table below: Transmit/Receive (Pin 21) - This input controls the offset
added to the data provided at the N inputs. This is normally
used for offsetting the YCO frequency by an amount equal
Reference Address Total to the IF frequency of the transceiver. This offset is fixed at
Code Divide 856 when T I R is low and gives no offset when T I R is high. A
RA2 RA1 RAO Yalue pull up resistor ensures that no connection will appear as a
0 0 0 8 logic one causing no offset addition.
0 0 1 128
0 1 0 256
0 1 1 512 OSCout, OSCin (Pins 26 and 27) - These pins form an
1 0 0 1024 on-chip reference oscillator when connected to terminals of
1 0 1 2048 an external parallel resonant crystal. Frequency setting
1 1 0 2410 capacitors of appropriate value must be connected from
1 1 1 8192 OSCin to ground and OSCout to ground. OSCin may also
This signal will typically be AC coupled to OSCin, but for
larger amplitude signals (standard CMOS-logic levelsl DC
q,R, q,y (Pins 8 and 9) - These phase detector outputs coupling may also be used. In the external reference mode,
can be combined externally for a loop-error signal. A single- no connection is required to OSCout.
ended output is also available for this purpose Isee PDoutl.
If frequency fy is greater than fR or if the phase of fy is LD (Pin 28) - Lock detector signal. High level when loop
leading, then error information is provided by q,y pulsing is locked (fR, fV of same phase and frequencyl. Pulses low
low. q,R remains essentially high. when loop is out of lock.
Fls) = --'--
A1CS + 1
II BJ Poout VCO
Al
~A<>--
A2
~V<>--
C
NOTE: Sometimes A 1 is split into two series resistors each R 1 .• 2. A capacitor Cc IS then placed from the midpoint to ground to further filter.v and
~A. The value for Cc should be such that the corner frequency of this network does not significantly affect ""N.
DEFINITIONS: N = Total Division Aatlo in feeoback loop

K~ = Voo/4r for Poout
K~ = Voo/2r for ~V and ~A
KVCo = 2r<l.fvco
<l.VVCo
for a typical design wN == t2r/10Hr (at phase detector input)

r
a 1
FIGURE 1
fR
Reference
lOse + Rl
tv
n n n n II
Feedback
(fin ••.. Nl
fl n
U
U ~ I
I I ~
NOTE: The Po output state is equal to either VOO or VSS when active. When not active, the output IS high Impedance and the voltage at that
pin IS determined by the low pass filter capacitor.

MC145144 4-Blt Data Single Modulus 3 State
MC145145 Bus Input Single Modulus 3 state/2 Output
MC145151 Parallel Input Single Modulus 3 state/2 Output
MC145155 Senal Input Single Modulus 3 state/2 Output
MC145157 Single Modulus 3 state/2 Output
MC145156 Dual Modulus 3 state/2 Output
MC145159 Dual Modulus 3 statel Analog
FIGURE 2 FIGURE 3
TYPICAL f-., MAXIMUM FREQUENCY VI VOO TYPICAL OSCin MAXIMUM FREQUENCY VI VOO
INPUT =
500 mV =
INPUT 500 mV
11Hz
50
-4O'C
40 -40'
/ 25'C
30
25'C
85"
II£- 85'C
II
20
V
10
10
FIGURE 4 FIGURE 5
TYPICAL f-., MAXIMUM FREQUENCY VI VOO-VSS TYPICAL OSCin MAXIMUM FREQUENCY VI VOo-VSS
INPUT =SQ WAVE INPUT= sa WAVE
30 MHz
t.
NOTE: To compute IOtallOO add component due to fin with that due to OSCin.
Voltage
Controlled
Oscillator
Transmit 440.0-470.0 MHz

Receive: 418.6-448.6 MHz
125 kHz Steps}
Transmit
IAdds 85610
-=- . N Value}
NOTES:
11 fR '" 4.1667 kHz; • R = 2410; 21.4 MHz low side injection during receive
21 MC145151 CUrlent drain .5 mA for VOO=5 Vdc
3) Frequency values shown are lor the 440- 470 MHz band. Similar implementation applies to the 406- 441 MHz band For 470- 512 MHz. consider reler
ence oscillator frequency X9 lor mixer injection signal 190.3750 MHz}
® MOTOROLA
The MC145152 is one of a family of LSI PLL frequency synthesizer PARALLEL INPUT PLL
parts from Motorola CMOS. The family includes devices having serial, FREQUENCY SYNTHESIZER
EI detector types and choice of reference divider integer values.

The MC145152 is programmed by sixteen parallel inputs. The device
features consist of a reference oscillator, selectable-reference divider,
two output phase detector, 1G-bit programmable divide-by-N counter
and 6-bit programmable + A counter. When combined with a loop filter
and VCO, the MC145152 can provide all the remaining functions for a
PLL frequency synthesizer operating up to the device's frequency limit.
For higher VCO frequency operation, a down mixer 0, a dual modulus 1
L SUFFIX
prescaler can be used between the VCO and MC145152. P SUFFIX
CERAMIC PACKAGE
PLASTIC PACKAGE
CASE 733
CASE 710
• General Purpose Applications -

CATV TV Tuning
AM/FM Radios Scanning Receivers 28
Two-Way Radios Amateur Radio
27
• Low Power Drain 26
• 3.0 to 9.0 Vdc Supply Range 25
• >30 MHz Typical Input Capability @ 5 Vdc 2'
• 8 User Selectable Reference Divider Values - 8, 64, 128,' 23
256,512, 1024, 1160,2048 22
• On- or Off-Chip Reference Oscillator Operation 71
• Lock Detect Signal 20
• Dual Modulus/Parallel Programming 19
• +N Range = 3to 1023,c-A Range=O to 63 t1 18
"
16
15
voooL.
VSSo£-
Note: NO through N9. AO through A5 and

RAO through RA2 have pullup resistors
not shown
MAXIMUM RAn IVoltages Referenced to VSS)
Rating Symbol Valua Unit
DC Supply Voltage VDD -0.5 to + 10 Vdc
Input Voltage, All Inputs Vin - 0.5 to VDD + 0.5 Vdc
DC Current Drain Per. Pin I 10 mA
Storage Temperature Range Tstg -65 to + 150 ·C
TLow 2S·C TH' h

Charaetariatic Symbol VDO Units
Mln Max Min Typ Max Min Max
Power Supply Voltage Range VDD - 3 9 3 - 9 3 9 Vdc
o Level 3 - 0.05 - 0 0.05 - 0.05

Output Voltage
VOL 5 0.05 - 0 0.05 - 0.05
Vin = VDO or 0 9 - 0.05 - 0 0.05 - 0.05
Vdc
3 2.95 - 2.95 3 - 2.95 -
Vin = OorVDD 1 Level VOH 5 4.95 - 4.95 5 - 4.95 -
9 8.95 - 8.95 9 - 8.95 -
Vo =2.5 or 0.5 3 - 0.9 - 1.35 0.9 - 0.9
VIL 1.5 1.5
Vo =4.5 or 0.5 5 - 1.5 - 2.25 -
Vo =8.5 or 1.5 9 - 2.7 - 4.05 2.7 - 2.7 Vdc
Vo = 0.5 or 2.5 1 Level 3 2.10 - 2.10 1.65 - 2.10 -
Vo = 0.5 or 4.5 VIH 5 3.5 - 3.5 2.75 - 3.5 -
Vo = 1.5 or 8.5 9 ~.3 - 6.3 4.95 - 6.3 -
VOH = 2.7 IOH
3 -0.44 - -0.35 -0.66 - -0.22 -
VOH = 4.6 5 -0.64 - -0.51 -0.88 - -0.36 -
VOH = 8.5 9 -1.3 - ~1.0 -1.3 - -0.7 - mAdc
VOL = 0.3 Sink 3 0.44 - 0.35 0.66 - 0.22 -
VOL = 0.4 IOL 5 0.64 - 0.51 0.88 - 0.36 -
VOl = 0.5 9 1.3 - 1.0 1.3 - 0.7 -
VOH = 2.7 3 0.15 - 0.25 0.5 - 0.06 -
VOH = 4.6 IOH 5 0.45 - 0.75 1.5 - 0.23 - mAdc
VOH = 8.5 9 0.75 - 1.25 2.5 - 0.36 -
Input Current Other Inputs IlL 9 - -60 - -25 -50 - -35
fin,OSCin 9 - ±15 - ±5 ±10 - ±8 ,.Ade
fin,OSCin 9 - ±15 - ±5 ±10 - ±8
IIH
Input Capacitance Gin 3-9 - 10 - 6 10 - 10 pF
Quiescent Current 3 - 800 - 200 800 - 1600
IDD 5 - 1200 - 300 1200 - 2400 I'Adc
9 - 1600 - 400 1600 - 3200
3-State Leakage Current PDout IL 9 - ±0.1 - ±O.OOOl ±0.1 - ±3.0 jlAde
NOTE: Tlow = - 4O·C

Thigh = 85·C
This device contains circuitry to protect the inputs against damage due to high static VOltages or electric fields; however. it is advised that normal
precautions be taken to avoid application of any voltage higher than maximum fated voltages to this high impedance circuit. For proper operation it
is recommended that Vin and Vout be constrained to the range VSS :5 (Vin or Vout) :5 VOD.
Unused inputs must always be tied to an appropriate logic voltage level {e.g., either VSS or Vaal.
Chareetorillie Symbol VOO Min Typ Max Un~
3 100 200
9 - 40 80
3 - 100 200
9 - 40 80
3 - 80 180
tPLH 5 - 50 100 ns
Propagation Delay Time 9 - ~ 80
Clock to Modulus Control 3 - 80 160
tpHL 5 - 50 100 ns
9 - ~ 60
.R •• V with IR in lWHI.1 5 50 100 150 ns
Phase with IV 9 ~ ~ 1~
Input Rise And Fall Times

3 - - 5
tTLH
5 - - 4 ,.s
OSCin.lin tTHL 9 - - 2
Input Pulse Width

3 40 ~ -
tw 5 35 20 - ns
OSCin.lin 9 25 15 -
Tiow 25°C T~ah

Chareeterilllc Symbol VOO Un~
Min M.x Min Typ M.x Min M.x
OSCin Input = sa Wave VDD - VSS lmax 5 - 33 - 55 27 - 21 MHz
9 - 35 - 65 35 - 33
Input = Sin Wave 500 mV p - p 3 - 11 - 21 10 - 9
fmax 5 - 20 - 34 17 - 15 MHz
9 - 17 - 34 17 - 15
fin Input = sa W.veVDD - VSS fmax 5 - 19 - ~ 15 - 15 MHz
9 - 31 - 52 26 - ~
Input = Sin Wave 500 mV p - p 3 - 10 - 15 7 - 6
fmax 5 - 18 - 31 15 - 15 MHz
9 - 21 - 31 15 - 15
Tlow = -40°C
Thigh = 85°C
PIN DESCRIPTIONS the beginning of a count cycle and will remain low until the
1;n (Pin 1\ - Input to the positive edge triggered .•.Nand .•.A counter has counted down from its programmed value .
.•.A counters. fin is typically derived from a dual modulus At this time, modulus control goes high and remains high
prescaler and is AC coupled into Pin 1. For larger amplitude until the .•.N counter has counted the rest of the way down
signals (standard CMOS logic levels) DC coupling may be from its programmed value (N - A additional counts since
used. both .•.Nand .•.A are counting down durin~ the first portion
of the cyclel. Modulus control is then set back low, the
counters preset to their respective programmed values, and
grammable divide value (NT) = NoP + A where P and P + 1
represent the dual modulus prescaler divide values respec-
RAO, RA1, RA2 (Pins 4,5, and 6) - These three inputs tively for high,and'!ow modulus control levels; N .the number
establish a code defining one of eight possible divide values programmed into the .•.N counter and A the number pro-
II
"for the total reference divider. The total reference divide grammed into the .•.A counter.
values, including the .•.2 block, are as follows:"
Reference Address N INPUTS (Pins 11 through 20) - The N inputs provide
Total the data that is preset into the'" N counter when it reaches
Code
Divide Value the count of zero. NO is the least significant digit and N9 is
RA2 RAl RAO
the most significant. Pullup resistors ensure that inputs left
0 0 0 8 open remain at a logic one and require only a SPST switch to
0 0 1 64 alter data to the zero state.
0 1 0 128
0 1 1 256
A INPUTS (Pins 23, 21, 22, 24, 25, 10) - The A inputs
1 0 0 512
1 define the number of clock cycles of fin that require a logic
1 0 1024
1 1 0 zer'!' on the modulus control output. See page 8 for explaina-
1160
1 1 2048 tion of dual'modulus prescaling. The A inputs all have inter-
1,
nal pullup resistors that ensure that inputs left open will re-
main at a logic one.
~R, ~V (Pins 7 and 8) - These phase detector outputs
can be combined externally for a loop error signal. OSCout, OSCin (Pins 26 and 27) - These pins form an
If frequency fV is greater than fR or if the phase of fV is on-chip reference oscillator when connected to terminals of
leading, then error information is provided by ~V pulsing an external parallel resonant crystal. Frequency setting
low. ~R remains essentially high. capacitors of appropriate value must be connected from
If the frequency of fV is less than fR or if the phase of fV is OSCin to ground and OSCout to ground. OSCin may also
lagging, then error information is provided by ~R pulsing serve as input for an externally-generated reference signal.
low. ~V remains essentially high. This signal will typically be AC coupled to OSCin, but for
If the frequency 'of fV = fR and both are in phase, then larger amplitude signals (standard CMOS-logic levels) DC
both ~V and ~R remain high except for a small minimum coupling may also be used. In the external reference mode,
time period when both pulse low in phase. no connection is required to OSCout.
MODULUS CONTROL (Pin 9) - Signal generated by the LD (Pin 281 - Lock detector signal. High level when loop
on-chip control logic circuitry for controlling an external dual is locked (fR, fV of same phase and frequencyl. Pulses low
modulus prescaler. The modulus control level will be low at when loop is out of lock.
c
I
NOTE: Sometimes Rl is split into two series resistors each R1 + 2 A capacitor Cc is then placed from the midpoint to ground to further
filter oV and oR. The value for Cc should be such that the corner frequency of this network does not significantly affect "'N.
DEFINITIONS: N = Total Division Retio in feedback loop

Kp = VDD/2ll
KVCO = 2llMVCO
dVVCO
for a typical design "'N '" (2ll/1 01 fr (at phase detector input)
~'" ,
I~e~:n~e} Jl... n... n n _
IV
Feedback
(fin ..•.. Nl

MC145144 4-Bit Data Single Modulus 3 State
MC145146 Format Dual Modulus 3 State/2 Output
MC145151 Parallel Input Single Modulus 3 State/2 Output
MC145155 Serial Input Single Modulus 3State/2 Output
MC145156 Format Dual Modulus 3State/2 Output
MC145157 Single Modulus 3State/2 Output
MC145158 Dual Modulus 3State/2 Output
MC145159 Dual Modulus 3 S tatel Analog
FIGURE 2 FIGURE 3
TYPICAL till MAXIMUM FREQUENCY VI VOO TYPICAL OSCin MAXIMUM FREQUENCY VI VOO
INPUT = 500 mV INPUT = 500 mV
-4Q'C
-4Q'C
/ 25'C
25'C
85'
f? 85'C
II
FIGURE 4 FIGURE 5
TYPICAL fJn MAXIMUM FREOUENCY VI VOO-VSS TYPICAL OSCin MAXIMUM FREQUENCY VI VOo-VSS
INPUT =
SQ WAVE =
INPUT SQ WAVE
10 20 30 11Hz
f.
NOTE: To compute tolel 100 add component due to fin with that due to OSCin.
For the maximum frequency into the prescaler (Fvco max),
the value used for P must be large enough such that:
The technique of dual modulus prescaling is well estab- A. Fvco max divided by P may not exceed the frequency
lished as a method of achieving high performance frequency capability of Pin I of the MC145152.
synthesizer operation at high frequencies. Basically, the ap- B. The period of Fvco divided by P must be greater than
proach allows relatively low-frequency programmable the sum of the times:
counters to be used as high-frequency programmahl~ a. Propagation delay through the dual modulus
counters with speed capability of several hundred MHz. This prescaler.
is possible without the sacrifice in system resolution and per- b. Prescaler setup or release time relative to its
formance that would otherwise result if a fixed (single modulus control signal.
modulus) divider was used for the prescaler. c. Propagation time from fin to the modulus control
In dual modulus prescaling, the lower speed counters output for the MC145152.
must be uniquely configured. Special control logic is A sometimes useful simplification in the MC145152 pro-
necessary to select the divide value P or P + 1 in the prescaler gramming code can be achieved by choosing the values for
for the required amount of time (see modulus control defini- P of 8, 16. 32 or 64. For these cases, the desired value for
tionl. The MC145152 contains this feature and can be used Ntotal will result when Ntotal in binary is used as the pro-
with a variety of dual modulus prescalers to allow speed, gram code to the + Nand + A counters treated in the follow-
complexity and cost to be tailored to the system re- ing manner:
quirements. Prescalers having P, P + I divide values in the
A. Assume the + A counter contains "b" bits where 2b
range of + 3/ + 4 to + 64/ + 65 can be controlled by the
= P.
MC145152. B. Always program all higher order + A counter bits
Several dual modulus prescaler approaches suitable for above "b" to zero.
use with the MC145152 are given in Figure 7. The ap- C. Assume the + N counter and the + A counter (with all
proaches range from the low cost + 15/ + 16, MC3393P the higher order bits above "b" ignored I combined in-
device capable of system speeds in excess of 100 MHz to the to a single binary counter of 10+ b bits in length. The
MC12000 series having capabilities extending to greater than M SB of this "hypothetical" counter is to correspond
500 MHz. Synthesizers featuring the MC145152 and dual to the MSB of + N and the LSB is to correspond to
modulus prescaling are shown in Figures 8 and 9 for two the LSB of + A. The system divide value, Ntotal, now
typical applications. results when the value of Ntotal in binary is used to
program the "New" 10+ b bit counter.
DESIGN GUIDELINES APPLICABLE

TO THE MC145152
The system total divide value (Ntotal) will be dictated by
the application. i.e.
MCI2009 +5/+6 440 MHz
MCI2011 +8/+9 500 MHz
MCI2013 +10/+11 500 MHz
°MC3393 + 15/+16 140 MHz
N is the number programmed into the + N counter; A is

the number programmed into the + A counter. P and P + I
are the two selectable divide ratios available in the two
modulus prescalers. To have a range of Ntotal values in se-
quence, the + A counter is programmed from zero through Modulus
P - I for a particular valu~ N in the divide N counter. N is Control
then incremented to N + I and the + A is sequenced from
zero through P- I again.
There are minimum and maximum values that can be
achieved for Ntotal. These values are a function of P and the ~
size of the + Nand + A counters. The constraint N ~ A
always applies. If Amax = P - I then Nmin ~ P - 1. Then
Ntotal- min = (P - II P + A or lP-lI P since A is free to
assume the value of zero.
To maximize system frequency capability, the dual modulus

prescaler's output must go from low to high after e~~h group
of P or P + I input cycles. The prescaler should divide by P
when its modulus control line is high and by P + I when its
modulus control is low.
NOTES:
= =
,. fR 50 kHz, + R 64; 22.0 MHz low side injection; NTOTAL 1720 - = 1919.
2. Using 22.0 MHz for the receiver I.F. demonstrates how the choice of I.F. value can sometimes reduce the number of +- N bits that must be
programmed. Using the more common 21.4 MHz I.F. would require six rather than four +- N programming inputs.
FIGURE 9 - SYNTHESIZER FOR LAND MOBILE RADIO UriF BAND

COVERAGE DEMONSTRATES USE OF THE MCl46152
IN SYSTEMS OPERATING TO SEVERAL HUNDRED MHz
Ref.Ose.
12.8 MHz
(On-Chip Ose.
Optional)
NOTES:
,. NTOT AL = N°64 +A = 32480 to 37600; N ~ 507 to 587; A = 0 to 63.
2. fR = 12.5 kHz, + R = 1024 (code 1011.
3. The prescaling approach can be chosen for the application to enhance economy 8.g . single chip MC3393P to approximately 100 MHz.
MC12011 or MC12013 with dual flip flop to approximately 250 MHz.
MC12011 or MC12013 with MC10178 to over 600 MHz.
® MOTOROLA
The MC145155 is one of a family of LSI PLL Frequency synthesizer

parts from Motorola CMOS. The family Includes devices having serial,
SERIAL INPUT PLL
II
The MC145155 is programmed by a clocked, serial input, 16-bit data
steam. The device features consist of a reference oscillator, selectable- FREQUENCY SYNTHESIZER
reference divider, digital-phase detector, 14-bit programmable divide-
by-N counter and the necessary shift register and latch circuitry for ac-
cepting the serial input data. When combined with a loop filter and
VCO, the MC145155 can provide all the remaining functions for a PLL
frequency synthesizer operating up to the device's frequency limit. For
higher VCO frequency operation, a down mixer or a fixed divide
~~
prescaler can be used between the VCO and MC145155.
• General Purpose Applications -

,~r\f u ijU ,1;Rltnp t
CATV TV Tuning 1
AM/ FM Radios Scanning Receivers L SUFFIX P SUFFIX
Two-Way Radios Amateur Radio CERAMIC PACKAGE PLASTIC PACKAGE
CASE 726 CASE 707
• Low Power Drain
• >3J MHz Typical Input Capability @ 5 Vdc
• 8 User Selectable Reference Divider Values - 16, 512, 1024, 2048,
3668, 4096, 6144, 8192
• On- or Off-Chip Reference Oscillator Operation with Buffered Output
• Two Open-Drain Switch Outputs
• Single Modulus/Serial Programming
• + N Range = 3 to 16383
Linearity
Single Ended !Three-Statel
Double Ended
OSCOU! 16
aSCin
voooi--
v 02--.
ss
o tages e erence to '~~i
R.ting Symbol V.lue Un~

DC Supply Voltage VDD -0.5 to + 10 Vdc
Input Voltage, All Inputs Vin 0.5 to VDD + 0.5 Vdc
DC Current Drain VDD or VSS Pins I ~ mA
Storage Temperature Range Tstg -65to +150 °C
TLow 2S°C TH' h

Characteriatic Symbol VDD UnM
Min M •• Min Typ M •• Min M ••
Power Supply Voltage Range VDD - 3 9 3 - 9 3 9 Vdc
3 - 0.05 - 0 005 - 0.05
Output.Voltage o Level 5 0.05 - 0 0.05 - 0.05
VOL
Vin = VDD or 0
9 - 0.05 - 0 0.05 - 0.05
Vdc
3 2.95 - 2.95 3 - 2.95 -
Vin = OorVDD 1 Level VOH 5 4.95 - 4.95 5 - 495 -
9 8.95 - 8.95 9 - 8.95 -
Input Voltago o Level
Va = 2.5 or 0.5
VIL
3 - 0.9 - 1.35 0.9 - 0.9
Va = 4.5 or 0.5 5 - 1.5 - 2.25 1.5 - 1.5
Va = 8.5 or 1.5 9 - 2.7 - 4.05 2.7 - 2.7 Vdc
Va = 0.5 or 2.5 1 Level 3 2.10 - 2.10 1.65 - 2.10 -
Va = 0.5 or 4.5 VIH. 5 3.5 - 35 2.75 - 3.5 -
Va = 1.5 or 8.5 9 63 - 6.3 4.95 - 6.3 -
Reverse Breakdown Voltage SW1, SW2 V8DSO 3-9 15 - 15 24 - 15 - V
VOH = 2.7 3 -0.44 - -0.35 -0.66 - -0.22 -
IOH
VOH = 4.6 5 -0.64 - -0.51 -0.88 - -0.36 -
VOH = 8.5 9 -1.3 - -1.0 -1.3 - -0.7 - mAde
VOL = 0.3 Sink 3 0.44 - 0.35 0.66 - 0.22 -

VOL = 0.4 IOL 5 0.64 - 0.51 0.88 - 0.36 -
VOL = 0.5 9 1.3 - 1.0 1.3 - 0.7 -
Output Current SW1, SW2 Sink
VOL = 0.3 3 0.48 - 0.8 1.6 - 0.24 -
mA
VOL = 0.4 10L 5 0.90 - 1.5 3 - 0.45 -
VOl = 0.5 9 2.1 - 3.5 7 - 1.1 -
Input Current Other Inputs 9 - ±0.3 - ±0.00001 ±0.1 - ± 1.0
Enable IlL 9 - -110 - - 50 -100 - -40
fin, OSCin 9 - ±15 - ±5 ±10 - ±8 ,.Ade
fin, OSCin 9 - ±15 - ±5 ±10 - ±8
IIH -
Other Inputs 9 - ±0.3 - ±0.00001 ±0.1 ±1.0
Output Capacitance Caut 3-9 - 10 - 6 10 - 10 pF
3 - 900 - 200 900 1600
Quiescent Current 100 5 - 1200 - 300 1200 - 2400
~Ade
9 - 1600 - 400 1600 - 3200
3-S18te Leakage Current SW1, SW2, PDout IL 9 - ±0.1 - ±0.0001 ±01 - ±3.0 ~Adc

Thigh = 85°C
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than maximum rated VOltages to this high impedance circuit. For proper operation it
is recommended that Vin and Vout be constrained to the range VSS S (Vin or Vout) S VOO.
Unused inputs must always be tied to an appropriate logic VOltage level {e.g., either VSS or VODL
Characteristic Symbol Voo Min Typ Max Units
3 - 100 200
9 - 40 9J
3 - 100 200
9 - 40 9J
3 - 70 140
tpLH 5 - 50 100 ns
Propagation Delay Time 9 - 40 9J
Enable to SW1, SW2 3 - 70 140
tPHL 5 - 50 100 ns
9 - 40 9J
S~tup Times 3 - 10 40
Data To Clock tsu 5 - 4 35 ns
9 - 0 30
3 - 30 50
Enable To Clock tsu 5 - 20 40 ns
9 - 20 40
Hold Time 3 - 10 40
Data To Clock th 5 - 4 35 ns
9 - 0 30
<l>R,<l>Vwith fR in tWHI<I» 5 50 100 150 ns
Phase With tv 9 30 9J 130
3 - - 5
DSCin, tin
tTLH
tTHL
5 - - 4 ,.s
9 - - 2
3 40 30 -
Input Pulse Width
OSCin, fin, Clock
tw 5 35 20 - ns
9 25 15 -
Tiow 25°C Th'oh

Min Max Min Typ Ma. Min Max
Operating FreQuency 3 - 17 - 27 14 - 12
OSCin Input = SaWaveVDD - VSS fmax 5 - 33 - 56 27 - 21 MHz
9 - 35 - 65 35 - 33
Input = Sin Wave 500 mVp-p 3 - 11 - 21 10 - 9
fmax 5 - 20 - 34 17 - 15 MHz
9 - 17 - 34 17 - 15
fin Input = SO Wave VDD - VSS fmax 5 - 19 - 30 15 - 15 MHz
9 - 31 - 52 26 - 22
Input = Sin Wave 500 mV p-p 3 - 10 - 15 7 - 6
fmax 5 - 18 - 31 15 - 15 MHz
9 - 21 - 31 15 - 15
Tlow = -40°C
Thigh = 85°C
RAO, RA1, RA2 (Pins 18, 1, and 2) - These three inputs CLOCK, DATA (Pins to and 11) - Shift register clock and
establish a code defining one of eight possible divide values data input. Each low-to-high transition clocks one bit into
for the total reference divider, as defined by the table below: the on-chip 16-bit shift register. The data is presented on the
DATA input at the time of the positive clock transition. The
DATA input provides programming information for the
14-bit + N counter and the two switch signals SW1 and
Reference Address Total SW2. The entry format is as follows:
Code Divide
RA2 RAl RAO Value
0
0
0
0
0
1
0
0
1
16
512
1024
i4
co
+ N Counter Bits -
co
(f) (f)
0 1 1 2048
...J
:2: '"~ ~
1 0 0 3668 z zof (f) (f)
of
1 0 1 4096
1
1
1
1
0
1
6144
8192
tLast Data Bit in IBit No. 161
J
4>v, 4>R(Pins 3 and 4) - These phase detector outputs
can be combiMd externally for a loop error signal. A single- ENABLE (Pin 12) - When high ("'''1 trartsfers contents of
ended output is also available for this purpose Isee POout) .. the shift register into the latches, and to the programmable
If frequency fV is greater than fR or if the phase of fV is counter inputs, and the switch outputs SW1 and SW2.
leading, then error information is provided by 4>v pulsing When low ("0") inhibits the above action and thus allows
low. 4>Rremains essentially high. changes to be made in the shift register data without affect-
If the frequency fV is less than fRor if the phase of fV is ing the counter programming and switch outputs. An on-
lagging, then error information is provided by 4>Rpulsing chip pull-up establishes a continuously high level for
low. 4>Vremains essentially high. . ENABLE when no external signal is applied to Pin 12.
If the frequency of fV = fR and both are in phase, then
both 4>v and 4>Rremain high except for a small minimum
time period when both pulse low in phase. SW1, SW2 (Pins 13 and 14) - SW1 and SW2 provide
latched open drain outputs corresponding to data bits
numbers one and two. These will typically be used for band
switch functions. A logic one will cause the output to
PDout (Pin 6) - Three state output of phase detector for assume a high-impedance state, while a logic zero will cause
use as loop error signal. Double-entied outputs are also an output logic zero.
available for this purpose (see 4>v and 4>R).
Frequency fV > fR or fV Leading: Negative Pulses.
Frequency fV < fR or fV Lagging: Positive Pulses. REFout (Pin 15) - Buffered output of on-chip reference
Frequency fV = fR and Phase Coincidence: High-- oscillator or externally provided reference-input signal.
Impedance State.
aSCout, aSCin (Pins 16 and 17) - These pins form an

on-chip reference oscillator when connected to terminals of
LD (Pin 81 - Lock detector signal. High level when loop is an external parallel resonant crystal. Frequency setting
locked (fR, fV of same phase and frequency). Pulses low capacitors of appropriate value must be connected from
when loop is out of lock. OSCin to ground and OSCout to ground. OSCin may also
1;n (Pin 9) - Input to + N portion of synthesizer. fin is This signal will typically be AC coupled to OSCin, but for
typically derived from loop VCO and is AC coupled into Pin larger amplitude signals (standard CMOS-logic levels) DC
9. For larger amplitude signals (standard CMOS Logic levelsl coupling may also be used. In the external reference mode,
DC coupling may be used. no connection is required to OSCout.
PDout~VCD
Al _...L
~Ao-- C
~Vo--
I
Fls) = --'--
A'CS + 1
Bl PDou1 VCD
Rl
~Ao--
A2
~Vo--
C
I
-
C
I
NOTE: Sometimes Rl is split into two series resistors each Rl +2. A capacitor Cc is then placed from the mtdpoint to ground to further filter.v and
~R· The value for Cc should be such that the corner frequency of this netwo", does not significantly affect "'N·
DEFINITIONS: N = Total Division Aatio in feedback loop

K~ = VDD/4 •• for PDout
K~ = VDD/2 •• for ~V and ~A
KVCD = 2••AfVCD
AVVCO
for a typical design "'N •• 12,,/1 01 Ir (at phase detector input)

r •• ,
MC145144 4-81t Data Single Modulus 3 State
MC145145 Bus Input Single Modulus 3 State/2 Output
MC145151 Parallel Input Single Modulus 3 State/2 Output
MC145155 Serial Input Single Modulus 3 State/2 Output
MC145157 Single Modulus 3 State/2 Output
MC145159 Dual Modulus 3 Statel Analog
FIGURE 2 FIGURE 3
TYPICAL fin MAXIMUM FREQUENCY va VOO TYPICAL OSCin MAXIMUM FREQUENCY va VOO
INPUT =
500 mV INPUT = 500 mV
MHz
50
-4O'C
40 -4O'C
2S'C
rv
~ 2S'C
30 85'
8S'C
20
'/
II 10
FIGURE 4 FIGURE 5
TYPICAL fin MAXIMUM FREQUENCY va VOO-VSS TYPICAL OSCin MAXIMUM FREQUENCY va VOo-VSS
INPUT = SQ WAVE INPUT = SQ WAVE
FIGURE 8
TYPICAL 100 va FREQUENCY
30 MHz
t"
NOTE: To compute total 'DO add component due to fin with that due to OSCin.
UHFI
VHF
Tuner
Or
CATV
Front
End
o C
a I
t 0
a c
k
® MOTOROLA

parts from Motorola CMOS. The family includes devices having serial,
The MC145156 is programmed by a clocked, serial input, 19-bit data
SERIAL INPUT PLL
II stream. The device features consist of a reference oscillator, selectable- FREQUENCY SYNTHESIZER
reference divider, digital-phase detector, 10-bit programmable divide-
by-N counter, 7-bit programmable'" A counter and the necessary shift
,-~
register and latch circuitry for accepting the serial input data. When
combined with a loop filter and VCO, the MC145156 can provide all the
remaining functions for a PLL frequency synthesizer operating up to the
device's frequency limit. For higher VCO frequency operation; a down
mixer or a dual modulus prescaler can be used between the VCO and
MC145156.
• General Purpose Applications - 1 1
CATV TV Tuning P SUFFIX
L SUFFIX
AM/ FM Radios Scanning Receivers CERAMICPACKAGE PLASTICPACKAGE
Two-Way Radios Amateur Radio CASE 732 CASE 738
• Low Power Drain
• >30 MHz Typical Input Capability @ 5 Vdc
• 8 User Selectable Reference Divider Values - 8, 64, 128, 256,
640 1000, 1024, 2048 RAl RAO
• On- or Off-Chip Reference Oscillator Operation with Buffered Output RA2 OSCin
• Lock Detect Signal ~V OSCOU!
• Two Open-Drain Switch Outputs ~R REFout
• Dual Modulus/ Serial Programming VDD Test
•.•. N Range = 3to1023,.,.A Range=Oto 127 PDout SW2
• "Linearized" Digital Phase Detector Enhances Transfer Function VSS SWl

Linearity Mod Control Enable
• Two Error Signal Ootions - LD Data
Single Ended (Three-State) fin Clock
Double Ended
REFout
Modul<JS
Control
tages e erenced to VSSI
RatIng Symbol Value Un~
DC Supply Voltage VDD -0.5 to + 10 Vde
Input Voltage, All Inputs Vin 0.5 to VDD + 0.5 Vde
DC Current Drain VDD or VSS Pins I 3J mA
Storage Temperature Range Tstg -60 to +150 ·C
TLow 2S·C TH' h

Chareeterill1ie Symbol VDD UnM
Min Max Min Typ Mex Min Max
Power Supply Voltage Range VDD - 3 9 3 - g 3 9 Vde
Voltage a Level 3 - 0.05 a 0.05 0.05

••••UlpU(
= VOL 5 0.05 - a 0.05 - 0.05

Vin VDDorO 9 - 0.05 - a 0.05 - 0.05
Vde
3 2.95 - 2.95 3 - 2.95 -
Vin = OorVOD 1 Level VOH 5 4.95 - 4.95 5 - 495 -
9 8.95 - 8.95 9 - 8.95 -
Input Voltage a Level
Vo =
2.5 or 0.5
VIL
3 - 0.9 - 1.35 0.9 - O.g
Vo =
4.5 or 0.5 5 - 1.5 - 2.75 1.5 - 1.5
Vo =
8.5 or 1.5 g - 2.7 - 4.05 2.7 - 2.7 Vdc
Vo = 0.5 or 2.5 1 Level 3 2.10 - 2.10 1.65 - 2.10 -
Vo = 0.5 or 4.5 VIH 5 3.5 - 3.5 2.75 - 3.5 -
Vo = 1.5 or 8.5 9 6.3 - 6.3 4.95 - 6.3 -
Reverse Breakdown Voltage SW1. SW2 V80S0 3-9 15 15 24 15 V
-
VOH = 2.7 IOH
3 -0.44 - -035 -066 - -0 22 -
VOH = 4.6 5 -064 - -0.51 -0.88 - -0.36 -
VOH = 8.5 9 -1.3 - -1.0 -1.3 - -0.7 - mAde
VOL = 0.3 Sink 3 0.44 - 0.35 0.66 - 0.22 -
VOL = 0.4 IOL 5 0.64 - 0.51 0.88 - 0.36 -
VOL = 0.5 9 1.3 - 1.0 1.3 - 0.7 -
VOH = 2.7 3 0.15 - 0.25 0.5 - 0.08 -
VOH = 4.6 IOH 5 0.45 - 0.75 1.5 - 0.23 - mAde
VOH = 8.5 9 0.75 - 1.25 2.5 - 0.38 -
Output Current SW1. SW2, MC>dulus Control
VOL = 0.3 Sink 3 0.48 - 0.8 1.6 - 0.24 -
VOL = 0.4 IOL 5 0.90 - 1.5 3 - 0.45 - mA
VOL = 0.5 9 2.10 - 3.5 7 - 1.05 -
--
Input Current Other· Inputs 9 - ±O.3 - ±0.00001 -±0.1 - ± 1.0
Enable IlL 9 - -110 - -50 -100 - -40
fin.OSCin 9 - ±15 - ±5 ±10 - ±8 pAde
fin,OSCin
IIH
9 - ±15 - ±5 ±1O - ±8
Other Inputs 9 - ±0.3 - ±0.OOOO1 ±0.1 - ± 1.0
Input Capeeitance (in 3-9 - 10 - 6 10 - 10 pF
Output Capeeitanee
Cnu'
3-g - 10 - 6 10 - 10 pF
J 900 200 900 1600
Quiescent Current 100 5 - 1200 - 3JO 1200 - 2400 pAde
9 - 1600 - 400 1600 - 3200
3-State Leakage Current PDout IL 9 - ±0.1 - ±0.OOO1 ±0.1 - ±3.0 pAde
NOTE: Tlow = - 4O·C

Thigh - 85·C
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it
i~ recommended that Vin and Vout be constrained to the range VSS s (Vin or Vout) s VOD.
Unused inputs must always be tied to an appropriate logic VOltage level le.g .• either VSS or VOOI.
Characteristic Symbol Voo Min Typ MIx Unitl
3 - 100 200
Output Rise Time ITLH 5 - 50 100 ns
9 - 40 BO
3 - 100 200
Outpul Fall Time ITHL 5 - 50 100 ns
9 - 40 BO
3 - 70 140
IPLH 5 - 50 100 ns
Propagation Delay Time 9 - 40 BO
Enable 10 SW1. SW2 3 - 70 140
IPHL 5 - 50 100 ns
9 - 40 BO
3 - BO 1eo
IPLH 5 - 50 100 ns
Propagation Delay Time 9 - ~ eo
Clock 10 Modulus Conlrol 3 - BO 1eo
tpHL 5 - 50 100 ns
9 - ~ eo
Setup Times 3 10 40
Data To Clock Isu 5 - 4 35 ns
9 - 0 ~
3 - ~ 50
Enable To Clock Isu 5 - 20 40 ns
9 - 20 40
Hold Time 3 10 40
Data To Clock th 5 - 4 35 ns
9 - 0 ~
.R •• V with fR in lWHI.' 5 50 100 150 ns
Phase With 'V 9 ~ BO 1~

3 - - 5
tTLH
5 - - 4 p.S
oscin. 'in tTHL 9 - - 2
Input Pulse Width

3 40 ~ -
tw 5 35 20 - ns
OSCin. 'in' Clock 9 25 15 -
Tiow 25"<: T~lgh

--
Chel'llCl8rialk: Symbol VOO Unitl
Min Max Min Tvo MIX Min MIX
Operlting Frequencv 3 - 17 - 27 14 - 12
OSCin Input ~ sa Wave VDD - VSS fmax 5 - 33 - 56 27 - 21 MHz
9 - 35 - 66 35 - 33
Input = Sin Wave 500 mVp-j) 3 - 11 - 21 10 - 9
fmax 5 - 20 - 34 17 - 15 MHz
9 - 17 - 34 17 - 15
Operating Frequencv 3 - 9 - 15 8 - 7
fin Input ~ sa Wave VDD - VSS fmax 5 - 19 - ~ 15 - 15 MHz
9 - 31 - 52 26 - 22
Input ~ Sin Wave 500 mVl>-p 3 - 10 - 15 7 - 6
fmax 5 - 18 - 31 15 - 15 MHz
9 - 21 - 31 15 - 15
Tiow. -40°C
Thigh ~ 85°C
PIN DESCRIPTIONS LD (Pin 9) - Lock detector signal. High level when loop is
RAO, RA1, RA2 (Pins 20, 1, and 2) - These three inputs locked (fR, fV of same phase and frequency). Pulses low
establish a code defining one of eight possible divide values when loop is out of lock.
for the total reference divider, as defined by the table below:
1;n (Pin 101 - Input to the positive edge triggers .•.Nand
Reference Address .•.A counters. fin is typically derived from a dual modulus
Total prescaler and is AC coupled into Pin 10. For larger amplitude
Code
Divide Value signals (standard CMOS logic levelsl DC coupling may be
RA2 RAl RAO
used.
0 0 0 8
0 0 1 64
CLOCK, DATA (Pins 11 and 12) - Shift register clock and
0 1 0 128 data input. Each low-to-high transition clocks one bit into
,
0
0
1
0
1 256
640
the on-chip 19-bit shift register. The data is presented on the
DATA input at the timEl of the positive clock transition. The
DATA input provides programming information for the
1 0 1 1000
lG-bit .•. N counter, the 7-bit .•.A counter and the two
1 1 0 1024
switch signals SWl and SW2. The entry format is as
1 1 1 2048 follows:
4Jv, 4JR (Pins 3 and 4) - These phase detector outputs

can be combined externally for a loop error signal. A single- alal
al al
ended output is also available for this purpose Isee PDoutl. Ul UlUl UlN~
If frequency fV is greater than fR or if the phase of fV is
....I
<{
::;;:....1
::;;: ~~
<{z ZUlUl
leading, then error information is provided by 4JV pulsing + + + +
low. 4JRremains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by 4JR pulsing
tLast Data Bit in IBit No. 191
First Data Bit in (Bit No. 1)
)1
low. 4Jv remains essentially high.
If the frequency of fV =' fR and both are in phase, then
both 4Jv and 4JR remain high except for a small minimum ENABLE (Pin 13) - When high ("1 ") transfers contents of
time period when both pulse low in phase. the shift register into the latches, and to the programmable
counter inputs, and the switch outputs SWl and SW2.
When low 1"0") inhibits the above action and thus allows
changes to be made in the shift register data without affect-
PDout (Pin 6) - Three state output of phase detector for ing the counter programming and switch outputs. An on-
use as loop error signal. Double-ended outputs are also chip pull-up establishes a continuously high level for
available for this purpose (see 4JVand 4JRl. ENABLE when no external signal is applied to Pin 13.
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses SW1, SW2 (Pins 14 and 15) - SWl and SW2 provide
Frequency fV = fR and Phase Coincidence: High- latched open drain outputs corresponding to data bits
Impedance State numbers one and two. These will typically be used for band
switch functions. A logic one will cause the output to
assume a high-impedance state, while a logic zero will cause
an output logic zero.
MODULUS CONTROL (Pin 81 - Signal generated by the
on-chip control logic circuitry for controlling an external dual TEST (Pin 16) - Used in manufacturing. Must be left open
modulus prescaler. The modulus control level will be low at or tied to VSS.
the beginning of a count cycle and will remain low until the
.•.A counter has counted down from its programmed value. REFout (Pin 17) - Buffered output of on-chip reference
At this time, modulus control goes high and remains high oscillato~ or externally provided reference-input signal.
until the'" N counter has counted the rest of the way down
from its programmed value IN - A additional counts since OSCout, OSCin (Pins 18 and 19) - These pins form an
both .•.Nand .•.A are counting down during the first portion on-chip reference oscillator when connected to terminals of
of the cyclel. Modulus control is then set back low, the an external parallel resonant crystal. Frequency setting
counters preset to their respective programmed values, and capacitors of appropriate value must be connected from
the above sequence repeated. This provides for a total pro- OSCin to ground and OSCout to ground. OSCin may also
grammable divide value 1NT) = N. P + A where P and P + serve as input for an externally-generated reference signal.
, represent the dual modulus prescaler divide values respec- This signal will typically be AC coupled to OSCin, but for
tively for high and low modulus control levels; N the number larger amplitude signals (standard CMOS-logic levels) DC
programmed into the .•.N counter and A the number pro- coupling may also be used. In the external reference mode,
grammed into the .•.A counter. no connection is required to OSCout.
PDout~Veo
Al _...L
4>AC>-- e
4>VO---
I_
- 1
Fls)=---
AleS + 1
BI PDout veo
Al
4>AO---
A2
4>vo---
e
e
I
NOTE: Sometimes A1 is split into two series resistors each Al + 2. A capacitor ee is then placed from toe midpoint to ground to further filter.vand
4>A· The value for ee should be such that the corner frequency of this network does not significantly affect "'N.
DEFINITIONS: N = Total Division Aatio in feeoback loop

K4> = VDD/4 •. for PDcut
K4> = VDD/2 •. for.v and 4>A
Kveo = 2dtveo
l1.Vveo
for a typical design "'N lIE 12nl1 01 fr {at phase detector input!
r •• 1
FIGURE 1
IR
Reference
(Ose + RI
IV
_n_n~n_n_
Feedback
Ifin + NI
_Il_n--u~_-
I
~
NOTE: The Po output state is equal to either VOO or VSS when active. When not active, the output is high impedance and the voltage at that
pin is determined by the low pass filter capacitor.

MC145151 Parallel Input Single Modulus '3 State/2 Output
MC145155 Serial Input Single Modulus 3 Statel2 Output
MC145158 Dual Modulus 3 State/2 Output
MC145159 Dual Modulus 3 Statel Analo9
FIGURE 2 AGURE3
TYPICAL fJn MAXIMUM FREQUENCY VI VOO TYPICAL OSCin MAXIMUM FREQUENCY VI VOO
INPUT = 500 mV INPUT= 500 mV
-4Q°C
/: 2SoC ~
-4Q°C-
2SoC
8SOC-
f£- 8SoC
V
V
FIGURE 4 FIGURE 5
TYPICAL fin MAXIMUM FREQUENCY VI VOo-VSS TYPICAL OSCin MAXIMUM FREQUENCY VI VOO-VSS
INPUT = SQ WAVE INPUT = SQ WAVE
30 11Hz
fll
NOTE: To compute 10181100 add componenl due 10 lin wilh lhal due 10 OSCin.
For the maximum frequency into the prescaler (Fvco max) ,
The technique of dual modulus prescaling is well estab- A. Fvco max divided by P may not exceed the frequency
lished as a method of achieving high performance frequency capability of Pin 10 of the MC145156.
synthesizer operation at high frequencies. Basically, the ap- B. The period of Fvco, divided by P,must be greater than
proach allows relatively low-frequency programmable the sum of the times:
counters to be used as high-frequency programmable a. Propagation delay through the dual modulus
counters with speed capability of several hundred MHz. This prescaler.
is possible without the sacrifice in system resolution and per- b. Prescaler setup or release time relative to its
formance that would otherwise result if a fixed (single modulus control signal.
modulus) divider was used for the prescaler. c. Propagation time from fin to the modulus control
In dual modulus prescaling, the lower speed counters output for the MC145156.
must be uniquely cpnfigured. Special control logic is
A sometimes useful simplification in the MC145156 pro-
necessary to select the divide value P or P + 1 in the prescaler
gramming code can be achieved by choosing the values for
for the required amount of time (see modulus control defini-
P of 8, 16, 32, 64 or 128. For these cases, the desired value
tion). The MC145156 contains this feature and can be used
for Ntotal will result when Ntotal in binary is used as the pro-
with a variety of dual modulus prescalers to allow speed,
gram code to the + Nand + A counters treated in the
complexity and cost to be tailored to the system re-
following manner:
quirements. Prescalers having P, P + 1 divide values in the
range of + 3/ + 4 to + 128/ + 129 can be controlled by the A. Assume the + A counter contains "b" bits where 2b
MC145156 = P.
B. Always program all higher order + A counter bits
Several dual modulus prescaler approaches suitable for
above "b" to zero.
use with the MC145156 are given in Figure 7. The ap-
C. Assume the + N counter and the + A counter (with all
proaches range from the low cost + 15/ + 16, MC3393P
the higher order bits above "b" ignored) combined in-
device capable of system speeds in excess of 100 MHz to the
to a single binary counter of 10+ b bits in length. The
MC12000 series having capabilities extending to greater than
MSB of this "hypothetical" counter is to correspond
500 MHz. Synthesizers featuring the MC145156 and dual
to the M SB of + N and the LS B is to correspond to
modulus prescaling are shown in Figures 8 and 9 for two
typical applications. the LSB of + A. The system divide value, Ntotal, now
results when the value of Ntotal in binary is used to
program the "New" 10+ b bit counter.
TO THE MC145156

the application. i.e.
MC12009 +5/+6 440 MHz
MC12011 +8/+9 500 MHz
MC12013 + 10/ + 11 500 MHz
·MC3393 +15/+ 16 140 MHz

the number programmed into the + A counter. P and P + 1
are the two selectable divide ratios available in the two
quence, the + A counter is programmed from zero through Modulus
P - 1 for a particular value N in the divide N counter. N is Control
then incremented to N + 1 and the + A is sequenced from
zero through P- 1 again.
achieved for Ntotal. These values are a function of P and the
size of the + Nand + A counters. The constraint N > A
~
always applies. If Amax = P - 1 then Nmin > P - 1. Then
Ntotal- min = (P-11 P+ A or (P-1) P since A is free to
Device
Device B
A MC12009 MC12011 MC12013
MC10131 +20/ +21 +32/ +33 +40/ +41
MC1013B +50/ +51 +80/ +81 + 100/ + 101
+40/ +41 +64/+65
prescaler's output must go from low to high after each group MC10178 or or +80/+81
of P or P + 1 input cycles. The prescaler should divide by P +80/ +81 + 128/ + 129
when its modulus control line is high and by P + 1 when its
modulus control is low.
~.l MHz
0 veo
NAV:
Range
97.300-107.250 MHz
::r:
- 19 18
COM-T:
COM-R:
118.000-135.975 MHz
139.400-157.375 MHz
OSCin OSCout
5 VDD
7 VSS MC145156
17
REFout
CloCk Data Enable fin Mod Control
11 12 13 10 8
~----------~--------- .• 40/ -+- 41 Dual Modulus Prescaler
NOTES:
1l for NAV: FR: 50 kHz, + R: 64 uSing 10.7 MHzlowside Injection, Ntotal: 1946·2145
for COM- T FR ~ 25 kHz, + R: 128 using 21.4 MHz highslde injection, Ntotal: 4720-5439
for COM-R FR: 25 kHz, + R: 128 using 21.4 MHz hlghslde injection, Ntotal: 5576-6295
21 A .• 32/ -+- 33 dual modulus approach is provided by substituting an Me,201 1 l -+- 8/ -+- 91 for the MC12013 The devices are pin equivalent.
31 A 6.4 MHz oscillator crystal can be used by selecting + R: 128 Icode 0101 fer NAV and + R: 256 Icode 0111 for COM
Optional
Loop
Error Signal
~v 3
Mod 8
Control
fin
10
NOTE 1:
for FM: channel spacing = 25 kHz. + R = + 128 Icode 010)
for AM: channel spacing = 5 kHz. + R = + 640 Icode 1001
@MOTOROLA
MC145157
MC145158
CMOS LSI
ILOW-POWER COMPLEMENTARY MaS)
The MC145157 and MC145158 are part of a family of CMOS Phase SERIAL INPUT PLL
Lock Loop frequency synthesizer devices from Motorola. These devices FREQUENCY SYNTHESIZER
utilize silicon-gate CMOS technology to achieve the operating speeds
necessary for high-frequency operation. The family includes devices
having serial, parallel, and 4-bit data bus programmable inputs. Options
include single- or dual-modulus capability, transmit/receive offsets, and
a choice of phase detector types.
The MC145157 and MC145158 have fully programmable 14-bit
reference counters, as well as fully programmable -;-N IMC145157) and
-;-N/ -;-A IMC1451581 counters. The counters are programmed serially
through a common data input and latched into the appropriate counter
latch, according to the last data bit (control bill entered.
16
~ ifIr )f If
1
III1 II II
When combined with a loop filter and VCO, these devices can pro-
vide all the remaining functions for a PLL frequency synthesizer L SUFFIX P SUFFIX
operating up to the device's frequency limit. For higher VCO frequency CERAMIC PACKAGE .PLASTIC PACKAGE
operation, a down mixer or a fixed-divide prescaler can be used CASE 620 CASE 648
between the VCO and the PLL for the MC145157 and a dual-modulus
prescaler for the MC145158.
• General Purpose Applications - MC14XXXXlli Suffix Denotes

CATV L Ceramic Package
AM/FM Radios P Plastic Package
Two-Way Radios C Limited Operating
TV Tuning Temperature Range
Scanning Receiv\lrs
Amateur Radio
• Low Power Drain PIN ASSIGNMENT
• 3.0 to 9.0 V Supply Range

MCl45157
• 30 MHz Typical Input Capability @ 5 V If,n Input)
OSCin 16 <j>R
• Fully Programmable Reference and -;- N Counters
• Reference Divider Range; 3 to 16383 OSCout 15 <j>V
• -;- N Range; 3 to 16383 for the MC145157 fv 3 14 REFout

; 3 to 1023 for the MC 1 451 58 VDD 4 13 fR
• Dual Modulus Capability for the MC 1 451 58 PDout 5 12 S/Rout
-;- A Range ; 0 to 1 27
VSS 6 11 LE
• fv and fr Outputs
LD 7 10 Data
fin 8 9 Clock
• "Linearized" Digital Phase Detector
• Single Ended (Three-State) or Double-Ended Phase Detector Out- • MCl45158
puts. 16 <j>R
OSCin
OSCOU\ 2 15 <j>V
fv 14 REFout
VDD 4 13 fR
12 Modu!us
PDou1 5
Control
VSS 6 11 LE
LD 7 10 Dala
fin 8 9 Clock
DC Supply Voltage VDD -0.5 to + 10 V inputs against damage due to high static
V voltages or electric fields; however. it IS ad-
Input Voltage. All Inputs Vin - 0.5 to VDD + 0.5
vised that normal precautions be taken to
avoid application of any voltage higher than
DC Current Drain VDD or VSS Pins I 30 mA maximum rated voltages to this hIgh im-
Operating Temperature Range TA -40 to +85 'c pedance circuit. For proper operation It is
Storage Temperature Range Tstg -65 to + 150 'c recommended that Vin and )/ out be con-
strained to the range GNO:s (Vin or
VoutlsVCC·
Unused Inputs must always be tied to an
appropnate logic voltage level le.g .. either
GND or VCCI.
TLow 25°C THigh

Power Supply Voltage Range VDD - 3 9 3 - 9 3 9 V
Output Voltage o Level 3 - 005 - 0 0.05 - 0.05
Vin= VDD or 0 VOL 5 0.05 - 0 005 - 005
9 - 005 - 0 0.05 - 0.05 V
3 2.95 - 2.95 3 - 295 -
Vin=O or VDD 1 Level VOH 5 4.95 - 4.95 5 - 4.95 -
9 8.95 - 8.95 9 - 8.95 -
VO=2.5 or 0.5 3 - 0.9 - 1.35 0.9 - 0.9
VO=4.5 or 0.5 VIL 5 - 1.5 - 2.75 1.5 - 1.5
VO=8.5 or 1.5 9 - 2.7 - 4.05 2.7 - 2.7 V
Vo=0.50r2.5 1 Level 3 2.10 - 2.10 1.65 - 2.10 -
VO=0.5 or 4.5 VIH 5 3.5 - 3.5 2.75 - 3.5 -
VO= 1.5 or 8.5 9 6.3 - 6.3 495 - 63 -
VOH=2.7 3 -0.44 - -035 -0.66 - -0.22 -
VOH=4.6 IOH 5 -0.64 - -0.51 -0.88 - -0.36 -
VOH=8.5 9 -1.3 - -1.0 -1.3 - -0.7 - mA
VOL =0.3 Sink 3 0.44 - 0.35 0.66 - 0.22 -
VOL=O.4 IOL 5 0.64 - 0.51 088 - 0.36 -
VOL =0.5 9 1.3 - 1.0 1.3 - 0.7 -
Output Current Modulus Control
Source
VOH=2.7 3 -0.25 - -015 -0.5 - -0.00 -
VOH=4.6 IOH 5 -0.75 - -0.45 -1.5 - -0.23 - mA
VOH=8.5 9 -1.25 - -0.75 -2.5 - -0.38 -
Output Current Modulus Control
VOL =03 Sink 3 08 - 0.48 1.6 - 0.24 -
VOL=O.4 IOL 5 1.5 - 0.90 3 - 0.45 - mA
VOL =0.5 9 3.5 - 2.10 7 - 1.05 -
Input Current Other Inputs 9 - ±0.3 - ±O.OOOOI ±0.1 - ± 1.0
Enable IlL 9 - -60 - -25 -50 - -35
fln.OSCin 9 - ± 15 - ±5 ±10 - ±8 pA
f,n,OSCin IH 9 - ± 15 - ±5 ±1O - ±8
Other Inputs 9 - ±0.3 - ±OOOOO1 ±0.1 - ±1.0
3 - 800 - 200 800 - 1800
Quiescent Current IDD 5 - 1200 - 300 1200 - 2400 pA
9 - 1800 - 400 1800 - 3200
3·State Leakage Current PDout IL 9 - ±0.1 - ±O.OOOI ±0.1 - ±30 pA
NOTE: Tlow= -40'C

Thigh = 85°C
Characteristic Symbol VOO Min Typ Max Units
3 - 100 200
Output Rise Time, Modulus Control (Figure 2)
. tTLH 5
9
3
-
-
-
50
40
50
100
80
100
ns
Output Fall Time. Modulus Control (Figure 2) tTHL 5 - 25 50 ns

9 - 20 40
3 - 140 280
Output Aise Time. LD. IV. IA (Figure 21 tTLH 5 - 90 180 ns
9 - 80 160
3 - 140 280
Output Fall Time. LD. IV.IA (Figure 21 tTHL 5 - 90 180 ns
9 - 80 160
3 - 100 200
tpLH 5 - 50 80 ns
Propagation Delay Time 9 - 30 50
'in to Modulus Control (Figure 31 3 - 80 200
tPHL 5 - 50 80 ns
9 - 30 50
Setup Times 3 - 20 50
Data To Clock tsu 5 - 10 25 ns
9 - B 20
3 - 25 60
Latch Enable To Clock IFigure 41 tsu 5 - B 15 ns
9 - 5 10
Hold Time 3 - 50 80
Data To Clock IFigure 4) th 5 - 30 50 ns
g - 10 25
q,A. q,V with fA in Phase With Iv (Figure 51 tW(q,1 5 50 100 150 ns
g 40 70 100
3 - - 5
Input Rise And Fall Times tTLH. 5 - - 4 "s
Clock. OSCin. lin (Figure 61 tTHL 9 - - 2
3 40 30 -
Input Pulse Width OSCin. fin. Clock (Figure 71 tw 5 35 20 - ns
9 25 15 -
..
Tlow * 25°C Thigh*
Character~tic Symbol VOO Units
OSCin Input~ SO Wave (VDD to VSSI fmax 5 - 13 - 20 10 - 8 MHz
9 - 18 - 32 16 - 13
Input = Sin Wave (500 mVp·pl 3 - 5 - 9 4 - 3
fmax 5 - B - 13 6 - 5 MHz
9 - 9 - 14 7 - 6
fin Input= SO Wave (VDD to VSSI fmax 5 - 30 - 30 22 - 18 MHz
9 - 30 - 49 41 - 31
Input~ Sin Wave (500 mVp-pl 3 - 14 - 17 11 - 8
fmax 5 - 29 - 30 22 - 17 MHz
9 - 37 40 30 24
*Tlow= -40°C
Thigh=85°C
OSC,n 1
2
OSCeu! 14
AEFeut
fin 8
OSCin 1
OSCeu! 2
AEFeut 14
<l>R,<I>V(Pins 16, 15) - Double-ended phase detector out-
puts. These outputs can be combined externally for a loop
INPUTS error signal. A single-ended output is also available for this
OSCin, OSCout (Pins 1, 2) - These pins form an on-chip purpose (see PDout!'
reference oscillator when connected to terminals of an exter- If frequency tv is greater than fR or if the phase of fV is
nal parallel resonant crystal. Frequency setting capacitors of leading, then error information is provided by <l>v pulsing
appropriate value must be connected from OSCin to ground low. <l>R remains essentially high (see Figure S for
and OSCout to ground. OSCin may also serve as input for an illustration!.
externally-generated reference signal. This signal will typi- If the frequency fV is less than fR or if the phase of fV is
cally be AC coupled to OSCin, but for larger amplitude lagging, then error information is provided by <l>Rpulsing
signals (standard CMOS-logic levelsl DC coupling may also low; <l>vremains essentially high.
be used. In the external reference mode, no connection is re- If the frequency of fV = fR and both are in phase, then
quired to OSCout. both <l>Vand <l>Rremain high except for a small minimum
II
fin (Pin 8) - Input frequency from VCO output. A rising time period when both pulse low in phase.
edge signal on this input decrements the + N counter (+ A StRout (Pin 12 of the MCl45157) - Shift register output.
or + N counter for the MC145158). This input has an inverter This output can be connected to an external shift register to
biased in the linear region to allow use with AC signals as low provide band switching, control information, and counter
as 500 mV p-p or with a square wave of VDD to VSS. programming code checking.
Clock, Data (Pins 9, 10) - Shift register clock and data in- Modulus Control (Pin 12 of the MCl45158) - Modulus
put. Each low-to-high transition of the clock shifts one bit of control output. This output generates a signal by the on-chip
data into the on-chip shift registers. The last data bit entered control logic circuitry for controlling an external dual
determines which counter storage latch is activated; a logic modulus prescaler. The modulus control level will be low at
one selects the reference counter latch and a logic zero the beginning of a count cycle and will remain low until the
selects the + N counter latch I + A, + N counter latch for the + A counter has counted down from its programmed value.
MC145158). The data entry format is as follows: At this time, modulus control goes high and remains high
until the + N counter has counted the rest of the way down
from its programmed value IN - A additional counts since
both + Nand + A are counting down during the first portion
of the cycle!. Modulus control is then set back low, the
counters preset to their respective programmed values, and
eC '"
tIl '"::;;
tIl grammable divide value (NT) = N' P + A where P and P +
0
u
-' 1 represent the dual modulus prescaler divide values respec-
tively for high and low modulus control levels, N the number
First .Data B.il Int~-3 programmed into the + N counter and A the number pro-
grammed into the + A counter. Note that when a prescaler is
needed, the dual modulus version offers a distinct advan-
tage. The dual modulus prescaler allows a higher reference
frequency at the phase detector input, increasing system
performance capability, and simplifying the loop filter
design.
LD (pin 7) - Lock detect signal. This output is at a high
eC logic level when the loop is locked IfR, fV of same phase and
0
'"
tIl
-'
'"
tIl
::;; '"-'
tIl '"
tIl
::;; frequencyl, and pulses low when the loop is out of lock.
u
REFout (Pin 14) - Suffered reference oscillator output.
First .Data B.it Into --"
This output can be used as a second local oscillator,
reference oscillator to another frequency synthesizer, or as
the system clock to a microprocessor controller.
OUTPUTS
fR, tv (Pins 13, 3) - Divided reference and fin frequency CONTROLS
outputs. The fR and fV outputs are connected internally to
LE (Pin 11) - Latch Enable Input. A logic high on this pin
the + Rand + N counter outputs respectively, allowing the
latches the data from the shift register into the reference
counters to be used independently, as well as monitoring the
divider or + N, + A latches depending on the control bit. The
phase detector inputs.
reference divider latches are activated if the control bit is at a
PDout (Pin 5) - Single ended (three-state) phase detector
logic high and the + N, + A latches are activated if the con-
output. This output produces a loop error signal that is used
trol bit is at a logic low. A logic low on the LE pin allows the
with a loop filter to control a VCO. This phase detector out-
user to change the data in the shift registers without affect-
put is described below and illustrated in Figure 8.
ing the counters.
Frequency fV>fR or fV Leading: Negative Pulses

Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: High-Impedance The technique of dual modulus prescaling is well estal>-
State lished as a method of achieving high performance frequency
synthesizer operation at high frequencies. Basically, the ap- b. Prescaler setup or release time relative to its
proach allows relatively low-frequency programmable modulus control signal.
counters to be used as high-frequency programmable c. Propagation time from fin to the modulus control
counters with speed capability of several hundred MHz. This output for the MC145158.
is possible without the sacrifice in system resolution and per- A sometimes useful simplification in the MC145158 pro-
formance that would otherwise result if a fixed (single gramming code can be achieved by choosing the values for P
modulus) divider was used for the prescaler. of 8, 16,32,64 or 128. For these cases, the desired value for
In dual modulus prescaling, the lower speed counters Ntotal will result when Ntotal in binary is used as the pro-
must be uniquely configured. Special control logic is gram code to the + Nand + A counters treated in the
necessary to select the divide value P or P+ 1 in the prescaler following manner:
for the required amount of time (see modulus control defini- A. Assume the + A counter contains "b" bits where 2b =
tion). The MC145158 contains this feature and can be used P.
with a variety of dual modulus prescalers to allow speed,
B. Always program all higher order + A counter bits
II
complexity and cost to be tailored to the system re-
above "b" to zero.
quirements. Prescalers having P, P+ 1 divide values in the
range of + 3/ + 4 to + 128/ + 129 can be controlled by the C. Assume the + N counter and the + A counter (with all
MC145158. the higher order bits above "b" ignored) combined in-
Several dual modulus prescaler approaches suitable for to a single binary counter of 10+ b bits in length. The
use with the MC145158 are given in Figure 1. The ap- MSB of this "hypothetical" counter is to correspond
proaches range from the low cost + 15/ + 16, MC3393P to the MSB of + N and the LSB is to correspond to the
device capable of system speeds in excess of 100 MHz to the LSB of + A. The system divide value, Ntotal, now
MC12000 series having capabilities extending to greater than results when the value of Ntotal in binary is used to
500 MHz. program the "New" 10+ b bit counter.
TO THE MC145158

the application, i.e.
MC12009 +5/+6 440 MHz Min
frequency into the prescaler MC12011 +8/+9 500 MHz Min
Ntotal= frequency into the phase detector = N-P+ A MC12013 + 10/+ 11 500 MHz Min
MC12015 +32/ +33 225 MHz Min
MC12016 +40/ +41 225 MHz Min
MC12017 +64/+65 225 MHz Min
the number programmed into the + A counter. P and P + 1
*MC12018 + 128/+ 129 520 MHz Min
are the two selectable divide ratios available in the two MC3393 + 15/+ 16 140 MHz Typ
quence, the + A counter is programmed from zero through
P- 1 for a particular value N in the + N counter. N is then in-
cremented to N + 1 and the + A is sequenced from zero
through P- 1 again.
achieved for Ntotal. These values are a function of P and the Modulus
size of the + Nand + A counters. the constraint N '" A Control
always applies. If Amax = P - 1 the Nmin '" P- 1. Then
N(total- mini = (P - 11 P + A or (P - 11 P since A is free to
~
prescaler's output must go from low to high after each group
Device
of P or P+ 1 input cycles. The prescaler should divide by P
Device B
when its modulus control line is high and by P + 1 when its MCl2009 MCl2011 MC12013
A
modulus control is low. MC10131 +201 +21 +321 +33 +401 +41
For the maximum frequency into the prescaler (Fvcomax),
MC10138 +~/+51 +001 +81 + 100/+ 101
+40/ +41 +64/ +65
A. Fvco max divided by P may not exceed the frequency or or
capability of Pin 8 of the MC145158. +001 +81 + 128/ + 129
B. The period of Fvco( max), divided by P, must be greater
than the sum of the times:
a. Propagation delay through the dual modulus
prescaler.
__r__
¢R,¢V* 50%\
IW
¢=1,-
FIGURE5
LE \ _
I~e~~~e} n...
Jl... .. n n _
IV
Feedback
(fIn'" N)
Po Out --l' ----- .

MC145145 Bus Input Single Modulus 3 State/2 Output
MC145146 Format Dual Modulus 3 Statel2 Output
MC145151 Parallel Input Single Modulus 3 Statel2 Output
MC145155 Serial Input Single Modulus 3 State/2 Output
MC145t59 Dual Modulus 3 S tatel Analog
POout~VCO
R1 _...L I
~Ro-- C
~V<>--
I
-
Fls) = --'--
R1CS + 1
BI POout VCO
Rt
~Ro--
R2
~Vo--
C
NOTE: Sometimes Rl is split into two series resistors each R 1. 2. A capacitor Cc is then placed from the mIdpoint to ground to further filter ~V and
~R. The value for Cc should be such that the corner frequency of this network does not significantly affect WN.
DEFINITIONS: N = Total DIvIsIon Ratio In feeoback loop

K~ = Voo/4r for POou'
K~ = Voo/2r for ~V and ~R
KVCO = 2r<1fvco
<1VVCO
for a typical design wN == 2:1'fr (at phase detector Input)
10
® MOTOROLA
CMOS LSI
(LOW-POWER COMPLEMENTARY MaS)
SERIAL INPUT PLL FREQUENCY SYNTHESIZERS

WITH ANALOG PHASE DETECTOR SERIAL INPUT PLL
The MC145159 is part of a family of CMOS Phase Lock Loop frequency
synthesizer devices from Motorola. This device utilizes silicon-gate CMOS
technology to achieve the operating speeds necessary for high-frequency
operation. The family includes devices having serial, parallel, and 4-bit
data bus programmable inputs. Options include single- or dual-modulus
capability, transmil/receive offsets, and a choice of phase detector types.
-
The MC145159 has a fully programmable 14-bit reference counter, as
well as fully programmable + NI + A counters. The counters are program-
med serially through a common data input and latched into the appro-
priate counter latch, according to the last data bit (control bit) entered. 20 L SUFFIX
CERAMIC PACKAGE
1 CASE 732
When combined with a loop filter and VCO, these devices can provide
all the remaining functions for a PLL frequency synthesizer operating up to
the device's frequency limit. For higher VCO frequency operation, a down
-
mixer or a fixed-divide prescaler can be used between the VCO and the
PLL.
• General Purpose Applications

CATV
P SUFFIX 1
AM/FM Radios PLASTIC PACKAGE
Two-Way Radios CASE 738
TV Tuning
Scanning Receivers
Amateur Radio
• Low Power Drain

• 3.0 to 9.0 V Supply Range
• > 30 MHz Typical Input Capability@ 5 V
• Fully Programmable Reference and "'eN/"'eA Counters
• Reference Divider Range = 3 to 16383
• "'eN Range = 3 to 1023
Ra CR
• Dual Modulus Capability
• "'eA range = 0 to 127 aselN vDD
• "Linearized" Digital Phase Detector aSCaUT Cs
• Single Ended (Three-State) or Analog Phase Detector Outputs. Charge PDA
VDD VSS
PDS RR
VSS S/RaUT
Modulus
latch Enable
Control
LE Data
F,n SIR Clock

® MOTOROLA
DUAL TUNEABLE CMOS LSI

LOW PASS SAMPLED DATA FILTERS
The MC145414 is sampled data, switched capacitor filter IC intended

to provide band limiting and signal restoration filtering. It is capable of DUAL TUNEABLE
operating from either a single or split power supply and can be
II powered-down when not in use. Included on the IC are two totally un-
LOW PASS
committed op amps for use elsewhere in the system as I to V con- SAMPLED DATA FILTERS
verters, gain adjust buffers, etc.
• Two General Purpose 5th Order Elliptic Low Pass Filters

• Low Operating Power Consumption - 30 mW ITypicall
• Power Down Capability - 1 mW IMaximum)
• ± 5 to ± 8 Volt Power Supply Ranges
• TTL or CMOS Compatible Inputs Using VLS Pin
• Two Operational Amplifiers Available to Reduce Component L SUFFIX P SUFFIX
Count CERAMIC PACKAGE PLASTIC PACKAGE
• Useful in LPC or CVSD Speech Applications CASE 620 CASE 648
• Passband Edges Tuneable With Clock Frequency From 1.25 kHz

to 10kHz
PIN ASSIGN"'1ENT
VAG VDD
+A Ain
-A 14 Aout
AO 13 Bin
BO 5 12 Bout
-B 11 CLK 1
+B 10 CLK 2
VSS VLS
::~
AO~
MC14XXXX
~:~ bL Ceramic Package

P Plastic Package
+B~
static voltages or electric fields; however,
CLK 1
it is advised that normal precautions be
CLK 2 taken to avoid application of any voltage
higher than maximum rated voltages to
VLS
this high impedance circuit. For proper
operation it is recommended that Vin and
Vout be constrained to the range
VSS:<IVin or Vout):<VDD.
Unused inputs must always be tied to
an appropriate logic voltage level (e.g .•
either VSS or VDDI.
DC Supply Voltage VDD-VSS 0.5 to 18 V
Input Voltage, All Pins Vin - 0.5 '0 VDD + 0.5 V

DC Current Drain per Pin IExcluding VDD, VSSI I 10 mA
Operating Temperature Range TA o to 85 ·C
Storage Temperature Range Tstg -65'0150 ·C
DC Supply Voltage
Clock I, 2 Frequency
VDD 2S·C
Vdc Min Typ Max
Operating Current IDD 12 - 2.0 4.0 mA
Power-Down Current IPDI=VSSI IpD 12 - 10 40 ~A
Input Capacitance Cin 12 - 50 - pF
MODE CONTROL LOGIC LEVELS
VLS Power· Down Mode VIH

12 11.5 11 - V
15 14.5 13 -
12 4.0 - 8 V
VLS TTL Mode -
15 50 - 9
12 - - 08
VLS CMOS Mode VIL V
15 - - 08
VAG Power-Down Mode

12 11.5 10.5 - V
VIH 15 14.5 13.5 -
VAG Analog-Ground Mode
12 - - 70
V
VIL - - 9.0
15
CMOS LOGIC LEVELS IVLS ~ VSSI
Input Current Clock I, 2 "1" Level 12 - 50 100
lin ~A
(Internal Pulldown Resistors) "0" Level 12 - -0.‫סס‬OO1 -0.3
Input Voltage Clock 1,2 "0" Level 12 - 5.25 3.0
VIL V
15 - 6.75 3.5
"1" Level 12 90 6.75
VIH - V
15 11.5 825
TIL LOGIC LEVELS IVLS=6 V, VSS=O VI
Input Current Clock I, 2 "1" Level 12 - 50 100
lin ~A
(Internal Pulldown Resistor) "0" Level 12 - -0‫סס‬oo1 -03
Input Voltage Clock 1,2 "0" Level VIL 12 - - VLS + 0.8
V
"1" Level VIH 12 VLS + 2.0 - -
25°C
Min Typ Max
Input Current Ain. Bin lin - ±0.OOOO1 ±10 ~A
Input Current VAG lin - ±0.OOOO1 ±10 ~A
AC Input Impedance 11 kHz! Ain. Bin Zin - 2 - MO
Input Common Mode Voltage Range Ain. Bin. + A. - A. + B. - B VICR 2.0 - 10.0 V
Input Offset Current + A to - A. + B to B 110 - ±10 - nA
Input Bias Current +A. -A. +B.-B liB - ±0.10 ± 1.0 nA
Input Offset Voltage + A to - A. + B to - B Via - ±10 ±70 mV
Output Voltage Range AO. BO. Aout. Bout
IRL =20 kO to VAG. RB= col 1.5 - 10.5
II
VOR V
IRL =600 0 to VAG. RB= 1.6 kO to VOO! 3.0 - B.3
IRL =900 0 to VAG. RB = 1.8 kO to Vaal 2.5 - 9.0
Small Signal Output Impedance 11 kHz) Aout 4> - 50 - 0
Bout - 50 -
Output Current
IVO=10.5VI Aout. Bout. AO. BO 10H -200 -400 - ~A
IVO=15V! Aout. Bout. AO. 80 10L 5 7.5 - mA
Unity Gain Output Noise AO. BO - - 15 - p.Vrms
FilTER A SPECIFICATIONS
IVDD-VEE~ 1 2 V. fCll' fel2 = 128 kHz. Vin=O dBmO. full scale = +3dBmO. 7 V pop!
25°C
Characteristic Unit
Min Typ Max
Gain 11020 HzI 17.4 18 186 dB
Passband Ripple 150 Hz to 3000 HzI - 0.24 1.0 dB
Out of Band Response
3400 Hz - -0.8 -1.5
dB
4000 Hz-4600 Hz -10 -15.5 -
4600 Hz-54 kHz -25 -33.0 -
Output Noise lAin - VAGI ref to 900 0 - 10 17 dBrncO
Dynamic Range 76 83 - dB
Differential Group Delay
1150 to 2300 kHz Delay - - -
~s
1000 to 2500 kHz Delay - - -
BOOto 2700 kHz Delay - - -
Power Supply Rejection Ratio (VDD= 12 V +0.1 VRMS @ 1 kHz! - 36 - dB
Crosstalk lAin - VAG. Bin = 0 dBmO Output at Aout at 3 kHz) - 76 - dB
DD·- EE ~ . 'rll' CL2 = z. in= m . full scale = + m pop

25°C
Characteristic Unit
Min Typ Max
Gain 11020 Hz! -0.7 ±0.15 +0.7 dB
Passband Ripple 1300 Hz to 3000 Hz) - 0.22 1.0 dB
Response
3400 Hz - -0.8 -1.7
dB
4000 Hz-4600 Hz -10 -15.5 -
4600 Hz-54 kHz -28 -33.0 -
Output Noise 1300 Hz-3400 Hz) - 8 14 dBrncO
Dynamic Range 17 V POp Max! 79 87 - dB
Differential Group Delay
1150 to 2300 kHz Delay - - -
~s
1000 to 2500 kHz Delay - - -
BOOto 2700 kHz Delay - - -
Crosstalk 18in=VAG. Ain=OdBmO@ 3 kHz Output at LPO @ 3 kHz) - 76 - dB
Power Supply Rejection Ratio - 36 - dB
CharacteriStics Symbol
o to 70·C Units
Min Typ Max
Input Rise Time Clock 1, 2 tTlH
- - 4 ~s
Input Fall Time tTHl
PulseWidth Clock 1, 2 tWH 200 ns
Clock Frequency Clock 1, 2 fCl 50 - 400 kHz
Clock 1, 2 Duty Cycle - 40 - 60 %
Pin 1 - VAG (Analog Ground) for the Clock 1, 2 inputs. If VLS is within 0.8 V of VSS, the
This pin should be held at approximately (VOO-VEE)/2, All thresholds will be for CMOS operating between VOO and
analog inputs and outputs are referenced to this pin. If this VSS. If VLS is within 1.0 V of VOO, the chip will power
pin is brought to within approximately 1.0 V of VOO, the down. If VLS is between VOO-2 V and VSS+2 V, the
chip will be powered down. thresholds for logic inputs at Clock 1, 2 will be between
VLS+0.8 V and VLS+2.0 V for TTL compatibility.
Pin2-+A
Non-inverting input of op-amp A. Pin 10 - Clock 1
Always tie clock 1 and clock 2 together.
Pin3--A
Inverting input of op-amp A. Pin 11 - Clock 2
Always tie clock 1 and clock 2 together.
Pin4-AO
Output of uncommitted op-amp A. Pin 12 - Bout (Lowpass Filter B)
This is the output of B lowpass filter.
Pin 5 - BO
Output of uncommitted op-amp B. Pin 13 - Bin (Lowpass Filter B)
This is the input to filter B.
Pin6--B
Inverting input of op-amp B. Pin 14 - Aout (Low pass Filter Al
This pin is the output to filter A.
Pin7-+B
Non-inverting input of op-amp B. Pin 15 - Ain (Lowpass Filter A)
This is the input to filter A.
Pin 8 - VSS
This is the most negative supply pin and digital ground for Pin 16 - VDD
the package. Nominally 12 volts.
Pin 9 - VLS (Logic Shift Voltage)

The voltage on this pin determines the logic compatibility
FILTER A DESCRIPTION FILTER B DESCRIPTION

Filter A of the MC145414 is a 5-pole elliptic tuneable Filter B in the MC1 4541 4 consists of a 5-pole elliptic
lowpass filter operating at a sampling rate determined by tuneable lowpass filter operating at a sampled rate deter-
clock 1 and clock 2. This filter provides band limiting that is mined by clock 1 and clock 2. Filter B is functionally similar
a direct function of clock 1 and clock 2. With a 128 kHz to filter A, except filter B has unity gain.
clock, the band limiting frequency is 3.6 kHz. By dividing the
clock in half to 64 kHz, the band limiting frequency is cut in
half to 1.8 kHz (as illustrated in Figure 11. Likewise by dou- Clock 1 and 2
bling the clock, the cutoff point will double (as illustrated in Logic levels of these signals can be either TTL or CMOS
Figures 3 and 41. The clock frequency can be varied from compatible. Choice of logic level can be user determined by
50 kHz to 400 kHz. Filter A, unlike filter B, has a gain of 18 applying the appropriate voltage to the level shift control pin,
db. Because the MC145414 is a switch capacitance filter, the VLS. Clock 1, 2 pins should be tied together.
sampled output signal will have switching noise present near
multiples of the switching frequency; a single-pole RC filter
may be required to reduce this. Power Down
To provide 50/60 Hz and 15 Hz rejection, a 3-pole The MC145414 may be powered down by bringing VAG to
Chebychev highpass filter can be externally realized with the within 1.7 V of VCC or by bringing VLS to within 1.7 V of
MC145414 by using the uncommitted op-amps as an active VOO
filter. This is shown in Figure 5 and 6.
iii
iii
:s 0
:s I II
11
•...
~ -5
~
~ -5
-liW-
::>
'" -10 '"g -10
!l
i -15 •...L15
~ -20 ~ -20
~ -25
~
l:i -25
:; -30
Iz ~ -30
""
~ -35 a:;:
-35
II ~o:
_
-40
-45
0.1 k
J -40
0.1 k
~ -0
-5
-10
I -5
!l -10
•...~
:: -15 i -15 l-
~
~
-20 ~
~ -20 I-
'" -25 "" -25

'" -30 !2
!C -30
~ -35 ~ -35
.S
':. -40 ~ -40
,} '\ ,.5
C1,C2,C3 4700 pF ±1%
C4 0.2 ~F - 20% +80%
R1 112 kll Y.W 1%
R2 620 kll Y.W 1%
R3 223 kll Y.W 1%
R4 100 kll Y.W 10%
R1
C4
Bin
Zin = 900 II
C1 C2
13
QA Low Pass
12
Bout
Vin Max= +3 dBm R10 R2 R3 R4

R6
R5
VAG VAG
VOO
Zout = 900 iJ R8
Q
Vout Max= +3 dBm R9
14 15
Ain
R7
Aout
R11 B Low Pass
C1, C2, C3 4700 pF ±1% R6 169 kll Y.W 1%

C4 0.2 ~F -20% +80% R7 24 kO 1f.W 1%
R1 236 kll Y.W 1% R8 33kll Y.W 1%
R2 294 kll Y.W 1% R9 1.B kll Y.W 10%
R3 223 klly.w 1% R10 SOOO'AW 1%
R4 100 kO V.w 10% R11 90011 Y.W 1%
R5 200 kO JAW 1%
AD0319
NOTE: In noisy environment. Al·A4 should be 10 kG or less to mInimize pickup.

1 16
VAG VDD R8 R5
16
R15 VCC
2 +A 15 EIO 15
Ain Encodel Decode
" 14
R9
~ Aout CLK 14 Bit Rate Clock
G 12 kHz to 32 kHz
::. Bin
13 01 13 DigItal Input
12 DTH 12
Bout
CLK2 11 VTIN 11
I\)
W
(11 CLKl 10 VCC 10
~ 2
R11
9
VLS 9 DO DigItal Output
R10
+12
C6 +
R13
I-
Analog
Output - 128 kHz
R12 C1 0.1 ~F 20% R6 47 kO 5%

C2 0.01 ~F 20% R7 5.1 kO 5%
NOTES: C3 0.1 ~F R8 10 kO 5%
1. Ain has a gain of 18 dB. Max Vin before clipping
2. Clock must be full VDD to VSS swing.
is 1 Vp-p.
- C4
C5
0.33 ~F
0.1 ~F
R9
Rl0
2000
1 kO
3. Digital 1/0 on MC3417118 is TTL compatible. C6 10 ~F R11 4.7 kO
R1 9.6 kO 5% R12 22 M
R2 400 kO 5% R13 2 kO
R3 7.5 kO 5% R14 10 kO
R4 15 kO 5% R15 2 kO
R5 8.2 kO 5%
II
Mechanical Data
The package availability for each device is indicated on the front page of the individual
data sheets. Dimensions for the packages are given in this chapter.
P SUFFIX
PLASTIC PACKAGE
CASE 626
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400 NOTES:
B 6.10 6.60 0.240 0.260 1. LEADS WITHIN 0.13 mm
C 3.94 4.45 0.155 0.175 (0.005) RADIUS OF TRUE
D 0.38 0.51 0.015 0.020 POSITION AT SEATING
F 1.02 1.52 0.040 0.060 PLANE AT MAXIMUM
G 2.54 BSC 0.100 BSC MATERIAL CONDITION.
H 0.76 1.27 0.030 I 0.050 2.' DIM "L" TO CENTER OF
J 0.20 0.30 0.008 I 0.012 LEADS WHEN FORMED
K 2.92 3.43 0.115 I 0.135 PARALLEl.
L 7.62 esc 0.300eSC 3. PACKAGE CONTOUR
M - 10° - 100 OPTIONAL (ROUND OR
N 0.51 0.76 0.020 I 0.030 SQUARE CORNERS)
..
~
L SUFFIX
CERAMIC PACKAGE
g
1
-II-oJ
7~
F
B P
CASE 632
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 19.05 19.94 0.750 0.785
B 610 7.49 0.240 0.295
C - 5.08 - 0.200
0 0.38 0.58 0.015 0.023
F 1.40 1.77 0.055 0.070
NOTES:
1. LEAOS WITHIN 0.13 mm (0.005) RAOIUS OF
TRUE POSITION AT SEATING PLANE AT MAX-
IMUM MATERIAL CONDITION.
G
H
J
K
2.54
1.9
0.20
3.18
sse
2.29
0.38
5.08
0.100
0.075
0.008
0.125
sse
0.090
0.015
0.200
II
2. DIMENSION "L" TO CENTER OF LEADS
L 7.62 sse 0.300 sse
WHEN FORMED PARALLEL. M - 1 15° - I 15°
3 DIMENSIONS "A" AND "B" DO NOT IN-
CLUDE GLASS RUN-OUT.
N 0.51 I 1.02 0.020 10.040
P SUFFIX
PLASTIC PACKAGE
CASE 646
l~:::::j]
I A-l
DIM
A
MILLIMETERS
MI.
18.16
MAX
19.56
MI.
0.115
INCHES
MAX
0.770
NOTES:
•
C
6.10
4.06
6.60
508
0.240
0.160
0.160
O.lDO
0 0.38 0.53 0015 0.021
1. LEADS WITHIN 0.13 mm (0.005) RADIUS
F 1.02 1.78 0040 0.070
,~:i~
OF TRUE POSITION AT SEATING PLANE
G 2.54 BSC 0.100 BSC
AT MAXIMUM MATERIAL CDNDITION. H 1.311 2.41 0.051 I 0.095
2. DIMENSION "L" TD CENTER OF LEADS
J
J 0.10 I 038 0.008 0.015
WHEN FORMED PARALLEL. K 1.911 343 0.115 I 0.135
3. DIMENSIDN "B" DOES NOT INCLUDE L 7.62 sse 0.300 BSC
~I- MOLD Fl ASH. M 0 I 10 o I 10
H --1 G t- -H--O PLANE 4. ROUNDED CORNERS OPTIONAL. • 0.51 1.01 0.020 0.040
L SUFFIX
CERAMIC PACKAGE
CASE 620
II
MilLIMETERS INCHES
DIM MIN MAX MIN MAX
A 19.05 19.94 0.750 0.785
B 6.10 7.49 0.240 0.295
C - 5.08 - 0.200
D 0.38 0.53 0.015 0.021
NOTES:
F 1.40 1.78 0.055 0.070 1. LEADS WITHIN 0.13 mm (0.005) RADIUS OF
G 2.54 sse 0.100 sse TRUE POSITION AT SEATING PLANE AT MAX-
H 0.51 1.14 0.020 0.045 2. PACKAGE INDEX: NOTCH IN LEAD NOTCH IN
J 0.20 0.30 0.008 0.012 CERAMIC OR INK DOT
3. DIM. T' TO CENTER OF LEADS WHEN
K 3.18 4.06 0.125 0.160 FORMED PARALLEL.
l 7.62 sse 0.300 sse 4. DIM. "A" AND "B" 00 NOT INCLUDE GLASS
RUN-OUT.
M - 15° - 15° 5. DIM" F" MAY NARROW TO 0.76 mm (0.030)
N 0.51 I 1.02 0.020 0.040 WHERE THE LEAD ENTERS THE CERAMIC
BODY.
P SUFFIX
PLASTIC PACKAGE
CASE 648
NOTES:
1. LEAOS WITHIN 0.13 mm
(0.005) RAOIUS OF TRUE
MILLIMETERS INCHES POSITION AT SEATING
DIM MIN MAX MIN MAX PLANE AT MAXIMUM
A 18.80 21.34 0.740 0.840 MATERIAL CONOITION.
B 6.10 6.60 0.240 0.260 2. DIMENSION "L" TO
C 4.06 5.08 0.160 0.200 CENTER OF LEADS
D 0.38 0.53 0.Q15 0.021 WHEN FORMED
F 1.02 1.78 0.040 0.070 PARALLEL.
II
G 2.54 8SC 0.100 BSC 3. DIMENSION "8" DOES NOT
H 0.38 I 2.41 0.Q15 I 0.095 INCLUDE MOLD FLASH
J 0.20 038 0.008 I 0.015
4. "F" DIMENSION IS FOR FULL
K 2.92 3.43 0.115 10.135 LEADS "HALF" LEADS ARE
L 7.62 8SC 0.3008SC OPTIONAL AT LEAD POSITIONS
M 0 0 100 00 I 100 1,8,9, and 16).
N 051 I 1.02 Lllil2~~ 5. ROUNDED CORNERS OPTIONAL.
P SUFFIX
PLASTIC PACKAGE
CASE 6488
MILLIMETERS INCHES NOTES:

DIM MIN MAX MIN MAX 1. LEADS WITHIN 0.13 mm (0.005)
A 18.80 21.34 0.740 0.840 RADIUS OF TRUE POSITION AT
B 6.10 6.60 0.240 0260 SEATING PLANE AT MAXIMUM
C 4.06 5.08 0.160 0.200 MATERIAL CONDITION.
D 0.38 0.53 0.015 0.021 2 DIMENSION "L" TO CENTER OF
F 1.02 1.78 0.040 0.070 LEADS WHEN FORMED
G 2.548SC 0100 BSC PARALLEL.
H 0.38 I 2.41 0.Q15 0.095 3. DIMENSION "B" DOES NOT
J 0.20 T 0.38 0.008 0.015 INCLUDE MOLD FLASH.
K 2.92 I 3.43 0.115 0.135 4. ROUNDED CORNERS
L 7.62 8SC 0.3008SC OPTIONAL.
M 00 I 100 00 100 5. EXTERNAL LEAD CONNECTION.
N 0.51 I 1.02 L 0.020 0.040 BETWEEN 15 AND 16 AS SHOWN.
P SUFFIX
PLASTIC PACKAGE
CASE 707
-
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 22.22 23.24 0.875 0.915
8 610 660 0.240 0.260
NOTES: C 3.56 457 0.140 0.180
II 1. POSITIONAL TOLERANCE OF LEADS (01, 0 036 0.56 0.014

SHALL BE WITHIN 0.25mmlO.Ol01 AT F 127 178 0050
~ 0070
MAXIMUM MATERIAL CONDITION, IN G 2.54 8SC 0.100 BSC
RELATION TO SEATING PLANE AND H 1.02 I 1.52 0.040 0060
EACH DTHE R. J 0.20 0.30 0.008 0.012
2. DIMENSION L TO CENTER OF LEADS K 2.92T 343 0115To135
WHEN FORMED PARALLEL. L 7.62 8SC 0.300 BSC
3. DIMENSION B DOES NOT INCLUDE M 00 1 150 001 15°
MOLD FLASH. N 0.51 r 1.02 0.020 I 0.040
L SUFFIX
CERAMIC PACKAGE
CASE 726
NOTES:
1. LEADS TRUE POSITIONEDWITHIN 0.25 mm
(0.010) DIA. AT SEATING PLANE AT MAX·
2. DIM. "L" TO CENTER OF LEADS WHEN
FORMEDPARALLEL.
3. DIM. "A" & "B" INCLUDESMENISCUS.
MILLIMETERS INCHES 1
DIM MIN MAX MIN MAX
A 22.35 23.11 0.880 0.910
B 6.10 7.49 0.240 0.295
C - 5.08 - 0200
D 0.38 0.53 0.015 0.021
F 1.40 1.78 0.055 0.070
G 2.54 sse 0.100 sse
H 0.51 1.14 0.020 0.045
J 0.20 0.30 0.008 0.012
K 3.18 4.32 0.125 0.170
L 7.62 sse 0.300 sse
M - 15° - 15°
N 0.51 1.02 0.020 10040
L SUFFIX
CERAMIC PACKAGE
CASE 732
t;~~-J~
F C [Lj DIM
MILLIMETERS
MIN MAX MIN
INCHES
MAX
-A?J'1\
A 2388 25.15 0940 0.990
-J - - -I-!-!-y.!
B 6.60 749 0.260 0.295
e 3.81
~ D 0.38
5.08 0.150 0.200
0.56 0015 0.022
I I I I I ~/~ F 1.40 1.65 0.055 0.065
SEATING . ../
f-_~_H__
--=-~LANE -j G f- K M r
G
H
2.54 BSC
0.51 127
0.100 sse
0020 0050
B
J 0.20 030 O.OOB 0.012
NOTES, K 3.18 4.06 0.125 0160
1. LEADS WITHIN 0.25 mm 10.010) L 7.62 SSC 0300 SSC
OIA, TRUE POSITION AT M 00 I 150 0° 15°
SEATING PLANE, AT MAXIMUM N 025 102 0.010 0040
MATERIAL CONDITION.
2. DIM L TO CENTE R 0 F LEADS
WHEN FORMED PARALLEL
3. DIM A AND B INCLUDES
MENISCUS.
P SUFFIX
PLASTIC PACKAGE
CASE 738
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
NOTES, A 2565 2718 1.010 1.070
1. DIMCA] IS DATUM. S 6.10 6.60 0.240 0.260
2. POSITIONAL TDL FOR LEADS; C 3.94 4.57 o 155 0.180
Itl~0.25 (O:OlOl(§jT IAel
0
F
0.38
1.27
0.56
1.78
0.015
0.050
0.022
0.070
3. IT] IS SEATING PLANE. G 2.54 8SC 0.1008SC
4. DIM "S" DOES NOT INCLUDE MOLD FLASH J 020 0.38 0.008 0.015
5. DIM [I] TO CENTER OF LEADS WHEN K 2.79 3.56 0.110 0.140
L 7.62 SSC 0300 SSC
FORMED PARALLEL.
M 0° 15° 0° 15°
6 DIMENSIONING AND TOLERANCING
PER ANSI Y14.5, 1973.
N 051 I 102 0.020 I 0.040
MilLIMETERS INCHES
P SUFFIX
DIM MIN MAX MIN MAX
PLASTIC PACKAGE
A 27.56 28.32 1.085 1.115
CASE 708 B 8.64 9.14 0.340 0.360
C 3.94 5.08 0.155 0.200
D 0.36 0.56 0.014 0.022
F 1.27 178 0050 0.070
G 2.54 sse 0.100 sse
H 1.02 1.52 0.040 0.060
J 0.20 0.38 0.008 0.015
K 2.92 3.43 0.115 0.135
l 10.16 sse 0.400 sse
M 0° 15° 0° 15°
N 051 1.02 0020 0040
NOTES:
1 POSITIONAL TOLERANCE OF LEAOS 101.
SHALL BE WITHIN 0.25mmI0.Ol0) AT
MAXIMUM MATERIAL CONOITiON. IN
RELATION TO SEATING PLANE ANO
EACH OTHER.
2. OIMENSION L TO CENTER OF LEADS
WHEN FORMEO PARALLEL.
3. OIMENSION B OOES NOT INCLUOE
MOLO FLASH.
L SUFFIX
CERAMIC PACKAGE
CASE 736
MilLIMETERS INCHES
DIM MIN MAX MIN MAX
A 26.80 27.81 1.055 1.095
B 9.14 9.91 0.360 0.390
C 3.81 5.46 0.150 0.215
D 0.38 0.53 0.015 0.021
F 127 165 0.050 0.065
G 2.54 sse 0.100 sse
H 0.51 1.27 0.020 0.050
J 0.20 0.30 0.008 0.012
K 3.18 4.32 0.125 0.170 NOTES:
1. LEAOS TRUE POSITIONED WITHIN 0.25 mm
l 9.91 10.41 0.390 0.410 (0.010) DIA. AT SEATING PLANE AT MAX·
M - 15° - 15° IMUM MATERIAL CONDITION (DIM "0").
2. DIM. "L" TO CENTER OF LEADS WHEN
N 0.25 0.89 0.010 0.035 FORMED PARALLEL.
L SUFFIX MILLIMETERS INCHES
CERAMIC PACKAGE DIM MIN MAX MIN MAX
CASE 623 A 31.24 32.77 1.230 1.290
B 12.70 15.49 0.500 0.610
C 4.06 5.59 0.160 0.220
D 0.41 0.51 0.016 0.020
[::::::::::u fitt'
F 1.27 1.52 0.050 0.060
G 2.54 sse 0.100 sse
J 0.20 I 0.30 0.008 0.012
K 3.18 I 4.06 0.125 0.160
L 15.24 sse 0.600 sse
M 0° I 15° 0° 15°
N 0.51 1.27 0.020 0.050
l-':~_.~ F A -- '_T!SEATINGPLANE NOTES:
1. DIM "L" TO CENTER OF
tF---+a LEADS WHEN FORMED
.,
-lGi-
~lC
_11-0
- - - __J-l.
N J --/
!~t~
l~\
M J-\'-
PARALLEL.
2. LEADS WITHIN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING
PLANEATMAXIMUM
MATERIAL CONIlITION.
K (WHEN FORMED PARALLEL)
P SUFFIX
PLASTIC PACKAGE
CASE 709
1It/f/IIIIJ!r.
,"'j.)
NOTES:
1 POSITIONAL TOLERANCE OF LEADS \01.
SMALL BE WITHIN 0 25 mm (00101 AT
MAXIMUM MATERIAL CONDITION. IN
RELATION TO SEATING PLANE AND
EACH OTHER
2 DIMENSION L TO CENHR OF LEADS
3 DIMENSION B DOES NOT INCLUDE MOLD
FLASH
P SUFFIX
MILLIMETERS INCHlL-
PLASTIC PACKAGE DIM MIN MAX MIN MAX
CASE 710 A -'6.45 37.1\ 1.435 1465
•C
13.71 14.11
3.94 508
0.540 0560
0.155 0100
0 036 0.56 0.014 0.011
F 101 151 0.040 0060
G 1.54 BSC 0.100 BSC
H 1.65 1.1S 0.065To.OB5
J 0.10 0.3B 0008 0.Q15
K 1.91 3.43 0.115 0.135
15.14 BSC 0.600 BSC
M D" 15° D" 15°
N 0.51 101 .9 010 0040
Cfi
NOTES:
1. POSITIONAL TOLERANCE IlF LEADS 101,
SHALL BE WITHIN 0.15mmI0.Ol01 AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER .
..J~ ..-!.-.{ K J - 1. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
o M 1 DIMENSION B ODES NOT INCLUDE
II
SIATI'tt:; __
'14,., MOLD FLASH.
L SUFFIX
CERAMIC PACKAGE
CASE 733
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 36.45 37.85 1.435 1.490
B 12.70 15.37 0.500 0.605
C 4.06 5.84 0.160 0.230
0 0.38 0.56 0.015 0.022
F 1.27 1.65 0.050 0.065
G 2.54 sse 0.100 sse
J 0.20 0.30 0.008 0.012
K 3.18 I 4.06 0.125 0.160
L 15.24 sse 0.600 sse
M 5° I 15° 5° I 15°
N 051 1 1.27 0.020 10.050
je C L-: NDTfS
/n:,t==\
I DIM L~ IS DATUM
1 POSITIONAL TOL FOR LEADS
[,"J II 0:RI~ion9n [""A"§.5I
Jl 1-
K M J
3 rn
5 DIM
IS SEATING PLANE
4 DIM A AND B INCLUDES MENISCUS
L· TO CENTER OF LEADS
P SUFFIX
PLASTIC PACKAGE MILLIMETERS INCHES
DIM MIN MAX MIN MAX
CASE 711 A 51.69 52.45 2.035 2.065
B 13.72 14.22 0.540 0.560
C 3.94 5.08 0.155 0.200
0 0.36 0.56 0.014 0.022
F 1.02 1.52 0.040 0.060
G 2.54 BSC 0.100 BSC
H 1.65 2.16 0.065 0.OB5
J 0.20 0.38 0.008 O. 15
K 2.92 3.43 O. 15 0.135
L 15.248SC 0.600 BSC
M 0" 15° 0° 15°
H 0.51 1.02 0.020 0.040
[::::::::::::::: ::IJleg
A
NOTES:
1 POSITIONAL TOLERANCE OF LEAOS 101.
SHALL BE WITHIN 0.25 mm (0.0101 AT
MAXIMUM MATERIAL rONOITION. IN
~~1~1
RELATION TO SEATING PLANE ANO
EACH OTHER.
1. OIMENSION L TO CENTER OF LEAOS
WHEN FORM EO PARALLEl.
3
3. OIMENSION B OOES NOT INCLUOE
\1111.·,,(,
MOLO FLASH.
L SUFFIX
CERAMIC PACKAGE
CASE 734
MILLIMETERS INCHES
DIM MTN MAX MIN MAX
A 51.31 53.24 2.020 2.096
B 12.70 15.49 O.SOO
-~
C 4.06 5.84 0.160 0.230
0 0.38 0.56 0.Q15 0.022 NOTES:
1.27 1.65 ,. OIM -A- ISOATUM.
F 0.050 0.065
2. POSITIONAL TOLERANCE FOR LEAOS:
G 2.54 BSC 0.1008SC
J 0.20 0.30 0.008 I 0.012 liI!:iliW.OIOI @I T I A@I
K 3.18 4.06 0.125 10.160 3 OJIS SEATING PLANE.
15.24 8SC 4. OIM L TO CENTER OF LEAOS WHEN
L 0.600 SSC
M 50 15° 50 r 150 FO RMEO PARALLEL.
5. OIMENSIONS A ANO B INCLUOE
N 0.51 1.27 0.020 I 0.050 MENISCUS.
Handling Precautions
Handling Procedures for CMOS Devices
Motorola CMOS devices have diode input protection against adverse electrical en-
vironments such as electrostatic discharge. In regards to this, the following statement
is included on each data sheet:
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields; however, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to
this high impedance circuit. For proper operation it is recommended that Vin and
Vout be constrained to the range VSS ~ (Vin or Vout) ~ VOO. Unused inputs
must always be tied to an appropriate logic voltage level (e.g., either VSS or
VOO)·
Unfortunately, severe electrical transient voltages can be generated during handling.

For example, static voltages generated by a person walking across a common waxed
floor have been measured in the 4 to 15 kV range (depending on humidity, surface con-
ditions, etc.). These static voltages are potentially dangerous when discharged into a
CMOS input, considering the energy stored in the capacity (= 300 pF) of the human
body at these voltage levels.
Present CMOS gate protection structures can generally protect against overvoltages.
This is usually sufficient except in the severe cases.
The input protection circuit, while adding some delay time, provides protection by
clamping positive and negative potentials to VOO and VSS respectively. Figure 1 shows
the internal circuitry for the diode-resistor protection.
The input protection circuit consists of a series isolation resistor RS, whose typical
value is 1.5 k.Q, and diodes 01 and 02, which clamp the input voltages between the
power supply pins VOO and VSS. Diode 03 is a distributed structure resulting from the
diffusion fabrication of RS.
In addition to the internal protection network, the following steps are recommended to
further reduce damage to CMOS integrated circuits due to improper handling.
1. All CMOS devices should be stored or transported in materials that are antistatic.
CMOS devices must not be inserted into conventional plastic "snow", styrofoam
or plastic trays, but should be left in their original container until ready for use.
2. The shipping rails are antistatically treated inside and outside. They provide ade-
quate protection during storage and test/assembly handling operations, but should
not be re-cycled as continuous use will cause deterioration of the antistatic
coating.
3. All CMOS devices should be placed on a grounded bench surface and operators
should ground themselves prior to handling devices, since a worker can be
statically charged with respect to the bench surface. Wrist straps in contact with
skin are strongly recommended. See Figure 2.
4. Nylon or other static generating materials should not come in contact with CMOS
circuits.
5. If automatic handling is being used, high levels of static electricity may be

generated by the movement of devices or boards. Avoid this by grounding suspect
areas and/or by the use of ionized air blowers, and/or air humidifiers.
6. Cold chambers using C02 for cooling should be equipped with baffles, and devices
must be contained on or in conductive material.
7. When lead-straightening or hand-soldering is necessary, provide ground straps for

the apparatus used and be sure that soldering ties are grounded.
8. The following steps should be observed during wave solder operations.

a. The solder pot and conductive conveyor system of the wave soldering machine
must be grounded to an earth ground.
II
NOTES: 1 1116 inch conductive sheet stock covering bench top work area.
2 Ground Strap.
3 Wrist Strap In contact with skin.
4 Static neutralizer. (loOlzed air blower directed at work), Pnmaoly for use in areas where
direct grounding IS impractical.
b. The loading and unloading work benches should have conductive tops which
are grounded to an earth ground.
c. Operators must comply with precautions previously explained.
d. Completed assemblies should be placed in antistatic containers prior to being
moved to subsequent stations.
9. The following steps should be observed during board cleaning operation.

a. Vapor degreasers and baskets must be grounded to an earth ground. Operators
must likewise be grounded.
b. Brush or spray cleaning should not be used.
c. Assemblies should be placed into the vapor degreaser immediately upon
removal from the antistatic container.
d. Cleaned assemblies should be placed in antistatic container immediately after
removal from the cleaning basket.
e. High velocity air movement or application of solvents and coatings should be
employed only when module circuits are grounded and a static eliminator is
directed at the module.
11. All low impedance equipment (pulse generators, etc.) should be connected to
CMOS inputs only after the CMOS is powered up. Similarly, this type of equipment
should be disconnected before power is turned off.
12. Equipment specifications should alert users to the presence of CMOS devices and
require familiarization with this specification prior to performing any kind of
maintenance or replacement of devices or modules.
1113
.
A circuit board containing CMOS devices is merely an extension of the device and
the same handling precautions apply. Contacting edge connectors wired directly
to CMOS device inputs can cause damage. Plastic wrapping should be avoided.
When external connections to a PC board address only an input of a CMOS in-
tegrated circuit, it is recommended that a resistance or 10 kQ or greater be used in
series with the input. This resistor will limit accidental damage if the PC board is
removed and brought into contact with static generating materials.
14. Do not insert or remove CMOS devices from test sockets with power applied.
Check all power supplies to be used for testing CMOS devices to be certain there
are no voltage transients present.
15. Double check test equipment setup for proper polarity of voltage before conduct-
ing parametric or functional testing.
Another type of precaution involves the CERDIPpackage. Since this device employs a
glass seal, a high stress on the leads can cause hermeticity failure which will eventually
result in aluminum corrosion on the die. To avoid this, the leads should never be flexed
above the seating plane. All insertion tools or automated equipment should contact the
lead at its narrowest dimension allowing it to bend without affecting the wide portion
above the seating plane.
15MIL /
MINIMUM WIDTH
II
Reliability and
Quality Assurance
Reliability and Quality Assurance
Motorola has an active Quality Improvement Program with the objective of improving
failure rates and permitting tighter AQLs. At the time of writing - 83Q2 - the follow-
ing data was applicable. For current data, please contact your Motorola Sales Office or
franchised Motorola distributor.
Functional/Parametric Combined 0.10% AQL Level II

Visual/Mechanical Combined 0.15% AQL Level II
Package Failure Rate in %/1000 hours at

Ambient Temperature:
500e 700e 85°e
Plastic 0.0003 0.0027 0.0109
Ceramic 0.0001 0.0006 0.0025
Our objective is to further improve our position as the quality leader in the supply of
semiconductor products.
Our strategies are:
1. Actively promote a quality conscious attitude and quality environment in all pro-
cess, manufacturing and support operations.
II
3. Maintain and improve programmes for the continuous improvement of outgoing
quality and reliability.
7. Further improve good working relationships with customers' quality/engineering

operations.
In order to assure conformance to specifications, and to assure high levels of quality
and reliability, there are R & QA activities in all parts of the production cycle.
Design and Wafer After

pre-production fabrication sales
Supporting all these activities is our product analysis group and providing supplemen-
tary support is our Hi-Rei operations group.
Quality Assurance starts before production commences. Within Motorola, all new pro-
duction related activities and modifications thereto must be specified, qualified and ap-
proved prior to implementation. The form of control is defined by the change, and dif-
ferent controls are used for suppliers, raw materials, processes, equipments, designs
and packages. Tables 2 and 3 list the qualification tests. Figure 1 shows two typical
qualification and approval flows, one for a new circuit and one for a process change.
Before approval is given, three consecutive lots must pass the tests. Once approved,
the specification is signed off and production can commence.
Test Condition Duration Reference
Electrical Endurance 125°C, 5V or 15V 1000 Hours BS9400

Temperature, Humidity 85°C, 85% R.H.
Bias 5V or 15V 1000 Hours -
Autoclave 121°C, 100% R.H. 240 Hours -
15 P.S.I.G.
High Temperature 150°C 1000 Hours BS9400 1.2.6.3
Storage
Thermal Cycle -65°C to 150°C 1000 Cycles BS9400 1.2.6.13
(Air to Air) 5 Min Dwell
Thermal Shock -65°C to 150°C 1000 Cycles BS9400 1.2.6.19
(Liquid to Liquid) 5 Min Dwell
1 500G, 3 per axis
0.5 mS BS9400 1.2.6.6/11
Shock & Vibration 20G, 1 50-2000Hz
2 Hours BS9400 1.2.6.8.1
per axis
1.85, 10-8 MIL STD 883
Hermeticity
STD CC/SEC
- Method 014.1
Visual Inspection - - BS9400 1.2.2.1
Dimensions - - BS9400 1.2.3
Marking
Permanency
- - BS9400 1.2.6.18
Solderability 230°C 3 Sec BS9400 1.2.6.15.1

Wire Bond Strength MIL STD 883,
(Post Seal)
1.5 Gram - Method 2011.1.C
Test Condition Duration Reference
Electrical Endurance 125°C, 5V or 15V 1000 Hours BS9400

Temperature, Humidity 85°C, 85% R.H.
Bias 5V or 15V 1000 Hours -
Autoclave 121°C, 100% R.H. 240 Hours -
15 P.S.I.G.
High Temperature 150°C 1000 Hours BS9400 1.2.6.3
Storage
Thermal Cycle -65°C to 150°C 1000 Cycles BS9400 1.2.6.13
lAir to Air) 5 Min Dwell -
Thermal Shock -65°C to 150°C ,
1000 Cycles BS9400 1.2.6.19
(Liquid to Liquid) 5 Min Dwell
1 500G, 3 per axis 0.5 mS BS9400 1.2.6.6/11
Shock & Vibration 150-2000Hz, 2 Hours BS9400 1.2.6.8.1
20G, per axis
Data Retention Bake
(Non Volatile 200/250°C 1000 Hours -
Memories)
FIGURE 1 - QUALIFICATION AND APPROVAL FLOW FOR A NEW CIRCUIT

AND A WAFER FABRICATION MODIFICATION
PROCESS CONTROL
PATTERNS
(OPTIONAl)
The Wafer fabrication process is a complex one, involving small geometries, physics,
chemistry and ultra high levels of purity and cleanliness. Figure 2 depicts the process
flow and highlights the major process steps. The quality assurance activities are de-
signed to give process control at each major process step, and to perform real time
evaluation of the process at intermediate points within the process.
The process control activities are:
1. Incoming inspection of raw materials.

2. Incoming inspection of masks.
3. Capacitance Voltage Drifts on Tubes/Product/Evaporator.
4. Oxide thickness/sheet resistance.
5. Vapox Chemical Vapour Deposition (Doped/Undopedl. thickness, % Phosphorous
and Integrity.
6. Gate oxide breakdown (Furnaces/Lomac).
7. Source bubbler monitor.
8. Gas bottle pressures.
9. Implant evaluation.
10. Furnace temp. profiles.
11. 4 Pt. Probe calibration check.
12. Spin Drier.
13. De-ionized water/bacteria monitor.
14. Mask clean inspection.
15. Photoresist equipment check, Resist thickness monitor, Pinhole check.
16. Scanning Electron Microscope - Surface profiles,
Junction depth.
17. Final visual inspection.
18. Shutter leakage, Metal thickness, Reflectivity, Sheet resistance and Monitors on
evaporators.
19. Fab environmental monitor - clean room and work stations.
20. Perkin Elmer aligner checks.
21. Junction depth monitor.
22. Oxidation induced stacking faults.
23. Quartzware check.
24. Monitor incoming acid quality.
25. Mylar burn and gas spectrum check on implanter.
26. Wafer analysis.
27. Electrical probe monitor.
These activities not only measure the characteristics of each lot, but also measure
trends within the process from which extrapolations are made to give forewarning of
potential problems. This feedback avoids reliability and quality problems and maintains
optimum operation of the Wafer fabrication facility.
P-Implant
Oxidation &
Drive-In
N + Deposition
Oxidation &
Drive-In
o In-Process Inspection
Assembly is highly automated - which benefits reliability and quality. In addition to the
100% screens, there are the following assembly quality activities:
1. Incoming inspection of raw materials.

2. Scribe audit.
3. Die high power visual inspection.
4. Die bond inspection.
5. Wire bond inspection.
6. Pre-cap inspection.
7. Hermeticity inspection.
8. Plating inspection.
9. Solderability.
10. Terminal strength.
11. Dimensions monitor.
12. Visual/mechanical inspection for flaws to body/leads.
13. Calibration monitor.
14. Moisture monitor.
An integral part of the assembly operation is to give every device a coded marking
which defines the assembly location, the Wafer fabrication lot and the assembly lot.
Thus it is possible to trace the history of every device.
FIGURE 3 - TYPICAL INTEGRATED CIRCUITS ASSEMBLY & FINAL TEST
FLOW CHART
After 100% electrical test, there is a final inspection before the product is shipped to
the warehouse. The inspection is
Functional/parametric combined 0.10% AQL Level 11*
Visual/mechanical combined 0.15% AQL Level 11*
Electrical parameters include all parameters on the data sheet. Visual/mechanical in-
cludes marking legibility, plating, dimensions, etc. We even include the orientation of
the devices within the tube!
We believe these are the best AQLs for standard CMOS product in the Semiconductor
Industry, and our objective is to maintain this position.
In addition, Motorola has a series of weekly audits as follows:
1. Finished goods.
2. Marking/marking permanency.
3. Hermeticity.
4. Dimensions.
5. Outgoing shipments.
6. Specifications/procedures.
7. Static protection.
8. General housekeeping.
9. Calibration.
The combination of audits and lot inspection is designed to give maximum protection to
our customers. Feedback from our customers shows that they find a reject rate of
typically less than 200 PPM, i.e. 1 failure in every 5,000 parts supplied. At this low
level, incoming inspection is not cost efficient and it is possible to reduce or eliminate
incoming inspection.
Of equal importance to incoming quality is product reliability. Motorola has a com-
prehensive reliability program which assesses all aspects of product reliability. The pro-
gram comprises the following periodic tests which are designed to provide mechanical,
environmental and electrical stresses which will accelerate the life cycle into a short
period:
Visual inspection.
Dimensions.
Marking permanency.
Resistance to cleaning fluids.
Solderability and plating.
Acceleration.
II
Wire bond.
Hermeticity.
Thermal shock.
Temperature cycling.
Mechanical shock and vibration.
Flammability.
High temperature storage.
High temperature electrical endurance.
Temperature/humidity /bias.
Pressure/temperature/humidity.
The most significant test is high temperature electrical endurance which is performed at
125°C with the application of a 15V static bias in accordance with the truth table of
the individual device. This test accelerates any inherent die related failure mechanisms.
Electrical tests to Motorola Data Sheet specifications are used to measure the perfor-
mance of the devices. The number of failures at the 1,008 hour readout (including both
parametric downgrades and catastrophics) are extrapolated to a lower temperature to
provide a failure rate at 85°C. The mathematical models employed to predict this are
detailed in the appendix to this chapter.
TABLE 4 - HIGH TEMPERATURE ELECTRICAL ENDURANCE RESULTS

FOR PLASTIC PACKAGES (1982)
No. of No. of No. of Equivalent No. of Failure Rate

Batches Devices Device Device Failures 0/0 I 1,000 hours
Hours Hours - - - Temperature- --
at 125°C at 85°C 50°C 70°C 85°C
35 3,302 3.33M 86.31 M 8 0.0003 0.0027 0.0109

(380 years) (9,850 years)
I I
The failure rate at 85°C of 0.0109% /1,000 hours (or a mean time between failures of
1,047 years) is graphed in Figure 4 and compares favourably with our 1981 standard
of 0.030% / 1,000 hours.
TABLE 5 - HIGH TEMPERATURE ELECTRICAL ENDURANCE RESULTS

FOR CERAMIC PACKAGES (1982)
No. of No. of No. of Equivalent No. of Failure Rate

Batches Devices Device Device Failures 0/0 I 1,000 hours
Hours Hours - - - Temperature- --
at 150°C at 85°C 50°C 70°C 85°C
25 2,394 2.41M 350.15M 9 0.0001 0.0007 0.003

(275 years) (39,971 years)
I I
The failure rate at 85°C of 0.003% /1,000 hours (or a mean time between failures of
3,805 years) is graphed in Figure 4 and is impressingly low when compared with our
1981 standard of 0.014% / 1,000 hours.
The steady reduction of plastic and ceramic failure rates reflects Motorola's commit-
ment to reliability and quality improvement. The improvements are such that many
customers who previously purchased burnt-in components now achieve the same or
better reliability using Motorola CMOS without burn-in.
It is recommended that hermetic ceramic product be used in extreme high temperature

or humidity environments. Plastic product will provide similarly excellent reliability for
lower cost in more normal operating conditions.
All plastic packaged devices are intrinsically non-hermetic as moisture can penetrate
the lead frame/package seal interface or diffuse through the bulk of the plastic. If water
reaches the surface of the chip and a bias is applied, an electrolytic cell is set up. Corro-
sion of the aluminium tracks/bond pads can occur which can downgrade the device
Failure Rate 7
vs
Temperature / "
/
/
/
/ /
/ /
10-3
Plastic
J /
t!
5
,
J: / 7
0
0
0
0-
/ / Ceramic
j.
!
ex:
10-4 / /
!
.2
..."c ,
/ /
/ /
7
/ I
I [I
I /
/ /
1/ / Activation Energy 1.0 eV
Confidence Limit 60%
I
,
I
I
j
V
1
105 115 125
parameters and lead to catastrophic (open metal) failures. This phenomenon is ac-
celerated by the presence of contaminants and Motorola is careful to minimize this ef-
fect by the use of quality grade materials/packaging and meticulous housekeeping. The
tests which best monitor the environmental related performance of the plastic package
are Temperature Humidity Bias, Autoclave, and Thermal Shock.
This environmental test is the most reliable method of highlighting any die/package in-
compatibility. It is performed at 85°C, 85% Relative Humidity with the application of a
static bias of 15V. The conditions of this test are far in excess of those ever expected to
be experienced by the device in a normal operating environment. The results below are
for 1982. It should be noted that there are a number of die and package modifications
pending which are expected to provide further significant improvements in the results.
TABLE 6 - TEMPERATURE HUMIDITY BIAS RESULTS

FOR PLASTIC PACKAGES (1982)
No. of No. of % Total Cumulative failure (test hours)

Batches Devices
168 336 504 774 1,008
3 378 0.31 0.31 0.63 0.63 0.94
% Cumulative Corrosion failures
3 378 0.31 0.31 0.31 0.31 0.63
The small number of failures due to corrosion of the metallization is a result of the close-
ly matched package components. The remaining rejects show the same failure modes
as noted for electrical endurance. These results are an improvement on those recorded
previously and verify that no new failure patterns have emerged in house or should be
expected in the field.
The conditions of this test are 121°C, 15 p.s.i.g. and 100% Relative Humidity. It is a
moisture resistance test without bias and is used to evaluate the durability of the plastic
package under extremely high temperature and humidity conditions. This test is used as
an ongoing assembly process monitor and supplements the T.H.B. corrosion failure
results. In view of the highly accelerated test environment and the fact that very small
changes in these test conditions can have a dramatic effect on the end results, the data
is included for information only.
No. of No. of % Cumulative failure (test hours)

Batches Devices
24 48 96 148 168
4 347 0.00 0.00 0.00 0.00 0.58

The Autoclave results augment those recorded for T.H.B. performance and demon-
strate the moisture resistant nature of the Motorola plastic encapsulated devices under
extreme conditions.
Thermal shock provides a quick and severe method of stress and is a liquid to liquid cy-
cle between -65°C to + 150°C with a dwell of five minutes at each temperature.
No. of No. of % Cumulative failure (test cycles)

Batches Devices
200 1,000
2 250 0.00 0.00
The results verify the plastic mould compound, bond wires and lead frames have closely
matched coefficients of expansion. This benefit reduces the potential of moisture in-
gress (e.g. during the T.H.B. test) within the package ensuring a stable encapsulant for
~he die.
There is one further important source of quality and reliability data-feedback from our
customers!
Customer feedback is obtained from incoming inspection and qualification results and
from returned defective product.
a) With certain customers who use large quantities of CMOS, Motorola has reached
agreement on joint quality improvement programs. These programs are basically an
exchange of information. Our customers provide feedback by device type on the
quality and reliability of our product. Analysis of this feedback highlights problems
not previously apparent, and corrective action is implemented. Both Motorola and all
our customers have benefitted from these programs. The incoming quality level as
reported by these customers is typically less than 200 PPM.
b) Due to the high quality of our product, it is possible to analyse every return of defec-
tive product. Approximately 40% of these are in fact non-defective and are the
result of correlation problems. Some of the returns have been mishandled (see
Chapter 4). the remainder are analysed to determine where action can be taken to
improve the outgoing quality.
Product analysis is used at all stages of manufacturing-from pre-production to after

sales-to determine failure mechanisms and how to avoid them. Various techniques are
Examination of the die surface (high
magnification), local chemical analysis
with spectrometry
used and our failure analysis laboratory is well equipped with a variety of equipment
including scanning electron microscopes, X-ray analysers and micromanipulative
probers. Figure 5 shows the flow used for finished product.
Motorola's Hi-Rei programs-for avionic, space and military applications-has indirect-

ly provided a considerable contribution to our commercial products. The Hi-Rei pro-
grams set the standards for the control of quality and the assessment of reliability, and
at Motorola we use these standards for our commercial product as well as our Hi-Rei
product. At the time of writing, Motorola has the following approvals for CMOS pro-
duct:
DEF STAN 05/31 - MOD Registration 1G9M01

DEF STAN OS/21 - MOD Registration 1G9M01
BSI App. No.1 085 M
CECC App. No. M0070/CECC/UK 1085 M
With design and manufacturing facilities in the U.S.A., Japan and Europe, Motorola's
experience in CMOS is unsurpassed. In Europe alone, Motorola has shipped over
500,000,000 CMOS devices. The levels of quality and reliability which we have
achieved are extremely high. Through our quality improvement program, we will
achieve even higher levels for the benefit of you, our customer.
Two mathematical models are employed to predict the failure rate. Firstly it is assumed
that the failure rate distribution follows an exponential probability density function.
F(X) = A. EXP I-A. t)
where F(X) probability density function
A. failure rate
t time
Since reliability evaluations usually involve random samples of a population, a point

estimation for the failure rate is calculated using the Chi-squared distribution.
):2 (a, 2r + 2), a = (100 - Cl)

2nt 100
where ):2 tabulated value

Cl confidence limit in percent
number of rejects
number of devices
t duration of the test
A confidence limit of 60% is employed in the formula.
The second model uses the Arrhenius Equation to relate the failure rate at test
temperature to that expected at normal operating conditions.
R(T) = Ro EXP (Ea / kT)
where R(T) = reaction rate at normal temperatures
Ro a constant
Ea activation energy (1eV)
k Boltzmann's constant
T junction temperature
The use of junction temperatures rather than ambient (Iifetest) temperature provides a
more accurate failure rate. The junction temperature is computed using the equation
below:
T(J) T(A) + (P x eJA)
where T(J) = junction temperature (0 C)
T(A)= ambient temperature (0 C)
P power (Watts)
eJA = average junction to ambient thermal resistance (0 C/W)
Publications and Applications
Additional information on CMOS products can be found in the following publications
available at your nearest Motorola Sales Office or Distributor.
B001 AID and 01A Conversion Manual

B002A CMOS Data Manual, Volume 1, Standard Logic
B002C CMOS Data Manual, Volume 3, High Speed CMOS
B003A Home Electronics I Integrated Circuits
B011 Memory Data Manual
B025 The European Master Selection
B039 Telecommunications Data Manual
F045 Telecommunications, A System Approach

F055 High Speed CMOS Function Selector Guide
F060 Catalog of Technical Literature
F062 CMOS Standard Logic Reliability Report
F072 Macrocell Arrays and CAD
F075 CMOS Function Selector Guide
F077 High Speed CMOS Life Test
A complete list of Application Notes can be found in the Catalog of Technical Literature
(Reference F0601.
AN-471 Analog-to-Digital Conversion Techniques.
The subject of AID conversion and many of the techniques that can be used
to accomplish it are discussed. The paper is written in general terms, from a
system point of view, and is intended to assist the reader in determining
which conversion technique is best suited for a given application.
II
AN-535 Phase-Locked Loop Design Fundamentals.
The fundamental design concepts for phase-locked loops implemented with
integrated circuits are outlined. The necessary equations are given in conjuc-
tion with a brief design example.
AN-71 6 Successive Approximation A/D Conversion.
This Application Note concerns the successive approximation type of A/D
Converter. The questions of why, how and where to use the successive ap-
proximation technique are discussed along with the basic theory of opera-
tion.
AN-741 Interface Considerations for Numeric Display Systems.

This note describes several methods of multiplexing multi-digit, seven-
segment. LCD, LED, GAS discharge, incandescent and fluorescent displays.
Interfaces and interface considerations are described in detail.
AN-759 A CMOS Keyboard Data Entry System for BUS Oriented Memory Systems.
This Application Note describes a keypad to binary data entry system for use
with CMOS or NMOS memories, either in minicomputer/microprocessor ap-
plication or as a part of any logic system containing random access memory.
Manual data entry using a keyboard avoids the use of a binary format, offer-
ing increased speed and accuracy of manual direct memory accessing.
AN-769 Autoranging Digital Multimeter Using the MC14433 CMOS A/D Converter.
This Application Note describes an autoranging DMM using the MC14433.
The multimeter includes AC and DC voltage ranges from 200mV to 200V,
AC and DC current from 2mA to 2A full scale, and resistance ranges from
2kQ to 2MQ full scale.
AN-770 Data Acquisition Networks with NMOS and CMOS.

This article describes an eight-channel data acquisition network using the
MC14433 A/D Converter and the MC6800 Microprocessor family. The A/D
conversion technique is a modified dual ramp featuring auto-zero, auto-
polarity, and high input impedance. Both hardware and MC6800 software
are shown.
AN-806 Operation of the MC14469

The MC 14469 is an addressable asynchronous receiver/transmitter that
finds applications in control of remote devices, transfer of data to and from
remote locations on a shared wire and as an interface from remote sensors to
a central processor.
AN-874 Macrocell Arrays: Concept-Features-CAD Interface.

High technology array based products offer the advantages of custom cir-
cuits, yet overcome the problems of high costs and long design cycles. Re-
cent developments in array technology make use of Macrocell building
blocks rather than primitive gates for easier design and higher performance.
Additional developments in computer-aided-design customer interface
II
•
systems simplify the job of developing array circuit options. This note ex-
amines Motorola's Macrocell array concept with special emphasis on the
CAD user interface.
AN-889 An Easy-to-Use Development System for the Engineer Utilising a
Microprocessor in a System Design.
This application note describes such a system for the MC 14500B industrial
control unit. The system features keyboard Data/Address entry, 256 pro-
gram steps, 7-segment readout and all CMOS construction, with flexibility
for expansion and modification.
HB-209 MC14500B Industrial Control Unit Handbook

Design and application manual for the MC14500B. Contains chapters on
software, hardware and systems.

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Publications and Applications

CMOS DATA MANUAL

Volume 3 contains data on High Speed CMOS.

Lists the publications available from Motorola Semiconductors.

AL 3 to 18 V, - 55 to + 125°C, Ceramic Package

Device Function Suffix Pins Page

MC54HCXXX High Speed CMOS Series .............................. J 0

x See the 8-Bit Microprocessors Data Manual.

MC14020B 14-Bit Binary Counter .................................. AL,CL,CP 16

MC14076B Quad D-Type Register .................................. AL,CL,CP 16

* See the CMOS Data Manual, Volume 1, Standard Logic.

Note A: Add Suffix 1 or 2. Example MC14413L2.

MC14530B Dual 5-lnput Majority Logic Gate .................... AL,CL,CP 16

40014B See MC14584B - Normally Pin for Pin

MC145107 PLL Frequency Synthesizer ........................... P 16 2-269

x See the 8-Bit Microprocessors Data Manual.

MCM14505 64 x 1-Bit Static RAM .......................... AL,CL,CP 14 2-116

+ See the Memory Data Manual.

Note D: Available only by special order.

MCM14505 64 x 1-Bit Static RAM . 2-116

PLL Frequency Synthesizer

A/D, D/A Converters/Logic Functions

MC144104 High Performance Remote Control Transmitter . 2-225

MC6220 4-Bit Microcomputer Unit with PLL Frequency Synthesizer . §

Device Programming 4-Bit 4-Bit 4-Blt

HCOO Quad 2-lnput NAND Gate LSOO 4011 LS 14

HC04 Hex Inverter LS04 *4069 LS/CMOS 14

HC85 4-Bit Magnitude Comparator LS85 *4585 LS 16

HC292 Programmable Frequency Divider/ LS292 LS 16

HC73 Dual J-K Flip-Flop with Reset LS73A *4027 LS 14

HC164 8-Bit Serial Input/Parallel Output LS164 *4034 LS 14

HC160 Programmable Decade Counter, LS160A 4160 LS/CMOS 16

HC123 Dual Retriggerable Monostable LS123 *4538 or LS 16

HC139 Dual 1-of-4 Decoder LS139 4555 LS/CMOS 16

HC173 4-Bit D-Type Register, 3-State LS173 4076 LS/CMOS 16

HCT138 1-of-8 Decoder/Demultiplexer LS138 *4028 LS 16

HC151 8-Channel Digital Multiplexer LS 151 *4512 LS 16

This device contains circultrv to protect

VDD AL CLlCP TYPlcill AL CLlCP

Output RIse Time tTLH ns

Input Resistance - PCA1n Aon 5.0 1.0 1.0 2.0 Mn

Maximum Frequency fmax 5.0 0.50 0.35 0.70 - MHz

- VCOln Aon 15 150 50 1500 MIl

DynamiC Resistance (lz '" 1 mAl

• The formulae given are for the typical characteristics only.

CIw,.et_istic Using Pha •• Comperltor 1 Using P•••• Com •••• eto< 2

Signel input noise rejection. High Low

Oepends on low-pess filter characteristics fC -fL

Note: These equ.tlon. ~re intended

compotMlnt Velues may be in error

PHASE LOCK EO LOOP - LOW PASS FILTER DESIGN

DEFINITIONS: N = Total Division Ratio in feec'back loop

Note: for further information. see: -VOH

The MC14411 bit rate generator is constructed with complementary

• Single 5.0 Vdc (±5%l Power Supply

External Clock May be Applied to Pin 21

• Internal Pullup Resistor on Reset Input

Rating Symbol Value Unit F7 21 Xta1in

Not Used 14 F12

1VO = 0.5 or 4.5 Vdcl VIH 5.0 3.5 - 35 2.75 - 3.5 - V

Output Drive Current

1VOL =0.4 VI Sink IOL 5.0 0.23 - 020 0.78 - 0.16 - mA

tFor dissipation at different external capacitance (eL) refer to corresponding formula: