Combinational Logic Gates in CMOS

References:
Adapted from: Digital Integrated Circuits: A Design
Perspective, J. Rabaey, Prentice Hall © UCB
Principles of CMOS VLSI Design: A Systems Perspective,
N. H. E. Weste, K. Eshraghian, Addison Wesley
Adapted from: EE216A Lecture Notes by Prof. K. Bult ©
UCLA
 Design Techniques for Large Fan-In

• Transistor Sizing
• Progressive Transistor Sizing
• Transistor Ordering
• Logic Design to reduce the gate fan-in
 Progressive Sizing

• When parasitic capacitance

Out
is significant (e.g., when fan-
in is large), needs to lnN MN

consider distributed RC
effect
ln3 M3
• Increasing the size of M1 has
the largest impact in terms of ln2 M2
delay reduction
ln1 M1
• M 1 > M2 > M 3 > … > M N
 Delay Optimization by Transistor Ordering

Critical path Critical path

Out Out

lnN MN ln1 M1

ln3 M3 ln3 M3

ln2 M2 ln2 M2

ln1 M1 lnN MN

Critical signal next to supply Critical signal next to output

 Improved Logic Design

Reduce the fan-in to each gate

 Example: F = ((A + B + C).D)

D which path is the slowest ?

B

C
output

A B C
 Example: F = ((A+B +C).D )

D
B
Slowest path
C

A B C Alternatives ?

If minimum-size: tdr 6 tdf,inv

tdf,inv = delay of a minimum inverter
 Example: F = ((A+B+C).D)

D
If minimum-size: tdr 7 tdf.inv
this approach is advantageous if driving larger load
 Design of an 8-Input AND

Approach 1

Approach 2

Approach 3
3-input NAND Gate with Parasitic Capacitors

P1 P2 P3
out

inc Cc Cp+load

N3
Cb
inb

N2
Ca
ina
N1
Macro Modeling for Worst Case Analysis

tdf = [RN1Ca] + [(RN1+RN2)Cb] + [(RN1 + RN2 + RN3)Cc] +

[(RN1 + RN2 + RN3)Cp + [(RN1 + RN2 + RN3)Cload]

Internal delay External load

td = Td, internal + x Cload

 Macro Modeling

2
m m mR N
t df RN C j ( mpC j
CL )
2 n
m: fan-in
n: sizing factor of NMOS transistors
p: sizing factor of PMOS transistors

Cinv,min = total gate capacitance of minimum size inverter

k = “fan-out” corresponding to CL
Cj = r Cinv,min

2 2
(m m )C j m pC j mkC inv , min
t df RN
2 n n

Keep m2 and m2p/n and mk/n reasonable

 Macro Modeling for NOR Gate

2 2
(m m )C j m nC j mkC inv , min
t dr , NOR RP
2 p p

Keep m2 and m2n/p and mk/p reasonable

mpC j kC inv , min

t df , NOR R N mC j
n n

Keep n as small as possible to minimize the impact on rise-delay

 Design Strategy

• Use minimum sized transistors

• Analyze critical path (slowest, maybe more than 1)
• Look at alternative implementations (substitute
NOR’s ?)
• Compare and choose best
• Analyze critical path(s) and optimize transistor
sizing
 Complementary Logic

• 2n transistors
• Complicated wiring
• No functional sizing required
Ratioed Logic
 Ratioed Logic

Reduce the number of devices over complementary logic

 Ratioed Logic

• Use PDN to implement the function (which is the

negation of the network)
• Total number of devices: n for the input, 1 for the
static load
• Minimum load is 1 unit-gate load
• Functional sizing is required to optimize noise margin
Functional Sizing in Ratioed Logic

• N transistors
• VOH = VDD

R PDN
• V OL V DD
R PDN RL

• Asymmetrical response
• Static power consumption
• tpLH = 0.69 RLCL
• tpHL = 0.69 (RL || RPDN) CL
 Current Source as the Static Load

C LV swing / 2
t pLH
I ave
• If current source equals VDD/RL
F
= initial charging current from
the resistive load
In1
C L RL
In2 PDN t pLH
In3 2

• More than 25% reduction

compared to resistive load
 Load Lines of Ratioed Gates

1
C urrent source

0 .7 5
I L (N o rm a lize d )

P seudo-N M O S
0 .5

D epletion load
0 .2 5
R esistive load

0
0 .0 1 .0 2 .0 3 .0 4 .0 5 .0
V o u t (V )
 NMOS Depletion Load

Use depletion mode NMOS transistor as pull-up

Vtdep of depletion transistor is < 0 V

The depletion mode transistor is always ON:

gate and source connected Vgs = 0

Vin = 0 transistor pull down is off Vout is high

 Voltage Output Low

Driver is in linear region with input high

Load is in saturation region
2
V OL load 2
driver
(V DD V tn )V OL ( V tdep )
2 2

Assume: VDD = 5.0V

Vtn = 1.0V = - Vtdep

Proper design: Vol < Vtn

Let: Vol = 0.5V

driver
0 . 267
load
 Gate Threshold Voltage

Gate threshold voltage = Vinv

= Input voltage at which Vin = Vout
Assume that both driver and load are in saturation with input Vinv

driver 2
I DS ( sat ) (V gs Vt )
2
driver 2 load 2
(V inv Vt ) ( V dep )
2 2

load
Hence, V inv Vt V dep
driver

If driver is increased relative to load then, Vinv decreases

PMOST Load with Constant VGS
Voh = 5.0V

Vol = ???

I = 0.5 p.(Vdd-Vtp)2

I= n Vdd-Vtn)Vol-0.5Vol2
2
n
0 . 5 (V dd V tp )
2
p ((V dd V tn )V ol 0 . 5V ol )
 Sizing for VOL
2
n
0 . 5 (V dd V tp )
2
p ((V dd V tn )V ol 0 . 5V ol )

Assume: Vdd = 5.0V

Vtn = Vtp = 1.0V

Proper design: Vol < Vth

Let: Vol = 0.5V

n
4 . 26
p
 Sizing for Gate Threshold Voltage

N-device: saturated (V out V in V tn )

n 2
I dsn (V in V tn )
2

P-device: non-saturated
V gsp V DD
2
(V out V DD )
I dsp p
[( V DD V tp )(V out V DD ) ]
2
Equating the two currents we obtain,
2
n 2 (V out V DD )
(V in V tn ) p
[( V DD V tp )(V out V DD ) ]
2 2
 Sizing for Gate Threshold Voltage

Solving for Vout

2
V out V tp (V DD V tp ) C

Where C = k (Vin - Vtn)2

n
k
p

2 2
(V DD V tp ) (V out V tp )
Also, n
2
p
(V in V tn )

To make gate threshold voltage = 0.5VDD

n
6 . 11
p
Forcing the Voltage Output Low
 Propagation Delay of Pseudo-NMOS Inverter

• Use average current

2
1 P 2 V DD V DD
I av ( L H) ( V DD V tp ) P
( V DD V tp )( ) ( )
2 2 2 8

2
1 N 2 V DD V DD
I av ( H L) (V DD V tn ) N
(V DD V tn ) P
(V DD V tn ) ( N P
)
2 2 2 8

• Propagation delay
C L (V DD / 2 )
tp
I av
 Power Consumption

• Consume power when the output is low

P 2
I av , low ( V DD V tp )
2

P 2
Pav , low V DD I av , low V DD (V DD V tp )
2
 Trade-offs to be Considered

• To reduce static power, ILoad should be low

• To obtain a reasonable NML, VOL = ILoadRPDN should
be low
• To reduce tpLH CLVDD/(2ILoad), ILoad should be high
• To reduce tpHL 0.69 RPDNCL, RPDN should be kept
small
 Pseudo-NMOS NOR Gate

A B C D

• Fan-in of N inputs requires only N+1 transistors,

smaller parasitic capacitance and area
• Smaller load to preceding gate
• Static power consumption at output low
• Pseudo-NMOS gates can be used effectively when
speed is importance and majority of the output is high
Pseudo-NMOS NAND Gate

VDD

GND
 Improved Loads (2)

VDD VDD

M1 M2

O ut O ut

A
A
PDN1 PDN2
B
B

V SS V SS

D ual C as cod e V oltage Sw itc h L ogic (D C V S L )

 Example

O ut

O ut

B B B B

A A

X O R -N X O R gate