//////////////////////////////////////////////////////////////////////////////////

module srff_327(rst,clk,s,r,q_327,qb );
output reg q_327;
output qb;
input rst,clk,s,r;
always@(posedge clk)
begin
if(rst) q_327<=0;
else if(s==0&&r==0) q_327<=q_327;
else if(s==0&&r==1) q_327<=0;
else if(s==1&&r==0) q_327<=1;
else q_327<=1'bx;
end
assign qb=~q_327;
endmodule

module srf_327_test;

// Inputs
reg rst;
reg clk;
reg s;
reg r;

// Outputs
wire q_327;
wire qb;

// Instantiate the Unit Under Test (UUT)

srff_327 uut (
.rst(rst),
.clk(clk),
.s(s),
.r(r),
.q_327(q_327),
.qb(qb)
);
always

#5 clk=~clk;

initial
begin

$monitor($time,"output q=%b qb=%b:input rst=%b s=%b r=%b",q_327,qb,rst,s,r);

// Initialize Inputs
rst = 1;
clk = 0;
s = 0;
r = 0;
 // Wait 100 ns for global reset to finish
#7 rst=0;
#5 r=1;
#10 s=1;r=0;
#10 r=1;
#10 $stop;

// Add stimulus here

end

endmodule
//////////////////////////////////////////////////////////////////////////////////
module jkff_327(q_327,qb,rst,clk,j,k);
output reg q_327,qb;
input rst,clk,j,k;
always@(posedge clk)
begin
if (rst==1) begin q_327=0; qb=1;end
else if (j==0&&k==0) begin q_327=q_327; qb=qb;end
if (j==0&&k==1) begin q_327=0; qb=1;end
if (j==1&&k==0) begin q_327=1; qb=0;end
if (j==1&&k==1) begin q_327=~q_327; qb=~qb;end
end

endmodule
module jkff_327_test;

// Inputs
reg rst;
reg clk;
reg j;
reg k;

// Outputs
wire q_327;
wire qb;

// Instantiate the Unit Under Test (UUT)

jkff_327 uut (
.q_327(q_327),
.qb(qb),
.rst(rst),
.clk(clk),
.j(j),
.k(k)
);
always
#5 clk=~clk;
 initial begin
$monitor($time,"output q=%b qb=%b:inputs rst=%b j=%b k=%b",q_327,qb,rst,j,k);
// Initialize Inputs
rst = 1;
clk = 0;
j = 0;
k = 0;

// Wait 100 ns for global reset to finish

#7 rst=0;
#10
#5 k=1;
#10 j=1;k=0;
#10 k=1;
#10 $stop;

// Add stimulus here

end

endmodule
//////////////////////////////////////////////////////////////////////////////////
module dff_327(q_327,qb,rst,clk,d );
output reg q_327;
output qb;
input rst,clk,d;
always@(posedge clk)
begin
if (rst==1) q_327=0;
else if (d==0) q_327=0;
else if (d==1) q_327=1;
end
assign qb=~q_327;
endmodule

module dff_327_test;

// Inputs
reg rst;
reg clk;
reg d;

// Outputs
wire q_327;
wire qb;

// Instantiate the Unit Under Test (UUT)

dff_327 uut (
.q_327(q_327),
.qb(qb),
 .rst(rst),
.clk(clk),
.d(d)
);
always
#5 clk=~clk;

initial
begin
$monitor($time,"output q=%b qb=%b : inputs rst=%b d=%b",q_327,qb,rst,d);
// Initialize Inputs
rst = 1;
clk = 0;
d = 0;

// Wait 100 ns for global reset to finish

#7 rst=0;
#15 d=1;
#10 d=0;
#10 d=1;
#10 $stop;

// Add stimulus here

end

endmodule
//////////////////////////////////////////////////////////////////////////////////
module tff_327(q_327,qb,rst,clk,t );
output reg q_327;
output qb;
input rst,clk,t;
always@(posedge clk)
begin
if(rst==1) q_327=0;
else if(t) q_327=~q_327;
end
assign qb=~q_327;

endmodule
module tff_327_test;

// Inputs
reg rst;
reg clk;
reg t;

// Outputs
wire q_327;
wire qb;
 // Instantiate the Unit Under Test (UUT)
tff_327 uut (
.q_327(q_327),
.qb(qb),
.rst(rst),
.clk(clk),
.t(t)
);
always
#5 clk=~clk;

initial begin
$monitor($time,"output q=%b qb=%qb : inputs rst=%b t=%b",q_327,qb,rst,t);

// Initialize Inputs
rst = 1;
clk = 0;
t = 0;

// Wait 100 ns for global reset to finish

#7 rst=0;
#5 t=1;
#10 t=0;
#10 t=1;
#10 $stop;

// Add stimulus here

end

endmodule