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October 2006
FDD4685 tm
Application
Inverter
Power Supplies
D G
G
S
D
TO-PA K
-2 52
(TO -252) D
Thermal Characteristics
RθJC Thermal Resistance, Junction to Case 1.8
°C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 40
Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = –250µA, VGS = 0V –40 V
∆BVDSS Breakdown Voltage Temperature
ID = –250µA, referenced to 25°C –33 mV/°C
∆TJ Coefficient
IDSS Zero Gate Voltage Drain Current VDS = –32V, VGS = 0V –1 µA
IGSS Gate to Source Leakage Current VGS = ±20V, VGS = 0V ±100 nA
On Characteristics (Note 2)
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = –250µA –1 –1.6 –3 V
∆VGS(th) Gate to Source Threshold Voltage
ID = –250µA, referenced to 25°C 4.9 mV/°C
∆TJ Temperature Coefficient
VGS = –10V, ID = –8.4A 23 27
rDS(on) Static Drain to Source On Resistance VGS = –4.5V, ID = –7A 30 35 mΩ
VGS = –10V, ID = –8.4A, TJ=125°C 33 42
gFS Forward Transconductance VDS = –5V, ID = –8.4A 23 S
Dynamic Characteristics
Ciss Input Capacitance 1790 2380 pF
VDS = –20V, VGS = 0V,
Coss Output Capacitance 260 345 pF
f = 1MHz
Crss Reverse Transfer Capacitance 140 205 pF
Rg Gate Resistance f = 1MHz 4 Ω
Switching Characteristics
td(on) Turn-On Delay Time 8 16 ns
VDD = –20V, ID = –8.4A
tr Rise Time 15 27 ns
VGS = –10V, RGEN = 6Ω
td(off) Turn-Off Delay Time 34 55 ns
tf Fall Time 14 26 ns
Qg(TOT) Total Gate Charge VDD =–20V, ID = –8.4A 19 27 nC
Qgs Gate to Source Gate Charge VGS = –5V 5.6 nC
Qgd Gate to Drain “Miller” Charge 6.1 nC
Notes:
1: RθJA is the sum of the junction-to-case and case-to- ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
RθJC is guaranteed by design while RθJA is determined by the user’s board design.
a. 40°C/W when mounted on a 1 in2 pad of 2 oz copper
b. 96°C/W when mounted on a minimum pad.
2: Pulse Test: Pulse Width < 300µs, Duty cycle < 2.0%.
3: Starting TJ = 25°C, L = 3mH, IAS = 9A, VDD = 40V, VGS = 10V.
VGS = -4V
2.2
NORMALIZED
60 VGS = -4.5V VGS = -4.5V
1.8
VGS = -4V VGS = -6V
40
1.4
20 VGS = -10V
1.0
VGS = -3V
0 0.6
0 1 2 3 4 0 20 40 60 80 100
-VDS, DRAIN TO SOURCE VOLTAGE (V) -ID, DRAIN CURRENT(A)
1.8
DRAIN TO SOURCE ON-RESISTANCE
ID =-8.4A 70
VGS = -10V ID = -8.4A PULSE DURATION = 80µs
50
1.2 TJ = 125oC
1.0 40
0.8 30
TJ = 25oC
0.6
-50 -25 0 25 50 75 100 125 150 20
2 3 4 5 6 7 8 9 10
TJ, JUNCTION TEMPERATURE (oC)
-VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance Figure 4. On-Resistance vs Gate to
vs Junction Temperature Source Voltage
100 40
-IS, REVERSE DRAIN CURRENT (A)
10
TJ = 150oC
60
TJ = 25oC
40 TJ = 25oC 1
20 TJ = 150oC TJ = -55oC
TJ = -55oC
0 0.1
1 2 3 4 5 6 0.4 0.6 0.8 1.0 1.2
-VGS, GATE TO SOURCE VOLTAGE (V) -VSD, BODY DIODE FORWARD VOLTAGE (V)
10 10
4
-VGS, GATE TO SOURCE VOLTAGE(V)
CAPACITANCE (pF)
3
VDD = -20V 10
6 Coss
VDD = -30V
4
2
10 Crss
2 f = 1MHz
VGS = 0V
0 10
1
0 10 20 30 40 0.1 1 10 50
Qg, GATE CHARGE(nC) -VDS, DRAIN TO SOURCE VOLTAGE (V)
10 50
9
8
-IAS, AVALANCHE CURRENT(A)
3
TJ = 125oC 20
2 Limited by Package
VGS = -4.5V
10
o
RθJC = 1.8 C/W
1 0
0.01 0.1 1 10 100 25 50 75 100 125 150
o
tAV, TIME IN AVALANCHE(ms) TC, CASE TEMPERATURE ( C)
200 300
P(PK), PEAK TRANSIENT POWER (W)
VGS = -10V
200 CURRENT AS FOLLOWS:
100us
150 – T
I = I25 c
150 -----------------------
10 125
Tc = 25oC
1ms
100
1 10ms
OPERATION IN THIS SINGLE PULSE
AREA MAY BE TJ = MAX RATED DC SINGLE PULSE
LIMITED BY rDS(on) TC = 25OC
0.1 50
-3 -2 -1 0 1
1 10 100 10 10 10 10 10
-VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (s)
Figure 11. Forward Bias Safe Figure 12. Single Pulse Maximum
Operating Area Power Dissipation
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
NORMALIZED THERMAL
0.2
IMPEDANCE, ZθJC
0.1
0.1 0.05
0.02 PDM
0.01
t1
0.01 t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
1E-3
-5 -4 -3 -2 -1 0 1
10 10 10 10 10 10 10
t, RECTANGULAR PULSE DURATION (s)
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OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE
RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS,
SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Rev. I20