VLSI DESIGN LAB

EC-6612

CONTENT

EX.NO LIST OF EXPERIMENT

1 Design of simple counter, FSM, Adder (8-bit), Multiplier (4-bit) and Simulate.
2 To Synthesis, P&R and post P&R simulation of the components simulation of counter
and find Critical paths and static timing analysis results to be identified
3 Implementation of the Hardware device by using Chip Scope Pro
IC Design Experiments – CADENCE tool
4 Design of simple Differential amplifier, calculate gain and CMRR
5 Layout generation, parasitic Extraction and post layout Simulation
6 Synthesis and Simulate the counter and find Identification of critical paths, power
consumption.
7 Floor plan, Power plan, routing, placement, Static timing analysis(STA) and Critical path
for counter
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EX: NO: 1 Design of simple counter, FSM, Adder (8-bit), Multiplier (4-bit)

AIM:

To Design of simple counter, FSM, Adder (8-bit), Multiplier (4-bit).

Tools Required:

Xilinx ISE 14.1

Procedure:

 file → new project → name

select the FPGA
file → new source → verilog module
compile → check syntax
synthesise
place and route
simulation

coding: ( counter)

module cnt(
input clk,
input rst,
output reg [3:0] count
);
always @ (posedge clk)

begin
if (rst)
count <= "0000";
else
count <=count+1;
end
endmodule

Simulation output:

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coding: (FSM)

module fsm(input wire clk,rst,

input wire a,b,
output wire y0,y1 );

localparam [1:0] s0 = 2'b00,

s1 = 2'b01,
s2 = 2'b10;

reg [1:0]state_reg,state_next;

always @ (posedge clk,posedge rst)

if (rst)
state_reg<=s0;
else
state_reg <= state_next;

always @ *
case (state_reg)
s0: if(a)
if(b)
state_next =s2;
else
state_next =s1;
else
state_next =s0;
s1:if (a)
state_next =s0;
else
state_next = s1;
s2:state_next = s0;

default:state_next =s0;

endcase

//Mealy state machine

assign y1 = (state_reg ==s0)||(state_reg ==s1);

//Moore state machine

assign y0 = (state_reg==s0) & a & b;

endmodule

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Simulation output:

coding:(adder)

module add_8(a, b, cin, sum, carry);

input [7:0]a;
input [7:0]b;
input cin;

output [7:0]sum;
output carry;
reg [7:0]sum;
reg carry;

reg [7:0]c;

always @ (a or b or cin)
begin

sum[0] <= a[0] ^ b[0] ^ cin;

c[0] <= (a[0] & b[0])| (b[0] & cin) | (cin & a[0]);
sum[1] <= a[1] ^ b[1] ^ c[0];
c[1] <= (a[1] & b[1])| (b[1] & c[0]) | (c[0] & a[1]);
sum[2] <= a[2] ^ b[2] ^ c[1];
c[2] <= (a[2] & b[2])| (b[2] & c[1]) | (c[1] & a[2]);
sum[3] <= a[3] ^ b[3] ^ c[2];
c[3] <= (a[3] & b[3])| (b[3] & c[2]) | (c[2] & a[3]);
sum[4] <= a[4] ^ b[4] ^ c[3];
c[4] <= (a[4] & b[4])| (b[4] & c[3]) | (c[3] & a[4]);
sum[5] <= a[5] ^ b[5] ^ c[4];
c[5] <= (a[5] & b[5])| (b[5] & c[4]) | (c[4] & a[5]);
sum[6] <= a[6] ^ b[6] ^ c[5];
c[6] <= (a[6] & b[6])| (b[6] & c[5]) | (c[5] & a[6]);
sum[7] <= a[7] ^ b[7] ^ c[6];
c[7] <= (a[7] & b[7])| (b[7] & c[6]) | (c[6] & a[7]);

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carry <= c[7];

end
end module

Simulation output:

coding: (multiplier-4)

module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout=a^b;
assign cout=(a&b);
endmodule

module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout=(a^b^cin);
assign cout=((a&b)|(a&cin)|(b&cin));
endmodule

module multiply4bits(product,inp1,inp2);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
assign product[0]=(inp1[0]&inp2[0]);
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,inp1[1]&inp2[1],(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);

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FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
End Module

Simulation output:

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EX.NO.2 : To Synthesis, P&R and post P&R simulation of the components simulation of
counter and find Critical paths and static timing analysis results to be
identified.

AIM:

To Synthesis, P&R and post P&R simulation of the components simulation of counter and find
Critical paths and static timing analysis results to be identified.

Procedure:

design:

module cnt(
input clk,
input rst,
output reg [3:0] count
);
always @ (posedge clk)

begin
if (rst)
count <= "0000";
else
count <=count+1;
end
endmodule

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Synthesize:

Place and route:

Post place and route:

Post place and route

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EX.NO. 3 Implementation of the Hardware device by using Chip Scope Pro

Aim:

To Implement the HDL code in FPGA by using Chip Scope Pro

Procedure:

Chip Scope Pro:

Xilinx provides Chip Scope Pro software to view hardware simulation (to view the current status of
the hardware signals in a FPGA board in PC). We can run the Chip Scope Pro for current project
and also configure the FPGA through Chip Scope Pro. An FPGA may get inputs from the outside
environment like switches or binary signals from external hardware and the Project output is
changed depending on the input. When we change the input in hardware we get the output changes
in hardware which is also updated in Chip Scope Pro simulation window. Thus we can view the real
time changes of hardware signals in software. Refer Xilinx website to know more details about
Chip Scope Pro.

Working procedure of Chip Scope Pro is given in the following section. Counter function is taken
as an example to view the hardware simulation. Create a new project file and give the Verilog
Coding, UCF file. Save the files and select New Source from Project menu. New Source Wizard
window will open, here select Chip Scope Definition and Connection File. Give the file name and
file location to store the file then click ‘Next’ and ‘Finish.

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Now cnt.cdc file is added in the source window. Double click cnt.cdc file and Chip Scope Pro

window will open. Refer Figure

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Clock input signal does not come under the Trigger ports. Other input and output signals are
considered as trigger signals and we must set the Data registration parameters such as memory
depth and data width of the trigger data and clock edge are selected here.

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Net Connections section shows the Clock port and Trigger ports. Double click the ports one by one
to make net connections. First select Clock port

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Shows the connected net for the ports. Now click ‘Return to Project Navigator’ to run Chip Scope
pro application and click ‘Yes’ to save the project.

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Run Analyze Design Using Chip Scope Pro in Process window. Then the Chip Scope Pro will open
shown

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Power-ON the Spartan-6 Project Board to make the connection between PC and Board via JTAG
cable. Select the type of cable we are using for the experiment. Xilinx JTAG USB cable is used.
Select it from JTAG Chain menu. Parameters of the JTAG cable are shown in the following
window. Check it and select OK. Two devices (FPGA & PROM) in the Board are detected and click
OK to finish the initial steps

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Xilinx Parallel cable selection

Device detection

Right click the FPGA device and select ‘Configure’ to select the operating files for the current
project

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Select .bit file and .cdc file from the directory and click OK.

Adding CDC file

likewise add the bit file also, After selecting the files open the trigger window by right click the
‘Trigger setup’option in Project window. Then open‘Waveform’window to view the hardware
waveforms for this experiment. The Trigger window and waveform window. In this experiment we
are using one trigger input (Reset).

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Trigger setup selection

Trigger Setup

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Waveform setup

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Now set the‘Trigger Run Mode’ as‘Repetitive’ to continuously read the hardware signals from
the Board. Run the project to display the experiment signals in the waveform window.

Trigger run mode setup

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Set the reset signal as low in Spartan-6 Project Board and we get 4-bit counter output in LEDs.
Hardware values are displayed in the Chip Scope Pro Waveform Window and it is updated at every
changes. Set the reset signal as high in Spartan-6 Project Board. Counter operation will be stopped
in hardware and also in waveform window. Chip Scope Pro is the only tool to view and analyze the
hardware signals of FPGA by viewing the hardware signals in software.

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IC Design Experiments – CADENCE Tool

EX.NO.4 Design of simple Differential amplifier, calculate gain and CMRR

AIM:

To design the simple Differential Amplifier by using cmos and calculate the gain and CMRR.

Procedure:

step-1: Open the virtuoso tool

step-2: create a cellview

file → new → cellview

draw the differential amplifier as shown in diagram

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Transistor M1 M2 M3 M4 M5 M6
Type Pmos Pmos Nmos Nmos Nmos Nmos
Width 15u 15u 3u 3u 4.5u 4.5u
Length 1u 1u 1u 1u 1u 1u

Analog lib Vsin AC Magnitude= 1; Amplitude= 5m; Frequency= 1K

Analog lib Vss,vdd Vdc=-2.5v ; vdc=2.5v
Analog lib idc Dc current = 30u

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step-3: To Simulate

Launch → ADE L

In the ADEL window

Analysis → choose → tran

stop time → 5m → ok

outputs → to be plotted → select on Schematic (select the possible nets in Schematic)

Simulation → Netlist and Run.

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After loading the waveform window display as below

step- 4: calculate gain of Amplifier

To calculate gain of the amplifier u have to analysis the AC

In the ADEL window

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Analysis → choose → AC
a. In the Analysis section, select ac.
b. In the AC Analysis section, turn on Frequency.
c. In the Sweep Range section select start and stop frequencies as 100 to 100G
d. Select Points per Decade as 20.
e. Check the enable button and then click Apply.
Click OK in the Choosing Analysis Form.

Now the ADEL window look like this

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click → Netlist and run

Next go to ADEL Window Results → Direct plot → AC dB20 and it direct to schematic window,
click the output nets from the schematic and press escape. The following waveform appears as
shown below

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Gain waveform

tools → calculator

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Select the waveform, the waveform detail is added in the calculator, now select average in the
function panel, click evaluate the buffer and stack, not the differ gain value is display on the
calculator window

Common gain:

Change the circuit as shown below

repeat the same process to calculate the common gain

CMRR

CMRR = |Ad/Ac | = Ad - (-Ac)

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EX.NO.5 Layout generation, parasitic Extraction and post layout Simulation

Aim:

Draw the layout 0f Differential Amplifier, extract parasitic component and post layout
Simulation.

Procedure:

Step-1:

open the schematic view of differential amplifier from that

launch → layout XL

draw the layout as shown below

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DRC

assura → run DRC

LVS

assura → run LVS

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II) Parasitic Extraction:

Assura → run QRC or RCX

go to that location and open the file

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III)POST LAYOUT SIMULATION

create a new file in the test bench name, type → config and ok.

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In the new configuration window

view → Schematic

use template → Spectre

now the new configuration window looks like this

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click → OK

Change the view type of differential amplifier from Schematic to av-extracted

as shown in below diagram save and click → open

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the test bench config file look like this

do the simulation process as usually and check the power and propagation time delay
and then compare to normal simulation output.

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EX.NO.6 Synthesis and Simulate the counter and find Identification of critical paths,
power consumption.

AIM:

To Synthesis and Simulate the counter and find Identification of critical paths, power
consumption.

Procedure:

In the terminal
Welcome to cadence Tool Suit

#cd NCO/rclabs/rtl
# gedit countervi.v

type the 4-bit counter

coding

module counter(
input clk,
input rst,
output reg [3:0] count
);
always @ (posedge clk)

begin
if (rst)
count <= "0000";
else
count <=count+1;
end
endmodule

compile

#ncvlog countervi.v -mess

ncvlog: 09.20-s045: (c) Copyright 1995-2011 Cadence Design Systems, Inc.

file: countervi.v
module worklib.counter
errors: 0, warnings: 0

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Simulation:

# irun countervi.v -access +rwc -mess -gui

the two windows will open

now minimize the console

window, in the design browser window, select the module name and click send to waveform
window. In the waveform window give values to clk and rst and run the simulation

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Constraints file for counter

In the terminal in rtl location open a new file for constraints

#gedit filename.g

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]

set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "count"] -clock [get_clocks "clk"]

save and close the file

Synthesize:

type the command in terminal

#rc -gui

this command will invoke the Cadence Encounter(RTL Compiler)

in the RC terminal type the following command

rc:/>set_attribute lib_search_path ../lib

rc:/> set_attribute library slow.lib
rc:/>read_hdl filename.v
rc:/>elaborate
after the elaboration the schematic view of rtl window

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rc:/> read_sdc filename.g

The failed component should be zero then only we proceed the synthesize process
completely

rc:/>synthesize -to_mapped -effort medium

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POWER CONSUMPTION:

rc:/> report power

CRITICAL PATH:

rc:/> report timing

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after synthesize write the netlist in new name

</:write_hdl > new_filename_net.v

</:rcwrite_hdl

now the netlist will written in the terminal, also write the constraints file in new
name

</:WRITE_SDC > NEW_FILENAME.SDC

rc:/> write_sdc
</:rcexit

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EX.NO.7 Floor plan, Power plan, routing, placement, clock routing for counter

AIM:

Design the Floor Plan, Power plan, Routing, Placement, Static timing analysis (STA) and
Critical path for counter

Procedure:

Tools → cadence Encounter (RTL-GDSII)

In Terminal type the command

# encounter

File → import design

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fill all the data that needed for the design click → ok

The PR boundary is loaded on the tool

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floor plan → specify floor plan

Fill the required Floorplan values click → ok

now the floorplan look like this

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Powerplan:

power → power planning → add rings

fill the above window for power rings click → ok

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power → power planning → add strip

fill the data in the add strip window click → ok

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route → special route

fill the required data in the window click → ok

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Placement:

place → place standard cell

click → ok

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Static Timing Analysis(STA):

The STA is static the analysis of the design is carried out statically and does not
depend upon the data values being applied at the input pins. This is in contrast to
simulation based timing analysis where a stimulus is applied on input signals,
resulting behavior is observed and verified, then time is advanced with new input
stimulus applied, and the new behavior is observed and verified and so on. a design
along with a set of clock definitions and the definition of the external environment
of the design, the purpose of static timing analysis is to validate if the design
can operate at the rated speed. That is, the design can operate safely at the specified
frequency of the clocks without any timing violations. Some examples of timing checks
are setup and hold checks. A setup check ensures that the data can arrive at a flip-flop
within the given clock period. A hold check ensures that the data is held for at least
a minimum time so that there is no unexpected pass-through of data through a flip-flop:
that is, it ensures that a flip-flop captures the intended data correctly. These
checks ensure that the proper data is ready and available for capture and latched
in for the new state.

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pre -CTS:

Timing → report timing

The Timing Analysis window is shown below, select → setup, click → ok

The Timing Analysis report is shown in the encounter Terminal

now do the same procedure to calculate the hold Analysis.

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Clock Tree Synthesize:

CTS is the process of insertion of buffers or inverters along the clock paths of ASIC
design in order to achieve zero/minimum skew or balanced skew. The goal of CTS is
to minimize skew and insertion delay. Apart from these, useful skew is also added
in the design by means of buffers and inverters. Clock is propagated after placement
because the exact physical location of cells and modules are needed for the clock’s
propagation which in turn impacts in dealing with accurate delay and operating
frequency and clock is propagated before routing because when compared to logical
routes, clock routs are given more priority. This is because, clock is the only signal
switches frequently which in acts as source for dynamic power dissipation.

Though wide range of clock routing algorithm are available, EDA tool chooses the
optimized algorithm automatically and it only shows the critical paths after
propagating the tree. If a design results in negative slack, increasing the clock
timing is an easy way but changing the clock period changes the operating frequency.
Solving the negative slack without changing the clock period is possible by up-sizing
or down-sizing the cell in critical paths.

clock → synthesize clock tree

click → Gen Spec

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In the Generate clock spec select all clkbuf and clkinv and click → add and ok

now the clk buffers that are place inside the standard cell, now the next step is
to route the clkbuf and clkinv .

Route → nano route → route

now the counter is shown below

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Post-CTS:

Timing → report timing

select → post-CTS and analysis → setup (or) Hold , click → ok.

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The output is displayed in the encounter Terminal

if there is any violation in the post-CTS design do the optimization process.

Again route → nano route → route.
Select the timing driven and click ok

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To find the time delay inside the nets type the command in encounter terminal report_timing
encounter 1> report_timing

CRITICAL PATH:

Critical path is the path having the more time delay inside the circuit is called
critical path.
TYPE COMMAND IN ENCOUNTER TERMINAL.

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ENCOUNTER 2> REPORT CRITNET

The critical nets should be “zero” else do the optimization process

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