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Electrical Thin Film Physics

and Process Technology


- Ch. 2 : Thermal Oxidation

授課教師: 劉柏村 教授
國立交通大學 光電工程系所
1
Thermal Oxidation
• Introduction
• Applications
• Mechanism
• Process
• System
• RTO

( Partially refer to Hong Xiao) 2


Introduction

• Silicon reacts with oxygen


• Stable oxide compound
• Widely used in IC manufacturing

Si + O2  SiO2

3
Thermal Oxidation

• Oxide would like to expand by


30% in all three dimensions to
accommodate the oxygen atoms.
• Silicon substrate prevents
expansion in the two lateral
directions, the volume is thus
accommodated by a 2.2 times
upward expansion of the oxide
compared to the volume of the
silicon oxidized (1.3)3~ 2.2.

4
Thermal Oxidation
Original Silicon Surface

Silicon Silicon
O2 Dioxide
O2 O2 O2
O2
O2 O2 O2
O2
O2
O2 O2
O2 O2
O2
55% 45%
5
Application of Oxidation
Uses of SiO2 in Silicon Technology

隔絕氧化層 隔絕氧化層
(Isolation oxide) (Isolation oxide)

6
Application of Oxidation
• Diffusion Masking Layer
• Surface Passivation
– Screen oxide, pad oxide, barrier oxide
• Isolation
– Field oxide and LOCOS
• Gate oxide

7
Diffusion Barrier
• Much lower B and P diffusion rates in SiO2 than
that in Si
• SiO2 can be used as diffusion mask

Dopant

SiO2 SiO2

Si

8
Application, Surface Passivation
Pad Oxide Screen Oxide
Sacrificial Oxide Barrier Oxide

SiO2

Si

Normally thin oxide layer (~150Å ) to protect silicon


defects from contamination and over-stress.
9
Screen Oxide

Dopant Ions

Photoresist Photoresist

Si Substrate

Screen Oxide

10
Pad and Barrier Oxides in STI Process
Nitride
Pad Oxide
Silicon
Trench Etch

Nitride USG
Pad Oxide
Silicon
Barrier Oxide Trench Fill
USG

Silicon
USG CMP; USG Anneal; Nitride and Pad Oxide Strip
11
Application, Pad Oxide

• Relieve strong tensile stress of the nitride


• Prevent stress induced silicon defects
Pad Oxide
Silicon nitride

Silicon Substrate

12
Application, Device Isolation

• Electronic isolation of neighboring devices


• Blanket field oxide
• Local oxidation of silicon (LOCOS)
• Thick oxide, usually 3,000 to 10,000 Å

13
Blanket Field Oxide Isolation
Silicon
Wafer Clean

Silicon Dioxide

Silicon
Activation Area Field Oxidation

Field Oxide

Silicon
Oxide Etch
14
LOCOS Process
Pad Oxide
Silicon nitride
P-type substrate
Pad oxidation, nitride deposition and patterning

Silicon nitride SiO2


p+ P-type substrate p+ Isolation Doping p+
LOCOS oxidation
Bird’s Beak
SiO2
p+ P-type substrate p+ Isolation Doping p+
Nitride and pad oxide strip
15
LOCOS
• Compare with blanket field oxide
– Better isolation
– Lower step height
– Less steep sidewall
• Disadvantage
– rough surface topography
– Bird’s beak
• Replacing by shallow trench isolation (STI)
16
Application, Sacrificial Oxide
• Defects removal from silicon surface
Sacrificial Oxide
STI USG
P-Well N-Well
Sacrificial Oxidation

STI USG
P-Well N-Well
Strip Sacrificial Oxide
Gate Oxide
STI USG
P-Well N-Well
Gate Oxidation

17
Application, Device Dielectric
• Gate oxide: thinnest and most critical layer
• Capacitor dielectric
VG VD > 0
Poly Si

Gate

Thin oxide
n+ n+
p-Si
Source Drain

Electrons
Si Substrate

18
Oxide and Applications
Name of the Oxide Thickness Application Time in application

Native 15 - 20 Å undesirable -

Screen ~ 200 Å Implantation Mid-70s to present

Masking ~ 5000 Å Diffusion 1960s to mid-1970s

Field and LOCOS 3000 - 5000 Å Isolation 1960s to 1990s

Pad 100 - 200 Å Nitride stress buffer 1960s to present

Sacrificial <1000 Å Defect removal 1970s to present

Gate 30 - 120 Å Gate dielectric 1960s to present

Barrier 100 - 200 Å STI 1980s to present

19
Silicon Dioxide Grown on Improperly
Cleaned Silicon Surface

20
Pre-oxidation Wafer Clean

• Particulates
• Organic residues
• Inorganic residues
• Native oxide layers

21
RCA Clean
• Developed by Kern and Puotinen in 1960 at RCA
• Most commonly used clean processes in IC fabs
• SC-1-- NH4OH:H2O2:H2O with 1:1:5 to 1:2:7 ratio at
70 to 80 C to remove organic contaminants.
• SC-2-- HCl:H2O2:H2Owith 1:1:6 to 1:2:8 ratio at 70 to
80 C to remove inorganic contaminates.
• DI water rinse
• HF dip or HF vapor etch to remove native oxide.
22
Pre-oxidation Wafer Clean
Particulate Removal

• High purity deionized (DI) water or


H2SO4:H2O2 followed by DI H2O rinse.
• High pressure scrub or immersion in heated
dunk tank followed by rinse, spin dry and/or dry
bake (100 to 125 °C).

23
Pre-oxidation Wafer Clean
Organic Removal
• Strong oxidants remove organic residues.
• H2SO4:H2O2 or NH3OH:H2O2 followed by DI
H2O rinse.
• High pressure scrub or immersion in heated
dunk tank followed by rinse, spin dry and/or dry
bake (100 to 125 °C).

24
Pre-oxidation Wafer Clean
Inorganic Removal

• HCl:H2O.
• Immersion in dunk tank followed by rinse, spin
dry and/or dry bake (100 to 125 °C).

25
Pre-oxidation Wafer Clean
Native Oxide Removal

• HF:H2O.
• Immersion in dunk tank or single wafer vapor
etcher followed by rinse, spin dry and/or dry
bake (100 to 125 °C).

26
Oxidation Mechanism

• Si + O2 SiO2
• Oxygen comes from gas
• Silicon comes from substrate
• Oxygen diffuse cross existing silicon
dioxide layer and react with silicon
• The thicker of the film, the lower of the
growth rate

27
Deal-Grove Model
(Linear Parabolic Law)

Oxidant flux from the gas phase to the silicon surface


During thermal oxidation. The bold line represents the
O2 or H2O concentration. 28
Oxidation Kinetic
數學模型:
(1) 氧化物從氣相被傳輸到氧化膜表面之過程
Mass-Transport Process: F1=hG(CG-CS)
(2) 氧化物由晶片外表面被吸收入晶片內表面
(即Co代表氧化物在SiO2內的溶解度)
Henry’s Law : C0=HPS ( and Ps PG)
(3) 氧化物從氧化膜內擴散至SiO2/Si 界面處
C C  CI
Fick’s Law: F2  D  D( 0 )
x x0
(4) 氧化物和Si在介面處進行化學反應,形成新的SiO2
F3=kSCI …………….. (a) (F3: 表面反應時,所需消耗的氧化物流量)
在穩態條件下, 三種氧化過程的流動必須相等, 所以 F1=F2=F3
C0 C0
CI   ……(b)
k S k S xo k x
1  1 S 0 29
h D D
Oxidation Kinetic
C0 C0
CI  
k S k S xo k x
1  1 S 0
h D D
若瓶頸在步驟3: ( KSx0/D <<1) CI  C0
Reaction Controlled reaction
若瓶頸在步驟4:( KSx0/D >>1) CI  0
Diffusion Controlled transport/Diffusion-limited reaction

30
Deal-Grove Relation
• Combing Eqs. (a) and (b) together with the definition of flux F3
dx0 k sC0
N1  F3 
dt k k x
1 S  S 0
h D
N1 is the number of oxidant molecules incorporated per unit volume of oxide grown.
N1 = 2.21022 cm-3 for O2 oxidation and twice this value for H2O oxidation
• Integrating this equation:
x0 t
k k x
N1  [1  S  S 0 ]dx  k sC0  dt
xi
h D 0

2 DC *
where B  and C* C0
x02  xi2 x0  xi
  t N1
B B/ A B C* C *k S
and  
A N ( 1  1) N1
1
kS h

x02 x
 0  t 
B B/ A xi2  Axi
where  
B
31
Thermal Oxidation Growth Model
• Oxidizing species diffuse through SiO2 to Si/SiO2
Deal-Grove Relation:
Linear Growth Regime
Tox2  ATox  B(t   )

Oxide Thickness
B
X= t
A
For short oxidation ( t << A2/B) Diffusion-limited Regime
B
Tox  (t   ) X=Bt
A
For long oxidation (t >> , t >> A2/B) Oxidation Time

Tox  Bt
2
A, B : temperature, ambient composition, pressure
and crystalline orientation
 is related to the initial oxide thickness
32
熱氧化的機制
氧化溫度介於900至1200℃
(1)開始時氧和矽穩定結合,為線性(linear)成長階段
(2)氧化物厚度500埃(A:萬分之一微米)後,生長速率減緩,
為拋物線(parabolic)成長階段
-受傳輸現象限制的反應(transport-limited reaction)
或受擴散現象限制的反應(diffusion limited reaction)
一般而言,在氧化層厚度低於1000埃時是由線性機制所控制

矽 矽 矽

圖 二氧化矽成長的各階段:(a) 初始;(b) 線性;(c) 拋物線 33


Oxidation Rate

• Temperature
• Chemistry, wet or dry oxidation
• Thickness
• Pressure
• Wafer orientation (<100> vs. <111>)
• Silicon dopant

34
<100> Silicon Dry Oxidation
1.2
Oxide Thickness (micron)

<100> Silicon Dry Oxidation 1200 °C


1.0

0.8 1150 °C

1100 °C
0.6
1050 °C
0.4 1000 °C
950 °C
0.2
900 °C
0 2 4 6 8 10 12 14 16 18 20
Oxidation Time (hours)
35
Wet (Steam) Oxidation
• Si + 2H2O SiO2 + 2H2
• At high temperature H2O is dissociated to H and
H-O
• H-O diffuses faster in SiO2 than O2
• Wet oxidation has higher growth rate than dry
oxidation.

36
<100> Silicon Wet Oxidation Rate
1150 °C
<100> Silicon Wet Oxidation
3.0 1100 °C
Oxide Thickness (micron)

1050 °C
2.5
1000 °C
2.0
950 °C
1.5 900 °C

1.0

0.5

0 2 4 6 8 10 12 14 16 18 20
Oxidation Time (hours)
37
Oxidation Rate
Temperature
• Oxidation rate is very sensitive (exponentially
related) to temperature
• Higher temperature will have much higher
oxidation rate.
• The higher of temperature is, the higher of the
chemical reaction rate between oxygen and
silicon is and the higher diffusion rate of
oxygen in silicon dioxide is.

38
Oxidation Rate
Wafer Orientation

• <111> surface has higher oxidation rate than


<100> surface.
• More silicon atoms on the surface.

39
Wet Oxidation Rate
Oxide Thickness (micron) 1.8
1200 °C
1.6 <111> Orientation
1.4 1100 °C
95 °C Water
1.2
1.0 1000 °C
0.8
0.6
0.4 920 °C
0.2

0 1 2 3 4
Oxidation Time (hours)

40
Oxidation Rate
Dopant Concentration
• Dopant elements and concentration
• Highly phosphorus doped silicon has higher
growth rate, less dense film and etch faster.
• Generally highly doped region has higher grow
rate than lightly doped region.
• More pronounced in the linear stage (thin
oxides) of oxidation.

41
Oxidation: Dopants
Pile-up and Depletion Effects
•N-type dopants (P, As, Sb) have higher
solubility in Si than in SiO2, when SiO2
grow they move into silicon, it is call pile-up
or snowplow effect.

•Boron tends to go to SiO2, it is called


depletion effect.

42
Depletion and Pile-up Effects
Original Si Surface Original Si Surface

Si-SiO2 interface Si-SiO2 interface

Dopant Concentration
Dopant Concentration

Original Distribution

SiO2 Si SiO2 Si

P-type Dopant Depletion N-type dopant Pile-up

43
Oxidation Rate
Doped oxidation (HCl)

• HCl is used to reduce mobile ion contamination.


• Widely used for gate oxidation process.
• Growth rate can increase from 1 to 5 percent.

44
Oxidation Rate
Differential Oxidation
• The thicker of the oxide film is, the slower of the
oxidation rate is.
• Oxygen need more time to diffuse cross the
existing oxide layer to react with substrate
silicon.

45
Pre-oxidation Clean

• Thermally grown SiO2 is amorphous.


• Tends to cross-link to form a crystal
• In nature, SiO2 exists as quartz and sand
• Defects and particles can be the nucleation sites
• Crystallized SiO2 with poor barrier capability.

• Need clean silicon surface before oxidation.


46
Oxidation Process

• Dry Oxidation, thin oxide


– Gate oxide
– Pad oxide, screen oxide, sacrificial oxide, etc.

• Wet Oxidation, thick oxide


– Field oxide
– Diffusion masking oxide

47
Dry Oxidation System
MFC
MFC To
Process
MFC Tube
MFC

Control Valves
Process N2

Purge N2

Regulator
HCl

O2

48
Dry Oxidation

• Dry O2 as the main process gas


• HCl is used to remove mobile ions for gate
oxidation
• High purity N2 as process purge gas
• Lower grade N2 as idle purge gas

49
Gate Oxidation Steps

• Idle with purge N2 flow


• Idle with process N2 flow
• Wafer boats push-in with process N2 flow
• Temperature ramp-up with process N2 flow
• Temperature stabilization with process N2 flow
• Oxidation with O2, HCl, stop N2 flow

50
Gate Oxidation Steps, Continue
• Oxide annealing, stop O2, start process flow N2
• Temperature cool-down with process N2 flow
• Wafer boats pull-out with process N2 flow
• Idle with process N2 flow
• Next boats and repeat process
• Idle with purge N2 flow

51
Wet Oxidation Process
• Faster, higher throughput
• Thick oxide, such as LOCOS
• Dry oxide has better quality

Process Temperature Film Thickness Oxidation Time

Dry oxidation 1000 ° C 1000 Å ~ 2 hours

Wet oxidation 1000 ° C 1000 Å ~ 12 minutes

52
Pyrogenic Steam System

Hydrogen Flame, 2 H2 + O2  2 H2O

O2
H2 To
Exhaust

Process Tube Wafer Boat


Thermal Couple Paddle

53
Pyrogenic System
• Advantage
– All gas system
– Precisely control of flow rate
• Disadvantage
– Introducing of flammable, explosive hydrogen

• Typical H2:O2 ratio is between 1.8:1 to 1.9:1.

54
Pyrogenic Wet Oxidation System

MFC Process Tube

MFC
MFC
MFC Wafers Burn Box

Control Valves
Process N 2

Purge N 2

Regulator
Scrubbier
O2
H2

Exhaust

55
Wet Oxidation Process Steps
• Idle with purge N2 flow
• Idle with process N2 flow
• Ramp O2 with process N2 flow
• Wafer boat push-in with process N2 and O2 flows
• Temperature ramp-up with process N2 and O2 flows
• Temperature stabilization with process N2 and O2 flows
• Ramp O2, turn-off N2 flow
• Stabilize the O2 flow

56
Wet Oxidation Process Steps
• Turn-on H2 flow, ignition and H2 flow stabilization
• Steam oxidation with O2 and H2 flow
• Hydrogen termination, turn-off H2 while keeping O2 flow
• Oxygen termination, turn-off O2 start process N2 flow
• Temperature ramp-down with process N2 flow
• Wafer boat pull-out with process N2 flow
• Idle with process N2 flow
• Next boats and repeat process
• Idle with purge N2 flow

57
Horizontal Diffusion Furnace Layout

58
Vertical Furnace Layout
• Many recently developed
furnaces are vertically oriented
since these take up less floor
space in a manufacturing facility.
• Wafers are loaded on boats.
Carried by cantilever system
without touching the wall to
avoid stir up particles.
• Furnace is normally divided in
three to five zones for
temperature control, the outer
zones are designed to help
compensate for heat losses out
the ends of tubes, so that a long
central section with uniform
temperature can be maintained.
59
Rapid Thermal Oxidation
• In recent years, gate oxide
thickness is less than <10 nm,
it requiring short, well-
controlled growth cycles.
Rapid thermal Oxidation (RTO)
is used to grow ultra-thin oxide.
(~100°C/sec). But it is a single
wafer machine.
• In RTO system, it is difficult to
know the exact temperature on
the wafer. Pyrometer is often
used with limited range.

60
Rapid Thermal Oxidation

• For gate oxidation of deep sub-micron device


• Very thin oxide film, < 30 Å
• Need very good control of temperature
uniformity, WIW and WTW.
• RTO will be used to achieve the device
requirement.

61
RTP Process Diagram

Load Ramp up RTO RTA Cool Unload


wafer 1& 2 down wafer

O2 flow Temperature

HCl flow

N2 flow

Time

62
Properties of SiO2

Oxygen
Silicon

• Bonding angle : 110~180  ( 144  )


• Density : 2.20 g/cm3
• Refractive Index : ~1.462
• Oxide layers is amorphous. Single-crystal oxide on silicon result in very
large stresses.
• SiO4 tetrahdra are the basic units, sharing oxygen (bridging) oxygen atoms. Bridging
Oxygen
• Nonbridging oxygen atoms are referred as fused silica.
• It is compressive stress. At high temperature above 1000°C, the oxide can
relieve some stress by viscous flow.
63
Electrical Properties of SiO2

64
Oxide Traps and Defects
• The densities of defects : 109-1011
Mobile Ionic Charge cm-2 (silicon surface atom density
K+ of 1015 cm-2.) Defects due to
Na+ incompletely oxidized Si atoms or
Oxide Trapped Charge Si atoms with dangling or
   unsatisfied bonds. (about 1 / 105 )
   Fixed Oxide Charge  Qm is the mobile oxide charge that
      may be located anywhere in the
         oxide, and was a serious problem in
the 1960s.
 With proper attention to cleanliness
Interface Trapped Charge in wafer fabrication facilities, this
problem largely disappeared by the
1970s.
(Deal, 1980)

65
HRTEM of SiO2/Silicon Interface

S. L. Wu

66
Dangling Bonds and Interface Charge
Interface State Charge (Positive)

Dangling
Bond
SiO2
+ + + + +

Si-SiO2 Si
Interface

67
Fixed Charge
• Origin : structural defects, i.e., ionized Si
• Location : in the oxide layer less than 1 nm from Si-
SiO2 interface
• The density is strongly related to fabrication process,
e.g. , oxidation ambient, temperature, cooling
condition, and silicon substrate orientation
• This charge can’t be annealed below 500C
• Electrical Property: not in electrical communication
with underlying Si

68
SiO2/Si Interface
• Interface states: imperfect bonds
– Electrically interacted with channel carriers
– Assuming each dangling bond give rise to one interface
state

Impact on device characteristics


– threshold voltage ( Vt )
– carrier mobility ( Gm )
– reliability, oxide integrity and HCI( hot-carrier-
injection) degradation

69
Distinguishing
• Difference: Qf is positive and fixed, Qit may be
positive, neutral, or negative and may change during
normal device operation because of the capture of
holes or electrons.
• Oxidizing a silicon surface usually results in a
density of Qit on the order of 109-1011cm-2eV-1, about
the same density as is found for Qf.
• In fact it is usually the case that a process that results
in a high value of Qf will also result in a high density
of Qit.

70
Oxide Trapped Charge
• Qox or oxide trapped charge, located anywhere in the oxide,
due to broken Si-O bonds in the bulk of the oxide. Plasma
etching, and ion implantation can damage oxide resulting
in traps in the bulk oxide. In addition, trapping may result
from radiation, avalanche injection, F-N tunneling,
substrate hot hole/electron injection
• This charge may be positive or negative due to holes or
electrons trapped in the bulk of the oxide
• Unlike fixed charge, it can be annealed by low temperature
treatment (<500C)
Impact
• Threshold voltage deviation from desired value with time
and reliability concerns
• Degrading oxide reliability 71
Oxide Measurement
• Thickness • Gate oxide
• Uniformity • Break down
voltage
• Color chart • C-V
• Ellipsometry characteristics
• Reflectometry

72
Ellipsometry
Elliptically Polarized
Reflected Light
Linearly Polarized Incident Light

p
s

n 1, k 1, t 1
n 2, k 2

73
Reflectometry
Human eye or
photodetector
Incident light
1
2

t Dielectric film, n( l )

Substrate

74
C-V Test Configuration
Large Resistor
Capacitor
Meter

Oxide Aluminum
Silicon
Metal Platform

Heater Heater

75
Surface Charge & C-V Curves
dQs
Qs vs. s (surface potential) C
dVg

76
76
Effect of Oxide Charges in C-V
Q f  Qm  Qot  Qit
VFB 
Cox

VFB VFB

VG VG

Net negative charges present Net positive charge present

77
Effect of Interface State at C-V
• The presence of interface states will induce the
stretch-out of high frequency C-V curve
– Minority carrier in the inversion layer will not respond to
ac signal
– But they will affect the dc gate bias and alter the band
bending compared to that without interface states
Ideal curve
Stretch-out
Donor-like
interface traps
Acceptor-like
interface traps
78
Summary of Oxidation
• Oxidation of silicon
• High stability and relatively easy to get.
• Application
– Isolation, masking, pad, barrier, gate, and etc.
• Wet and Dry
• More dry processes for advanced IC chips
• Rapid thermal oxidation and annealing for ultra-
thin gate oxide
79
Limits and Future Trends in
Technologies
• Oxynitride, SiOxNy, will replace SiO2 in deep submicron
devices. Oxynitride has high dielectric constant, stronger
Si-N bonds that are formed near the Si/SiO2 interface, no
hydrogen incorporation, resistant to dopant penetration
through dielectric.
• High-k materials will be the mainstream materials as
thickness less than 1.0 nm.

80