INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Int. J. Circ. Theor. Appl. 2013; 41:1074–1084

Published online 25 July 2012 in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.1826

Digitally programmable second generation current

conveyor-based FPAA

Soliman A. Mahmoud1,2,*,† and Eman A. Soliman3

1
Electrical and Computer Engineering Department, Sharjah University, Sharjah University City, Sharjah,
Postcode 27272, UAE
2
Electrical Engineering Department, Fayoum University, Fayoum, Egypt
3
Electrical and Electronics Engineering Department, German University in Cairo, Cairo, Postcode 11835, Egypt

ABSTRACT
A novel fully differential digitally programmable current conveyor (DPCCII) is presented in this paper. The
programmability of the proposed DPCCII is achieved using three-bit MOS R-2R ladder current division
network. The DPCCII is used to realize a field programmable analog array (FPAA). The FPAA consists
of seven configurable analog blocks arranged in a hexagonal form. The FPAA power consumption is
72.3 mW from 1 V voltage supply. A second-order programmable universal filter is realized using the
proposed FPAA as an application. All the circuits are realized and simulated using 90 nm IBM CMOS
technology model under balanced supply voltage of
0.5 V. Copyright © 2012 John Wiley & Sons, Ltd.

Received 2 July 2011; Revised 24 January 2012; Accepted 25 March 2012

KEY WORDS: current division network; digitally programmable current conveyor; field programmable
analog array; universal filter

1. INTRODUCTION

Field programmable analog arrays (FPAA) are analog reconfigurable hardware platforms. The FPAA chip
can be used to realize different analog circuits such as continuous time filters, variable gain amplifiers,
oscillators, etc. [1]. The FPAA architecture consists of configurable analog blocks (CAB) connected
together to realize the FPAA. The CAB can be implemented using different analog active circuits like a
tunable unity gain frequency operational amplifier [2], programmable operational trans-conductance
amplifier (OTA) [1] or programmable current conveyor (CC) [3]. The CABs are connected together by
means of interconnecting network such that the voltage/current signals are routed inside the
FPAA [1,4–6]. The design challenges of the FPAA are mainly the CAB active circuit and the
interconnection network. The active circuit can be designed with programmable I–V characteristics by
means of analog/digital control signals. If the active circuit is programmable, then the FPAA user can
implement tunable analog circuit applications such as tunable filters and variable gain amplifiers.
However, due to the design complexity of programmable active circuits, most of the FPAA designs did
not use programmable active circuits especially for voltage op-amps and CC-based FPAAs. However,
for the OTA-based FPAAs, there were designs based on tunable OTAs. The OTAs were tuned by
using a pre-defined set of control voltage signals [6]. However; this technique requires extra hardware
to save the control voltage values. The second challenge in the FPAA design is the interconnection
network responsible for signal routing between CABs. This network is considered as overhead
hardware because it is not used in signal processing application circuits realized using the FPAA. In

*Correspondence to: Soliman A. Mahmoud, Electrical and Computer Engineering Department, Sharjah University,
Sharjah University City, Sharjah, Postcode27272, UAE.
†
E-mail: solimanm@sharjah.ac.ae, sam00@fayoum.edu.eg

Copyright © 2012 John Wiley & Sons, Ltd.

 DIGITALLY PROGRAMMABLE CURRENT CONVEYOR, FPAA, UNIVERSAL FILTER 1075

addition, the interconnection network increases the total parasitic capacitance in the signal path. This may
lead to a significant degradation of the realized FPAA frequency response.
In this paper, a novel CMOS realization of a fully differential digitally programmable current conveyor
(DPCCII) is presented. The DPCCII is tuned by means of a three-bit digital control codeword. The
DPCCII is used to realize a FPAA. A second-order tunable universal filter is realized as an application
for the FPAA. The proposed FPAA is digitally controlled, and no interconnection network is used to
avoid adding extra hardware for signal routing inside the FPAA. The paper is organized as follows:
section II explains the proposed CMOS realization of the DPCCII, section III discusses the proposed
DPCCII-based FPAA architecture; in section IV, a second-order tunable universal filter is realized and
simulated, and finally the paper is concluded in section V.

2. PROPOSED CMOS REALIZATION OF DPCCII

2.1. Review of programmable current conveyors

The CC is an active circuit that was introduced in [7, 8]. The CC has three ports named Y, X and Z. The Y
port voltage is conveyed to the X port while the X port current is conveyed to the Z port. Three generations
of the CC were defined. For the first (CC) and third generation current conveyors (CCIII), the X port
current is also conveyed to the Y port in the same or opposite direction of the X port current,
respectively. As for the second generation CC (CCII), the current at Y port is zero. Many single-ended
and fully differential realizations for the CCII were proposed. The CCII can be realized by cascading a
voltage follower and a current follower to achieve the required I–V characteristics.
To design a programmable CCII, two approaches were used. The first one was using a current division
network (CDN) added in cascade with the current follower. Thus, the Z port current becomes a scaled
copy of the X port current. This approach was used in [3]; however, the CDN in [3] achieved the
required current scaling provided that the CDN’s transistors mode of operation was the saturation
mode. If the transistors were driven outside the saturation mode, then the required current scaling will
not be achieved. In addition, the CDN needed to be biased using current sources which increased the
circuit power consumption. The second approach was using current mirrors to scale the current at the Z
port [9]. However, this method was subjected to transistors mismatching problems.
In the following section, a proposed DPCCII is realized using fully differential CCIIs and three-bit
MOS R-2R ladder CDN.

2.2. Proposed DPCCII CMOS realization

The proposed DPCCII block diagram is shown in Figure 1. The circuit consists of two fully differential
CCIIs and two three-bit MOS R-2R ladders CDNs. The first CCII voltage conveying action is used.
The differential voltage applied to the Y port is conveyed to the X port.

VXd ¼ VYd (1)

As for the X port current, it is also conveyed to the Z port, and then it flows into a three-bit MOS R-2R
ladder CDN [10]. This CDN divides its input current into two output currents using a current scaling factor
‘a’ given by the following equations:

Figure 1. Proposed DPCCII block diagram.

Copyright © 2012 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2013; 41:1074–1084
DOI: 10.1002/cta
1076 S. A. MAHMOUD AND E. A. SOLIMAN

Io1 ¼ aIin (2)

Io2 ¼ ð1  aÞIin (3)

1X 2
a¼ 2i ai (4)
8 i¼0

The MOS R-2R ladder circuit diagram is shown in Figure 2. The current scaling factor changes with
the digital codeword applied to the CDN ‘a2a1a0’. The MOS R-2R ladder CDN consists of three current
division cells. Each cell divides its input current into two halves, one half goes to the next cell, and the
other half flows in one of two parallel MOS switches. These switches are controlled using a digital bit
‘a’ and its complement. Finally, the currents of the switches controlled using ‘a’ are added together to
give the CDN output current Io1, while the currents of the switches controlled using ‘a’ and the last cell
second half current are added to give the second output current Io2. The current division principle
depends on the fact that the value of the equivalent resistance seen at the cell output nodes – the one
connected to the next cell and the one connected to the switches – are equal. This can be achieved
only when the output current nodes Io1 and Io2 potentials are zero regardless of the transistors mode
of operation. Thus, a second CCII X port is connected to the CDN first output node while
grounding the CCII’s Y port to obtain a virtual ground. This X port differential current is conveyed
to the Z port such that the relation between the X and Z port differential currents is given by:

IZd ¼ aIXd (5)

The CCII CMOS circuit diagram is shown in Figure 3. The circuit voltage conveying action
between Y and X ports is realized using a fully differential voltage buffer [11]. The buffer consists
of two NMOS differential amplifiers (M1–M2 and M3–M4) having two of their transistors
connected to a constant current source (M5 and M6), and they have the same biasing tail currents
(M7 and M8). If all transistors operate in the saturation region, then the differential amplifiers will
have equal differential voltages. The current conveying action is achieved using two class AB
output stages M11, 12, 20, 21 and M15, 16, 22, 23. The standby current of the class AB output
stage is controlled using transistors M9, 10, 13, 14, 17, 18 and 19. Finally, a simple common-mode
feedback circuit is used to adjust the X port common mode value by generating the biasing voltage
VCMFB and applying it to the gates of M24 and M25.
The DPCCII is realized and simulated using 90 nm IBM CMOS technology model under balanced
supply voltage of
0.5 V. The DC standby power consumption of the DPCCII is 2.41 mW. The
differential voltage conveying action between the Y and X ports is tested with single-ended 1 kΩ

Figure 2. Circuit diagram of three-bit MOS R-2R CDN [10].

Copyright © 2012 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2013; 41:1074–1084
DOI: 10.1002/cta
 DIGITALLY PROGRAMMABLE CURRENT CONVEYOR, FPAA, UNIVERSAL FILTER 1077

Figure 3. CMOS circuit diagram of the fully differential CCII used to realize the DPCCII [11].

load at X port while varying the codeword ‘a2a1a0’. The digital bit logic ‘1’ and ‘0’ are given by 0.5 V
and 0.5 V, respectively. The voltage conveying action is shown in Figure 4. The voltage conveying
is achieved while the Y differential voltage is varied from 0.2 V to 0.2 V. It is also shown that the
voltage conveying action is not affected by the codeword variation as expected. The DPCCII
current conveying and scaling properties are also tested. The X and Z ports are connected to single-
ended 1 kΩ while applying a variable differential voltage source at Y port. The ratio between the Z port
negative differential current and the Y port differential voltage is defined as the trans-conductance gain
of the DPCCII. The trans-conductance gain simulation result is shown in Figure 5 while varying the
codeword. The differential current at Z port is linearly proportional to the Y port differential voltage
with proportionality constant ‘a’. The finite output resistance at X port and the offset voltage are shown
in Figures 6 and 7, respectively. They vary slightly with the codeword. Table I contains summary of
the proposed DPCCII simulation results.
The DPCCII input referred noise is dominated by flicker noise. Its value is around 50 nV/sqrt (Hz) at
the 3-dB bandwidth. It is almost constant with respect to the codeword. The third-order harmonic
distortion is at 100 mVpp and 1 MHz frequency while the codeword is ‘111’ is 46.37 dB.
The simulation results show that the proposed DPCCII can be used to realize high-frequency
applications. The DPCCII can be digitally controlled to give zero output current by setting the value
of the codeword to ‘000’. This feature makes the circuit a perfect candidate to be used in any
hierarchal structure. Any number of DPCCII circuits’ outputs can be connected together, yet each
one can be independently controlled.

Figure 4. Voltage conveying action of the DPCCII.

Copyright © 2012 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2013; 41:1074–1084
DOI: 10.1002/cta
1078 S. A. MAHMOUD AND E. A. SOLIMAN

Figure 5. Ratio between Z differential current and Y differential voltage of the proposed DPCCII.

Figure 6. Finite resistance at X terminal of the proposed DPCCII.

Figure 7. Offset voltage at X port of the proposed DPCCII.

3. PROPOSED DPCCII-BASED FPAA

Almost all the previous FPAAs were able to realize analog circuits that can operate in the range of a few
hundred kilo Hertz. The factor responsible for degrading the FPAAs frequency response was the
interconnecting network. Pass transistors, floating gate transistors and transmission gates were used to
realize the interconnection network [12,13]. However, the parasitic capacitance in the signal path was

Copyright © 2012 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2013; 41:1074–1084
DOI: 10.1002/cta
 Table I. Proposed DPCCII simulation results.

Copyright © 2012 John Wiley & Sons, Ltd.

Parameter Codeword ‘a2a1a0’
000 001 010 011 100 101 110 111

Voltage conveying range [mV]
200

Current conveying range [mA]
200
Standby DC power consumption [mW] 2.41
Maximum offset voltage at X port [mV] 2.43 2.49 2.53 2.59 2.67 2.78 2.93 3.27
Maximum finite resistance at X port [Ω] 12.4 12.7 13 13.3 14 14.9 16.8 20.9
Voltage conveying gain open circuit 3 dB-BW [GHz] 1.17 1.2 1.23 1.25 1.29 1.29 1.33 1.37
Current conveying gain 3-dB BW under 1 kΩ load [MHz] -- 178 174 172 227 172 194 207
Ideal trans-conductance gain between Z and Y ports 0 0.125 0.25 0.375 0.5 0.625 0.75 0.875
at 1 kΩ load [mA/V]
Simulated trans-conductance gain between Z and Y 0 0.118 0.235 0.34 0.46 0.57 0.7 0.81
ports at 1 kΩ load [mA/V]
DIGITALLY PROGRAMMABLE CURRENT CONVEYOR, FPAA, UNIVERSAL FILTER

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1080 S. A. MAHMOUD AND E. A. SOLIMAN

still high or the switches programming was complicated. Thus, some designs eliminated the use of
interconnection network by using CABs that can be turned on/off. This method can be achieved by
connecting the CAB biasing current sources to the voltage supplies via switches [6,14]. However, the
power consumption of the FPAA was not fixed, and to realize programmable applications, the CABs had
to be designed using programmable active circuits. The design of programmable OTA or voltage op-amp
was not an easy task. Thus, the need for a simple yet controllable active circuit for FPAA became a must.
The proposed FPAA architecture is shown in Figure 8. The FPAA consists of seven CABs arranged in
a hexagonal lattice. The CABs consists of DPCCII whose output current can be set to zero by setting the
codeword to ‘000’; thus, one can connect more than one DPCCII to a single summing node and control
which DPCCII circuits are turned on/off. This connection will only increase the total parasitic
capacitance at the summing node. This problem can be solved by careful sizing of the DPCCIIs. Each
CAB has a single summing node. By this hexagonal arrangement, no interconnection network is
needed. This is considered a great advantage compared to other FPAA designs [1,5,12, 13]. The
hexagonal arrangement was used for OTA-based FPAA [6]; however, programming the OTA was
done by realizing tunable biasing current sources – through analog control voltage – and additional
shift registers were needed to save the control voltages values. The proposed FPAA is programmed in a
much simpler way using only digital codeword.
The proposed FPAA consists of seven CABs. The CABs at the edges of the FPAA have the same
design, while the CAB at the center has different architecture. The FPAA has seven differential
summing ports that can be used as an input voltage port or as an output current port. These differential
ports are located at the center of each CAB. The CABs located at the edges of the FPAA contain four
DPCCII named ‘A, B, C and D’. For simplicity, a single-ended DPCCII is drawn inside the CABs as
shown in Figure 8. The Y ports of the DPCCIIs inside each CAB are connected to the summing node
located at the center of the CAB, while each circuit Z port is connected to the summing node of an
adjacent CAB except for the ‘D’ circuit. The Z port of the ‘D’ circuits of CABs one, two and three are
connected to the X port of circuit ‘A’ in CAB number four and those of CABs four, five and six to the
X port of circuit ‘A’ in CAB number one. These connections provide multiple order feedback
connections between different DPCCIIs. These connections are essential for realizing different filter
topologies. As for the centered CAB, it consists of six DPCCIIs ‘A, B, C, D, E and F’. Their Y ports
are connected to the summing node at the center of the CAB, and each circuit Z port is connected to
one adjacent CAB summing node.
The summing node current of each CAB is used as the FPAA output current signal. A grounded
resistor and/or capacitor can be connected to the summing node at the center of each CAB to realize
different analog circuits like amplifiers or integrators. These passive elements are placed off chip to

Figure 8. Proposed DPCCII-based FPAA architecture.

Copyright © 2012 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2013; 41:1074–1084
DOI: 10.1002/cta
 DIGITALLY PROGRAMMABLE CURRENT CONVEYOR, FPAA, UNIVERSAL FILTER 1081

reduce the chip size and to enable the FPAA user to have a degree of freedom to select their values
according to his design and also to compensate for process variations unlike previous FPAA designs.
For instance, in [15] the CAB used can be tuned using programmable current source. The current
source biasing circuit was realized using current mirrors which make the circuit subjected to transistor
mismatching problems. Also, it is worth mentioning that the CCII is a very attractive active circuit that
can be used to realize different two port networks like negative impedance converters [16]. Thus, the
proposed FPAA can be used to realize almost any filter topology. The FPAA standby DC power
consumption is 72.4 mW. The proposed FPAA is digitally programmed, thus no extra hardware is
needed neither for storing the programming biasing voltages nor for the signal routing between
different CABs. Table II contains comparison between the presented work and previous FPAA design.

4. APPLICATIONS USING DPCCII-BASED FPAA

A second-order tunable universal filter based on DPCCII is realized using the proposed FPAA. The filter
block diagram is shown in Figure 9 [17]. The filter has three different responses: high pass, band pass and
low pass. The transfer functions of the filter are given by the following equations:

VHP R S2 a1
¼  2 (6)
Vin Ri S þ S R1 R2 C4 R þ Ra1Ra2Ra3Ca5 CR
a a a
1 4 1 1 2 3 1 2

VBP R S Ra11 Ca21

¼  2 (7)
Vin Ri S þ S aR1 aR2 aC4 R þ Ra1Ra2Ra3Ca5 CR
1 4 1 1 2 3 1 2

1 2 3 a a a
VLP R R1 R2 C1 C2
¼  2 (8)
Vin Ri S þ S R1 R2 C4 R þ Ra1Ra2Ra3Ca5 CR
a a a
1 4 1 1 2 3 1 2

The filter cutoff frequency and quality can be independently controlled using the programmable current
scaling factors. For example, considering the following design parameters: Ri = R1 = R2 = R3 = R, equal C,
a1 = a5 = 0.875, a2 = a3 = ao and a4 = aQ; then the cutoff frequency and quality factor will be defined by the
equations (9) and (10) respectively.

0:875ao
oo ¼ (9)
RC

R4
Q¼ (10)
aQ R

Table II. Comparison between the proposed FPAA and prior design.
Parameter This work The work in [6]
Technology 90 nm 0.13 mm
Power dissipation 72.4 mW 70 mW
CAB’s active circuit DPCCII OTA cell
Number of CABs 7 7
Number of active circuits 30 55
Applications based on the FPAA BPF/LPF/HPF BPF/LPF
Number of bits required to configure a CAB 12 to 18 49
Need for additional memory for CAB control None per CAB 35 per CAB
Maximum input voltage for CAB/supply voltage 40% 8.33%

Copyright © 2012 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2013; 41:1074–1084
DOI: 10.1002/cta
1082 S. A. MAHMOUD AND E. A. SOLIMAN

Figure 9. DPCCII-based second-order tunable universal filter.

Figure 10. Universal filter mapped on the proposed FPAA.

Thus, the filter cutoff frequency and quality factor can be tuned using ao and aQ, respectively. The
filter is mapped on the FPAA such that ‘A1, B6, A4, D5 and D4’ are the DPCCIIs used and they are
programmed using a1, a2, a3, a4 and a5, respectively, as shown in Figure 10. The filter is simulated

Copyright © 2012 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2013; 41:1074–1084
DOI: 10.1002/cta
 DIGITALLY PROGRAMMABLE CURRENT CONVEYOR, FPAA, UNIVERSAL FILTER 1083

using the same design equations above, and the values of R and C are selected at 0.65 kΩ and 50 pF,
respectively. The cutoff frequency programmability is shown in Figures 11 and 12 where the low-pass
and high-pass responses are shown, respectively. The cutoff frequency is varied from 3.5 MHz to 2
MHz with step 0.5 MHz while varying the codeword ao from 0.875 to 0.5, respectively. The filter
quality factor tuning is examined using the previous design equations at R and C of 0.5 kΩ and
50 pF while varying the current gain factor aQ as shown in Figure 13. The filter noise is measured

Figure 11. Magnitude response of the filter’s low-pass output.

Figure 12. Magnitude response of the filter’s high-pass output.

Figure 13. Magnitude response of band-pass output while varying aQ.

Copyright © 2012 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2013; 41:1074–1084
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1084 S. A. MAHMOUD AND E. A. SOLIMAN

from simulations. The measured band-pass filter input referred noise at the center frequency while
ao = 0.875 is constant at 80 nV/sqrt (Hz).

5. CONCLUSION

A novel hexagonal DPCCII-based FPAA is introduced. The FPAA is digitally controlled with no added
hardware for CAB interconnection. The FPAA consists of seven CABs. The CAB basic unit is a novel
DPCCII realized using fully differential CCII and three-bit MOS R-2R ladder CDN. The circuit is
realized using 90 nm CMOS technology under supply voltage of
0.5 V. The DPCCII-based FPAA
total power consumption is 72.4 mW. The FPAA is used to realize a second-order tunable universal
filter. The filter cutoff frequency and quality factor are digitally programmed.

ACKNOWLEDGMENTS
The work in this paper is a part of the project with title: ‘Design of CMOS Field Programmable Analog
Array and its Applications’ and with ID # 648. This project is funded by the Science and Technology
Development Fund (STDF) of the Arab Republic of Egypt and the Federal Ministry of Education and
Research (BMBF) of the Federal Republic of Germany of regulations governing the funding of joint
innovative projects in the field of applied research through the ‘Egyptian-German Fund’.

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Copyright © 2012 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2013; 41:1074–1084
DOI: 10.1002/cta