BICOL STATE COLLEGE OF APPLIED SCIENCES AND TECHNOLOGY

City of Naga
College of Engineering and Architecture

Electronics Circuits Analysis and Design

TWO STAGE CASCADED TRANSISTOR AMPLIFIER

Kristle Irene Mae B. Albino

BSECE - 3B

Engr. Bennyvic Joyce Esguerra

Instructor

October 18, 2017

OBJECTIVE

To achieve higher levels of gain without sacrificing gain flatness across the design
bandwidth of interest. This project will show the overall gain, and coupling of RC-Coupled
BJT Amplifier.

INTRODUCTION

Often, a single stage transistor amplifier may not provide enough gain or input/output
impedance for a desired application, to avoid this problem, we can use amplifier stages to form
a multistage amplifier with the desirable gain or impedance properties. A single stage amplifier
didn’t provide sufficient gain and bandwidth and moreover didn’t have matched input and
output impedance. To overcome such problems multiple amplifiers are combined for better
performance and amplification.

Multiple amplifiers are connected in cascade to increase the overall voltage gain of the
amplifier. Multistage amplifiers are made up of single transistor amplifiers connected in
cascade. The first stage usually provides a high input impedance to minimize loading the source
(transducer). The middle stages usually account for most of the desired voltage gain. The final
stage provides a low output impedance to prevent loss of signal (gain) and to be able to handle
the amount of current required by the load. In analyzing multistage amplifiers, the loading
effect of the next stage must be considered since the input impedance of the next stage acts as
the load for the current stage. Therefore, the AC analysis of a multistage amplifier is usually
done starting with the final stage. The individual stages are usually coupled by either capacitor
or direct coupling. Capacitor coupling is most often used when the signals being amplified are
AC signals. In capacitor coupling the stages are separated by a capacitor which blocks the DC
voltages between each stage. This DC blocking prevents the bias point of each stage from being
upset.

The overall gain of the amplifier is the product of all the gain of each amplifier within
the stage which is given by

Av = A1 x A2….. x An
Two Stage Cascaded Transistor Amplifier Circuit Design

Computations:

Computing for Beta

𝐼𝐶
𝛽=
𝐼𝐵

8.78𝑚𝐴
=
39.8𝜇𝐴

𝛽 = 𝟐𝟐𝟎
DC Analysis

𝑹𝑻𝑯 = 𝑅1 ||𝑅2 = 4.7𝑘𝛺||2.2𝑘𝛺

= 𝟏. 𝟒𝟗𝟗𝒌𝜴

𝑅2 2.2𝑘𝛺
𝑬𝑻𝑯 = 𝑉𝐶𝐶 ( ) = 30𝑉 ( )
𝑅1 + 𝑅2 4.7𝑘𝛺 + 2.2𝑘𝛺

= 𝟗. 𝟓𝟔𝟓𝑽

𝐸𝑇𝐻 − 𝑉𝐵𝐸 9.565𝑉 − 0.7𝑉

𝑰𝑩 = =
𝑅𝑇𝐻 + (𝛽 + 1)(𝑅𝐸 ) 1.499𝑘𝛺 + (220 + 1)(1𝑘𝛺)

= 𝟑𝟗. 𝟖𝟒𝟒𝝁𝑨

𝑰𝑬 = 𝐼𝐵 (𝛽 + 1) = (39.844𝜇𝐴)(220 + 1)

= 𝟖. 𝟖𝟎𝟔𝒎𝑨

𝑽𝑪 = 𝑉𝑐𝑐 − 𝐼𝑐 𝑅𝑐 = 30𝑉 − (8.766𝑚𝐴)(1.5𝑘𝛺)

= 16.852V

𝑽𝑬 = 𝐼𝐸 𝑅𝐸 = (8.806𝑚𝐴)(1𝑘𝛺)

=8.806V

𝑽𝑩 = 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸 = 0.7 + (8.806𝑚𝐴)(1𝑘𝛺)

=9.506V

AC Analysis
26𝑚𝑉 26𝑚𝑉
𝒓𝒆 = =
𝐼𝐸 8.806𝑚𝐴
𝒓𝒆 = 𝟐. 𝟗𝟓𝟑𝜴

𝒁𝒊 = 𝑅1 ||𝑅2 ||𝛽𝑟𝑒 = 4.7𝑘𝛺||2.2𝑘𝛺||(220)(2.953𝛺)

𝑹𝒊 = 𝟒𝟓𝟑. 𝟏𝟓𝟖𝜴

1 1
𝒇𝑳𝑺 = =
2𝜋𝑅𝑖 𝐶𝑠 2𝜋(453.158𝛺)(0.1𝜇𝐹)

𝒇𝑳𝑺 = 𝟑. 𝟓𝟏𝟐𝒌𝑯𝒛
 𝑹𝒐 = 𝑅𝐶 = 1.5𝑘𝛺

1 1
𝒇𝑳𝑪 = =
2𝜋(𝑅𝑜 + 𝑅𝐿 )𝐶𝐶 2𝜋(1.5𝑘𝛺 + 1𝑘𝛺)(. 1𝜇𝐹)

𝒇𝑳𝑪 = 𝟔𝟑𝟔. 𝟔𝟐𝟎𝑯𝒛

𝑅1 ||𝑅2 4.7𝑘𝛺||2.2𝑘𝛺
𝑹𝒆 = 𝑅𝐸 ||( + 𝑟𝑒 ) = 1𝑘𝛺|| ( + 2.953𝛺)
𝛽 220

= 𝟗. 𝟔𝟕𝟎𝜴

1 1
𝒇𝑳𝑬 = =
2𝜋𝑅𝑒 𝐶𝐸 2𝜋(9.670𝛺)(0.1𝜇𝐹)

𝒇𝑳𝑬 = 𝟏. 𝟔𝟒𝟔𝒌𝑯𝒛

𝒇𝑪 = 𝟑. 𝟓𝟏𝟐𝒌𝑯𝒛

𝑅𝑐 ||(𝑅1 ||𝑅2 ||𝛽𝑟𝑒 ) 1.5𝑘𝛺||(4.7𝑘𝛺||2.2𝑘𝛺||(220)(2.953𝛺))

𝑨𝒗𝟏 = − =−
𝑟𝑒 2.953𝛺

= −𝟏𝟏𝟕. 𝟖𝟔𝟓

𝑅𝑐 ||𝑅𝐿 1.5𝑘𝛺||1𝑘𝛺
𝑨𝒗𝟐 = − =−
𝑟𝑒 2.953𝛺

= −𝟐𝟎𝟑. 𝟐𝟎𝟒

𝑨𝒗𝑻 = (𝐴𝑉1 )(𝐴𝑉2 ) = (−117.865)(−203.204)

𝑨𝒗𝑻 = 𝟐𝟑. 𝟗𝟓𝟏 × 𝟏𝟎𝟑

𝑽𝒐 = 𝐴𝑉𝑇 𝑉𝑖𝑛 = (23.951 × 103 )(. 1𝑉)

=2.3951kV
 Signal Results

 Input
 Output

CONCLUSION

When voltage is increase beyond 30V the gain increases but the output is clipped off.
The gain and bandwidth of the amplifier is optimized precisely with all the biasing circuit
elements. The maximum allowable input swing is 100mV peak to peak.