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PD - 94149

IRF3205S/L
HEXFET® Power MOSFET
l Advanced Process Technology D
l Ultra Low On-Resistance VDSS = 55V
l Dynamic dv/dt Rating
l 175°C Operating Temperature RDS(on) = 8.0mΩ
l Fast Switching G
l Fully Avalanche Rated ID = 110A…
S
Description
Advanced HEXFET® Power MOSFETs from International Rectifier
utilize advanced processing techniques to achieve extremely low on-
resistance per silicon area. This benefit, combined with the fast
switching speed and ruggedized device design that HEXFET power
MOSFETs are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of applications.

The D 2 Pak is a surface mount power package capable of


accommodating die sizes up to HEX-4. It provides the highest power
capability and the lowest possible on-resistance in any existing surface
mount package. The D2Pak is suitable for high current applications D2Pak TO-262
because of its low internal connection resistance and can dissipate up IRF3205S IRF3205L
to 2.0W in a typical surface mount application.
The through-hole version (IRF3205L) is available for low-profile
applications.

Absolute Maximum Ratings


Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 110 …
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 80 A
IDM Pulsed Drain Current  390
PD @TC = 25°C Power Dissipation 200 W
Linear Derating Factor 1.3 W/°C
VGS Gate-to-Source Voltage ± 20 V
IAR Avalanche Current 62 A
EAR Repetitive Avalanche Energy 20 mJ
dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting torque, 6-32 or M3 srew 10 lbf•in (1.1N•m)

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.75 °C/W
RθJA Junction-to-Ambient (PCB mounted, steady-state)* ––– 40

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03/09/01
IRF3205S/L
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.057 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 8.0 mΩ VGS = 10V, ID = 62A „
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 44 ––– ––– S VDS = 25V, ID = 62A„
––– ––– 25 VDS = 55V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 44V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
Qg Total Gate Charge ––– ––– 146 ID = 62A
Qgs Gate-to-Source Charge ––– ––– 35 nC VDS = 44V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 54 VGS = 10V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 14 ––– VDD = 28V
tr Rise Time ––– 101 ––– ID = 62A
ns
td(off) Turn-Off Delay Time ––– 50 ––– RG = 4.5Ω
tf Fall Time ––– 65 ––– VGS = 10V, See Fig. 10 „
Between lead, D
LD Internal Drain Inductance ––– 4.5 –––
6mm (0.25in.)
nH G
from package
LS Internal Source Inductance ––– 7.5 –––
and center of die contact S

Ciss Input Capacitance ––– 3247 ––– VGS = 0V


Coss Output Capacitance ––– 781 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 211 ––– pF ƒ = 1.0MHz, See Fig. 5
EAS Single Pulse Avalanche Energy‚ ––– 1050† 264‡ mJ IAS = 62A, L = 138µH

Source-Drain Ratings and Characteristics


Parameter Min. Typ. Max. Units Conditions
D
IS Continuous Source Current MOSFET symbol
––– ––– 110
(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

––– ––– 390


(Body Diode) p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 62A, VGS = 0V „
trr Reverse Recovery Time ––– 69 104 ns TJ = 25°C, IF = 62A
Qrr Reverse Recovery Charge ––– 143 215 nC di/dt = 100A/µs „
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Repetitive rating; pulse width limited by „ Pulse width ≤ 400µs; duty cycle ≤ 2%.
max. junction temperature. ( See fig. 11 )
… Calculated continuous current based on maximum allowable
‚ Starting TJ = 25°C, L = 138µH junction temperature. Package limitation current is 75A.
RG = 25Ω, IAS = 62A. (See Figure 12)
† This is a typical value at device destruction and represents
ƒ ISD ≤ 62A, di/dt ≤ 207A/µs, VDD ≤ V(BR)DSS, operation outside rated limits.
TJ ≤ 175°C
‡This is a calculated value limited to TJ = 175°C.
* When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
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IRF3205S/L
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
I D , Drain-to-Source Current (A)

I D , Drain-to-Source Current (A)


8.0V 8.0V
7.0V 7.0V
6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
BOTTOM 4.5V BOTTOM 4.5V
100 100

4.5V

10 10
4.5V

20µs PULSE WIDTH 20µs PULSE WIDTH


TJ = 25 °C TJ = 175°C
1 1
0.1 1 10 100 0.1 1 10 100
VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.5
RDS(on) , Drain-to-Source On Resistance

ID = 107A
I D , Drain-to-Source Current (A)

TJ = 25 ° C
2.0
TJ = 175° C
100
(Normalized)

1.5

1.0
10

0.5

V DS = 25V
20µs PULSE WIDTH VGS = 10V
1 0.0
4 6 8 10 12 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature ( ° C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance


Vs. Temperature

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IRF3205S/L
6000 16
VGS = 0V, f = 1 MHZ ID = 62A

VGS , Gate-to-Source Voltage (V)


Ciss = Cgs + Cgd, Cds SHORTED V DS= 44V
14 V DS= 27V
5000 Crss = Cgd
V DS= 11V
Coss = Cds + Cgd
12
C, Capacitance(pF)

4000
Ciss 10

3000 8

6
2000 Coss
4
1000
Crss 2

0 0
1 10 100 0 20 40 60 80 100 120
QG , Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.


Drain-to-Source Voltage Gate-to-Source Voltage

1000 10000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
ISD , Reverse Drain Current (A)

TJ = 175° C
100
ID , Drain Current (A)

1000

10us

10 100
100us

TJ = 25 ° C
1ms
1 10
10ms
TC = 25 ° C
TJ = 175 °C
V GS = 0 V Single Pulse
0.1 1
0.2 0.8 1.4 2.0 2.6 1 10 100 1000
VSD ,Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area


Forward Voltage

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IRF3205S/L
RD
120 VDS
LIMITED BY PACKAGE VGS
D.U.T.
100 RG
+
V DD
ID , Drain Current (A)

-
80
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
60

Fig 10a. Switching Time Test Circuit


40
VDS

20 90%

0
25 50 75 100 125 150 175
TC , Case Temperature ( ° C) 10%
VGS
td(on) tr t d(off) tf

Fig 9. Maximum Drain Current Vs. Fig 10b. Switching Time Waveforms
Case Temperature

1
Thermal Response(Z thJC )

D = 0.50

0.20

0.1 0.10

0.05 PDM

SINGLE PULSE t1
0.02 (THERMAL RESPONSE)
0.01 t2

Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x ZthJC + TC
0.01
0.00001 0.0001 0.001 0.01 0.1 1
t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRF3205S/L
500

EAS , Single Pulse Avalanche Energy (mJ)


15V ID
TOP 25A
44A
400 BOTTOM 62A
L D R IV E R
VDS

300
RG D .U .T +
- VD D
IA S A
20V
tp 0 .0 1 Ω 200

Fig 12a. Unclamped Inductive Test Circuit


100

V (B R )D S S
tp 0
25 50 75 100 125 150 175
Starting TJ , Junction Temperature ( ° C)

Fig 12c. Maximum Avalanche Energy


Vs. Drain Current

IAS

Fig 12b. Unclamped Inductive Waveforms


Current Regulator
Same Type as D.U.T.

50KΩ

12V .2µF
QG .3µF

10 V +
V
D.U.T. - DS
QGS QGD
VGS
VG 3mA

IG ID
Charge Current Sampling Resistors

Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit

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IRF3205S/L
Peak Diode Recovery dv/dt Test Circuit

+ Circuit Layout Considerations


D.U.T
• Low Stray Inductance
• Ground Plane
ƒ
• Low Leakage Inductance
Current Transformer
-

+
‚
„
- +
-


RG • dv/dt controlled by RG +
• Driver same type as D.U.T. VDD
-
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test

Driver Gate Drive


P.W.
Period D=
P.W. Period

VGS=10V *

D.U.T. ISD Waveform

Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD

Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 14. For N-Channel HEXFETS


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IRF3205S/L

D2Pak Package Outline

10.54 (.415) -B- 10.16 (.400)


10.29 (.405) 4.69 (.185) REF.
1.40 (.055) 4.20 (.165)
-A- 1.32 (.052)
M A X. 1.22 (.048)
2
6.47 (.255)
6.18 (.243)

1.78 (.070) 15.49 (.610) 2.79 (.110)


1.27 (.050) 1 3 14.73 (.580) 2.29 (.090)

5.28 (.208) 2.61 (.103)


4.78 (.188) 2.32 (.091)

8.89 (.350)
1.40 (.055) 1 .39 (.055) REF.
3X
1.14 (.045) 0.93 (.037) 0.55 (.022) 1 .14 (.045)
3X 0.46 (.018)
0.69 (.027)
5.08 (.200 ) 0.25 (.010) M B A M M IN IM U M R E C O M M E N D E D F O O TP R IN T

11.43 (.4 50)

N O TE S : LE A D A S S IG N M E N TS 8.89 (.350)
1 D IM E N S IO N S A F T E R S O LD E R D IP . 1 - G A TE
2 - D R A IN 17.78 (.700)
2 D IM E N S IO N IN G & TO LE R A N C IN G P E R A N S I Y 14.5M , 1982.
3 - SOURCE
3 C O N T R O LLIN G D IM E N S IO N : IN C H .
4 H E A TS IN K & LE A D D IM E N S IO N S D O N O T IN C LU D E B U R R S .
3.81 (.150)

2.54 (.100)
2.08 (.082) 2X
2X

D2Pak Part Marking Information

A
IN TE R N A T IO N A L PART NUMBER
R E C TIF IE R
F530S
LOGO
9246
9B 1M D A TE C O D E
(Y Y W W )
ASSEMBLY
YY = YEAR
LOT CODE
W W = W EEK
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IRF3205S/L

TO-262 Package Outline

TO-262 Part Marking Information

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IRF3205S/L

D2Pak Tape & Reel Information


TRR

1 .6 0 (.0 6 3 )
1 .5 0 (.0 5 9 )
1.60 (.06 3)
4 .1 0 (.1 6 1 ) 1.50 (.05 9)
3 .9 0 (.1 5 3 ) 0 .3 68 (.014 5 )
0 .3 42 (.013 5 )

F E E D D IR E C T IO N 1 .8 5 (.0 7 3 ) 1 1 .6 0 (.4 57 )
1 .6 5 (.0 6 5 ) 1 1 .4 0 (.4 49 ) 2 4.30 (.9 5 7)
15 .4 2 (.60 9 )
2 3.90 (.9 4 1)
15 .2 2 (.60 1 )
TR L
1.75 (.0 69 )
10 .9 0 (.42 9 ) 1.25 (.0 49 )
10 .7 0 (.42 1 ) 4.7 2 (.1 36 )
1 6 .10 (.6 3 4) 4.5 2 (.1 78 )
1 5 .90 (.6 2 6)

F E E D D IR E C T IO N

13.50 (.532) 27.40 (1.079)


12.80 (.504) 23.90 (.941)

330.00 60.00 (2.362)


(14.1 73) M IN .
M A X.

30.40 (1.197)
NOTES : M AX.
1. C O M F O R M S TO E IA-418. 26 .40 (1.039) 4
2. C O N T R O LLIN G D IM EN S IO N : M ILLIM E T ER . 24 .40 (.961)
3. D IM E N S IO N M E A S U R E D @ H U B .
3
4. IN C LU D E S F LA N G E D IS T O R T IO N @ O U T E R E D G E .

Data and specifications subject to change without notice.


This product has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.3/01
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