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April 1999
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iv
TABLE OF CONTENTS
Page
1. INTRODUCTION..........................................................................................................I
Purpose................................................................ I
ts> to
Assumptions And Limitations......................
Summary OfThe Remainder OfThis Thesis
2. LITERATURE AND INDUSTRY REVIEW ................. ......................................... 3
Introduction..............................................................................................................3
Patents......................................................................................................................3
Technical Journals...................................................................................................4
Industry Publications.............................................................................................. 7
Product Advertisements.........................................................................................7
Product Literature...................................................................................................8
3. METHODOLOGY .....................................................................................................9
Introduction...................................................................................................... 9
System Component Characteristics..................... 9
Testing T echnique...................................... .....................................j....................11
Fault Location Process...........................................................................................12
Power Supply................ 15
4. PRESENTATION AND ANALYSIS OF THE DATA...............................................16
Cable Testing Issues..............................................................................................16
Cable Characteristics............................... 16
Cable Required Charging Energy................................. 20
Cable Simulation.......................................................................................... 20
Residential Pad Mounted Transformer............. 21
Embedded Controller................................................................................... 27
TDR Supply Module............................................. 28
TDR Transmitter Module.............................................................................34
TDR Receiver/D elector Module....,........ .....................................................39
Time-to-Digital Converter............................................................................43
High-Voltage Supply Controls and Voltage Monitor Buffers..................... 49
High-Voltage Test Section.....................................................................................52
HV Capacitor.......................................................... !............................................54
Discharge Resistor.................................................................................................54
High-voltage Switch..............................................................................................55
ARM Filter.............................................................................................................59
TABLE OF CONTENTS—Continued
Page
TDR Coupler..........................................................................................................64
EM/ES Noise Control............................................................................................67
Battery Supply.......................................................................................................67
Battery Charger......................................... 68
Low-Voltage Supplies...........................................................................................68
Project Test Results.............................................................. 70
Project Demonstration Anomalies.........................................................................92
5. SUMMARY, CONCLUSIONS, AND RECOMMENDATIONS................ 93
Summary........................................................................................ 93
Conclusions............................................................................................................94
Recommendations..................................................................................................95
REFERENCES..................................................................................................................97
BIBLIOGRAPHY................................................................................................... 99
APPENDICES................................................................................................................. 101
LIST OF TABLES—Continued
Page
LIST OF FIGURES
Page
TTST OF FTGTTRES-Continued
Page
Utility power companies which service residential customers with 7200 VAC
underground cable circuits (15 kV Class Cable) that fault (circuit interrupter activated)
are faced with determining circuit integrity prior to energizing the circuit. Current testing
techniques involve energizing the circuit with a new fuse. If the fuse holds, the faulted
circuit is cleared. If fused, however, the circuit is systematically sectionalized until the
faulted section is localized and isolated. This sectional troubleshooting process produces
line surges on adjacent customer circuits, causing such inconveniences as the necessity of
rebooting computers, and stresses on the power system, lighting, and appliances.
Power cable testing equipment presently exists which could be used to pretest the
circuit, however, the equipment may not be economically feasible or convenient to use.
The object of this study is to investigate an economically feasible, portable tester which
can pretest a faulted circuit and report the approximate distance to a detected fault.
A review of applicable literature; power industry products; cable and connected
transformer characteristics; circuit simulation and fault analysis is included.
A micro-controlled prototype using a TDR time-to-digital technique to determine
cable/fault distance, coupled with a high-voltage impulse generator (thumper) is designed
and demonstrated. Modular circuit design, implementation, test results, and parts lists are
outlined. The test results reported are for various cable circuit conditions: open circuit,
short circuit, high-impedance fault, minimum resistive termination that results in a no
fault detection, maximum resistive termination that causes a detected fault, high-
impedance fault with a transformer, minimum resistive termination that results in a no
fault detection with a transformer, and maximum resistive termination that causes a
detected fault with a transformer.
This thesis concludes with a brief summary of the study, conclusions drawn from
the prototype results, and resulting recommendations.
I
CHAPTER I
INTRODUCTION
Utility power companies which service residential customers with 7200 VAC
underground cable circuits (15 kV Class Cable) that experience a fault condition (circuit
breaker activated) are faced with determining circuit integrity prior to energizing the
circuit. The testing technique currently used by most power companies to evaluate a
faulted circuit involves energizing the circuit with a new fuse and, if the fuse holds, then
the circuit fault is cleared. However, if fused, the circuit is systematically sectionalized,
re-fused and re-energized until the faulted section is localized and isolated. This
sectional troubleshooting process causes undesirable stress on the power system, and line
surges on adjacent customer circuits, resulting in added stresses to motors, lighting, and
Utility power company service personnel need a portable device that can be
a fault is detected, the approximate distance from the testing location to the fault needs to
be determined.
Purpose
economical and conveniently portable underground cable tester which has the ability to
i
2
energized circuits, thus eliminating the risk to customers' property which is inherent in
For convenient portability, it is assumed the cable tester to be under 1.0 cubic foot
in size and less than 50 pounds in weight. For cost considerations, a market value of less
than $3000 is assumed to be feasible. For normal/fault test reliability, 80% or better is
product literature which address underground cable fault detection processes and
including which process to use when performing a cable test; which instrumentation
technique to use for sensing a fault; and, the fault location process and portable power
process, portable power requirements and prototype results. Chapter 5 summarizes this
study, states conclusions to the data reported in Chapter 4, and makes recommendations
CHAPTER 2
Introduction
industrial techniques were available or being used to meet this need of power companies
as outlined in the previous chapter. The search was limited to appropriate US. patents
listed in the last five years; technical journals (IEEE Transactions on Instrumentation and
advertisements over the past seven years; and manufacturer's product literature.
Patents
Of the 25 related patents found, No. 5,210,498 is the most applicable to this
project. Titled "Detector for Locating Underground Cable and Faults Therein Using
transmitting an inducted signal into the cable and monitoring the signal on the surface.
4
Technical Journals
system with time delay. The estimator can be used to locate a discontinuity in a cable.
Fault location was based on the Time Domain Reflectometry (TDR) principle. The cable
was stimulated with a short duration pulse. The stimulus and first reflection were
sampled and the first F spectral line determined by the fast Fourier transform (FFT) is
sent to the estimation algorithm. The propagation velocity of the cable was required to
determine the final location of the fault. A simplified analytical model reported by
Abullma'atti [2] involves the modeling of a resistively or capacitively (RC) loaded line
based on finding the approximate poles of the transfer function. This transfer model
A transient propagation analysis through nonuni form structures and uniform lines
was reported by Schutt-Aine [3]. The analysis uses a scattering parameter formulation in
the time domain to establish closed-form algorithms for current and voltage variables in
the line. The technique was applied to microstrips, uniform, and tapered lines.
A digital signal process (DSP) algorithm was developed to estimate the location
of a fault by a line parameter estimation technique. Van Biesen [4], This process was
applied to sampled TDR data of a known unfaulted cable for calibration of line
parameters and compared with a faulted line to locate the discontinuity. The technique
5
requires the knowledge of the propagation speed for accuracy. The process is reported to
distortion from the harmonics present. The technique was applied to passive devices to
Fiber optic technology has been applied to locate cable faults, Kawai [6]. This
technique requires a fiber optic distributed temperature sensor (FODT) composite cable.
The premise is that a temperature rise occurs from the arc at a ground fault location.
Detection of the temperature rise is based on the Raman backscattering light which is
Accuracy was reported to be one meter (m) within a maximum measuring distance of ten
kilometers (km).
megasamples per second (Msps), analog-to-digital converter (ADC), frioue [7], The
system topology includes a 1000 m segmented cable section with fast, I MHz bandwidth,
optical current transformers (CT) mounted at each end. Optical fiber interconnects the
CTs to the O/E converter, ADC, and CPU. When a ground fault happens the surge
current flows from the point of the fault to both ends of the cable. The system monitors
6
the time delay of the surge current from each end and determines the fault location. The
reported location error of the system is less than 10 meters in a 1000 meter cable length.
Wiggins [8], Some of the characteristics of the fault wave are reported as a damped
Amps(A) near the fault, and 20 kV /1 0 A near the open end was measured for a 15 kV
open end (no transformer) was measured to be 60 ns at 1,100 ft from the fault, 100 ns at
1847 ft from the fault, and 20 ns at the open end, 90 ft from the fault. The maximum
frequency component is 50 MHz near the fault. The fault duration ranged between a
velocity varies from 440 ft/ps to 570 ft/ps for URD cables and 503 ft/ps for TRXLP. A
U.S. patent (No. 5,206,595) has been issued for digital circuitry of a calculator-sized fault
procedure, Steiner [9]. The first step determines the fault between two transformers and
the second step pinpoints the fault. The process for the first step involves the operator
entering estimated distances between all connected transformers into the testing device,
and performing a TDR test. The automated testing device determines the fault location
between two transformers. The second step involves the operator isolating the cable
7
section and reconnecting the test device at one end of the section. Another TDR test is
generated to estimate the fault location within 2% accuracy. An antenna is then placed
on both sides of the suspected fault location and another TDR test is generated. The test
device calculates the relative distance to the fault from the antenna. This process
determines the fault within 250 centimeters (cm). The defense for this process is that the
wave propagation rate is not predictable enough to get precise accuracy's in finding the
location. The demonstration site was at Purdue University. Details of the antenna design
Industry Publications
Product Advertisements
Searching the last five years of ELECTRICAL WORLD for related advertised
Product Literature
Of the products listed in Table I, none meet the industry's need for hand
CHAPTER 3
METHODOLOGY
Introduction
The purpose of this study is to evaluate the feasibility of developing a small hand-
portable, underground cable tester which can determine fault/no-fault conditions of de
energized circuits and estimates the distance to the fault while residential transformers are
connected, and which also meets portability (size under 1.0 cubic feet), weight (under 50
resistance, impedance, etc.) in the cable circuit to instrument such that faulted and normal
conditions can be discriminated. Since the objective is to determine the integrity of the
power circuit while de-energized, low DC voltage and low current measurements could
be used to calculate the resistance of the circuit, with a predetermined low resistance
value being an indicator of a fault. However, this testing technique is limited to low-
voltage breakdown faults and to direct short-circuits due to the primary resistance of the
attached transformers being of the order of one ohm (see Appendix A.) It is evident,
from the literature review, that the more difficult and frequent fault condition is the high-
10
resistance breakdown in which the circuit faults only when the nominal operating
voltage, 7200 VAC (10.2 kV peak), is applied. This fault condition is most frequently
mechanical deformation, etc.). In order to test the cable under these conditions, a high-
voltage needs to be applied to the cable in such a manner as to not have adverse effects to
measurable “fast” (>600 Hz) energy pulse can be used to charge a cable to near peak
voltage while having minimal effect on power customer’s equipment. In light of the
above, several cable testing issues posed in Table 5 are evaluated by use of published
Testing Technique
shown in Figure I.
HVOn 4-
MONHV - -L C D E N -
HVReIay 4- — LCDRW- 20x1 Character LCD DISPLAY
BIeedReIay 4- — LCD R S-
TDRDrvrHV 4- -DATA — * Battery^
Low Fault • TEST
— LEDBatLo — a Charger VOLTAGE
Q
CC
— LEDFauIt — NoFauIt •
UJ
On
Q g — LEDNoFauIt- a Main [0 ]U p
TDRStartTest 4- Q 0 — LEDReady — Power Velocity [o]
TDRDetStart —
UJ
DD 1 Factor I unitsJ [ o ] Dn
-VFU pS W —
TDRDetNoFauIt — O o n [o ] [o ]U p • Ready
O -VFDnSW —
TDRDetFauIt —
-UnitsSW — OFF [o] [ o ] Dn
[^ st
HVTest 4-
TDRDetRS 4- -TVUpSW —
TDRDetEN 4- -TVDnSW — OPERATOR PANEL
TDR DATA 4— TestSW ------
HVREF 4- DAC J — Beep----------
CLOCK RESET
The operator panel includes functional groupings of status and control switches.
In the primary power group, Main Power On is indicated by a green LED and controlled
by the ON and OFF switches. A yellow LED indicates when the charger is connected
(Charger On) and a red LED lights when the battery condition is too low to continue. In
the velocity factor group, two switches, Up and Dn, are used to select a velocity factor
between 50% and 100%. A Units switch is used to select between displayed distances in
feet or meters. In the Test group, two switches, Up and Dn, are used to select the high-
voltage (HV) test voltage and a yellow LED, Ready, indicates when the HV Test switch
12
can be pressed. Two LEDs, a red Fault and a green No Fault, are used to indicate the
results of low or high-voltage cable tests. The LCD display shows the velocity factor,
distance, and HV textual values and a graphical display indicates a relative battery
technique used to determine fault distance. This technique works on the principle that
I
energy traveling in a medium, cable in this case, takes an increment of time to traverse
encountered. When the discontinuity is an open ended cable the energy reflects in the
same polarity and traverses the medium in the opposite direction. If the discontinuity is a
short-circuit, however, the energy reflects in the opposite polarity (energy conservation
met for boundary conditions in both cases). If the instrumentation point in the system is
at the cable tester, then time variations in the reflected energy could determine if the
cable is faulted (reverse polarity) as well as the approximate distance to the fault (one-
half the time between start of the test pulse to the detected reflection).
The TDR process, depicted in Figure 2, connects to the test cable through the
TDR CONNECTOR and is used to determine the test cable’s low-voltage response. The
TDR TRANSMITTER produces test pulses with sufficient energy supplied from the
TDR SUPPLY to transverse the cable circuit in both directions and be detected by the
produces a HI signal for the test pulse and its unfaulted reflection or a LO signal when a
fault is detected in the cable circuit. The TIME-TO-DIGITAL CONVERTER latches the
state of the reflected pulse (HI or LO) and measures time by counting clock ticks between
the test pulse and the reflected pulse. The TDR DATA is presented to the processor for
scaling and displaying to the user. For high-voltage testing, a Thumper is added.
TDR
TDRDrvrHV
SU PPLY
TDR
CONNECTOR TDR
TDRStartTest
TRANSMITTER
TDRDetStart
TDRDetNoFauIt
TDRDetFauIt
Tl ME-TO-D IGITAL
R E C E IV E R / HVReIay
CONVERTER
DETECTOR TDRDetRS
TDRDetEN
TDR DATA
TD C
CLOCK
locating the position of a faulted cable. The Thumper presents high-voltage pulses which
create a "thump" sound at the site of a breakdown in an isolated cable circuit. Thumpers
are also used to “bum” the fault location to such an extent that physical destruction
occurs, aiding in locating the position. Thumpers are generally large, heavy, and
14
expensive, so one intention of this study is to design a scaled down Thumper for use in
The concept of a Thumper to perform the high-voltage cable test is used (see the
desired energy level and selectively switched via the HVRelay control into the TEST
CABLE circuit. The BleedRelay control in this circuit is used to decrease the stored
energy when the user selects a lower test voltage or turns the primary power off.
TEST CABLE
LV S U P P L Y ■
HVOn ■
HVREF ■
MONHV
test (Thumper) and the low-voltage TDR test circuit described above. Since there is only
a need for the high-voltage test to charge the cable only to a level that activates a high-
impedance fault, the high-voltage pulse can be conditioned so its dominate frequency
component is much lower than the TDR's operating frequency range. The ARM (Arc
Reflection Method) FILTER functions as the high-voltage test pulse conditioner and is
designed so the test pulse frequency component is at least an order of magnitude above
the nominal 60 Hertz (Hz) operating frequency of the test cable circuit. The TDR
COUPLER circuit is a bi-directional high-pass circuit, with its cut-off frequency set to be
15
FILTER. The design considerations regarding the above testing technique are listed in
Power Supply
After determining the circuitry needed to perform the cable testing, the last issue
of concern is how to power the system such that it will be convenient for the user.
System power requirements issues are listed in Table 7 and addressed in Chapter 4.
CHAPTER 4
Cable Characteristics
Cable parameters considered in the analysis for the cable tester include the per
unit length values of Resistance (R), Inductance (L), Capacitance (C), and Conductance
R^A L^a
Gt^A-=
illustrated in Figure 5, for a 15 kV class coaxial power cable with aluminum wire and
cross-linked Polyethylene (XLPE) dielectric insulation with sr=2.9 (see Appendix B.)
17
Using free space parameters, aluminum conductivity, and XLPE loss [11] of
F
S0 = 8.854 p- iXLPE Sf-
meter " ' meter
the per unit length cable parameters for resistance (DC and 10 MHz), inductance,
are as follows:
4
<yA7td"
530 //
meter ''IOMHz -LId- S L 30.2 m- ^
v2#/ D meter
/do
:146 n- C=I ^ =2 2 1 ^
Vu / meter meter
G J l n a ^ _ 43y —_ k„ = ■ = 0.587
f T \\
meter meters
299.8 M
sec
Zo —J — = 26 Q 1 I 76M l L I
4lc sec
18
The distributed model is used for wave transmission analysis and the lumped
parameter model is used for energy analysis. The lumped parameters for a maximum
R-DCmax 2.65 O,
Lmax = 730 pH, and
Cmax = 1.10 pp.
-z
T F (/) = 20 log
2nfRC + i(4n2f 2L C - \) ;
The frequency response of this model, plotted in Figure 6, exhibits a flat response
indicates that the cable acts like a low pass filter with a cutoff frequency around 40 MHz
(25ns). An analysis assumption is made that the cable characteristics are uniformly
distributed.
R e ( T F t f ) ) 30
1 * 106 1 * 107 1 * 10 ®
£
X Z
f-1 R I 1 J r 2C - A L
impulse (0 exp sinh
J r 2C2 - alc / <2 ^ y X2 JUc
in which the exponential term is the decay portion and the sinh term is the oscillatory
portion. The oscillatory portion matches the peak displayed in Figure 6, at 28 MHz
(t=35.7 ns). The decay expression is plotted in Figure 7 and shows that for a 50 ns TDR
test pulse width, R iomhz, the amplitude is down 80% at 10 ps, a distance of approximately
2000 ft where a 500 ns TDR test pulse, R imhz, is down 80% around 32 ps, a distance of
o io ; 30 40
------ R(IMHz) T im e , (us)
------ R( I OMHz)
Figure 7. Cable Impulse Response
20
L 146 tiH
TC 4.83 ps .
Rw MHz 30.2 mQ.
E charge _y
~ ^
2s-i
C ' ^ m ax
55 J
and the energy used to sustain a characteristic impedance breakdown for 2 ps is I Joule
Cable Simulation
includes models for: a high-voltage supply (Cpso, Rpso2, Rpso3, CpsoI, and RpsoI); a
current limit resistor (Rol); an energy storage capacitor (Col); a 2000:1 instrumentation
voltage divider (Ro2, Ro3); a low pass filter (Rio4, Cmo2); two lengths of cable (T l, T2);
shunt leakage's (Ro5, Ro6); and a representative cable connector Bushing capacitance
(Co3, Co4). The PSPICE per unit lossy cable model includes a shunt dielectric loss
on the energy storage capacitor, a run time of 160 ps, and first cable length of 1000 m
and 5000 m for the second cable value (Lval). The cable’s velocity factor is
21
2 * 6000 meters
= 0.583.
meters
(68.715 H 299.8 M
< sec
A factor of two is used in the above calculation to account for the actual wave travel
distance to and from the reflection point. The simulation result indicates that 57% of the
initial voltage is still in the cable when the maximum cable length, 6000 m, is reflected..
A PSPICE cable simulation of a faulted two-section cable circuit with all the
same parameters as the unfaulted simulation, except for the end terminated resistance of
resistance 25 Q placed at the end of the second section, is shown in Figure 10.
The simulation results depicted in Figure 11 show that for either length of the
second section, 1100 or 6000 m, the plot decays with the same rate through the
simulation time; less than 20% of the initial voltage is in the cable at 160 ps.
residential pad mounted transformers were not found. However, after careful review of
the literature, study, and discussions with professors in the power industry, it was
bushing’s capacitance (between 100 pF and 1000 pF). The simulations in Figure 8 and
Figure 10, include a chosen 500 pF shunt capacitance in each cable section to account for
bushing capacitances.
22
customer’s equipment.
The primary side of the transformers effect can be seen in its low frequency
response. An early project exercise demonstrated that for higher voltage tests (above 5
R p so 3 R p so 2
I-jWV-T-WV ----1I-------- 1
-ir; ) r— ;
I OOk
_r '
LEN-(Lval)
% PA RA M ETERS:
I M eg
I000
(25.. 2 5 0 u , 4 . 7 0 1 8 )
L v a l =5000
2.0U-!
CKN - 2 /2 4 /9 6
RpsO a R p s2 a R sl
M on2
-L C psl a R s4 O K)
LA
C p s2 a R psl — C sl
R s6
----- SSOpF
250pF 2uF '-A W -" {Rval2}
2 5 OMeg I OkV l00
RsO Cs2
I SOk I nF
X PARAMETERS:
R val2 25
U-BUjl
Ni
Os
L v a l= IO O
2 . BU J
CKN - 2 / 2 4 / 9 6
BU H------------------------------------------- 1------------------------------------------T------------------------------------------ 1------------------------------------------- 1
Bs UBus 8 Bus 12 Bus 16 Bus
□ » U(Mon2)
Time
Embedded Controller
Since the TDR detection and conversion is handled with high speed devices, the
embedded controller’s processing speed is not critical to this application. However, the
calculation of the distance to the fault, from the data created in the Time-to-Digital
The TDR supply module provides enough energy for a detectable test pulse to
and the maximum time of interest, tmax, the worst case for a full cable length, and a
t_ .= = 66.7//sec.
meters
0.5 *299.8 M
sec
Solving the expression to find the initial voltage required for a detectable one-volt final
voltage, gives
n„,M= ^ r = 31.5.
A value of 100 V is chosen for Vjnitiai to meet unaccounted losses in the cable circuit, the
The TDR boost converter, shown in Figure 13, is designed to operate the inductor
in a discontinuous current mode and a constant duty cycle of approximately 50%. The
characteristics of the inductor are listed in Table 9, and include a chosen operating
frequency, f0, of 3.7 kHz. Rg and Ci set the operating frequency and are determined by
R5 = — = 27 AQ
The duty-cycle, D, is controlled by setting the input voltage level on the DTC pin
4 of Ui between 0 and 3.3 Vdc (see Table 12) to get an on duty-cycle between -100% to
-0%. The chosen 50% duty-cycle is set by the following expression using R2=6.8 kO
and Ri=I 5 kO
{ R2 ' 6.8 k
( 5)
15 A+ 6.8 Ay
(52%fo47%)
(3.0 3.3) (3 or 3.3)
relationship from Faraday’s Law, which essentially states that the average voltage across
an inductor over a complete period is zero. The Off duty-cycle, Di, inductor current
shown in Figure 12, is determined by the following expression using Vc=12, D=0.50, and
V0Ut- IOO
VcD _ (12X0.50)
VcD ~ tyouT ~ Vc )D\ ->■A 0.0682
f o u r - P c ) " (100-12)
VcDT (12X18.4/Z?)
M = 1.08 A
A 1.5 rnH
1.08 A
(1.5 mH 88 r .
18.4
# —►
The total filter capacitance, C4 and C5, shown in Figure 13, is determined by
choosing a maximum voltage droop of I volt when the TDR transmitter pulse, of 50 ns, is
activated, giving
-t -5 0 ns
C TOTAL 99.5 n F .
99
Am, l n ( - m
inital
50lntW
Two parallel connected 100 nF / 200 V film capacitors are chosen. Since the inductor’s
current rating is 50 mA, a current-limiting resistor is required and a chosen value of 100
V
v C
- Vy DS(ON) 12 6.6
-
-R8 97 Q .
/n 50 m
Both error amplifiers in the controller are used to cut off the output drive when the output
voltage is up to 100 V. Since the error amp is referenced to Vref=5, the 100 V output
must be scaled through a voltage divider to match Vref. The value of Rg is chosen to be I ;
R 10 I" Ip f 5 )
LlOO-5J I M = 52.6 K l .
—
Iv g —
A value of 47 kO is chosen to raise the output voltage slightly. The inline diode, D%, is
chosen for its characteristics of high speed, low forward voltage drop, and a fast recovery
u>
U)
The TDR supply output response to a TDR transmit pulse is shown in Figure 14.
The top trace is the TDR Supply output voltage and the bottom trace is the TDRStartTest
control signal. Three things are noted: (I) There is an approximate 150 ns delay between
the initiation of the TDRStartTest and the response in the supply; (2) there is an
instantaneous 5 V drop on the -112 V supply at the leading edge of the TDR pulse; and,
............... •*!..................
7.5V
SBnn^dlv 451 na
/IB
■rfB
IvnV.....
....
.....;
tl- 1 5 0 . Bnn
tS - 1 3 5 . Sn=
Paired &t- 4 5 . 50ns Cureor 2
Dote IfA t- 21.51MHz:
The objective of the TDR transmitter module is to generate the test pulse which
meets the requirements discussed in the TDR Supply Module section. The design goal is
to efficiently switch the TDR supply output, 100 V, onto the cable circuit utilizing
35
M2 in Figure 15, is chosen for the high-side switch and some of its characteristics are
listed in Table 13
The value of 68 O for Re is chosen to be near the output coaxial cable impedance
of 50 Q, and Re,. The duty cycle for M2 is approximately 5 cycles of 50 ns On-time per
DZ2
1N 4745
M2
V P0650
270pF
RS V cc
R2 M1
150k V N 0650
LM C 555
TDR R E C E I V E R
GND
45ns/83V 48 ns/5.5V
The high-side switch driver circuit includes DZ2, R5, R4, C3, and Mi. DZ2 is a
15V zener diode used as gate protection during power-up and power-down times. Mi is a
V qs of 10 V, is chosen from the data sheet and the value of 10 kQ for R4 is determined by
A value of 22 Q is chosen for R5 so that the time constant, TC, of the input capacitance
and R5 are close to the 10 ns risetime, tr, of M2. This means R5 must be
t. 10 n s
R' = 180.
130 + 50^(0.125X68)
The On voltage transition of Mi is coupled to the M2 gate through C3. The On-time
resistance across C3 is
R C3 R5+R M lDS(O A r) = 22 + 11 = 33 0 .
38
Choosing a time constant, TC, for the coupling of C3 and its parallel equivalent
resistance to closely match the 10 ns risetime, tr, of Mi. A value of 270 pF is chosen by
C 10 ns
303 p F .
Rc3 33 Q
TDRStartTest is high. The output is high for the duration of the timing cycle and is
forced low whenever TDRStartTest goes low, if not timed out. Di forces the charging
path to begin from the supply and go through Ri and Cl. An approximate On-time is
The discharge path begins with Ci and goes through Rz and Ui pin 7. An approximate
Off-time is
t2 w O.dPSR^ C1 =1.04 ms .
The period, T, is
T = tx+t2 =1.047 ms ,
Ry and Rg form a voltage divider circuit to scale the TDR signal from the
expected 100 Vpk to 8 Vmaxpk with a total resistance much higher than the characteristic
impedance of the TDR output circuit. A value of 2.2 kO is chosen for Rg and the input
resistance of the receiver is R rxin -15 kO (Ri, Figure 16.) The chosen value of 22 kO for
Ry is found by
Fm \ fioo >
R1 = (-K8I-r JWW Vout = 1919 • 1 ‘ I 22.06 h£l.
/ I 8 )
39
Actual measurements and waveforms are shown at the bottom of Figure 15 for
various circuit responses (cable unconnected) and with the TDRStartTest signal being
generated by the embedded controller. It is noted that the risetimes are close to the
The objective of the TDR Receiver/Detector Module is to convert the TDR analog
signal into a precision digital signal. This is accomplished by impedance matching the
«1919 Q input TDR signal from the TDR Transmitter Module and driving a relatively
low input impedance, «50 O, window detector. The chosen wide-hand, 120 MHz @
chosen to be much larger than the output impedance of the TDRSig to provide
termination of the input to the op-amp in the event the module is not externally
terminated. The application notes of the AD811 state the device uses a current feedback
architecture which is dependant on the closed-loop bandwidth and gain. The desired
closed-loop gain and bandwidth are realized by adjusting the feedback resistor, Ra, for
bandwidth and adjusting resistor, Rn, value for gain. A table in the application notes of
the data sheets, titled "-3dB Bandwidth vs. Closed-Loop Gain and Resistance Values"
shows a value of 560 Q being used for both Ra and Ri when a +/-5 VDC supply is used,
giving a closed loop gain of +2 and bandwidth of 80 MHz. The final value of 360 O for
the feedback resistor, Ra, is determined after fabricating the module board and adjusting
the value to give a full representative output signal. This procedure is required because
40
of unaccounted parasitic capacitances and inductances associated with the parts layout
and resistor types used. Since the AD811 is designed to drive coaxial cables, a value of
I L M 4 0 4 0 C IM 3 - 5 .0
comparators AD9696, U2 and U3. These comparators exhibit a 4.5 ns propagation delay,
risetime of 1.85 ns, and fall time of 1.36 ns. Precautions required for successful
application and prevention of destructive oscillation include keeping the inputs of each
comparator from becoming equal for any period (e.g. slow slew rate) and ensuring the
input signal overdrives the comparator logic. The detection window is set to ±1.17 V by
the voltage divider networks OfR4-R5 and Rg-Rg (I kQ and 3.3 kQ each, respectively.)
The complementary outputs of the comparators are terminated with I kQ resistors, Re,
R7, Rio, and Rn. The labeled H output is the result of detecting the starting TDR pulse
and any reflected positive pulse when there is no fault, and the labeled L output is the
V reference for U3 and negative supply for Ui and U3. The total current load is 2.5 mA
for U3, 14.5mA for Ui, and 1.16 mA for the divider = 18.2 mA. Setting a ImA static
current through DZi gives a total current of 19.2 mA through R^. The value OfRi2 is
R12 O1 2 +5L 3 6 0 Q,
19.2 mA
Figure 17 shows measured results of the above design in which it can be see that
the input waveform. A, follows closely the output of the op-amp, B, and that the window
detector outputs, C and D, are 604 ns apart for an end shorted 190 ft (57.9 m) coaxial
43
cable. This length of time matches the calculation for the cable length with a velocity
factor of 64%:
{!Length)
t 604
k (299.8 M
r\ sec J
1 .4 /
...I..... !
v l - JdTTBrV T l- 3 . ID fT H
Type v2- 1 0 , BBrV t Zm 6 0 3 . SnH
5p I Lt fi, v - 3 1 2 , BnV A t - 6 0 3 , Snn
Dotu I ' ' A t - 1 , 657MHz
Rrnovc
Nfn 3
Cl
BaLn
Time-to-Digital Converter
12-bit counter when the TDR test pulse, H, starts, and stop the counter when the
reflection, H or L, happens. Each counter value, starting from zero, is the number of
clock cycles between the test pulse and the reflection. This functionality is represented
by the logic diagram shown in Figure 18, with input signals: HSClk, the high-speed
I
44
clock; H, the detected high signal; L, the detected low signal fault; HVRelayn, the control
used for the high-voltage test; and TDRStartTest, the control used to start a TDR test.
The TDRDetStart output is a latched state indicating that the start pulse is detected. The
latched fault reflection. The initial deactivated state is HVRelayn high and TDRStartTest
Low forcing all data flip-flops (DFFx) to a cleared state and the counter gated off.
The sequential operation of this converter for a low-voltage TDR test is:
1. The TDRStartTest line, the same control sent to the TDR Transmitter, goes
2. The first expected detected signal is the starting of the TDR test pulse coming
in as a high on the H line which is ANDed ,Al, with HSClk causing DFFi to
latch high on the rising edge of the clock. The output of DFFi enables the
counter to count with the clock, sets the level for TDRDetStart, and enables
3. Upon the falling edge of the H line, DFFz latches its output high enabling, A4
signal is locked out from detection for the first 12 counts of the counter.
5. Either the H line or L line goes high latching the EndDetected, DFF3, high
causing the counter to stop and the respective TDRDetNoFault, DFF4, and
When performing a high-voltage test, the high-voltage pulse is activated with the
HVRelayn control and is used to disable the TDRStartTest control from restarting the
converter when any fault is captured. In operation, there is an approximate 9ms relay
activation delay between the start of HVRelayn and the first detection of H. For the next
900 (as, the controller toggles the TDRStartTest control as fast as possible, ~40 (as cycle
time, to reset the counter. If a fault is detected at any time during the 900 jas detection
window, the counter is locked and any further toggles of the TDRStartTest are disabled.
Note, since the time period of Ui, TDR transmitter driver, is ~1 ms it generates only one
TDR pulse during the test window. This means that the detection is completely from the
19. TDRDetRS is used to select A0-A7, the low byte or A7-A11, the high byte, and
An issue of concern for this converter design is the accuracy of the control of the
The path of the H, start test pulse, is from Ai(Ins) to DFFi(Ins) to Al. The worst case
A3 and L includes Ag(Ins). The worst case ending time includes 1Z2 the clock period,
H S C l k I---------- >
Ftr 1 1
E n d D e te c te d
-I---------- > T D R D e t S t a r t
T D R D e tN o F a u It
CUtM 4^
H C Z >
^-----------> T D R D e t F a u I t
H V R e Ia y n I >
T D R S ta rtT e s t I >
TDRDetEN
TDRDetRS
controlled by the HVOn line, P2 pin I, shown in Figure 20 . The output voltage ranges
between 0 and 10 kV and is set by an analog voltage ranging between 0 and 10 VDC on
the HVREF line, P2 pin 5. The digital-to-analog converter (DAC) chosen to set the high-
voltage level is an ML2350 Single Supply Programmable 8-bit D/A Converter, U3, from
Micro Linear which have characteristics listed in Table 16. Jumping GAINq to GAINi
and VRin to VR0ut, Vout outputs 0 V for a 0x00 binary input and 10 V for a OxFF binary
input. This DAC is set by the micro controller under software control.
the HVMON line, P2 pin 6, with an output impedance of approximately 500 kO. An op-
amp, LM2904 with selected characteristics listed in Table 17, is chosen to buffer this
monitor line and allow further voltage scaling, 2 to I, to meet the 0 to 5 V input range of
the ADC in the micro-controller. Rt4 and Ri5, each I kQ, resistors form the final 2 to I
50
voltage divider network for the HVMON signal. This monitor line requires low-pass
filtering, C21, to remove some of the high-frequency switching component of the supply.
maximum supply voltage of 29 V to 5 V which is then buffered and sent to the micro
controller’s ADC.
H V O n O
-12
O
-V C C
OO O -
D1 O - D B I
02
HV S U P P L Y
O - D B 2
03 O - D B 3
04 O - D B -4
D S O - D B S
DS O - D B E
DT O - D B T V R ln
V R o u t
X F E R
Q A IN O
V za
O A I N I
D O N D A O N D
Figure 20. High-Voltage Supply Controls and Voltage Monitor Buffers Schematic
52
The problem of generating the test pulse was given much consideration because
of the high-voltage requirements. Early in the research process an idea surfaced to use
the 7200 VAC utility line to supply the needed test pulse. In the process of researching
solid state switches for this project, Dr. Giri Venkataramanan, Asst. Professor, E.E.,
Montana State University, was contacted several times in discussion of various potential
concepts. Recommendation was made to contact Chris Jensen, Electrical Engineer with
Fermi National Accelerator Lab, who has experience in the design of high-voltage solid
state switches. In conversations with Chris, he stated it would cost between $5000 and,
$10000 to develop a solid state switch to pulse a 7200 VAC line to generate the test
pulse.
When considering the typical fault test sequence, it became obvious that the 7200
VAC would not be available at the loop circuit transformers beyond the first transformer,
if the fault existed beyond the first transformer. The test sequence would require field
service personnel going to the next transformer, disconnecting its feed, then returning,
and testing that section before energizing it. This would result in an additional trip
between transformers to clear the section. The solution was to design the test unit with
the necessary parts to generate the test pulse without the need of external power. This
distribution location and testing both feed and load cables, resulting in a quick
Company, was contacted about this issue and he indicated that their present
sectionalizing procedure uses more than one person; one person stays at the energizing
point and another opens the loop along the circuit until the faulted section is found.
alternative methods of generating the energy pulse, discussion was initiated with John
Paul, a transformer applications engineer with Scientific Conversion, Novato, CA.. The
discussion centered on the practicality of using a pulse transformer for this application.
He indicated that the practical limit of the turns ratio of any pulse transformer is not more
than 5 to I. This means that an interstage voltage boost would be needed for this
application. He also stated that realizable pulse widths are between 200 ns and 2 ps. The
primary issue, of whether enough energy could be feasibly and economically packed into
R b r S W te s t
-AAAr LU
a
CL
D
s
Ll
W
£ X S W b r
<
4l
<7
O
Figure 21. High-voltage Storage and Control Schematic
After considering the above information, the high-voltage and control circuit
shown in Figure 21, is determined to be the most economical and feasible for a portable
HV Capacitor
c J 2 K ^ =j( 5 6 L =1
V2 IOOOO2
breakdown impedance, voltage, and 10% capacitance tolerance,. This capacitor has a
rated working voltage of 10 kV and a temperature operating range of -55 0C to +85 °C.
measuring 4.56”x3.75”x7.5” and weighing 8 lbs. The capacitor received for the
prototype is LK125-205NA rated to 12.5 kV and weighs 15 lbs (the desired value not in
Discharge Resistor
A bleeder resistance, Rbr, is required for safety and for discharging the capacitor
when the charged voltage is higher than the user has selected. The limiting factor for a
discharge cycle is the current rating of the series connected switch, SWbr- The relay
selected (Crydom 24HV1B100) has a maximum contact rating of 50 W and current rating
the expected life of the relay. Because of corona problems experienced while using the
above relay, it is decided to limit the upper HV test voltage to 7.5 kV. The bleeder
resistance calculates to be
55
I . SkV
R br = SQQk.
25 mA
resistors.
100 V '
t { (3 0 0 iX 2 /iF )X ln ) = 2.59 sec, I
V
7.5 ^
and -56 J of energy dissipated.
High-voltage Switch
The HV switch, SWt6St, must hold-off a 10 kV working voltage and pass a peak
current of 400 A in I ms. The following is a review of the pros and cons of each possible
IGBTs and MOSFETs that easily exceed the current requirements of this HV
switch are available, however, single unit devices meeting the voltage requirements are
not available. Multiple devices are required to be series-connected to meet the voltage
requirement. The design problem with series connections of these devices is that upon
transition from "off to "on", each device must be made to "see" no more than its share
of the total voltage or the reverse hold-off voltage will be exceeded. Techniques are
developed to solve this problem by adding R and RC snubbers on the power side of each
device. Another solution to this problem would be to individually control the gate drive
in a closed-loop fashion, monitoring the voltage drop across the device and adjusting the
56
drive accordingly [12] [13]. This solution is very effective, however, the control circuitry
is not trivial. Table 18 lists the pros and Cons for IGBTs and MOSFETs.
THYRISTORs and GTOs are available in single units that easily exceed the
current requirements of the HV switch, but single units which meet the voltage
requirements are not available. High power thyristor switches have been developed
which handle 250 kV and 4 kA, but they are prohibitive in size (more than 50 feet high)
[14]. These switches consist of a matrix of small devices connected in series to withstand
the voltage and many series units connected in parallel to pass the current.
For this project to meet the 10 kV hold-off voltage, a minimum of ten ($13 each)
thyristors in series, each device in the string has to match, otherwise when triggered to
turn on, the slowest device would easily exceed its maximum breakdown voltage. This
equalization, each thyristor has a parallel resistance, Rs, added. The dynamic equalizing
network is chosen to limit the voltage buildup on the fastest thyristor, allowing the
The trigger control for the string must be applied to each device simultaneously.
This poses a design problem because each device is not referenced to the same point,
Simultaneous triggering techniques have been developed [15] using either a pulse
transformer, or using light control of a photo thyristor in the gate circuit. Table 19 lists
the Pros and Cons of using Thyristors and GTOs as switches for this project.
SPARK GAPs are available with voltage and current ratings easily meeting the
switch parameters of the switch. The concept behind the spark gap is that two electrodes
are mounted in an evacuated or gas filled chamber. The hold-off voltage is high but will
break down (ionize) at a set potential, or it can be triggered into conduction by using a
high-voltage (< 10 kV) electric field external to the chamber. The characteristics of the
spark gap are such that once conduction is started it does not shut off until the current
stops, much like thyristors. Table 20 lists the Pros and Cons of using Spark Gaps for this
project.
58
HIGH-VOLTAGE RELAYS are available that meet both the voltage and current
requirements of this switch. The four basic types of relays are in-air, in-oil, in-vacuum,
or in-gas. In-air HV relays are larger in size than the vacuum or gas filled types because
atmospheric gasses have a lower breakdown voltage. The operation of a HV relay differs
Ross Engineering supplies both in-air and in-oil, single-pole, double-throw relays.
Their in-air relay is 27 inches high, 11.4 inches wide, 7.25 inches deep, and costs $4000.
Their in-oil relay is 9.03 inches high, 3.5 inches wide, 4.38 inches deep, and costs $668.
Kilovac Corporation supplies vacuum and gas HV relays. Their gas filled relay
claims to be the best choice for power switching of capacitive discharge applications by
having a bounce free characteristic and the lowest leakage current. Their HV relay which
meets the requirements of the switch measures 1.37 inches in diameter, 2.26 inches high,
weighs 3 ounces, is rated for a million mechanical cycles, and costs $463. This relay is
chosen to meet the requirements of the switch. Table 21 lists the Pros and Cons of using
ARM Filter
The purpose of the Arc Reflection Method (ARM) filter is to frequency-limit the
nominal power frequency so that the high frequency fault pulses can be easily separated
for detection.
Ls
The ARM filter, Figure 22, forms a low-pass filter, Ls and a shunt snubbing filter,
Cp, Rp, and Lp. The value of Ls is chosen to be as small as possible so that it can be
60
The maximum current in the inductor occurs when the output is shorted and the
where
a = — = 200
2L
md = ^( g/ q2 - a 2) = 7068
B1 = iL(o ) = 0, and
B2 ^ = 141.5.
The design of this inductor posed difficulties because of the high voltage, limited
space, and weight requirements. Dale Nickol of Micrometals, Inc was contacted for
assistance in meeting the requirements of this inductor. This inductor is composed of ten
hand-wound series connected toroid inductors stacked into two modules, each containing
five series-connected toroids stacked into a 2” diameter by 5” long schedule 40 PVC pipe
61
and end-capped with two cut and flattened pipe sections. The specification of each I mH
inductor is follows.
E LI |( l A)2 = 459 mJ
2
The core material, (“-2 ” of the part number) is chosen for its saturation and high
r L V/2
N= = 258 turns.
\A lj
Wire with a fusing Current rating of 82.4 A (18 AWG) is chosen, and using the MLT
It was determined, however, that 50 ft of wire “closely” packed gives the required turns.
Since this inductor is used in an ‘intermittent’ test pulse application, power loss (heat
g = ( 4 j g ) = M 258X 30.3)L
I 11.2
[(5 0 0 )(l0 , )1
B pk = 32140 G .
(AANf) [(4X1.34X258X1125)]
These values are well off the saturation charts of the material for analysis, however.
Dale’s information is that these cores have been used in similar applications and the low
The snubbing section of the ARM filter contains Cp, Rp, and Lp and is included to
dampen the natural frequency (-3.3 kHz) oscillations caused when the cable is unfaulted
or open circuit conditions exist, and to further frequency limit the high-voltage pulse but
not impede the high frequency test responses. The chosen cut-off frequency, f0, of this
second-order filter is 15 kHz. Choosing a value for Cp = 250 nF, with a 10 kV working
i
LP = 450 p H .
N J c ,
63
The design of this inductor follows the same analysis as discussed above, but uses a
smaller, T l57-2 core, with 183 turns using 41 ft of 18 AWG wire. The DC resistance of
the inductor is 262 mG and the reactance of the inductor at the cut-off frequency is
e = ^ = 169.
Rl
The natural frequency of the circuit is now changed by adding the snubbing circuit (for
I
a = 222 n F .
I I
(C j C
3.3 kHz.
{2xW & )
A circuit is considered critically damped when the damping factor is equivalent to the
natural frequency, which allows the determination of the damping resistor value to be
a= 2 ^ , ^ ^ = 2 ^ ( 2 4 ) = 4320.
TDR Coupler
The purpose of the TDR coupler is to interface the high voltage test section with
the low voltage TDR transmitter/receiver such that TDR pulses can traverse in both
directions without appreciable losses and can impede the high voltage. The TDR coupler
BN C 2 2 n F /1 2 .5 k V
LI L2
470 1 OOuH 1 OOuH
G ND
This filter is analyzed using a general impedance model shown in Figure 24 in which Zt
represents the TDR Transmitter/Receiver output impedance and Z6 represents the total
load impedance, for this analysis the ARM Filter snubber circuit.
V0 = I 2Z 9 ^ i 2 =I z l .
Solving simultaneously for T, I2, and I3 in terms of V0ZVi gives the following transfer
function
K ______________ Z 2Z 4Z 6_________________________
Vi (z, +Z2 Xz1 +z, +z6 Xz,)+[(z, + Z 5 +Z6 Xz2 M z 5 +zJzJKz,)+
(z5 +z6 )z,z2
Applying equivalent high-pass component frequency-dependant impedance
Zg=(sCp)'1+Rp+sLp, where Cp, Rp and Lp are the ARM Filter snubbing circuit shown in
10 kV, Cp=250 nF, Rp=I kO and Lp=470 pH; and running a frequency sweep simulation
between I kHz and 10 MHz on the transfer function, gives the magnitude and angular
plots shown in Figure 25 and Figure 26. The angular plot folds over at -180 degrees to
66
+180 and continues to 0 degrees (-360 degrees actually). The magnitude plot peak around
/
-jO
/
/
/■
8 /
/
-100 /
/
/
-150
1000 I-IO4 I-IO5 VlO5 VlO7
Fhqujmcyj (Hz)
\
X
90
-90
N V
-iso
1000 I-IO4 I-IO5 1 -1 ? I-IO7
Fteqoency-(Hz)
The effects of these fields are minimized by careful placement of all the HV components,
(i.e. using the shortest possible interconnections), using lead shielding for all low-voltage
circuitry and separating the HV circuitry grounding from the low-voltage grounding, (i.e.
Battery Supply
The battery supply is chosen to allow extended use, with an estimated utilization
factor of 40% (the unit being on and requiring total voltage not more than 40% of the
time). The Main Board supply measures a draw of 350 mA on the 24 VDC supply. The
HV supply draws a maximum of I A during charging and less than ImA to regulate a
high-voltage setting. Using worst case values, the total current requirement is 1.35 A
from the 24 VDC supply, resulting in a 32.4 Watt (W) power rating. Applying the
utilization factor gives 13 W. Two series connected 12 VDC 7Amp-hour (Ah) batteries
are chosen for the 24 VDC supply. These produce 6.65 Ah x 23 Vavg = 153 Watt-hour
(Wh) of energy (using battery specs). The estimated run duration for fully charged new
batteries is 153 Wh / 13 W or 11.8 hrs. As the batteries age, the expected usable time
will decrease 30-50% over a 3 year period if they are recharged after each use without
Battery Charger
the tester with or without batteries. This supply is a 40 W, single, adjustable output, with
Low-Voltage Supplies
Power to all analog, digital, and control circuitry is supplied by the Main Power
Board, see Figure 27. This board is designed to isolate the control of the HV relays using
opto-isolation and to be the only point of mixing of the high-voltage and low-voltage
grounds. The series lamp, Li, functions as a current limiting resistor, allowing the
charger supply. Each of the supply lines leaving this board are fused for over-current
protection.
VZ
BATTERY BOX
J1 -1 J 3-1
C O N T R O L PANEL
J3 -1
R 1 -3
J3 -1
J 3 - Tx
CHARGER
R 6K E 33A
OSL O n /O f f
C om
ZSJVIn = S V o u t
JZ -1
HV R E L A Y B L E E D E R R E L A Y
Os
SO
J3 -1
R 6K E33A
JE--I
R SK E33A
J 5- 3
SUPPLY
P S Z SDZ--4
---- O -24
2A
The project results are based on modeling several circuit variation tests as listed in
Table 23. Low-voltage, LV, tests are the results of the running TDR and the high-voltage
tester.
2 Short circuit cable at or very near the tester. V —
3 Unterminated cable. V V ■
4 Short circuit cable end. v ■ V
5 Unterminated cable with a high-impedance fault —
V
6 Cable terminated with the minimum resistance that V V
causes a no-fault result.
I Cable terminated with the maximum resistance that V •v
causes a fault result.
8 Cable terminated with a transformer. V V
9 Cable terminated with a transformer and the V V
minimum resistance that causes a no-fault result.
10 Cable terminated with a transformer and the V V
maximum resistance that causes a fault result.
11 Cable terminated with a transformer and high- —
V
impedance breakdown fault.
The system test set-up and monitored nodes are shown in Figure 28 with the Rx node
located at the output of the receiver’s amplifier, Figure 16, Ifr, pin 6; the H and L nodes
located at the output of the detected high (no-fault) and low (fault) TDR signals, Uz and
U 3 , pin 7 respectively; the LT node located at the test cable connector; the HT node
located at the mid-point junction of the divide by 10 voltage divider. All monitored
71
nodes are connected to an oscilloscope with I Ox, 300 MHz probes which report vertical
units 1/10 of the actual value except for the HT node which is 1/100.
TDR
Coupler
XFM R
Snuhber
Two lengths, 150 ft and 300 ft, of RG-59U cable are used for modeling the 15 kV Class
cable with characteristics listed in Table 24. The impulse response vs distance of the test
cable is shown in Figure 30 for three TDR pulse widths, 50 ns (10 MHz), 500 ns (I
MHz), and 5000 ns (100 kHz), as related to the high-frequency effect in the cable’s series
resistance, R.
The lowest terminated cable resistance test model which gives a no-fault test result is
Wirewound
246 n
The highest terminated cable resistance test model which gives a fault test result is shown
in Figure 31.
73
IRC 5 W
io n
CaAon
The cable terminated high-impedance breakdown test model is shown in Figure 32.
MEPCO
CO5DK101 v IM n
/^ Z N R M-18
-%>"85VAC 0.05%
The pad-mount utility power transformer test model is shown in Figure 33.
Y705TC (N)
115 VAC IKW Rating
Domestic Microwave Transformer
Test #1, a broken cable center conductor or axial shield at or near the tester, results are
shown in Table 25 and Figure 34. It is noted that there are no reflected TDR signals.
V e r tic a l d o r lr o n ta l Upper V e r t B l z e i LI
De b c De b c E r a t L c u Le IVd Lv
LI Ma i n L in ear V e r t O f f s e t ; LI
Faat IlB ZiB ntn __________ I V ____________
Impedance C n u p L Lp b BH L im it
AL I KIf mB
Btatue
Test #2, a shorted cable at or very near the tester, results are shown in Table 26 and
Figure 35.
—"'r‘
EBBna^dLv I , B B 4 j» b
DrfHfn
-ISE na E B B n a ^ d Lv 11 BB4j“ b
V e r t Lea.L Her L r o n t a l R equire Upper HaLn E i r e
De b c De b c Deac G r a t L c u Le E B B n a ^ d Lv
LI Ma i n ContLnuoua L in ear HaLn P oa
Faat S I BE4B o t a - ZZI B n B
Inprdance C o u p L Lng BN L ln lt PaBC Reno ve Pan<r
to N fn I Eoon
I HD DC 4BBHHr RLL N f i i a LI o ff
BtatU B Ma I n
Test #3, unterminated cable low-voltage test, results are shown in Table 27 and Figure
36.
Test #3, unterminated cable high-voltage test, results are shown in Table 28 and Figure
37.
-500rV .
100j<Hrd Iv g0E>-H
T rIgger Source Leve I TLne M ain S iz e
S e le c t Denc H old off 1 0 0 * n /y Iv
M ain LI 4 . EV I^n M ain Pon
-110*n
Mode C o u p I Lng S lop e N lndou Renove P an/1
I o ld o ff Md N fn I Zoon
M ornal DC ■h HO; none LI o ff
F r L B ; MaL n Ma L n
Test #4, a short circuit cable low-voltage test, results are shown in Table 29 and Figure
38.
Test #4, short circuit cable high-voltage test, results are shown in Table 30 and Figure 39.
SBBrI I L
Lv
HTY
m a th
tnltfti
jr
n
- Z 't
- 490>in SBBfBfd Lv 4 , Slnn
DrfHfn
SBBn'i r
I 0 0n' 1
fd Lv
Rf
I
JW
M
-SBBr|V
- 490j»n SBB^nrd Lv 4 . Slnn
Vr r t LcnL Hnr Lznnt nl RcquLrr Upper Vr r t S i z e ; LI
Drnc Drnc Drnc Sr n t Lcu Lr SBBnV^d I v
LI MnLn CnntLnunuo Ll n e n r / r r t D f f n e t ; LI
Fnnt SI 0240 ntn SBBnV
Inprdnner CnupL Lna BN L l n l t P h.be Rr nuvr Chnn
to Nfn I SrL
IMD DC 40BMHz AL I Nfnn LI LI
St a t u H MnLn
Test #5, unterminated cable high-impedance fault high-voltage test, results are shown in
/■rf Lv
Test #6, cable terminated with the minimum resistance that causes a no-fault low-voltage
IV
'd Ly
- 1 4 . 9 n V ____ m i
-196na I.
V e r tic a l M nrl r n n t a l M ainS ir e
Dcnc SBBnn^d Iv
M ain M ain Pnn
S1B34B ntn
Coup 1 1 n B BH L lirlt Page
to
Al I N frn
Btatun
Figure 41. Test #6 LV Probed Results
82
Test #6, cable terminated with the minimum resistance that causes a no-fault high
-49E1#ib Iv 4 . S lnn
DrfHhi
SB B n/'
IBBnV
Iv . .
-SBBnV-
-43B f a SBBjia^d Iv 4. S ln a
E r I bbet Source Leve L T ine Cr Ib L ev e l; N
Sc I r c t Dcoc H oLdoff Bd Lv
N ln dov R Bd I v 4 . SSSfa T L n e Ho L d o f f ; K
4 . SB Sfa
Mode C oupL lna S lop e N ln dov Renove Main
H o L d o f f Md N fn I Fr La
NornaL DC ■h HO; n o n e LI
Trln; Main M ain
Test #7, cable terminated with the maximum resistance that causes a fault low-voltage
MiMil
d a t e : 28_M t in e : 2 :5 6 : 4 8 In S tr j j - i e r i + B 010I3 6
fl * . . . . C im m ht i r i nj ] OrfHhr
5V
IV
t
I::
Iv
L T ^
I m tf tr ....V F ........:. .
:
:
:
:
tntfd
:
:
:
:
jr ................ ................
M
:
:
:
:
:
:
:
:
-SV
-ISBnn Z B B n n ^ d Lv I . BB4j»n
OrfHhn
ZV
............... ! L ...........
............... f \ .........
EBBrl R x j ,
' d LV
T
X
H I
JW
N
I
Il
.................. n . . .
- 1 4 . = InV
-ISB nn ZBBnn^dIv I , BB4^n
V e r tic a l dor L z a n t a l R equire Upper M ain S i z e
Dcnc Denc Denc B r a t L c u Le ZBBnnrdLv
LI M ain Cont ln u ou n L in ear M ain Pon
Faet i l BZ4B n tn -ZZBn■
Irp ed ance C o u p I Lng BH L lr lt PttflE Renove Panr
to H fn I Zoon
I MQ DC 4BBMHz AL L N f r n Li o ft
BttttUH Ha I n
Test #7, cable terminated with the maximum resistance that causes a fault high-voltage
SBBnV
I'd Iv
Irietf
trl^d
- 1 , 5V.
-19Bjva ZBB.*Brd Lv
DrfHfn
SBBnVr'
IBBnV
'd Iv Rx'
'T - T r-T
-SBBnV.
-IS B fa Z B BfafdLv I, 9B4nn
T r Lb h e t Source Levc L TLne Vert S L ie ; LI
Sc Irct Dcbc H oLdoff SBBnVfd Iv
M ain LI IV Ina Vert O f f a e t : LI
IV
Made C o u p I Lna S lop e NLndov Renove Chan
Ho L d n f f Md N fn I Se L
NarnaL DC ■h HO; none LI LI
Tr Ln ; M a i n HaLn
Test #8, cable terminated with a transformer low-voltage test, results are shown in Table
IV
'd Lv
I .884*=
V ert IcaL TnrLED ntaT R e q u i r e M a i n 5 LEe
Dcbc Dcac Dbbc EBBna^dLv
LI M ain C ent Lnunua M ain Pna
FlLBt *10240 DtB -EEBn a
C nuplL nB BN L lhL t Rennve
N fn I
RLL Nfna LI
Ba Ln
Test #8, cable terminated with a transformer high-voltage test, results are shown in Table
-49El>-e 5 0 0 X 8 I 'd I v 4, S ln a
DrfHfn
500nV
100nV
rd Iv
r : i I ; ; ; ;
- 5 0 0 n V ___
-490X8 5 0 0 xb ■'d Lv 4, S ln a
T rL bhet Source Leve I lin e M ain SL ze
S e Le c I Droc H oLdoff 5 0 0 x 8 r d Lv
HeLn LI ZV I no M a i n P db
- 550x8
Mode Coup L Lna SLopE N lndou Rrnovr Panr
Ho L d o f f Md N fn I Zoon
NorneL DC ■h HO; none LI o ff
F r L n ; Mn. Ln Mn. L n
Test #9, cable terminated with a transformer and the minimum resistance that causes a
no-fault low-voltage test, results are shown in Table 38 and Figure 47. The TDR
response is below detection and a 150 ft cable is required to demonstrate this test.
4 .........
I
IV
/d Lv ... a ..:......... i.......
C M Ai j - ■
In etf L I ......
tric'd
JT
M
-5V
- 1 9Bna EBBna ' A l v I . BB4><b
DrfHhi
ZV
k .........
....... ...A
Z B B h 1I
/d lif
SO j \ i . .............
W - 1
MUi
..n
H........ I
M
. I ...........
L
!
- 1 4 . InV
- 1 5 IBna EBBnn^dLv I . BB4 * < n
V rrt Leal Her L z n n t a L Rcqu Ire Upper Main B L ze
Deac Deac Deac E r a t Lcu I e Z B B n a r d Lv
LI Main Cnnt Lnunua L inear M ain Pna
Fnat S1BZ4B nta -ZZBn a
Irpedanca Coup LI n B BH L l r L t PaBE Rernve Panr
to N fr I Znnr
IMQ DC 4BBMHz A LL N f n o LI n ff
Btatuo Main
Test #9, cable terminated with a transformer and the minimum resistance that causes a
no-fault high-voltage test, results are shown in Table 39 and Figure 48.
.....L L
\
. . . . . .... L
trirfi
.id
100nV
'4 Lv .......i .
I
'I
-50 0 n V _
- 4 9 0 * ib 500*18 ^ d Lv 4 . S lna
Ir Lhbet Snurce Leve L T Lne M ain S iz e
S e Iect Drnc H n ld n ff S B B w a f 4 Lv
M ain LI IV Ina M ain Pna
-550*iB
MndE C n u p L Lna SLnpe N ln dn u Rennve Pan/
H n L d n f f Md N fn I Znnn
NnrnaL DC I" HO; none LI n ff
F r L n ; Mb . L n Mn. L n
Test #10, cable terminated with a transformer and the maximum resistance that causes a
fault low-voltage test, results are shown in Table 40 and Figure 49.
Test #10, cable terminated with a transformer and the maximum resistance that causes a
fault high-voltage test, results are shown in Table 41 and Figure 50.
t
SBBr1
' d Ly
' L i. ............> r v ........
H T ^ \ / s
Im th / ........ X y
IrigTd
JW
M
-2.5V 1
-49B*ia SBBj-H^dLy 4. S lrn
DrfHfr
S B B n 1r
I BBr', 1
' d Ly
RX
'I
...'.. I
I
JW
M
- B B B r iV
-49B>m 5 B B > H ^ d Ly 4, S ln n
IrL B flcr Source Leye L T ire Trlfl L e y e I; H
S e L ect Deac H oLdoff 3BBnV
M ain LI 3BBnV Ine Tine Ho L d o f f :
i na
Mode C o up Llnfl BLnpc NLndou Renoye NaLn
No L d o f f He N fn I T rig
NarnaL DC HO; n o n e LI
T rio: M ain Ma I n
Test #11, cable terminated with a transformer and high-impedance breakdown high-
displayed because the first positive detected pulse undershoot extends the
2. The range of TDR detection and distance measurement is limited to less than
450 ft because the reflected wave is attenuated below the level of detection.
This is caused by the energy level in the TDR test pulse width being set
deliberately to minimize the ‘dead zone’ of the pulse so shorter distances can
be detected.
a. a small phase shift in the TDR echo response, causing an increase in the
4. Cable lengths under 100 ft are reported with distances greatly inflated due to a
CHAPTER 5
Summary
Utility power company service personnel have needed a device that can be
quickly connected to any residential circuit to determine if a fault exists before re
energizing the circuit, presenting an approximate distance from the testing location to an
existing fault. In the past five years the problem of determining an underground cable
fault location has been studied from several methodologies; the most common technique
used is Time Domain Reflectometry. For a moderate investment, there are products
available which can locate cable faults within 1% to 2% accuracy, however, they do not
The 15 kV Class coaxial cable characteristics and pulsed energy responses are
The purpose of this study was to evaluate the feasibility of a small hand portable
underground cable tester which can determine fault/no fault conditions of de-energized
circuits and which can estimate the distance to a fault while residential transformers are
connected, and which meets portable size, weight, and cost constraints.
94
specified. A summary of the modules and costs is listed in Table 43. See Appendix C
Conclusions
Time Domain Reflectometry methods can identify open circuits near the tester,
and short circuits, low-resistance faults, and high-impedance faults anywhere in the TDR
detectable range. The TDR detectable range is limited to the energy level in the test
pulse because of cable and instrumentation losses. From the demonstration project, it.
was found that a 50 ns TDR test pulse limits the maximum detectable range to around
450 ft.
equipment or posing a safety issue, however, there is a small phase shift added to the test
pulse that adds time to the reflected wave, affecting distance measurements.
It is desirable to use low-voltage TDR tests for determining cable length and low
energy integrity before engaging a high voltage test for high-impedance faults.
The most feasible method for a portable tester to generate a diagnostic high
energy pulse is to charge a capacitor to the desired high-voltage and switch it onto the
cable under test. An ARM Filter is required to allow the separation of the high-frequency
The demonstration prototype met the all of the objective constraints and
requirements except the maximum distance, 3000 ft, and accuracy to with 5 ft throughout
Recommendations
the rise and fall times are not critical because of the ARM Filter, slower
100 VDC to allow for an auto-ranging algorithm to determine the cable length
° Redesign of the TDR Coupler/ARM Filter snubber to reduce the phase shift
and attenuation of the reflected TDR wave. It was demonstrated that for the
low-voltage tests, short cable lengths are reported correctly when the TDR
REFERENCES
[4] Leo P. Van Biesen, Jean Renneboog, Alain RE. Barel, "High Accuracy
Location of Faults on Electrical Lines Using Digital Signal Processing," IEEE
Transactions on Instrumentation and Measurements. VoL 39, No. I, pp 175-179,
February 1990.
[7] N. Inoue, T. Tsunekage, S. Sakai, "On-Line Fault Location System For 66kV
Underground Cables with Fast O/E and Fast A/D Technique," IEEE Transactions on
Power Delivery. VoL 9, No. I, pp 579-584, January 1994.
[8] C.M. Wiggins, D.E. Thomas, T.M. Salas, F.S. Nickel, H.W. Ng, "A Novel
Concept For URD Cable Fault Location," IEEE Transactions on Power Delivery, VoL 9,
No. I, pp 591-597, January 1994.
[9] J.P. Steiner, W.L. Weeks, H.W. Ng, "An Automated Fault Locating System,"
IEEE Transactions on Power Delivery. VoL 7, No. 2, pp 967-978, April 1992.
[14] Ake Ekstrom, Lars Eklund, "HVDC Thyristor Valve Development," IEEE
Transactions on Power Electronics. Vol. PE-2, No. 3, pp. 177-185, July 1987.
[15] D.R. Graflam - editor, SCR Manual Sixth Edition. Prentice-Hall, Chapter 6 -
Series and Parallel Operation, pp. 149-179, 1979.
99
BIBLIOGRAPHY
William J. Hepp., C. Frank Wheatly, Jr., "A New PSPICE Subcircuit for the
Power MOSFET Featuring Global Temperature Options," Harris Semiconductor. No.
AN9210, p. 10-15 to 10-26, February 1992.
September 1993.
J.P. Russell, A.M. Goodman, LA. Goodman, J.M. Neilson, "The IGBTs - A New
High Conductance MOS-Gated Device," Harris Semiconductor. No. AN8602.1, pp. 10-
64 to 10-66, May 1992.
A.M. Goodman, J.P. Russell, LA. Goodman, C.J. Nuese, J.M. Neilson,
"Improved IGBTs with Fast Switching Speed and High-current Capability," Harris
Semiconductor. No. AN8603.2, pp. 10-67 to 10-70, December 1993.
CM. Wiggins, "A Novel Concept For URD Cable Fault Location," IEEE
Transactions on Power Delivery. Vol. 9, No. I, pp. 591-597, January 1994.
101
APPENDICES
102
APPENDIX A
APPENDIX A
APPENDIX B
APPENDIX C
PARTS LISTS
107
iiiiNinnuiiiiiiiii
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