Vous êtes sur la page 1sur 2
EC/EE/EI-215 Hall Ticket Number: IV/IV B.Tech (Supply) DEGREE EXAMINATION JULY, 2015 First Semester DIGITAL ELECTRONICS (Common to ECE, EEE & EIE) Time: Three Hours Maximum : 60 Marks Answer Question No.1 compulsorily. (1X12 = 12 Marks) Answer ONE question from each unit (4X12=48 Marks) 1. Answer all questions (12X1=12 Marks) a) Determine the value of base x if (211),=(152)s? b) Find 2’s complement of the binary number 10001110002 ©) Find the commutative and associative operations of NAND? d) What is the size of the ROM for the Boolean function f(x, y, z) = I m (0, 1, 3)? ©) How many 4:1 multiplexers are required to construct 16:1 multiplexer? f) If the Boolean expressionPQ + QR + PR, what is the minimized expression? g) Write the characteristic equation of JK-flip-flop? h) What is the output frequency of a 3-bit Johnson counter if its clock frequency is 18 KHz? Assume the initial content of the register is 101. i) What is the difference between synchronous and asynchronous counters? j) Define active pull-up and passive pull-up? k) Give any advantages of DTL logic family? 1) Which is the fastest logic gate family? UNIT -1 2.8) Convert the following numbers. (6M) i) (41.6875), to binary i) (1001001 .011); to decimal iii) (100011), to gray code b) Add and multiply the following numbers without converting them to decimal. (om) i) Binary number 1011 and 101 ii) Hexadecimal number 2E and 34 (OR) 3. a) Show that the dual of the Exclusive — OR is equal to its complement. (oy +b) Draw the NAND logic diagram for each of the following expressions using multiple-level NAND gates circuits (i) (AB'+CD')E + BC(A+B) (GM) (ii) w(t y +2) + xyz. @M) UNIT -II 4. a )Simplify the following Boolean function using 4-varaiable K-map and implement the simplified function with NOR gates only. (om) {(A.B,C.D) = Ym(0,1,2,4,5,7,11,15) b) Minimize the following Boolean expression using Quine Me clusky method. (om) flwary, = Y(14,6,7,8.9,10,11,15) (OR) 5. a) Implement the following Boolean function using 8:1 multiplexer. (om) {(A,B,C.D)=ABD+ABD+BCD+ACD ) Implement the following sum of min-term equation by using a decoder and logic gates. (eM) (A,B,C) = Sm, 2, 3, 7) UNIT =I 6. a) What is Race-around problem in JK flip-flop? Explain how it is eliminated in Master Slave JK flip-flop. (6M) b) Determine the function table of the following logic circuit. (6M) (OR) 7. a) What is the difference between a serial and parallel transfer? Explain how to convert serial data to parallel and parallel to serial. What type of register is needed? (om) 'b) Design a synchronous counter for the count sequence 0+3-+1+2-+0 using positive edge trigger D flip-flop, (mM) UNIT ~IV 8 a) Design a DTL NAND gate and explain its operation. (™) b) Implement the following gates using CMOS logic family. (™) (@ INVERTER (ii) NOR (OR) 9. a) Write a short notes on (i) Noise Margin (ii) Fan-Out Propagation delay. (om) 'b) What is the significance of Totem-pole output in TTL gates? eo