Week12 Resources

EE-231 Electronics I
Engr. Dr. Hadeed Ahmed Sher
Ghulam Ishaq Khan Institute of Engineering Sciences and Technology, TOPI 23460
hadeed@giki.edu.pk
April 16, 2018
Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 12 Resources April 16, 2018 1 / 30
1 AC analysis of BJT
CE emitter bias configuration
CC Emitter follower configuration
Common base configuration
Collector feedback configuration
Collector DC feedback configuration
2 Effect of Rs and RL
3 Determining the current gain
4 Two-port system approach
AC analysis of BJT CE emitter bias configuration
To analyze the circuit it is considered that RE is not bypassed and the ro

is absent. The effect of ro will be incorporated later on.

Applying KVL on the input side of Fig.3
Vi = Ib βre + Ie RE = Ib βre + (β + 1)Ib RE (1)
Note that in an un-bypassed case the emitter is not connected to ground.
Therefore, as suggested by Fig.4, input impedance Zb is equal to
Vi
Zb = = βre + (β + 1)RE ≈ β(re + RE ) ≈ βRE (2)
Ib

The input impedance Zi as applied on Fig.3 is a parallel combination of
RB and Zb .
The output impedance Zo is calculated in a similar way as thevenin
resistance i.e shorting the input voltage Vi thus making Ib =0 and this
leads to Zo =Rc .
The voltage gain is calculated as follows
Vi
Ib = (3)
Zb
Vi
Vo = −Io Rc = −βIb Rc = −β( )Rc (4)
Zb
The gain Av is given as
Vo −βRc
Av = = (5)
Vi Zb
Using the value of Zb as given in (2) in (5)
Vo −Rc
Av = ≈ (6)
Vi re + RE
Because Zb ≈ βRE
Vo −Rc
Av = ≈ (7)
Vi RE
This shows that the voltage gain is independent of β. The negative sign
reveals that the input voltage and output voltage have a 180◦ phase shift.

Now considering that ro is part of the network then,
RC
(β + 1) + ro
Zb = βre + RE 1+(Rc +RE )
(8)
ro
RC
Using some assumptions like ro <<(|beta + 1) and ro ≥ 10(RC + RE ),
(11) can be expressed as
Zb ≈ βre + (β + 1)RE ≈ β(re + RE ) (9)


Now considering ro the value of Zo is,

β(ro + re )
Zo = RC || ro + (10)
1 + βr
RE
e
Using some assumptions like ro >>re and using typical values of β = 100,
re = 10 and RE = 1k , (10) can be expressed as
Zo ≈ Rc (11)
Gain is expressed as

−βRC re RC
Zb 1+ ro + ro
Vo −βRC
Av = = RC
≈ (12)
Vi 1+ ro
Zb
AC analysis of BJT CC Emitter follower configuration

This configuration is frequently used for impedance matching as it offers a
high impedance on input side and low impedance on output side. The
effect of ro will be incorporated later on.
The input impedance is given as
Zi = RB ||Zb (13)
where,
Zb = βre + (β + 1)RE ≈ β(re + RE ) ≈ βRE (14)
Vi
The output impedance is calculated by first finding the current Ib = Zb .
This can be converted to Ie if multiplied by (β + 1).
Therefore,(β + 1)Ib = (β + 1) ZVbi .
(β+1)Vi
Substituting the value of Zb from (14), Ie = βre +(β+1)RE . Using
assumptions for β the final value for Ie is
Vi
Ie ≈ (15)
re + RE
This circuit is based on (15) and therefore the output impedance is

Zo = RE ||re ≈ re (16)
The voltage gain of this configuration can be calculated by first finding the
Vo which by using VDR is RREE+rVi
e
.
Vo RE
Av = = (17)
Vi RE + re
Because RE >>re therefore,
Vo
Av = ≈1 (18)
Vi

If ro is included then the input impedance is calculated as
(β + 1)RE
Zb = βre + RE
(19)
1+ ro
If the condition ro >>10RE then this expression is similar to the one
discussed earlier. The output impedance Zo is calculated as
βre
Zo = ro ||RE || (20)
(β + 1)
Using assumptions for β and because ro >>re
Zo ≈ RE ||re (21)
The gain is calculated as
(β + 1) RZEb
Av = RE
(22)
1+ ro
AC analysis of BJT Common base configuration

This configuration offers a low impedance on input side and high
impedance on output side.
AC analysis of BJT Common base configuration
The input impedance is

Zi = RE ||re (23)
The output impedance is
Zo = R C (24)
The voltage gain is calculated by first finding
Vi
Vo = −Io RC = −(−Ic )RC = αIe RC with Ie = re therefore,
Vo αRC RC
Av = = ≈ (25)
Vi re re
The current gain, by assuming RE >>re is
Io −αIe
Ai = = ≈ −α ≈ −1 (26)
Ii Ie
AC analysis of BJT Collector feedback configuration
The input impedance is Zi which is calculated in the similar way as did

before,
Io = I ‘ + βIb (27) RC RC + re
I ‘(1 + ) = −βIb (32)
and RF RF
Vo − Vi
I‘ = (28) R C + re
RF I ‘ = −βIb (33)
Vo + −Io RC = −(I ‘ + βIb )RC (29) RC + RF

0 RC + re
with Ii = Ib − I = Ib 1 + β
RC + RF
Vi = Ib βre (30)
(34)
therefore, Substituting the value of this current,
(I 0 + βIb )RC − Ib βre re

I0 = (31) Zi = 1 RC
(35)
RF β + RC +RF
The output impedance is Zo is, If Ro is included then,
Zo ≈ RC ||RF (36) re
Zi ≈ 1 RC
(40)
β + RC +RF
To find voltage gain first Vo is
calculated Zo = ro ||RC ||RF ≈ RC (41)
Gain is
Vo = −Io RC = −(I 0 + βIb )RC (37)

RF RC ||ro
Av = −

RC + re
Vo = −βIb 1 − RC (38) RC ||ro + RF re
RC + RF (42)
Now If ro ≥ 10RC and RF >>RC

RF RC −RC
Av = − (39) Av ≈ (43)
RC + RF re re
AC analysis of BJT Collector DC feedback configuration

For the feedback path divided into two resistors then,
AC analysis of BJT Collector DC feedback configuration
Zi = RF1 ||βre (44)

Zo = RC ||RF2 ||ro ≈ RC ||RF2 (45)
To find voltage gain
R 0 = RC ||RF2 ||ro (46)
Vo = −βIb R 0 (47)
Vi
Ib = (48)
βre
Vi
Vo = −βR 0 (49)
βre
Vo −RC ||RF2 ||ro RF ||RC
Av = = ≈− 2 (50)
Vi re re
Effect of Rs and RL
Effect of Rs and RL
So far all the analysis is based on unloaded circuits i.e. no load connected
as an output and the input source without any resistance.
In order to distinguish between these sceneries the following are defined.
AvNL
If the effect of source resistance Rs and load resistance RL is neglected
then gain is expressed as AvNL = VVoi
AvL
If the effect of source resistance Rs is neglected and only load resistance
RL is considered then gain is expressed as AvL = VVoi
Avs
If the effect of both the source resistance Rs and load resistance RL is
considered then gain is expressed as Avs = VVoi
Effect of Rs and RL
Effect of Rs and RL
Considering these three expressions for gain
Point 1
For same configuration AvNL >AvL >Avs
Point 2
For a particular design larger the value of RL , the greater is the level of ac
gain.
Point 3
For a particular design smaller the value of RS , the greater is the level of
ac gain.
Point 4
The source and load resistance do not affect the dc biasing levels.
Effect of Rs and RL
Effect of Rs and RL
The fixed bias circuit can be rearranged with RS and RL as shown below.
RL0 = ro ||RC ||RL (51)

Vo = −βIb RL0
= −βIb (RC ||RL ) (52)
Vi
Ib = (53)
βre
Vi
Vo = −β( )(RC ||RL ) (54)
βre
Vo −RC ||RL
AvL = = (55)
Vi re
Effect of Rs and RL
Effect of Rs and RL
The input impedance is
Zi = RB ||βre (56)
The output impedance is
Zo = RC ||ro (57)
With the source resistance included
Zi Vs Vi Zi
Vi = =⇒ = (58)
Zi + R s Vs Zi + R s
Vo Vo Vi Zi
Avs = = = AvL (59)
Vi Vi Vs Zi + Rs
Zi
Avs = Av (60)
Zi + Rs L
Because the factor Zi Z+R
i
s
is always less than one , therefore the gain Avs is
always less than AvL .
Determining the current gain
Determining the current gain

For the cases discussed above the current gain is not calculated. However,
it can be calculated easily by following the ohm’s law.
−Vo
Io RL −Vo Zi
Ai = = Vi
= (61)
Ii Zi
Vi RL
Zi
AiL = −AvL (62)
RL
Two-port system approach

The two port system provides the basis of a packaged device with only
important parameters given.
This can be expressed as

The two port system provides the basis of a packaged device with only
important parameters given.
This can be expressed as

In a two port network shown in Fig.26
Vo = AvNL Vi (63)
As there is no load connected therefore, I=0 and hence the drop across
Ro =0, therefore
Zo = Ro (64)
The input impedance is given as
Zi = Ri (65)
With the load connected as RL across the output terminals, the output
voltage is calculated by applying VDR
RL AVNL Vi
Vo = (66)
RL + Ro

The voltage gain with load connected
Vo RL
AvL = = AV (67)
Vi RL + Ro NL
As the ratio of RLR+R
L
o
is always less than 1 therefore, loaded gain is always
less than no load gain.
The current gain AiL is given as
Zi
AiL = −AVL (68)
RL
Therefore, current gain can be calculated using the voltage gain. With the
source resistance included
Ri Vs
Vi = (69)
Ri + Rs
This means that greater the value of Rs lower is the voltage at the input
terminals and therefore, lower is the overall gain of the system.
The output voltage for only source resistance included is
Vo = AvNL Vi (70)
Ri Vs
Vi = (71)
Ri + Rs
Ri
Vo = AvNL Vs (72)
Ri + Rs
Vo Ri
Avs = = Av (73)
Vs Ri + Rs NL
If Rs and RL are considered simultaneously, then
Vi Ri
= (74)
Vs Ri + Rs

The output voltage is
RL
Vo = AvNL Vi (75)
RL + Ro
Vo RL AVNL
AvL = = (76)
Vi RL + Ro
For the voltage gain AVs ,
Vo Vo Vi
= Avs = (77)
Vi Vi Vs
Vo Ri RL
Avs = = Av (78)
Vs Ri + Rs RL + Ro NL
For the current gain,
Ri
AiL = −AvL (79)
RL
Rs + Ri
Ais = −Avs (80)
RL

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EE-231 Electronics I

Engr. Dr. Hadeed Ahmed Sher

April 16, 2018

3 Determining the current gain

4 Two-port system approach

CE emitter bias configuration

To analyze the circuit it is considered that RE is not bypassed and the ro

CE emitter bias configuration

CE emitter bias configuration

CE emitter bias configuration

Using the value of Zb as given in (2) in (5)

CE emitter bias configuration

Zb ≈ βre + (β + 1)RE ≈ β(re + RE ) (9)

CE emitter bias configuration

CC Emitter follower configuration

CC Emitter follower configuration

The input impedance is given as

CC Emitter follower configuration

This circuit is based on (15) and therefore the output impedance is

CC Emitter follower configuration

Common base configuration

Common base configuration

The input impedance is

Collector feedback configuration

Collector feedback configuration

The input impedance is Zi which is calculated in the similar way as did

(I 0 + βIb )RC − Ib βre re

Collector feedback configuration

The output impedance is Zo is, If Ro is included then,

Collector DC feedback configuration

Collector DC feedback configuration

Zi = RF1 ||βre (44)

RL0 = ro ||RC ||RL (51)

Determining the current gain

Two-port system approach

This can be expressed as

Two-port system approach

This can be expressed as

Two-port system approach

Two-port system approach

Two-port system approach

The output voltage for only source resistance included is

Two-port system approach

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