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Series-Connected HV-IGBTs Using Active

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DOI: 10.1109/TPEL.2014.2360189

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 8, AUGUST 2015
Series-Connected HV-IGBTs Using Active Voltage
Balancing Control With Status Feedback Circuit
Shiqi Ji, Student Member, IEEE, Ting Lu, Member, IEEE, Zhengming Zhao, Senior Member, IEEE,
Hualong Yu, Student Member, IEEE, and Liqiang Yuan, Member, IEEE
Abstract—Transient voltage unbalance is the major problem
that limits the application of series-connected IGBTs in high-
voltage and high-power converters. Asynchronous gate delay
causes series-connected IGBTs not to turn-on and turn-off at the
same time resulting in severely unbalanced voltage sharing. An ac-
tive voltage balancing control technique is proposed in this paper
to solve the asynchronous gate delay problem. By sampling the
feedback signal caused by unbalanced voltage sharing, the micro-
controller generates a time delay for the gate driver to compensate
the asynchronous gate delay. The most vital part of active voltage
balancing control, the status feedback circuit, is also discussed in
detail in this paper. The function of the status feedback circuit and
the effect of active voltage balancing control are verified in a two
series-connected HV-IGBTs platform in rated operation (5 kV bus
voltage and 600 A load current).
Index Terms—Active voltage balancing control, series-connected
IGBTs, status feedback.
I. INTRODUCTION
EDIUM/high-voltage and high-power converters have
M been widely applied in recent years, such as for high-
voltage motor drives, the static synchronous compensator
(STATCOM), and so on [1]–[3]. The high-voltage insulated
gated bipolar transistor (HVIGBT) is commonly used in these
power electronic converters. However, the maximum voltage
blocking capability of IGBTs is 6.5 kV in commercial produc-
tion. Considering that peak voltage during turn-off transient is
higher than its off-state voltage, failure in time (FIT) increases
with its off-state voltage, short-circuit protection is only tested
at a lower bus voltage, etc., an IGBT generally operate at a bus
voltage Vbus , which is much lower than its rated voltage VCES
(commonly Vbus is only one half of VCES ). The relationship
between VCES and Vbus , which is recommended by Infineon is
shown in Table I. The common two-level and three-level topol-
ogy can hardly be applied at a bus voltage higher than 6 kV. This
is not sufficient for some applications such as distribution net-
works [4]. Modular multilevel converter (MMC) is a good way
to achieve high-voltage converters [5]. Using series-connected
Manuscript received May 19, 2014; revised August 4, 2014; accepted Septem-
ber 16, 2014. Date of publication September 25, 2014; date of current version
March 5, 2015. This work was supported in part by the National Natural Science
Foundation of China (51407099) and in part by the Grants from the Power Elec-
tronics Science and Education Development Program of Delta Environmental
and Educational Foundation (DREG2013002). Recommended for publication
by Associate Editor A. Lindemann.
The authors are with the State Key Laboratory of Power System, De-
partment of Electrical Engineering, Tsinghua University, Beijing 100084,
China (e-mail: sxjisq@gmail.com; lut@mails.tsinghua.edu.cn; zhaozm@
mail.tsinghua.edu.cn; yhlong1@163.com; ylq@tsinghua.edu.cn).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2014.2360189
0885-8993 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
4165
TABLE I
INFINEON RECOMMENDED BUS VOLTAGE FOR VARIABLE-RATED
VOLTAGE IGBTS
Vb u s V C E S /two-level V C E S /three levels
600 V 1.2 kV –
750 V 1.7 kV –
1.5 V 3.3 kV 1.7 kV
3 kV 6.5 kV 3.3 kV
5.9 kV – 6.5 kV
IGBTs is also a good choice so that the switching unit would be
able to operate at a voltage level higher than the rated voltage
of single IGBT.
Compared to MMC, total harmonic distortion of series-
connected IGBTs converter is worse and a large number of
passive power filters are needed to meet the requirement of the
IEEE standard. But device number of the converter using series-
connected IGBTs is just one half of that of MMC and control
strategy of series-connected IGBTs converter is much easier.
Transient unbalanced voltage sharing is a major constraint for
the application of series-connected IGBTs. The voltage sharing
in the transient is decided by many factors such as the stray
capacitance of main circuit, gate driver parasitic capacitance
[6], IGBT parasitic parameters (mainly collector-to-gate capac-
itance Cgc ) [7], and the control signal of gate driver [8]. Among
them, the asynchronous gate delay has the largest effect while
the consistency of the other parameters can be ensured by the
manufacturer. The asynchronous gate delay is determined by
the microcontroller and the transmission from microcontroller
to the gate driver, which is difficult to know in advance. The
asynchronous gate delay is commonly from tens of nanosec-
onds to hundreds of nanoseconds. It is desired that the converter
should operate normally even though there is a 500 ns asyn-
chronous gate delay.
Even though the voltage unbalance can be reduced by the
improvement of main circuit design at some level [9], active
voltage control is more attractive because the disturbance of the
converter cannot be easily observed and active control can im-
prove the system stiffness. Some other active control strategies
have been published in [7], [10], and [11]. An active voltage
control technique using dVce /dt in series-connected IGBTs is
proposed in [7]. In [10], a method to achieve active thermal
control by estimating the junction temperature is presented. The
active current balancing for parallel-connected SiC MOSFETS by
utilizing a differential current transformer to measure the current
is given in [11]. The system performance is greatly improved
by these methods.
4166
Fig. 1. Two series-connected HV-IGBTs platform.
A novel active voltage balancing control for series-connected
HV-IGBTs is proposed in this paper to solve the asynchronous
gate delay. The discussion is for a switching unit using two
series-connected IGBTs (FZ600R65KF1). As shown in Table I,
this unit can be applied at 5 kV bus voltage in two-level topology
and 10 kV bus voltage in three-level topology. A bus voltage
of 10 kV is a good choice for distribution power system [12],
[13]. In order to validate the voltage balancing control strategy,
a two-level half bridge with 5 kV bus voltage is established as
shown in Fig. 1. The snubber circuits consist of static voltage
balance circuit (Rs = 25 kΩ) and transient RC snubber circuit
(Rd = 20 Ω, Cd = 68 nF). The driver circuits of the series-
connected HV-IGBTs utilize 1SD210F2 produced by Concept,
which share the same parameters (Rg (on) = 4.5 Ω, Rg (off ) =
22 Ω, Vg (on) = 15 V, Vg (off ) = −15 V, Cge = 152 nF, including
the parasitic capacitance of IGBT). The microcontroller utilizes
an FPGA, which has an 80 MHz clock to achieve a high-speed
control. The active voltage balancing control technique pro-
posed in this paper should make sure the whole system able
to operate normally and achieve balanced voltage sharing even
though there is an asynchronous gate delay up to 500 ns in rated
operation. The active voltage balancing control is shown in Sec-
tion II and the status feedback circuit is given in Section III.
The validations for active voltage balancing control are given in
Section IV.
It is assumed that there is an asynchronous gate delay of Δtd
(the gate delay of T2 is Δtd more than the delay of T1). The
turn-on and turn-off experimental waveforms during a transient
are shown in Fig. 2 with Δtd = 400 ns. The test and analysis of
control method in this paper mainly focuses on turn-off transient
considering that:
1) the effect of asynchronous gate delay is more serious in
the turn-off transient with a higher maximum Vce and
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 8, AUGUST 2015
Fig. 2. Experiment waveforms with 400 ns asynchronous delay: (a) turn-on
transient and (b) turn-off transient.
Fig. 3. Active voltage balancing control circuit.
larger power loss difference between series-connected
IGBTs (17.2% in turn-on transient but 50% in turn-off
transient shown in Fig. 2);
2) the voltage sharing in the turn-off transient also influences
the turn-on transient and static voltage sharing by the
effect of the tail current, which is given in [7] and [14];
3) the asynchronous gate delays during turn-on and in turn-
off transient in the communication path are nearly the
same.
II. ACTIVE VOLTAGE BALANCING CONTROL
The active voltage balancing control mainly focuses on the
voltage unbalance caused by asynchronous gate delay. The pro-
tection circuit and status feedback circuit are integrated together
to achieve the control shown in Fig. 3.
A. Protection Circuit
There is no doubt that serious unbalanced voltage sharing re-
sults in the breakdown of IGBT in series connection. Therefore,
a protection circuit should be included in the whole system in
order to clamp the maximum Vce into a safe region when voltage
unbalance happens. The two-stage active gate clamping circuit
using transient voltage suppressors (TVS), which has been pro-
posed in [15], [16] and utilized by Alston and ABB is applied
here shown in Fig. 3. Its principle is also given in these papers.
By using the active gate clamping circuit, the maximum Vce is
JI et al.: SERIES-CONNECTED HV-IGBTS USING ACTIVE VOLTAGE BALANCING CONTROL WITH STATUS FEEDBACK CIRCUIT
Fig. 4. Active voltage balancing control schematic: (a) control schematic and
(b) microcontroller and gate driver delay.
clamped to Vclam p effectively
Vclam p = Vclam p + Vclam p2
In this technique, the protection circuit and the status feed-
back circuit are integrated together. When Vce reaches Vclam p1 ,
there is a current that flows through TVS and sample resistor
(Rsam ple ). The voltage unbalance can be presented by the cur-
rent in the clamping circuit. Therefore, Vclam p is decided by the
safe operation area (SOA) of the IGBT while Vclam p1 is the peak
voltage when IGBT operates at rated bus voltage and maximum
load current (Vbus = 5 kV, IL = 600 A) with perfect voltage
balance, which can be approximately represented as
 
1 IL
Vclam p1 = Vbus + 2Ls (2)
2 tf
where Ls is the stray inductance in main circuit and tf is the
fall time of current in the turn-off transient. If the asynchronous
delay happens, one of IGBTs is clamped and the voltage un-
balance will be detected by the current in the clamping circuit.
Through this method, the voltage unbalance in turn-off transient
can be well measured.
B. Status Feedback Circuit
The action time of clamping instead of the maximum Vce is
used as the feedback signal to describe the unbalanced voltage
sharing considering the maximum Vce is clamped at a certain
value when the voltage unbalance happens. A longer action
time of clamping means a more serious voltage unbalance. The
status feedback circuit converts the current in the active gate
clamp circuit into a 0–5 V pulse, which can be recognized by
microcontroller. The pulse width AC1 and AC2 represents the
action time of clamping of T1 and T2, respectively. The control
schematic is shown in Fig. 4.
An initial compensation Δtc0 can be set to decrease the effect
of differences between stray capacitance in main circuit (ΔCce )
[6] and parasitic capacitance of IGBT (mainly ΔCgc ) [7]. Com-
4167
Fig. 5. Experimental result with a 570 V bus voltage and different load cur-
rents: (a) Δtc 0 = 0 ns and (b) Δtc 0 = −25 ns.
monly, these differences are very small if the system is well
designed. The value of Δtc0 is related to the bus voltage and
approximately independent from load current. Fig. 5 shows the
experimental results for a 570 V bus voltage and various load
currents with Δtc0 = −25 ns.
If there is asynchronous gate delay, one of the series-
connected IGBTs is clamped and the microcontroller can receive
the feedback status AC1 and AC2 , which represents the clamp-
ing time of T1 and T2, respectively. In two series-connected IG-
(1) BTs, only one of them has a nonzero value in normal operation.
In the microcontroller, a compensation time Δtc is generated,
which means the control signal of T1 is delayed Δtc in the mi-
crocontroller before it is sent to gate driver. The voltage of T1
and T2 can be balanced only if Δtc = Δtd .
If the gate drive of T2 has a Δtd delay from T1, then T1
will withstand high voltage and will have a feedback signal of
AC1 . As shown in Fig. 6, at t0 , the gate voltage Vge begins to
fall. After a period of gate discharging, Vce1 begins to increase
typically at t1 . The time between t0 and t1 is mainly decided
by the gate driver resistance, gate-to-emitter capacitance and
gate-to-collector oxide capacitance, which do not have critical
differences between T1 and T2. Therefore, Vce2 begins to rise
typically at t1 + Δtd . When Vce1 gets to Vclam p1 at t2 , the mi-
crocontroller can receive the feedback signal of T1. The change
of Vce1 is very small and can be ignored after it reaches Vclam p1 .
At t3 , Vce2 is Vbus – Vclam p1 and the current though the IGBT
Ic begins to fall rapidly. After a fall time of tf , Ic falls to the tail
current. At one point between t3 and t3 + tf , Vce1 is going to be
smaller than Vclam p1 and the feedback signal of T1 disappears.
This point is difficult to calculate accurately but is much closer to
t3 , especially with large asynchronous gate delay. Accordingly,
AC1 can be approximately represented as
AC1 = t3 − t2 . (3)
The gate voltage of T1 and T2 keeps constant in this pe-
riod. Using the model in [17] to describe the voltage-dependent
capacitance of the IGBT, the time can be solved
  
Δtd = AC1 + k Vclam p1 − Vbus − Vclam p1 (4)
where k is a constant that is related to gate discharging cur-
rent at miller stage and gate-to-collector capacitance. Therefore,
there is an approximately linearly relationship between Δtd and
ΔAC(AC1 − AC2 ). The experiment results with 570 V bus
voltage and 100 A load current are shown in Fig. 7. ΔAC shows
4168
Fig. 6. Turn-off waveforms with asynchronous gate delay.
Fig. 7. Experiment result of relationship between Δtd and ΔAC.
linear changes with Δtd and the ratio approximately equals to
1. Therefore, a multiplier Kp is a constant used to estimate the
increment of the compensation time using the active clamping
time.
It should be emphasized that the voltage unbalance is also
caused by the tail current difference in period II shown in Fig. 8.
Vout shows the action time of clamping. In period II, the action
time is much longer. However, it is not included in the effective
feedback signal because the time in this period is much longer
than Δtd , and it is hard to estimate Δtd from the active clamping
time in period II. The method to eliminate this effect will be
discussed in Section III.
The proposed active clamping circuit with status feedback and
the voltage balancing control strategy is probable to be extended
for the series connection circuit with three or more HV-IGBTs.
In this case, the proposed method is applied to every two adja-
cent HV-IGBTs. The number of the series-connected HV-IGBTs
is assumed to be N. The switching off time of T1 remains un-
changed. After every switching process, the regulation time of
the delay between the drive signals of T1 and T2 is calculated
according to the active clamping conduction durations tAC 1 and
tAC 2 , and then implemented by adjusting the switching time of
T2 in the next switching process for the voltage balancing of
T1 and T2. The regulation time of the delay between the drive
signals of T2 and T3 is calculated according to tAC 2 and tAC 3 ,
and then implemented by adjusting the switching time of T3
in the next switching process for the voltage balancing of T2
and T3 while considering the switching time adjustment of T2
for the voltage balancing of T1 and T2. By analogy, the reg-
ulation time of the delay between the drive signals of Tk and
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 8, AUGUST 2015
T (k + 1)(2 ≤ k ≤ N − 1) is calculated according to the active
clamping conduction durations tAC k and tAC ( k + 1 ) , and then im-
plemented by adjusting the switching time of T(k + 1) in the
next switching process for the voltage balancing of Tk and T(k
+ 1), while considering the switching time adjustment of Tk for
the voltage balancing of T(k − 1) and Tk. Adopting this voltage
balancing control strategy for multiple series-connected HV-
IGBTs, the collector–emitter voltages of all of the HV-IGBTs
in the series connection circuit (T1 to TN) are expected to be
balanced within several switching periods. Based on the feature
of the principle, this strategy is named as chained voltage bal-
ancing control, which will be implemented and verified in the
future.
III. STATUS FEEDBACK CIRCUIT DESIGN
In order to achieve the active voltage balance, it is vital to
measure the action time of clamping accurately. Considering
the operation condition of the active clamping circuit, several
characteristic requirements of the status feedback circuit should
be satisfied through the design.
A. High Speed and Accuracy
The timescale of active clamping feedback signal is very
short, commonly from tens of nanoseconds to hundreds of
nanoseconds. Therefore, the devices in the status feedback cir-
cuit should have fast response and high transfer speed. In order
to transform and transfer the feedback signal timely, a high-
speed comparator (ADCMP600), 10MBd fiber optic transmit-
ter (HFBR-1528) and receiver (HFBR-2528) are adopted. The
fiber optic transmitter is driven directly by the comparator so
as to avoid the signal transmission delay caused by additional
optical drive circuit. The devices adopted are all for TTL level.
Some other levels such as PSEL have better performance in high
speed, but they are more complex and their reliabilities cannot
be guaranteed in this application. The noninductance resistor is
applied as the sample resistor Rsam ple . Considering the largest
current in clamping circuit is smaller than 10 A within 500 ns
asynchronous gate delay and Vref equals to 5 V, the sample
resistance is 0.5 Ω.
The feedback signal has a significant effect on the voltage bal-
ancing performance and safe operation of the series-connected
HV-IGBTs. However, the signal distortions are introduced both
in sampling and signal transfer processes. Therefore, the pre-
cision of the status feedback circuit should be estimated and
calibrated according to the test results. The status feedback sub-
circuit can be tested by applying a square wave voltage, which
is generated by a programmable signal generator, on the sam-
pling resistor Rsam ple , and measuring the output signal of the
fiber optic receiver (input signal of the microcontroller). The
input signal of the status feedback subcircuit is generated by
a signal generator. The output results under input signals with
different pulse width are shown in Table II. The test wave-
forms with 16 MHz input signal is shown in Fig. 9. It can be
concluded from the test results that the bandwidth of the sta-
tus feedback subcircuit is at least 16 MHz (maximum output
frequency of the signal generator). In other words, the short-
est active clamping conduction time, which can be identified
JI et al.: SERIES-CONNECTED HV-IGBTS USING ACTIVE VOLTAGE BALANCING CONTROL WITH STATUS FEEDBACK CIRCUIT 4169

TABLE II
TEST DATA OF STATUS FEEDBACK SUBCIRCUIT

f Rise Delay Fall Delay Tin To u t

1 MHz 80 ns 95 ns 491 ns 506 ns

5 MHz 80 ns 93 ns 93 ns 106 ns
10 MHz 81 ns 92.4 ns 43.6 ns 55 ns
16 MHz 82 ns 90 ns 26 ns 34 ns

Fig. 9. Input and output signal with 16 MHz frequency and 31.25 ns pulse
width.

Fig. 10. Equivalent circuit of TVS.

Fig. 8. Voltage unbalance with asynchronous gate delay: (a) Section I. (b)
Section II.

by the status feedback subcircuit and the microcontroller is no

longer than 1 s/16 MHz/2 = 31.25 ns. Considering the clock of
microcontroller is 80 MHz, the speed and accuracy are satisfied.

B. Anti-EMI
The electromagnetic interference (EMI), especially dVce /dt
has very significant effect on the performance of feedback cir-
cuit. The TVS can be seen as an ideal TVS and a voltage-
dependent capacitor CTVS , which is similar with the capacitance
in IGBT in parallel connection as shown in Fig. 10. The current
through CTVS is considerable with large dVce /dt. Therefore,
there is current through active clamping circuit even though
the IGBT transient voltage is well shared and the TVS voltage
does not reach its breakdown voltage. The experimental result
of the active clamping circuit Iac is shown in Fig. 10 with 1 and
2 μs asynchronous gate delay in 570 V bus voltage and 100 A
load current. The interference signal results in worse control.
The EMI is analyzed later. The interference signal of EMI is
caused by displacement current of CTVS . At this time, Iac can
be represented as
dVce
Iac = CTVS . (5)
dt
Fig. 11. Experimental results of Ia c with different asynchronous gate delay.
Accordingly, CTVS is significant on the EMI. Commonly, the
TVS in higher power level have larger parasitic capacitance,
which is not good for the EMC. However, the low-power-level
TVS does not satisfies the requirement of the active clamping
circuit current (maximum current should be at least 10 A in 5 kV
bus voltage). Therefore, the TVS utilizes 5 KP, which means the
peak power loss in the transient can reach 5 kW.
The large dVce /dt happens in period [t1 , t2 ] as shown in
Fig. 6. The IGBT current IT keeps constant and equals the load
current IL . Vge stays at the miller stage Vm iller . The equivalent
circuit of IGBT is shown in Fig. 12.
The current through CTVS and Cgc keep the gate-to-emitter
voltage at a constant value Vm iller , which is also called miller
4170
Fig. 12. Equivalent circuit of IGBT in period [t1 , t2 ].
Fig. 13. Equivalent circuit of IGBT in period [t2 , t3 ].
stage. Therefore, the total current through the active clamp
circuit and miller capacitor equals to the discharging current
through gate resistance Rg (off ) and Iac can be represented as
CTVS CTVS Vm iller − Vge(off )
Iac = Ig =
CTVS + Cgc CTVS + Cgc Rg (off )
Iac causes a voltage drop on Rsam ple and the control system
detects an interference feedback signal.
The useful feedback signal is measured when Vce reaches
Vclam p1 in period [t2 , t3 ] as shown in Fig. 11. In this period, Vce
is clamped and nearly unchanged. Vge still stays at the miller
stage Vm iller . The equivalent circuit of IGBT is shown in Fig. 13.
The active clamp circuit supplies all the gate discharging
current, which is equal to
Vm iller − Vge(off )
Iac = Ig = . (7)
Rg (off )
A typical active clamp circuit current waveform is shown in
Fig. 14. As discussed later, the current in the first period is EMI,
which is caused by displacement current through CTVS and the
current in the second period is useful feedback signal, which
presents the action time of active clamping circuit. A method of
classifying the useful feedback signal from EMI is to compare
Iac with a threshold current ITH . When Iac is higher than ITH ,
there is feedback signal. Therefore, ITH should satisfy
CTVS
Ig < ITH < Ig
CTVS + Cgc
Vm iller increases with the increasing of the load current. The
highest Vm iller (in rated current 600 A) is about 9.2 V. CTVS
and Cgc can be obtained in the datasheet and the largest ratio of
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 8, AUGUST 2015
Fig. 14. Typical active clamp circuit current waveform.
Fig. 15. Experiment waveform for EMI test. (a) Without anti-EMI and
(b) with anti-EMI.
.
(6) these capacitances is about 0.126. Therefore, the maximum Iac
caused by EMI is approximately equal to 0.14 A.
Considering Vm iller changes with the load current, the small-
est clamping current is 0.95 A. Therefore, the threshold ITH
should be set between 0.14 and 0.95 A in order to withstand
the EMI but accept the real clamping signal. Here, ITH is set to
0.2 A.
As shown in Fig. 3, the voltage drop on Rsam ple equals
Iac Rsam ple , which is also anode voltage of comparator. Cathode
voltage of comparator is dividing of Vref by Rref and R− and
equals Vref R− /(Rref + R− ). When the anode voltage is higher
than cathode voltage, output of comparator is a high level and
there is a feedback signal. Therefore, ITH is determined by Vref ,
Rref , and R− , which can be represented as
Vref R−
ITH = . (9)
(Rref + R− )Rsam ple
Accordingly, Rref and R− are 50 and 1 kΩ, respectively. The
experimental waveforms with anti-EMI are shown in Fig. 15
and a contrast without anti-EMI is also given. Vout is the feed-
back status received by microcontroller. It is shown there is a
significant interference for feedback circuit without anti-EMI.
(8)
C. Tail Current Effect Elimination
The tail current difference between series-connected IGBTs
may cause large voltage unbalance and long clamp time in pe-
JI et al.: SERIES-CONNECTED HV-IGBTS USING ACTIVE VOLTAGE BALANCING CONTROL WITH STATUS FEEDBACK CIRCUIT
Fig. 16. IGBT cell structure.
riod II shown in Fig. 7, which will disturb the active voltage
balancing control. Therefore, the tail current effect on clamping
time should be eliminated. The voltage unbalance caused by tail
current difference is also shown in [13] and [18]. But there is no
detail analysis.
A cell structure of IGBT is shown in Fig. 16. When IGBT
operates in on-state, there are a large number of holes injecting
into n– base. During turn-off transient, the holes are pumped
out of the n– base. The pumping current of the holes is the tail
current. Therefore, the tail current is caused by the hole behavior
in the n– base.
For a unit using two series-connected IGBTs, the hole quan-
tity in the base of two IGBTs is the same in on-state. If T1
turns off earlier than T2, the holes of T1 will be pumped out
earlier than that of T2. Therefore, in tail current period, the hole
quantity of T1 is smaller than that of T2. The tail current can be
seen as exponent function approximately
   
−t −t
Itail1 = IT1 exp , Itail2 = IT2 exp (10)
τ τ
IT 1 and IT 2 are the tail current at the beginning of tail current
period. As the hole quantity of T1 is smaller than T2, IT 1 < IT 2 .
Therefore, the tail current of T1 Itail 1 in the whole tail current
period is smaller than that of T2 Itail 2 . A detailed model to
describe the tail current difference is given in [19].
IGBT in tail current period can be seen as a current source
Itail . The equivalent circuit of the converter without RC snubber
is shown in Fig. 17. In this period, freewheel diode is in on-
state and its voltage equals 0. Voltage drop on stray inductance
Ls can be ignored. Therefore, the sum of Vce1 and Vce2 is the
bus voltage Vbus . Considering Rs is a large value, the maxi-
mum voltage unbalance caused by tail current difference can be
approximately solved
τ (IT2 − IT2 )
ΔVce m ax = . (11)
Cce
As Cce is a very small value at high voltage, a small tail cur-
rent difference will cause large ΔVce . One way to eliminate the
tail current difference is to increase the collector-to-emitter ca-
pacitance. In this paper, the RC snubber (Rd and Cd as shown in
4171
Fig. 17. Equivalent circuit of the converter without RC snubber during tail
current.
Fig. 18. Elimination of effect of tail current difference using RC snubber
circuit: (a) without RC snubber and (b) with RC snubber.
Fig. 1) is applied to reduce the tail current difference in period II.
The value of snubber capacitance Cd need not to be a large value
(68 nF is enough here). The RC snubber has small effect on pe-
riod I but can effectively eliminate the tail current influence as
shown in Fig. 18.
In Section II, even though the active gate clamp circuit acts,
the Vce cannot be clamped effectively because the gate voltage is
equal to Vge(off ) at that time and the IGBT needs a long response
time (several microseconds for HV-IGBT driver) to turn on. Vce
continues to rise in this period and IGBT may be broken down.
Therefore, an RC snubber circuit is also very useful to keep the
IGBT operating in its SOA. Because the voltage unbalance in
high bus voltage (5 kV) without RC snubber may cause break-
down, the test and comparison are only completed in a low bus
voltage (200 V).
IV. EXPERIMENT VERIFICATION
The proposed active voltage balancing control circuit is im-
plemented and applied in series-connected HV-IGBTs as shown
in Fig. 19. The two-level half-bridge platform using two series-
connected HV-IGBTs is shown in Fig. 20. Its equivalent circuit
is shown in Fig. 1. The parameters of gate driver and main
circuit have been given in Section I. The parameters of active
voltage balancing control circuit as shown in Fig. 3 are given
in Table III. The experiment results are all obtained with static
voltage balance circuit (Rs = 25 kΩ) and RC snubber circuit
(Rd = 20 Ω, Cd = 68 nF).
4172 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 8, AUGUST 2015

Fig. 19. Active voltage balancing control circuit. (a) PCB of active voltage
balancing control circuit. (b) Connection with HV-IGBT.

Fig. 21. Collector-to-emitter voltage and feedback status during turn-off.

The comparison without the active voltage balancing control is

also given.
It is apparent that the voltage can achieve balance sharing in
series-connected HV-IGBTs even with a 500 ns asynchronous
gate delay using the active voltage balancing control proposed in
this paper. The performance is significantly improved compared
the system without active voltage balancing control. It should be
Fig. 20. Two-level half-bridge platform using two series-connected noticed that the unbalance in turn-on transient is difficult to ob-
HV-IGBTs.
serve using this method because there is no peak voltage caused
TABLE III by stray inductance during the turn-on transient. As shown in
PARAMETERS OF ACTIVE VOLTAGE BALANCING CONTROL CIRCUIT
Fig. 2(a), Vce is not clamped in the turn-on transient and there is
no feedback signal even if there is a 400 ns asynchronous gate
Component Value Component Value delay. One way to solve this problem is to assume that the asyn-
R1 20 Ω R2 1 kΩ chronous gate delays in turn-on and in turn-off are the same.
C1 10 nF Vc la m p 1 3.13 kV Further improvement is needed to achieve the turn-on active
Vc la m p 2 340 V Rsa m p le 0.5 Ω
voltage balancing control.
R+ 1 kΩ R− 1 kΩ
Rref 50 kΩ Vref 5V
Rd r 300 Ω
C. Comparison of Different Voltage Balance Methods
Many voltage balance strategies have been proposed in pre-
A. Validation for Protection Circuit and Status vious years. These methods were compared from many aspects
Feedback Circuit including voltage balance effect, losses, complexity, reliabil-
ity, and so on, in [20]. But the comparison on voltage balance
The two-stage active gate clamping circuit using transient
effect is too simple. The main factors that cause the voltage un-
voltage suppressors (TVS) is applied to clamp the maximum
balance are mainly different stray capacitance of main circuit,
collector-to-emitter voltage in a safe region even when serious
which can be equivalent to IGBT’s collector-to-emitter capaci-
voltage unbalance happens. Using this method, the maximum
tance Cce (or different Cce , for short), different IGBT parasitic
Vce is smaller than Vclam p1 + Vclam p2 (3.47 kV). By sampling
collector-to-gate capacitance Cgc (or different Cgc , for short)
the current in active clamping circuit, the feedback status is
and asynchronous gate control signal. Here, these strategies are
obtained. The effect of clamping circuit and feedback circuit
divided into four categories and their effects on eliminating the
is given in Fig. 21. The feedback status Vout is measured at
voltage unbalance caused by these three factors are compared
the output of optic receiver HFBR-2528. The maximum Vce is
in Table IV.
clamped effectively.
1) Passive snubber between collector and emitter:. It can
be RC snubber or transient voltage suppressors between
B. Validation for Active Voltage Balancing Control Strategy collector and emitter. This strategy is a good way to elim-
The active voltage balancing control is applied to solve the inate voltage unbalance caused by different Cce because a
voltage unbalance caused by the asynchronous gate delay. Its large snubber capacitance can lower the impact caused by
function in rated operation (Vbus = 5 kV, IL = 600 A) is veri- different Cce . In high-voltage converter, the power loss in
fied with 500 ns asynchronous gate delay and shown in Fig. 22. the snubber is very high.
JI et al.: SERIES-CONNECTED HV-IGBTS USING ACTIVE VOLTAGE BALANCING CONTROL WITH STATUS FEEDBACK CIRCUIT
Fig. 22. Active voltage balancing control in rated operation: (a) without the
control and (b) with the control.
4173
TABLE IV
COMPARISON OF DIFFERENT VOLTAGE BALANCE STRATEGIES
Strategy Different C c e Different C g c Asynchronous Gate
Control Signal
1) Good Bad Bad
2) Medium Medium Bad
3) Medium Good Bad
4) Medium Medium Medium
Proposed method Good Medium Good
2) Active gate clamping: The most advantage of this strategy
compared to the first one is to save cost and size of whole
system. Its effect of eliminating the voltage unbalance
caused by different Cce is not as good as the first one, but
it is better on eliminating unbalance caused by the other
two factors. This method will also cause large power loss
in the IGBT.
3) Vce reference clamping: This strategy is to ensure that
Vce can track a reference value Vref in a switching tran-
sient regardless of collector-to-gate capacitance differ-
ence. Therefore, it is a good method to eliminate un-
balance caused by different Cgc . This tracking method
is achieved by controlling injection current into gate ca-
pacitance Cge . For example, if Vce is higher than Vref in
turn-off transient, there will be a positive injection current
into Cge and rising rate of Vce will decrease so that Vref is
tracked. The Vref can be set in digital IC or achieved by
analog circuit. The active gate clamping can be seen as a
typical Vce reference clamping with a step wave of Vref .
However, as the Vref is triggered by gate control signal,
the Vce reference clamping cannot be used to eliminate
unbalance caused by asynchronous gate control signal.
4) Gate signal delay control: This control strategy mainly
focuses on the unbalance caused by asynchronous gate
control signal [21]. Uses unbalance voltage caused by tail
current difference as feedback signal to compensate the
asynchronous gate control signal. However, the relation-
ship between the unbalance and the asynchronous gate
control signal difference can hardly be obtained and it is
not a good feedback signal. There are also other gate sig-
nal delay control methods [22]. But it is still very hard to
get a method with high effectiveness and low complexity.
In this paper, 1), 2), and 4) are integrated together effectively.
Different from snubbers in other strategies of 1), a very small
snubber capacitance (Cd = 68 nF) is enough. The gate active
clamping just works in several pulses in the beginning. After
some pulses of regulation, the voltage balance will be achieved
and Vce will not be larger than threshold of the gate active
clamping. Therefore, the power loss of IGBT will not increase.
The action time of the gate active clamping during a turn-off
transient is used to compensate the control signal, which can
get a better effect. But considering the slight voltage unbalance
can hardly be detected by the feedback circuit, the effect on
eliminating the unbalance caused by different Cgc is not as
good as Vce reference clamping.
4174
V. CONCLUSION
A novel active voltage balancing control used in series-
connected HV-IGBTs is proposed in this paper. Using the action
time of clamping as a feedback signal, the unbalanced voltage
sharing, which is caused by asynchronous gate delay can be sig-
nificantly reduced. The design method of status feedback is also
given in detail considering high speed and accuracy, anti-EMI,
and tail current. The function is verified in rated bus voltage and
load current and the voltage sharing performance is significantly
improved using this technique.
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Shiqi Ji (S’10) received the B.S. degree in electri-
cal engineering from Tsinghua University, Beijing,
China, in 2010, where he is currently working toward
the Ph.D. degree in electrical engineering at the State
Key Laboratory of Power System.
His current research interests include semiconduc-
tor device modeling and design of high-voltage and
high-power converter.
Ting Lu (M’09) was born in Shenyang, China, in
1982. He received the B.S. and Ph.D. degrees in elec-
trical engineering from Tsinghua University, Beijing,
China, in 2005 and 2010, respectively.
He is currently a Postdoctoral Fellow in the De-
partment of Electrical Engineering, Tsinghua Uni-
versity. His current research interests include high-
power, high-voltage power electronics conversion.
Zhengming Zhao (M’02–SM’03) received the B.Sc.
and M.Sc. degrees in electrical engineering from Hu-
nan University, Changsha, China, in 1982 and 1985,
respectively, and the Ph.D. degree from Tsinghua
University, Beijing, China, in 1991.
In 1993, he was an Associate Professor with the
Department of Electrical Engineering, Tsinghua Uni-
versity, where he was a Full Professor in 1999. From
1994 to 1996, he was a Postdoctoral Fellow with the
Ohio State University, Columbus, USA. In 1997, he
joined the University of California, Irvine, as a Visit-
ing Scholar. In 1998, he joined the University of British Columbia, Vancouver,
BC, Canada, as a Visiting Scholar for three months. In 1999, he was invited to
visit the University of Hong Kong, Pokfulam, Hong Kong, as a Research Assis-
tant Professor for another three months. He is currently the Deputy Chairman
in the Department of Electrical Engineering, Tsinghua University, and the Vice
Director of the National Key Laboratory for Power System. His current research
interests include power electronics, motor design and drive, integration of drive
systems, and solar energy applications.
Hualong Yu (S’10) received the B.S. degree in elec-
trical engineering from Tsinghua University, Beijing,
China, in 2010, where he is currently working toward
the Ph.D. degree in electrical engineering at State Key
Laboratory of Power System.
His current research interests include power con-
verters, stray parameters, and bus bar structure de-
sign.
Liqiang Yuan(M’02) was born in Dalian City, Liaon-
ing Province, China. He received the B.S. and Ph.D.
degrees from Tsinghua University, Beijing, China, in
1999 and 2004, respectively.
During 2004–2008, he was a Lecturer with the
Department of Electrical Engineering, Tsinghua Uni-
versity, where he is currently an Associate Professor
with the Power Electronics and Motor System Lab-
oratory. His current research interests include pho-
tovoltaic power systems and adjustable-speed drive
systems.