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Quick Start Guide

Voltus IC Power Integrity Solution

©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/161


©2016 Cadence Design Systems, Inc. All rights reserved.
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©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/162


Table of Contents
1. Introduction .............................................................................................................. 4
2. Data requirements .................................................................................................... 4
3. Installation and documentation ................................................................................ 5
4. Analysis Preparation – Library Generation................................................................ 6
6. Static Power Analysis ................................................................................................ 8
8. Dynamic power and rail analysis ............................................................................. 11
9. Early Rail analysis (ERA) .......................................................................................... 13
10. Additional Topics ..................................................................................................... 15
11. Additional Resources............................................................................................... 16

©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/163


1. Introduction
The Voltus IC Integrity Solution (Voltus) is an integral part of the Silicon Signoff &
Verification (SSV) Solutions offer by Cadence. Voltus delivers unprecedented
performance and industry endorsed sign-­­off power and IR drop analysis for the world’s
largest and most complex designs.

Voltus can be used throughout the entire design flow to identify possible IR drop issues
before signoff. From silicon prototyping and floorplanning, all the way down to
optimization and signoff, the seamless integration with Innovus System, Tempus Timing
Signoff Solution (Tempus), and Sigrity help improve productivity and convergence.

The Quick Start Guide will demonstrate the basics of generating power-­­grid library, and
running a power and IR drop analysis using TCL scripts. For GUI and more advance flow,
please download the official training kit.

2. Data requirements
The following are a list of input files required for Voltus

Mandatory design data


o QRC techfile and technology LEF file
o LEF and layermap
o Timing/Power Libraries (.lib)
o Verilog
o SDC or TWF
o DEF
o SPEF

Recommended design data


o SPICE sub-­­circuit netlist/model with XY coordinates for design components
o GDS and layermap for design components

Optional design data


o Common Power Format (CPF) / View Definition File
o Package model
o Power pads
o VCD/FSDB

©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/164


3. Installation and documentation
Product Installation
• See README file at any of these locations:
o https://downloads.cadence.com: review the README before
downloading the Voltus software
o In the software installation
o At the top level of your installation hierarchy

Environment Setup
• Set the installation directory in following environment variables:
o PATH: <Install_dir>/<platform>/bin
o LD_LIBRARY_PATH: <Install_dir>/<platform>/lib
• Set the license variable using CDS_LICENSE_FILE
o Example: setenv CDS_LICENSE_FILE 5280@lic_server

Starting Voltus IC Integrity Solution software


• To start a Voltus session, type the following at the shell prompt:
> voltus
[-­­log logFileName]
[-­­nowin]
[-­­init tclFileName]

Documentation
• Full documentation can be accessed from the Cadence Support website or from
the installed software. From the software, you have access to the Cadence
online documentation system, which includes documentation library viewing and
search capabilities.

• You can launch cdnshelp:


o By clicking on the Help button in the GUI form
o By typing “cdnshelp &” in the Voltus console
o Using help on TCL command from command Console

©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/165


4. Analysis Preparation – Library Generation
Library generation involves modeling the power network, decoupling capacitance, and
current draw location/behavior for each of the design components. These libraries are
used in power/rail analysis to correctly mimic the behavior of each cell. In Voltus, there
are two types of library: Technology Power -Grid library and Cell Power­Grid library.

Technology PG library is a minimum requirement for running static/dynamic rail analysis.


It contains the extraction tech file, filler/decap/powergate identifications, and a Tech
view for every cell. A tech view is a blackbox modeling used for flow verification; the
power network consist of LEF power pins, and decoupling capacitance is estimated using
area capacitance.

Cell PG library is generated to enable more accurate rail analysis. These libraries are
generated for standard cells, memories, IOs and custom macros in the design. The Cell PG
library contain three types of views for each cell viz. Early, IR and EM. Based on the
analysis type and accuracy requirement in rail analysis, Voltus will pick the best
view to model the design components.

Tip: For standard cells, the PGV model each standard cells with SPICE
simulated decoupling capacitances. For macros/IOs/memories, PGV model
the design components using SPICE simulated decoupling capacitance,
GDS extracted power network, and more accurate current distribution.
Refer to Voltus User Guide for more information.

The library generation for technology and power-­­grid library is very similar other than
additional inputs (spice netlist/model, GDS, etc.) for standard cells and macros. The
Quick Start Guide will demonstrate generating a technology library, which can be used
to run rail analysis.

voltus> read_lef –lef technology.lef <other_design_lefs>


voltus> set_pg_library_mode \
-celltype techonly \
-default_area_cap 0.01 \
-filler_cells *FILL* \
-decap_cells *CAP* \
-extraction_tech_file ./qrcTechfile \
-lef_layermap ./lefdef.layermap \
-power_pins {VDD 0.9 VDDG 0.9 VDDI 1.1} \
-ground_pins VSS
voltus> generate_pg_library -output ./
You should see a techonly.cl folder generated in local directory.

Note: It is recommended not to merge Tech and Cell PG libraries,


latest version of Voltus will error out if Tech and Cell library
merging is attempted.
©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/166
5. Design Loading
There are three ways to load design into Voltus to run analysis:

• Import Innovus database

• Import OA database

• Import third party design

Import Innovus/OA Database


Loading Innovus/OA database into Voltus is simple.
Innovus
voltus> read_design –physical_data design.enc
voltus> read_spef design.spef
OA
voltus> restore_oa_design OAlibrary design layout \
-physical_data

Note: Voltus requires verilog, LEF, SDC, DEF and timing libraries to run
analysis. If the database is missing some of the required input, it must be
loaded first using setup script or Innovus configuration file.

Import Third Party Design


Use the following commands to load each of the required input into Voltus:
voltus> read_lib -lef tech.lef allcells.lef
voltus> read_lib stdcells.lib memories.lib
voltus> read_verilog design.v
voltus> set_top_module design
voltus> read_sdc design.sdc OR read_twf design.twf
voltus> read_def design.def.gz
voltus> read_spef design.spef.gz

Tip: Voltus offers design browser and sanity checks to help verify the completeness
of input data. Refer to Voltus User Guide on following commands:
• check_design (Check LEF, physical/logical netlists, SPEF data)
• checkTimingLibrary (Check missing power tables in .lib)
• verify_connectivity (Check power grid integrity)
• verify_power_via (Check missing vias)

©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/167


6. Static Power Analysis
Voltus static power engine offers signoff quality average power calculations. Some of
the key features supported by Static Power Analysis include:
• Support Timing Window File (TWF) or on-­­the-­­fly timing analysis using Tempus to
query slews, constants, external load and clock domain information
• Support Common Power Format (CPF) to specify power domains and switch nets
• Flexible activity specification using full or partial VCD, FSDB, TCF, SAF files and
activity propagation based on user inputs
• Power-­­gate support to analyze total and leakage power savings

After the design is loaded, set up the power analysis options using the command
set_power_analysis_mode, follow by setting up the activity factors and import any
activity files. Start the power analysis using report_power command (sample below)
voltus> set_power_analysis_mode \
-method static \
-create_binary_db true \
–write_static_currents true
voltus> set_default_switching_activity \
-global_activity 0.15
voltus> set_power_output_dir static_power
voltus> report_power -outfile static_power/design.rpt

Tip: create_binary_db will create power database that can be used at later
time for GUI interactive debug, write_static_currents will
generate the current files required for rail analysis

Once the static power analysis is complete, static power summary report can be found
in the log file (Total Switching/Internal/Leakage Power), detailed report will be written
to file specified through ‐outfile. User can generate incremental reports using additional
report_power commands for clock domain, power domain/net, hierarchy level,
instance/cell/cell types.

Voltus GUI offers many more debugging features to analyze power result:
• Layout overlay power plots: total power, internal power, switching power,
leakage power, frequency domain, transition density and loading capacitance
• Static power histograms and pie-charts
• Interactive queries and violation browser to debug high power instances

Tip: Refer to Voltus User Guide and Voltus Training material on GUI usage
©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/168
7. Static Rail Analysis
Voltus static rail engine offers static IR drop and ElectroMigration (EM) analysis. The rail
analysis by default will also perform power-­­grid integrity, voltage source/resistor/tap
current, effective instance voltage, and power-­­gate/package analysis as applicable. Some
of the key features supported by Static Rail Analysis include:
• Full power-­­grid extraction for DEF, RDL and full-­­chip GDS design
• Support extracting manufacturing effects like erosion, wire edge enlargement,
temperature, dishing, slotting, cladding, etc. for signoff
• Accuracy settings to adjust performance/accuracy tradeoff
• Support package model for realistic IR drop behavior
Note: 1. Analysis type is picked as per command option used and input data provided
2. Voltus support concurrent Power and rail analysis

Once static power analysis is complete, set up the rail analysis options using the
command set_rail_analysis_mode, followed by specifying the power
domain/nets and pad locations. Start the rail analysis using analyze_rail command
(sample below)
voltus> set_rail_analysis_mode \
-method static \
-accuracy hd \
-power_grid_library {techonly.cl stdcell.cl} \
voltus> set_power_domain -name All -pwrnets VDD -gndnets VSS
voltus> set_pg_nets -net VDD -voltage 1.08
voltus> set_pg_nets -net VSS -voltage 0.0
voltus> set_power_data -format current -scale 1 \
{static_VDD.ptiavg static_VSS.ptiavg}
voltus> set_power_pads -net VDD -format xy -file VDD.ppl
voltus> set_power_pads -net VSS -format xy -file VSS.ppl
voltus> analyze_rail -type domain \
-results_directory static_rail All

Note: The technology library (see above techonly.cl) need to be the first
power_grid_library input, followed by cell power-grid libraries. Voltus
will pick Early view for xd accuracy, IR view for hd accuracy, and EM
view for hd accuracy if EM analysis is enabled. If power grid library for
a cell is not available, the tech view from the technology library will be
used.

Once the static rail analysis is complete, all the analysis summary can be found in the log
file, and the individual ascii/html report will be outputted to <PG_net> and
<PG_net>/Reports directories. A gif plot for each of the analysis is also available
under <PG_net> directory.

©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/169


The Voltus GUI offers additional debugging features to analyze rail result:
• Layout overlay rail analysis plots: IR drop, current density, current across
resistors, device tap currents, drop across package, instance based voltage,
instance based effective resistance, unconnected grid, etc.
• Interactive queries and violation browser to debug IR hotspots
• Highlight Least Effective Resistance Path for the instance

Tip: Refer to Voltus User Guide and Voltus Training material on GUI usage

©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/1610


8. Dynamic power and rail analysis
Voltus offers sign­off quality dynamic power and rail analysis. The flow for dynamic is
nearly identical as the static flow; instead of analyzing average power/rail drop, dynamic
analysis is simulated over a period of time.

Dynamic power analysis supports two flows: vectorbased and vectorless. The
vectorbased flow uses the waveform activities from VCD/FSDB, while the vectorless flow
uses activity propagation with user specified activity level, or partial/full annotation of
VCD/FSDB/TCF/SAF files.

Dynamic rail supports additional analysis not available in static:


• Decap optimization (removal/ECO): Placement/Timing/Leakage/Area aware
• Package analysis and die-model generation to take into account the on-chip
dynamic switching effects during package design.
• Power switch analysis: steady­state On/Off, Power­up or In-rush current, ECO flow
• Dynamic IR drop waveform and movies

Since the emphases of dynamic analysis is placed on IR drop, Power-up, and Decap
analysis, it is common to run dynamic power and rail analysis concurrently. Voltus
supports running dynamic analysis using a single analyze_rail command as illustrated
below.
voltus> set_power_analysis_mode \
-method dynamic_vectorless \
-power_grid_library {techonly.cl}
voltus> set_default_switching_activity \
-global_activity 0.15
voltus> set_rail_analysis_mode \
-method dynamic \
-accuracy hd \
-power_grid_library {tech.cl std.cl mem.cl} \
-report_power_in_parallel true \
-decap_opt_method feasibility \
-generate_decap_eco true
voltus> set_power_domain -name All -pwrnets VDD -gndnets VSS
voltus> set_pg_nets -net VDD -voltage 1.08
voltus> set_pg_nets -net VSS -voltage 0.0
voltus> set_power_pads -net VDD -format xy -file VDD.ppl
voltus> set_power_pads -net VSS -format xy -file VSS.ppl
voltus> analyze_rail -type domain All

©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/1611


Tip1: The report_power and set_power_data commands are not
required when running power/rail analysis together
(report_power_in_parallel true). This flow is also
supported for static analysis but incremental power report generation
will not work. Minimum 8 CPUs are required to enable concurrent
Power and Rail analysis.
Tip2: Voltus Dynamic power analysis also supports Static power analysis in
the same run, this can be achieved by adding “-disable_static
false” in the power analysis option. Refer to Voltus User Guide for
more information.

Once the dynamic rail analysis is complete, all the analysis summary can be found in the
log file, and the individual ascii/html reports and gif plots will be outputted to <PG_net>
and <PG_net>/Reports directories.

The Voltus GUI offers additional debugging features to analyze dynamic power/rail
result:
• Plots instance/total current, composite waveforms, voltage source current, etc.
• Layout overlay rail analysis plots: IR drop, Decap Density, Effective Instance
Voltage, grid capacitance, device tap currents, drop across package, instance
based effective resistance, unconnected grid, etc.
• Dynamic IR Drop and Tap Current movies
• Interactive queries and violation browser to debug IR hotspots

©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/1612


9. Early Rail analysis (ERA)

Traditionally ERA was part of Innovus, starting 15.1 Voltus standalone also support this
capability. ERA does not need fully routed power-grid because it has the ability to create
virtual power connections based on logical connectivity. ERA allows variety of user defined
power constraints in interactive manner which enables it to quickly perform rail analysis and
check if design meets those power constraints.

Figure: Early Rail analysis Flow

Preparing for Early Rail Analysis:


1. The design must have power stripes for a net to be analyzed.
2. Instances must be logically connected to the PG net under consideration.
3. The design must be loaded into memory for virtual follow pin routing and virtual
via completion.
4. If the design has no instances, a single current region can be automatically created
with all current attached to it

Tip: Static Power and Rail Analysis without PGV can also be run using the
Innovus license.

©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/1613


An example TCL command for the Floorplan stage design grid analysis with current regions
is as follows:
voltus> read_lib -lef full.lef
voltus> read_verilog test.v.gz
voltus> set_top_module test
voltus> read_def full.def
voltus> set_rail_analysis_mode \
-method era_static \
-accuracy xd \
-extraction_tech_file qrc.tch \
-era_current_region_file current.region
voltus> set_pg_nets -net VDD \
-voltage 1.1 \
-threshold 1.067
voltus> set_power_pads -net VDD -format xy \
-file vdd.pp
voltus> set_power_data -format area -power 1 \
-bias_voltage 1
voltus> analyze_rail -type net \
-results_directory early_vdd VDD

Viewing Early Rail Analysis results


User interface to view analysis result is same as in Innovus and Voltus.

For additional information on ERA refer Voltus user guide at: https://support.cadence.com
ResourcesProduct ManualsSSV13.2(Latest Version)  Voltus User Guide

For “do yourself” refer Voltus RAK (Rapid Adoption Kit) for ERA at ‘Related Solutions’
sections below the PDF.
This pdf can be searched with the document title on https://support.cadence.com

©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/1614


10. Additional Topics
IR drop aware timing analysis with Tempus
Voltus static and dynamic rail analysis generates instance voltage file (.iv file) under
output (state) directory e.g. domain_25c_dynamic_1/vdd_vss.iv. The instance voltage
file is the worse rail-to­rail voltage for each instance, and it can be used to perform IR drop
aware delay calculation and timing analysis.

During dynamic rail analysis, the effective instance voltage is calculated inside the
switching window of the instance to obtain the worst operating voltage between power
and ground.

To run IR drop aware timing analysis, use following commands:


voltus> read_instance_voltage –ir_drop {domain.iv}
voltus> report_timing
Note: The report_timing command will use the Tempus toolset and
requires Tempus license. The IR drop aware delay calculation requires
timing libraries with k-factors or timing libraries characterized at same
corner with different voltages.

Voltus power and rail analysis with Innovus


Voltus power and rail analysis use­model is fully integrated inside Innovus System. The
analysis TCL commands are identical and the same GUI can be accessed under Innovus
“Power” menu.

©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/1615


11. Additional Resources

Cadence Support
https://support.cadence.com
877-­­CDS-­­4911 (877-­­237-­­4911)

Cadence User Community


http://www.cadence.com/community

©2016 Cadence Design Systems, Inc. All rights reserved. 10/03/1616