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DIGITAL CIRCUITS:

COMBINATIONAL CIRCUITS
The digital circuits are of 2 types:

1. Combinational circuits: In this type of circuits, output depends only on present

inputs and we don’t need memory element.

1. Sequential circuits: In this type of circuits output depends on both present inputs
and past output hence we need memory elements.

Combinational circuits: Combinational circuits consist of input binary variables, logic

gates and output binary variables. While considering the design of combinational circuits
we need to see that we use minimum number of gates, we have minimum propagation time
or delay etc

Lets design the combinatonal circuit for binary adder. A combinational circuit that performs
the addition of two bits is called Half adder while the circuit which adds 3 bits is called Full

Half adder: For this adder we have two inputs and two outputs. The two inputs are those 2
bits a and b which are to be added and the the 2 outputs are the sum and the carry. The
following table shows the result of different combinations of inputs:

a b S(sum) C(carry)

0 0 0 0

1 0 1 0

0 1 1 0

1 1 0 1

Now we can see from the table that carry is one only when both inputs are 1 while sum is 1
when only one of the two is 1 like a XOR gate.So

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S= a’b + ab’
C= ab

Or we can get the equations from the K-map also which are discussed on the next page

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The full adder has 3 inputs and 2 ouputs. The first 2 inputs are the 2 bits a & b to add while
the 3rd input c is the carry from the previous significant bit while the outputs are the same:
sum S and the carry C. The following table shows the result of different combinations of
inputs:

a b c S(sum) C(carry)

0 0 0 0 0

0 1 0 1 0

1 0 0 1 0

1 1 0 0 1

0 0 1 1 0

0 1 1 0 1

1 0 1 0 1

1 1 1 1 1

K-map for the output variable SUM is as follow:

This circuit is a level 3 circuit as we also need inverters at level 1, then we have 4 3-input
AND gates at level 2 and 4-input OR gate at level 3. So we need 3 gate delays (3Δ) to get
the output for Sum.

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When we implement this circuit we see that this is a level 2 circuit as we have AND gates at
level 1 and 3-input OR gate at level 2 and hence we need 2 gate delays (2Δ) to get carry
output.

= b’ (ac’ + a’c) + b (a’c’ + ac) = b’ (ac’ + a’c) + b (ac’ + a’c)’

=b’ (a xor c) + b (a xor c)’ {We know (ac’ + a’c)’ = a’c’ + ac and a’c + ac’ =
a xor c}

= b’z + z’b= b xor z {z= (a xor c)}

= b xor a xor c

S = a xor b xor c

and C = ab + ac + bc = ab(c + c’) + ac (b + b’) + bc (a + a’) = abc + abc’ + abc + ab’c + abc
+ a’bc = abc +a’bc+ab’c+abc’= Σ(3,5,6,7)

So we can draw the circuits using XOR, NOT, AND & OR gates

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FA using HAs

Ans: Yes we can implement the Full Adder using 2 half adders and one OR gate as follow:

And the circuit diagram is as:

NUMBER SYSTEMS

If we have a number n4n3 n2 n1 n-1 n-2 n-3 and base or radix is b so the value of the
number is

n3*b3 + n2 *b2+ n1 *b1+ n0 *b0 + n-1 *b-1+ n-2 *b-2

So we can vary the value of b to get a different number system. We specify the value of the
base as suffix to the number to represent which number system is being used. There are
following number systems which are generally used to represent a value.

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This is the one which would accept bit by bit input of the n-bit numbers and there is a bit by
bit output of the n-bit Sum. In this adder we would be required one full adder and a memory
element.

Hence we see we require lesser hardware. The circuit for serial addition is as follow:

Parallel adder is the one where we input the all the bits of two given numbers and we don’t
need any memory element.

4-bit parallel adder is as follow:

Let’s now calculate the time required for the carry to propagate from adder 1 to last adder
and when we get the final result.

If at time t=0 we input the variables, we’ll the carry of 1st adder at t=2Δ which would be
propagated to 2nd adder and at t=3Δ we get the sum variable S1. When at t=2Δ carry C1 is
propagated to 2nd adder, we get the carry output of 2nd adder at t=4Δ and at t=5Δ we get
the S2. At t=4Δ we have carry available at
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3rd adder so its carry output comes at t=6Δ and sum output comes at t=7Δ. Similarly we
get the final carry of 4 bit parallel adder at t=8Δ and sum S4 & hence complete output at
t=9Δ.

And for n-bit adder we have the total time taken as 2 * (n-1) Δ + 3Δ = (2n+1) Δ

which can be written as Ci+1 = Gi + Pi Ci

Gi is called carry generate function as it generates carry when Ai =1 & Bi =1 and Pi is called
carry propagate function because it propagates the carry when we have Ai =1 or Bi =1.
Using these Gi and Pi we can get following equations:

C2=G1+P1*C1

C1*P1*P2*P3

= G4 + G3*P4 + G2*P3*P4 + G1*P2*P3*P4 + C1*P1*P2*P3*P4

These equations suggest that C2, C3, C4, C5 can be calculated from C1 directly. Hence it
is called carry look ahead adder. This is a 4 stage circuit.

We have AND gates at level 1 and OR gate at level 2 in the circuit. Also fan-in of the OR
gate in level 2 & that of AND gate is 5 and we have a maximum fan-in of about 8 So we
can’t extend this circuit to higher stage carry look ahead but can use this 4-stage circuit in
cascaded form. In the following diagram we have cascaded two 4-stage circuits to make it

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So if we have all Gi and Pi and C1 available then we can calculate all the carries only in
gate delay equal to 2Δ and we can obtain all Gi and Pi from the inputs in 1 gate delay(1Δ ).
Hence we can calculate the carry in 3 gate delays (3Δ) for 4-stage circuit to calculate C4
and to obtain the S5 we need 3 gate delays (3Δ). Hence we need a total of 6 gate delays
(6Δ) for 4-stage CLA circuit.

For a 16-bit adder we need total delay= Δ + 2Δ + 2Δ + 2Δ + 2Δ + 3Δ = 12Δ which is also

illustrated below:

so we see that we have been able to reduce the delay for a 16 bit adder from 33Δ to 12Δ
which is lesser by a factor of about 3 times.

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Q-Implement BCD to Excess 3 converter using parallel adder.

Ans: As we know to get Excess-3 from BCD we need to add 3 (0011) to the BCD number.
So the circuit to implement the above is:

Subtractors:
Similar to the adder, we can also design subtractors and we also have half and full
subtractors.

Half subtractor (HS): This circuit subtracts two bits and gives Borrow and Differenceas 2
outputs. The following table shows the result for different combinations of inputs:

a b B(borrow) D(difference)= D = a – b

0 0 0 0

1 0 0 1

0 1 1 1

1 1 0 0

We scan easily see that diference is 1 only when we have one of the inputs as 1 and other
as 0 just like a XOR gate. So equation for difference is D= a’b + ab’

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And the digital circuit to implement the above functions is as follow:

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Full subtractor (FS):
This has 3 inputs- 2 are the numbers to be subtracted and c is the borrow which is taken for
previous bit and we have 2 outputs Difference and the Borrow. The following table shows
the results for all combinations of inputs:

a b c B(borrow) D(difference)= D = a – b – c

0 0 0 0 0

0 1 0 1 1

1 0 0 0 1

1 1 0 0 0

0 0 1 1 1

0 1 1 1 0

1 0 1 0 0

1 1 1 1 1

So we can get the equations for the D and B from the K-maps as shown on next page.

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We can get the output in 2 gate delays as we assume that a, b the input numbers are
stored in flipflops hence we can have the complimented a from the flipflop directly. So we
don’t consider the delay of the inverter shown in the circuit.

Similar to the adder we have D = ab’c’ + a’b’c + a’bc’ + abc = a xor b xor c

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FS using HSs
Q- Can be get the full Subtractor from 2 half Subtractor?

Ans: Yes we can implement the Full Subtractor using 2 half Subtractors and one OR
gate as follow:

And the circuit diagram is

Similar to the adder case we can have serial and parallel subtractors as shown below:

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Serial subtractor:

In this circuit, we have Input number coming bit by bit and output comes bit by bit and the
final borrow at the end:

Borrow-propagate subtractor:

Similar to the case of adder we can have the circuit as follow:

Similar to the adder case we have the delay for n-bit subtractor as (2n+1) Δ and so for 16
bit subtractor as 33Δ.

Hence to reduce this time delay we employ another method to design the subtractor same

B2=G1+P1*B1

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B4=G3+P3*B3=G3 + P3*(G2+G1*P2 + P1*P2*B1)= G3+G2*P3 + G1*P2*P3 +
B1*P1*P2*P3

= G4 + G3*P4 + G2*P3*P4 + G1*P2*P3*P4 + B1*P1*P2*P3*P4

Similar to the adder circuit we have the delay for borrow look ahead subtractor is for a 16-

And delay is reduced by factor of 3.

We can also do subtraction using adders. As we have already studied that we can do
subtraction by 2’s compliment method in which we add 2’s compliment of subtrahend to
minuend and 2’s compliment can be found by inverting all bits of subtrahend and then
adding one. So we have to do as

F= A – B = A + 2’S compliment of B = A + 1’S compliment of B + 1

So we give A at one input, invert of B at 2nd input and give 1 at carry. Hence we implement
the above function.

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4-bit ADDER and SUBTRACTOR in a SINGLE CIRCUIT
Q- Implement the 4-bit ADDER and SUBTRACTOR in a single circuit where we select
one of the two using a select pin SEL.

Ans: The following circuit would work as required: In this circuit we use property of XOR
gate by which XOR gate acts as a inverter when we have one input as 1.

When sel = 0 we get B1B2B3B4 un-complimented through XOR gate and also we have
carry to circuit as 0 hence we get the result as sum of A and B

Y=A+B

When sel = 0 we get B1B2B3B4 complimented through XOR gate (as one input of XOR
gate is 1) and also we have carry to circuit as 1 hence we get the result as difference of A
and B

Y=A–B

COMPARATORS
Here we’ll be designing circuits to compare different binary numbers. Suppose we have
two numbers A & B at the input and 3 output as A>B, A=B, A<B and only one of the three
outputs would be high accordingly if A is greater than or equal to or less than B.

1-bit comparator: Let’s begin with 1 bit comparator and from the name we can easily
make out that this circuit would be used to compare 1 bit binary numbers. If we list all the
input combinations at the input then we get the following table describing the corresponding
outputs.

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A B f (A>B) f (A=B) f (A<B)

0 0 0 1 0

1 0 1 0 0

0 1 0 0 1

1 1 0 1 0

And now we find the equations using K-maps each for f (A>B), f (A=B) and f (A<B) as
follow:

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2-bit comparator
Similarly we can have 2 bit comparator and the table to list all the combinations at input and
their corresponding outputs is as:

A B f (A>B) f (A=B) f (A<B)

00 00 0 1 0

01 00 1 0 0

10 00 1 0 0

11 00 1 0 0

00 01 0 0 1

01 01 0 1 0

10 01 1 0 0

11 01 1 0 0

00 10 0 0 1

01 10 0 0 1

10 10 0 1 0

11 10 1 0 0

00 11 0 0 1

01 11 0 0 1

10 11 0 0 1

11 11 0 1 0

And we get the equations for all three outputs from the K-maps as

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We can also obtain these equations orally as for A1A0 to be greater than B1B0 either A1 is
greater than B1 (i.e. A1=1 & B1=0) or A1 is equal to B1 (or A1is not less than B1i.e. (f(A1<B1))’
= (A1’B1)’= (A1 + B1‘) & A0 is greater than B0 (i.e. A0=1 & B0=0).

Hence the equation we get is f (A>B) = A1B1‘+ (A1 + B1’) A0B0’ = A1B1‘+ A0 B1’B0’+ A1A0B0’

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We can also get the equation orally similar to the above case.

Now we can implement the above equation easily. Similarly we can implement other higher comparators

Ans: Yes we can implement the above required as follow:

Firstly lower two bits of A & B are compared and then next bits and then next. We feed the
result of first 2 bits to lower bit of next comparator. Then we feed the result of this
comparator to lower bit of next comparator. This way with the use of 3 2-bit comparators we
get 4-bit comparator.

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We firstly compare 11 (A1A0) and 10 (B1B0) and we get a HIGH at f (A>B). Hence we put a
HIGH at A0 & a LOW at B0 and A2 & B2 at A1 B1 pins of next comparator. So if A2 is greater
than B2 then we get a high at f(A>B) for 3 bits and if A2 is less than B2then we get a high
at f(A<B) for 3 bits and if A2 is equal to B2 then we compare A0and B0. Similarly we repeat
this and get the result.

QUESTIONS

Ans: We can implement this as follow:

Decoders:

n to m decoder is the combinational circuit which convert binary information from n lines of
input to m lines of output and m=<2 n. Let’s have an example of 3 to 8 decoder. This
encoder just puts the 1 on the line which is equal to the decimal equivalent of binary
number abc2 at the input and 0 on the remaining lines. There is an ENABLE input which
when 0 activates the decoder circuit otherwise decoder is deactivated and it does not
matter what we have at the inputs any more. The following table shows the functioning of
decoder:

a b c D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

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1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

As we see that D0 is 1 only for a=0 b=0 c=0 hence we can directly write equation as
D0=a’b’c’=m0

Similarly we have D1=a’b’c= m1, D2=a’bc’= m2, D3=a’bc= m3, D4=a’bc= m4, D5=ab’c=
m5, D6=abc’= m6,

D7=abc= m7 and from the equations we can draw the digital circuit.

FA using DECODER

a’bc

So we can implement it from decoder using OR gates as follow:

One can obtain larger decoder circuit from given decoder circuit as shown on next page.

Q- Obtain a 4 to 16 decoder using (a) 2 to 4 decoder (b) 3 to 8 decoder

Ans: (a) we take abcd2 as the input to the decoder. Following is the diagram to design 4 to
16 decoder using 2 to 4 decoders

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When we have a=0 b=0 then top most decoder is enabled and 1 is placed on the output
line out of 0 to 3 based on the value of cd2

When we have a=0 b=1 then 2nd decoder from top is enabled and 1 is placed on the output
line out of 4 to 7 based on the value of cd2

When we have a=1 b=0 then 3rd decoder is enabled and 1 is placed on the output line out
of 8 to 11 based on the value of cd2

When we have a=1 b=1 then bottom most decoder is enabled and 1 is placed on the output
line out of 12 to 15 based on the value of cd2

Hence top 4 outputs generate min terms 0000 to 0011, next 4 generates min terms
0100 to 0111, next generates 1000 to 1011 and the last 4 outputs generate min terms
1100 to 1111.

(b) Similarly we can obtain the circuit to obtain 4 to 16 decoder using 3 to 8 decodersHere
first 8 outputs generate min terms 0000 to 0111 while next 8 generate 1000 to 1111.

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Demultiplexer:

It is a combinational circuit which receives 1-bit information and puts this information on the
line which is selected by the binary input on the selection lines. This is different from
decoder circuit as there is also an information line and we don’t have to put 1 every time on
output (as in decoder) but the bit which is present on information line. It is also generally
called by Demux.

Following is block representation for Demux

We can also have n-bit inputs in place of 1-bit inputs and hence we’ll have n-bit output
which can be represented as

Encoder:
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This digital circuit does exact opposite of the function of a decoder. It converts the
information from 2 n to n lines. The truth table is:

We can easily design the circuit diagram from this table. How ever if mistakenly we have ‘1’
at two of the inputs then we’ll have wrong answer from the circuit. But the encoders which
come in the form of ICs are priority encoders. These encoders establish a priority to make
sure that only highest input is encoded in case of two or more inputs. So if we have 1s at
input line 2 and 5, then we’ll have output as 101 as encoder would accept highest input
which is 5.

QUESTIONS
Q- Implement the Octal to Binary encoder (only first 8 numbers).

Ans: In this circuit, we have 8 inputs and 3 outputs. The octal number is feed into the
encoder by placing a high (1) on the corresponding line and we get the binary equivalent as
output.

From the above truth table we can easily get equations and implement the circuit.

Similarly we have decimal to binary encoder where we have 10 inputs and 4 outputs. The
decimal number is feed into the encoder by placing a high (1) on the corresponding line and
we get the binary equivalent as output.

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Multiplexers:

It is a combinational circuit which selects one of the 2n input lines and transmits the
information from that line to the output line. The selection of the input line depends upon the
‘n’ input selection lines. It is also called data selector and is also referred to by only MUX.

Smallest MUX we have is 2 to 1 mux which has 2 input lines, 1 output line and 1 selection line. We
also have 4 to 1, 8 to 1 mux and so on

Q- Implement the 2 to 1 MUX

Ans: Here we have 2 input, 1 selection pin and 1 output pin and truth table is

SEL(s) Y

0 D0

1 D1

Y = s’D0 + sD1

which can be implemented using gates as follow:

For a 4 to 1 MUX we have total of 6 inputs (4 input lines and 2 selection lines). So we’ll
have 64 combinations. The block representation and the truth table is as:

a b Output (Y)

0 0 D0

1 0 D1

0 1 D2

1 1 D3

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BOOLEAN FUNCTION IMPLEMENTATION USING MUXes-PART I

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Ans: While implementing any function using MUX, if we have N variables in the function
then we take (N-1) variables on the selection lines and 1 variable is used for inputs of MUX.
As we have N-1 variables on selection lines we need to have 2 N-1 to 1 MUX. We just have
to connect A, A’, 0 or 1 to different input lines.

e.g. To implement the function F(A, B, C)= Σ (1, 2, 5, 7) using (a)8 to 1 MUX (b)4 to 1
MUX

Ans: (a) We can implement it using all three variables at selection lines. We put 1 on the
min term lines which are present in functions and 0 on the rest.

N=3 so we use 2 N-1 = 2 2 = 4 to 1 MUX.

Suppose we have B, C on the selection lines. So when we have BC=00, put B=0, C=0 in
the function and we see output of the function should be 0 hence we connect 0 to 0th input
line.

When BC=01, then output of the function should be A’+ A = 1. Hence we connect 1 to 1st line.

When BC=10, then output of the function should be A’. Hence we connect A’ to 2nd line.

When BC=11, then output of the function should be A. Hence we connect A to 3rd line.

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BOOLEAN FUNCTION IMPLEMENTATION USING MUXes-PART II

Another procedure to implement the function using MUX

 Take one variable for input lines and rest of the term for selection lines.
 Then list the min terms with the variable selected in complimented form in 1 st row
and list the
 The min terms with variable selected in un-complimented form in 2nd row.
 Then encircle the min terms which are present in the function.
o If we have no circled variable in the column, then we put 0 on the
corresponding line
o If we have both circled variables, then we put 1 on the line
o If bottom variable is circled and top is not circled, apply A to input line
o If bottom variable is not circled and top is circled, apply A’ to input line

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e.g. To implement the function F(A, B, C)= Σ (1, 2, 5, 7) using MUX.

Let’s now take the variable A for input lines and B & C for selection lines.

So we list the min terms as follow:

So the circuit is

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e.g. To implement the function F(A, B, C)= Σ (1, 2, 5, 7) using MUX using
different variable as selection variable.

Let’s now take the variable B for input lines and A & C for selection lines. The min terms
with B in compliment form are 0, 1, 4, 5 and the min terms with B in un-complimented form
are 2, 3, 6, 7

So the circuit is as follow:

e.g. To implement the function F(A, B, C, D)= Σ (1, 2, 5, 7, 9, 14) using MUX
using different variable as selection variable.

Let’s now take the variable A for input lines and B, C & D for selection lines.

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IMPLEMENTATION OF LOGIC GATES USING MUX

Q- Using 2 to 1 MUX implement the following 2-input gates: (a) OR (b) AND (c) NOR
(d) NAND (e) XOR (f) XNOR (g) NOT.

Ans: To implement the above for every gate, either we can derive the different gates using
the logic (the truth table) or the procedure to implement any function with MUX (discussed
earlier)

(a)OR

Truth table:

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USING PROCEDURE TO IMPLEMENT ANY FUNCTION USING MUX:

We take X as the select line

Now write the min terms with Y’ (compliment) and then Y (un-complimented) as follow:

Hence we get that input at line 0 is Y and at line 1 is ‘1’ and we get the circuit same as
above.

(b) AND: Similar to the case of OR gate we can derive the circuit for AND gate as below:

(c) NOR

(d) NAND

(e) XOR

(f) XNOR

(g) NOT.

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Binary to Gray Code converter:

In this circuit we’ll convert BINARY numbers to GRAY numbers. Following is the truth table
for it:

B3 B2 B1 B0 G3 G2 G1 G0

0. 0 0 0 0 0 0 0 0

1. 0 0 0 1 0 0 0 1

2. 0 0 1 0 0 0 1 1

3. 0 0 1 1 0 0 1 0

4. 0 1 0 0 0 1 1 0

5. 0 1 0 1 0 1 1 1

6. 0 1 1 1 0 1 0 0

8. 1 0 0 0 1 1 0 0

9. 1 0 0 1 1 1 0 1

10. 1 0 1 0 1 1 1 1

11. 1 0 1 1 1 1 1 0

12. 1 1 0 0 1 0 1 0

13. 1 1 0 1 1 0 1 1

14. 1 1 1 0 1 0 0 1

15. 1 1 1 1 1 0 0 0

K-MAPS:

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Equation for G3= B3

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Equation for G1= B1’ B2 + B1 B2’= B1 XOR B2

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GRAY TO BINARY:

We have already discussed the procedure for this and procedure can be described by
following diagram:

From the diagram above we can derive the equations directly without any maps.

xor G2

B0= B1 xor G0

PARITY GENERATOR (4-bit MESSAGE):

Q-Implement the parity generator (a) Even (b) Odd for 4-bit message

Ans: (a) Following is the truth table and K-map for even parity

0000 0

0001 1

0010 1

0011 0

0100 1

0101 0

0110 0

0111 1

1000 1

1001 0

1010 0

1011 1

1100 0

1101 1

1110 1

1111 0

K-MAP for even parity:

We know this is the K-map for XOR gate. Hence the equation we get is P (even) = x
xor y xor z xor w

(b) Following is the truth table and K-map for odd parity

0000 1

0001 0

0010 0

0011 1

0100 0

0101 1

0110 1

0111 0

1000 0

1001 1

1010 1

1011 0

1100 1

1101 0

1110 0

1111 1

K-map for odd parity:

We know this is K-map for XNOR gate. Hence the equation we get is P (odd) = x xnor
y xnor z xnor w

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PARITY GENERATOR (3-bit MESSAGE):

Q-Implement the parity generator (a) Even (b) Odd for 3-bit message

Ans: (a) Following is the truth table and K-map for even parity

a b c P(even)

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

K-MAP:

OR P (even) = x xnor y xnor z

(b) Following is the truth table and K-map for odd parity

a b c P(odd)

0 0 0 1

0 0 1 0
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0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0

K-MAP:

Hence the equation we get is P (odd) = x xnor y xor z = x xor y xnor z = (x xor y xor z)’ = (x
xnor y xnor z)’

Hence we see that equations for Parity change with odd or even number of variables

P (even parity) = x xor y xor z = x xnor y xnor z

P (odd parity) = x xnor y xor z = x xor y xnor z = (x xor y xor z)’ = (x xnor y xnor z)’

P (odd parity) = x xnor y xnor z xnor w

We can similarly implement the following by writing their TRUTH TABLES and drawing their
K-MAPS like

Digital Logic Design Notes from www.exploreroots.com Page 43

Q- We are implementing a 3-input AND gate using the following circuit:

We can replace BLOCK with number of (a) Buffers or (b) Inverters. The delay of
buffer is Tp=2ns. Now we need to choose components such that we have proper
output at F= X.Y.Z and the waveforms are as:

Ans: Now if we orally AND all 3 inputs we get that output of the circuit should be a LOW
pulse although after a certain delay. So to ensure proper output at the output line F we
have to make sure that all the input signals reach the input lines of NOR gate after equal
delay.

F = {INVERT(X AND Y)} NOR {INVERT (Z)}

As we need invert (Z) at input of OR gate. As there is already one inverter, hence while we
decide the components for BLOCK we have to make sure that output of the BLOCK is
equal to Input of BLOCK.

Also as delay of inputs X & Y is 4+1 = 5 ns

Hence delay for input Z should also be 5 ns but delay of Z = delay (BLOCK) + delay
(INVERTER)

Digital Logic Design Notes from www.exploreroots.com Page 44

Delay (BLOCK) = 5 – 1 = 4 ns

 output of the BLOCK is equal to Input of BLOCK

 Delay (BLOCK) = 4 ns

Hence we can replace the BLOCK with 2 Buffers (Tp=2ns) as follow:

Also we can design the block as follow: With four inverters so that we have output equal to
input and delay = 4 ns as:

Also we can design the block as follow: With 2 inverters and one BUFFER so that we have
output equal to input and delay = 4 ns as

Digital Logic Design Notes from www.exploreroots.com Page 45

And we get the required output.

Q- Now I make a certain change in the required output. The circuit is same as
the one in the above question but it is not required to be AND gate anymore
and output required is a HIGH pulse with width of 2 ns as:

Now one has to choose the BLOCK such that we get the above waveform as output
of the whole circuit.

Ans: In the previous question we had the 2 inputs of NOR gate as follow:

Digital Logic Design Notes from www.exploreroots.com Page 46

By modifying the BLOCK we can only change the 2nd I/P and 1st input would remain the same.
Now if we analyze the required O/P also given below to see how we need to change the

2nd I/P

And we know that output is NOR of two inputs. And we get a ‘1’ only when we have ‘0’ at
both inputs.We need high pulse of width 2 ns so we need that both inputs remain ‘0’ for 2
ns. Hence to get the required O/P we need to insert the extra delay of 2 ns to the 2nd pulse.
And I/P pulses would be

As we just have to delay the 2nd pulse by 2 ns so we insert an extra buffer or two extra
inverters in the BLOCK as shown on next page:

Or

Or

etc.

Q- Implement the following equations using only Half Adder circuits.

D= A XOR B XOR C

E = A’BC + AB’C

F = ABC’ + (A’+B’) C

G= ABC

Ans: We know the equations for Half Adder are

S = A xor B and C = AB

Digital Logic Design Notes from www.exploreroots.com Page 48

And the other output of 2nd adder is (A XOR B) C = A’BC+ AB’C which is actually E

Now we need F = ABC’ + (A’ + B’) C

which can be written as F = AB C’ + (AB)’ C = (AB) XOR C hence connect carry output of
1st adder (which is AB) with input C as follow:

Digital Logic Design Notes from www.exploreroots.com Page 49

Q- Find out the situation when the following circuit of MUX 2 to 1 would not
work as expected and how can we eliminate the error.

Ans: When we have the static values at the inputs circuit would work fine but when ever
there is a transition in the value of Select pin we have a situation we neither of the two
inputs are selected. Following is the truth table for 2 to 1 MUX

SEL(s) Y

0 A

1 B

(a) Suppose we have the SEL = 1, then we have ‘B’ at the output and when we have SEL= 0
we have ‘A’ at the output. But when there is a transition from SEL= 1 to SEL=0 there is
problem we face.

When we change SEL from 1 to 0, AND2 deactivates and hence ‘B’ is not passed and as we
have a delay of inverter, hence it would take 1 ns extra to activate the AND1 and hence even
A is not immediately passed. So we see that neither A nor B is passed to Z for this 1 ns.

(b) Suppose we have the SEL = 0, then we have ‘A’ at the output and when we have SEL=
1 we have ‘B’ at the output. But when there is a transition from SEL= 0 to SEL=1 there is
problem we face.

When we change SEL from 0 to 1, then it would take 1 ns extra to deactivate the AND1 and
hence input ‘A’ gets passed to OR gate for this 1 ns. Also immediately after the change of
SEL pin from 0 to1 we have the AND2 activated hence ‘B’ is also passed to OR gate for this
1 ns. So both the inputs A & B are passed to output for this 1 ns. But after the 1 ns we have
correctly only ‘B’ at the output

Hence we see that in both transitions we have error for period of 1 ns

To correct this we can have an extra Buffer in the circuit which has a delay same as that of
inverter i.e. 1 ns as shown next.
Digital Logic Design Notes from www.exploreroots.com Page 50
Q- Draw the circuit to check a PALINDROME number of even bits.

Ans: Palindrome number (in bits) is the number which is same whether seen from the first
and the last bit. E.g. 1001, 0110, 0000, 1111 in 4 bits

So to check this we need to have same value of bit at 1st bit and 4th bit, 2nd and 3rdbit
position for a 4-bit number. For a 6-bit number we need to have same bits at 1stand 6th bit,
2nd and 5th bit, 3rd and 4th bit positions.

Hence to check whether bits in different pairs have same value we need to have XNOR
gate and then AND them to see whether all pairs satisfy the condition.

Digital Logic Design Notes from www.exploreroots.com Page 51

We can verify this for a 4-bit number as done next.

So K-map for that is as

And hence we see that we need to XNOR the corresponding bits and then take AND of all
outputs of XNORs

Q- Design and implement the following with a combinational circuit (with A

and B being 4-bit numbers):

S1 S0 Output

0 0 A plus B

0 1 left shift A

1 0 A plus B plus 1

1 1 2A + 1

Ans: We need one 4-bit parallel ADDER and MUX to implement the above. As we
can see that we need atleast one A at the input of ADDER so put A at one of the
inputs

And for the 2nd input we have to choose out of different options, hence we use a MUX

And we see that we have to add an extra 1 when s1=1 & s0=0 and s1=1 & s0=1. In both
cases we have s1=1 so we attach s1 to carry pin also.

Digital Logic Design Notes from www.exploreroots.com Page 52

Q- Design and implement the following with a combinational circuit (with A
and B being 4-bit numbers):

S2 S1 S0 Output

0 0 0 2A

0 0 1 A plus B

0 1 0 A plus B’

0 1 1 A minus 1

1 0 0 2A + 1

1 0 1 A plus B plus 1

1 1 0 A minus B (2’s compliment)

1 1 1 A

Ans: We need one 4-bit parallel ADDER and MUX to implement the above. As we
can see that we need at least one A at the input of ADDER so put A at one of the
inputs

And for the 2nd input we have to choose out of different options, hence we use a MUX

Digital Logic Design Notes from www.exploreroots.com Page 53

And we see that we have to add an extra 1 when s2=1

When S1=0 S0=0 we need 2nd input as A to get 2A & 2A+1, when S1=0 S0=1 we need
2nd input as B to get A + B & A+B+1, when S1=1 S0=0 we need 3rd input as B’ to get A + B
& A+B’+1 as B’+1 is 2’s compliment of B hence A+B’+1 = A – B, whenS1=1 S0=1 we need
4th input as – 1(11112) to get A – 1 & A – 1 + 1 = A

Q- Design and implement the following logical functions with a combinational

circuit (with A and B being 4-bit numbers):

S1 S0 Output

0 0 A OR B

0 1 A AND B

1 0 A’

1 1 A XOR B

Digital Logic Design Notes from www.exploreroots.com Page 54

Q- Can we implement 4 to 1 MUX using (a) three 2 to 1 MUX (b) only two 2 to 1
MUX and a OR gate & NOT gate?

Ans: (a) We can implement 4 to 1 MUX from 2 to 1 MUX as shown below:

(b) We have already implemented 8 to 1 MUX using two 4 to 1 MUX and one 2 to 1 MUX
but as here we have to implement without using 2 to 1 MUX but a OR gate hence we’ll
utilize Enable pin of the MUX and skip the use of 2 to 1 MUX as shown below:

Digital Logic Design Notes from www.exploreroots.com Page 55

Whenever E pin is HIGH, that MUX is selected

Q- Implement a basic ALU which performs the operations of logical AND,

logical OR, ADD, SUBRACT depending on the values of S1 & S0

Ans: We need to use an ADDER, AND gate, OR gate and some MUXes to implement the
above function. We select the functions using the two variables S0 & S1 as:

S1 S0 F (S0, S1)

0 0 AND

0 1 OR

1 0 ADD A & B

1 1 SUBTRACT B FROM A

Firstly we’ll select one out of two logical operations and one out of two arithmetic operations
using 2 to 1 MUX and then we select one out of 2 already selected operations and get the
result.

Digital Logic Design Notes from www.exploreroots.com Page 56

Digital Logic Design Notes from www.exploreroots.com Page 57
SEQUENTIAL CIRCUITS

INTRODUCTION

In Sequential circuits output is a function of present inputs and pat output. These
circuits have a feedback element or memory element which stores the output of the circuit
and makes it available at the input. The following is the general diagram of sequential
circuits:

The binary information stored in the memory element that is fed back into the circuit defines
the state of the circuit. Sequential circuits are of two types:

Synchronous circuits: In these types of circuit, output is defined only on the basis of
values of inputs at discrete instants of time. In these circuits we use flip-flops as memory
devices and a common clock is used to control the working of the circuit. A clock is a
periodic wave which continuously changes its state from 1 to 0 and 0 to 1 as

When-ever pulse goes from high to low, it is called FALLING or TRAILING EDGE and when
pulse goes from low to high, it is called RISING EDGE.

Asynchronous circuits: In these types of circuit every change in the inputs affects output
and output depends on values at every instant of the inputs. All the circuits which don’t
have any flip-flops or clock are called Asynchronous circuits. Hence all the combinational
circuits are Asynchronous circuits.

Digital Logic Design Notes from www.exploreroots.com Page 58

CLOCK

A clock signal is defined by clock period or clock frequency. The clock period is defined
as time interval after which clock repeats it self or we can define it as time gap between two
consecutive falling edges or two consecutive rising edges and clock frequency is defined as
number of clock pulses in a second.

Clock freq = 1/ clock period

Duty Cycle: of a periodic wave is defined as percentage of the clock period we have a HIGH
pulse.

i.e. Duty cycle = (time for which pulse is 1)*100 / Clock period

Digital Logic Design Notes from www.exploreroots.com Page 59

BISTABLE MULTIVIBRATOR

FLIP-FLOP is another name of Bi-stable Multi-vibrator. A flip-flop is the basic element of

sequential circuit. It has the capability of storing 1 bit. The circuit of the Bi-stable Multi-
vibrator using transistors is as follow:

The two transistors are used to store a single bit and they can hold data without external assistance as far
as power is supplied to the circuit. If Q is high we get high as an input to the transistor T1 and hence Q bar
is low and as Q bar is low we get LOW as input to transistor T2 and hence Q is HIGH. We can see how
output is maintained by the circuit itself. So we don’t need t refresh the circuit again and again.

DERIVING THE CIRCUIT OF FLIPFLOP (from digital components):

To understand the logic let’s consider a basic circuit of an inverter with a feedback as
below:

Now what would be the output of the circuit?

We know what ever is at input, we’ll get inverse of that at output and as output is fed back
to input so again it would be inverted and this way we’ll have a pulse oscillating between 0
and 1. Hence the output is as follow:

And width of the pulse (either LOW or HIGH) would be equal to the total delay of the gate and wires. Hence
we have the clock period equal to 2*(gate delay + wire delay).

Digital Logic Design Notes from www.exploreroots.com Page 60

DERIVING CIRCUIT OF FLIPFLOP CONTD..

But basic function of a sequential element is to hold the value but in the above circuit we
have an oscillating value and hence no permanent value is stored.

To store a value what we can do is use 2 inverters and hence only one value would be
stored in the value as net effect of 2 inverters is same output as input. So we are able to
store one bit in the cell.

But even there is a problem associated with this circuit as we don’t know the value stored in
the circuit, as soon as we complete this circuit a value is stored immediately and circuit
becomes stable.

Now if we try to input a 1 to the circuit from the input as:

It would be of no use as providing a +5v (high) and a 0v (low) would result in sinking the
whole voltage and hence net input as zero voltage. We’ll not be able to change the value
stored as input would still be zero and hence value stored would be zero.

And hence there is no provision that we can set a value in the circuit.

Digital Logic Design Notes from www.exploreroots.com Page 61

DERIVING CIRCUIT OF FLIPFLOP CONTD..

To make this provision we make a change in the circuit as follow:

We have place an OR gate with one input as S and the other input being the feed back
input. So in this circuit initial value stored is 0.

Role of S: what ever is the value of S, that value is stored in the circuit. Now if we make
S=1 then we’ll get a 1 as output of OR gate and hence 1 is stored in the circuit. Now the
situation of the circuit is as follow:

Another problem in the circuit –

How to make it zero now:

now 1 is stored in the circuit and if we want to store a 0 again in the circuit then we make
S=0. But when we make S=0, we are not able to change the value from 1 to 0. So we find
that there is another problem with this circuit that we are not able change value to 0. What
now..?

Now we make another change in the circuit as follow so that we can change the value to 0
or 1 as we want: As we have seen that we can put a 1 on the line using OR gate but we
need to put a 0 at the input of first inverter to store a 0 in the circuit. So what do we do
now? Let’s see values at different points in the circuit if a 0 is stored.

And we see that if we can place a 1 in the middle of two inverters we can change the value
stored to 0 and hence we include an OR gate in the middle of inverters as follow:

Digital Logic Design Notes from www.exploreroots.com Page 62

DERIVING CIRCUIT OF FLIPFLOP CONTD..

We can represent the above circuit as follow (replacing OR & NOT with NOR):

In the middle of two NOR gates we have the invert of what we have at the output. hence we
can represent the middle point with Q bar.

And with little adjustments we can represent the above circuit as given on the next page:

This circuit is called RS latch and we can store either a 0 or a 1 in this circuit depending
upon the value of R & S as discussed on next page.

Digital Logic Design Notes from www.exploreroots.com Page 63

RS FLIPFLOP

When R=0, S=0 we don’t have a change in the output in the circuit.

When R=1, S=0 we have the output as Q=0 and Q bar = 1

But when we have R=1, S=1, both R and S make outputs of their NOR gates 0. Hence we
have Q=0, Q bar = 0 which is not a valid case as Q & Q bar should be compliment of
each other and hence we don’t consider this case. This is calledRACE CONDITION. All
these cases can be collectively represented in a table as follow:

Let’s draw the timing diagram of the RS latch: t is the delay for a NOR gate.

Initially we have R=0, S=0 and Q=0. When value of S changes to 1, we see in the circuit of RS
latch, output of NOR gate (which is Q’) becomes 0 after delay of t ns. Hence both Q & Q’ are
0.Now inputs of other NOR gate become R=0 & Q’=0 and hence we get Q as 1 after another
delay of t ns which is shown in the timing diagram. Similarly other outputs are shown.

Digital Logic Design Notes from www.exploreroots.com Page 64

COVERSION OF NOR TO NAND IMPLEMENTATION OF RS FLIPFLOP

We can also represent the above circuit using NAND gates as: Let’s convert to NAND
circuit step by step.

Now we replace R by R (bar) and S by S (bar) and eliminating the 2 circles and hence final
circuit.

R'S' FLIPFLOP

The characteristics of the FF are as given in table:

Clocking RS latch:

We can control RS Latch with clock by ANDing both inputs with clock separately as:

Hence when we have CLK (OR E) = 1, R & S gets passed to the RS latch circuit and hence
the output is affected by the inputs only when CLK (OR E) = 1 and when CLK (OR E)=0,
inputs are not passed to the circuit and hence whole circuit is isolated from R & S. As this
circuit is enabled only when Level of the CLK (OR E) is HIGH and disabled when level of
CLK (OR E) is LOW, this is called LEVEL SENSITIVE (LATCH). So when ever CLK (OR
E) is high all the changes in the input are transmitted to the output as shown in the
waveforms below:

Digital Logic Design Notes from www.exploreroots.com Page 66

D Latch:

As we have already discussed that when ever we have both R & S equal to 1 we witness
an ambiguous state. Hence to avoid this we have made an arrangement in which we’ll
never have both R & S equal. We connect the two inputs with an inverter between them as
shown below:

This is the flip-flop which is most widely used in real world applications. This is also called
delay Latch. The following table would show the overall functioning of the D-latch:

Digital Logic Design Notes from www.exploreroots.com Page 67

JK LATCH:

This is very similar to RS latch but the ambiguous state has been eliminated and output is
fed back to the AND gates. Also in this latch we get a complimented output when both the
inputs are 1. Inputs are designated as J and K. The circuit diagram is as follow:

Let’s now try to understand this circuit.

We can see that in the circuit above we have ANDed Q bar with J & CLK (OR E) and Q with K
& CLK(OR E). Hence when we have previous Q=1, Q bar=0 then J would not be passed
further and K would be passed which means latch can be cleared if we have previous Q=1.

When we have Q=0, Q bar=1 then only K would not be passed and J would be passed
and we see that Latch can be set if previous output is 0.

When J=1.K=1

If previous Q=0, then we need to get output as Q=1(compliment of previous output), Q

bar=0 hence we need to have inputs reaching the basic flip-flop are J=1, K=0. Hence we
AND input K with the previous output Q and J with Q bar, due to which only upper AND is
activated and only J is passed and hence we get the output=1.

Digital Logic Design Notes from www.exploreroots.com Page 68

If previous Q=1, then we need to get output as Q=0 (compliment of previous output), Q
bar=1. Hence we need inputs to the basic flip-flop as J=0, K=1 to clear the output. As we
have ANDed J with previous Q bar and K with Q, lower AND gate is activated and K=1 is
passed to clear the output.

When J=1, K=0

As J is ANDed with Q’ so J=1 would be passed only when we have we have Q’=1. Hence
when we have Q=0 & Q’=1, upper AND gate is activated and J would be passed further
and hence output would be set to 1. And if we have previous outputs as Q=1 & Q’=0, we
need not pass J as output would be same even if we pass it.

When J=0, K=1

As K is ANDed with Q, so K=1 would be passed further if we have previous Q=1 & Q’=0
(lower AND gate is activated) and hence output would be cleared but if previous Q=0, Q’=1
then we need not pass the inputs J=0, K=1 (which would clear the output) as they’ll not
affect the output independent of whether inputs are passed or not.

Digital Logic Design Notes from www.exploreroots.com Page 69

T Latch:

This latch is obtained from JK by connecting both the inputs. This is also known
asToggle latch as output is toggled if T=1. The truth table is:

TIMING PROBLEM IN LATCHES:

Well in sequential circuits, paths exit between latches through combinational circuits from
one latch to other or from output of latch to input of same latch. When we give a feed back
to input of same latch then we face a timing problem as shown:

Suppose we have the following circuit:

In this circuit when ever we have E=1, output Q of latch is complimenting again and again
as we have connect the Q-bar to D input. We represent the above in waveforms as:

Digital Logic Design Notes from www.exploreroots.com Page 70

But ideal is that we have only one transition in the output per clock. Hence to avoid this
problem we use edge triggered flip-flops.

PROBLEM IN JK & T LATCH: When we have J=1, K=1 or T=1 then output is
complimented and if CLK (OR E) is still HIGH, then when the new output is fed back, output
is complimented again and this way output is continuously complimented. This problem is
called RACE AROUND PROBLEM. We can observe this as:

Let Q=1,Q’=0 with J=1, K=1 or T=1, then lower AND gate is enabled and hence J=0, K=1
is passed and output is cleared and we have Q=0, Q’=1. If CLK (OR E) is still HIGH and
now as Q=0, Q’=1, then upper AND gate is activated and J=1, K=0 is passed, hence output
is now set i.e. Q=1,Q’=0 and so on….

To avoid this RACE AROUND PROBLEM we can make sure that pulse width of the clock
is less than the propagation delay of the Latch. Due to this restriction JK & T latches are
generally not used in this form but as edge triggered flip-flops which are discussed later.

ASYNCHRONOUS INPUTS:

There are two special inputs which are used to clear and preset the value of the flip-flop
asynchronously which are usually called CLEAR and PRESET respectively. These inputs
are called asynchronous or direct inputs because these signal don’t wait for the clock to
come but can affect the output independent of the clock. These inputs can be of two types:

Active LOW: This means when the input is LOW, it would affect the output otherwise if
input is HIGH then it causes no change.

Active HIGH: This means when input is HIGH then it can change the output otherwise if
input is LOW, it doesn’t cause any change in the output.

These inputs can be adjusted in the circuit diagram of the flip-flop with Active HIGH
DIRECT

INPUTS as:

Red colored line defines the boundary of the flip-flop.

The following table shows the output for various combinations of inputs with Active
HIGH direct inputs:

Similarly we can have the circuit for Active LOW direct inputs

Waveforms illustrating the functions of CLEAR & PRESET inputs for T Flip-flop are as:

Digital Logic Design Notes from www.exploreroots.com Page 72

Note: When we have both PRESET & CLEAR equal to 1 (in Active high inputs) we
have RACE CONDITION as PRESET tries to make output equal to 1 and CLEAR tries to
make output equal to 0 simultaneously which is not possible..

Similarly we have RACE CONDITION when both PRESET & CLEAR are equal to 0 in
Active low inputs.

Different parameters of clock pulses:

Note that we need the width of PRESET pulse, CLEAR pulse etc to be greater than some
minimum values for proper operation of every flip-flop. This width is measured between
50% transition points of rising and trailing edges of the given signal.

Setup and Hold time are measured w.r.t the activating clock edge. The Setup time is the
difference between the 50% transition point of DATA input before clock edge and 50%
transition point of activating clock edge while Hold time is measured between 50%

transition point of activating clock edge and 50% transition point of the DATA after clock
edge as shown below:

Digital Logic Design Notes from www.exploreroots.com Page 73

Propagation time is measured between 50% transition point of activating clock edge and
the 50% transition point of output for the corresponding edge but it is generally different
when output changes from 1 to 0 or 0 to 1. Hence we define propagation time T pHL as
difference between 50% transition point of activating clock edge and 50% transition point of
the output change from HIGH to LOW

while propagation time TpLH as difference between 50% transition point of activating clock
edge and 50% transition point of the output change from LOW to HIGH.

And we take average of both TpHL and TpLH to specify the propagation time

QUESTIONS:

Q-What is the difference between LATCH & FLIP-Flop?

Ans: We can easily find the answer after going through the theory given:

1. Latches are level sensitive while flip-flops are edge sensitive devices
2. Hence latches faces problems like glitches in the output while no such problem
occurs in flip-flops.
3. As we can see from different circuits given earlier, we need more gates to
implement flip-flops than latches.

Q- Implement the function of D latch using MUX?

Ans: We know D-LATCH can be triggered when CLK is 1 (positive level triggered) or when
CLK is 0 (negative level triggered). Hence we can implement both of these as follow:

Digital Logic Design Notes from www.exploreroots.com Page 74

And we can make a truth table for each of these as:

Those are actually the truth tables for D-LATCH. Hence we get the D-latch using
MUX.

Digital Logic Design Notes from www.exploreroots.com Page 75

EDGE SENSITIVE LATCH (i.e. FLIP-FLOP):

Latches which are activated by the edge of the clock are called Flip-flops. If it is apositive
edged flip-flop then inputs are accepted only when a LOW to HIGH transition occurs in the
clock and if it is a negative edged flip-flop then inputs are accepted only when there is a
HIGH to LOW transition in the clock signal.

When we use a pulse triggered latches in the circuit then every fluctuation in the input is
visible in output. Hence we use edge triggered flip-flop and output is generated only
depending upon the value of input at the clock edge. We represent the flip-flop similar to
latch but in flip-flops we place a triangle near CLK terminal as shown: And to represent a
negative edged flip-flop we place a circle before the triangle (as we do in case of inverter)
shown below:

One way to make flip-flop respond to edge of the clock only, we use a RC circuit to produce
a edged clock rather than a pulsed clock. This RC circuit generates spikes in response to
the transitions in the clock pulse as shown below and we use either positive or negative
spikes and neglecting the other spike.

Digital Logic Design Notes from www.exploreroots.com Page 76

Master slave flip-flop- PART I:
We use 2 separate latches to construct a master-slave flip-flop. One latch acts as a Master
and other acts as a Slave. Both are level triggered latches but one is latched on positive
level and other on negative level.

Diagram of the RS master-slave flip-flop is as:

First latch acts as a master and 2nd latch acts as a slave. Master latch is enabled on
positive level and slave latch is enabled on negative level. Hence when ever CLK goes
positive, master latch starts accepting the inputs and generates the outputs
correspondingly. But as slave latch is disabled it accepts none of the generated outputs but
when CLK goes LOW, 2nd latch starts accepting inputs and inputs are actually the final
output of the master latch (which is the output corresponding to the inputs at last moments
of HIGH pulse to master latch just before falling edge) . Hence slave latch just passes that
final output of the master latch to the output terminals or we can say as a whole, output is
produced only corresponding to the inputs which are just before the falling edge and the
whole circuit acts as anegative edged flip-flop.

Circuit diagram of RS master-slave is as:

Similarly we can achieve a positive edged flip-flop by triggering master flip-flop on negative
level and slave flip-flop on positive level of the pulse. We’ll use inverter to master flip-flop

Digital Logic Design Notes from www.exploreroots.com Page 77

MASTER SLAVE FF - PART II

We can have a Master-Slave JK flip-flop as following diagram:

And while drawing the circuit diagram we instead of giving two feed backs (one for each
flip-flop), we’ll draw only a single feedback from the final output of the whole circuit to the
input of the circuit and implement the JK flip-flop. We can analyze the circuit as we did in
case JK latch and see that JK flip-flop is implemented by following circuit:

-: Master Slave JK flip-flop:-

Following waveforms for positive edge triggered flip-flop would further illustrate the working
of an edge triggered flip-flops:

Digital Logic Design Notes from www.exploreroots.com Page 78

PROBLEM IN MASTER SLAVE:

We have a problem in master-slave flip-flops. Consider a RS Master-Slave Flip-flop and

following waveforms are the expected output of RS flip-flop

While when we actually give the above inputs to RS master-slave flip-flop, we get the
following outputs

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And we see that at the 4th and 5th edge we have the wrong transitions. Why so?

Before the 4th negative edge, there is small R pulse which resets the output of Master RS
flip-flop and after resetting the output of master RS flip-flop R goes low. Now we have S=0
& R=0 and output of master stays low and hence when transition of CLK occurs from 1 to 0,
we have S=0 & R=1 (instead of S=1 & R=0) at the slave FF and hence final output is reset.
So we notice that a high pulse at R has affected output even when pulse occurred much
before the negative edge.

Before the 5th negative edge, a short high pulse occurs at S input of master due to which
output of master is set to 1 and after some time S resets and we have S=0 & R=0 and
hence output of master stays high and when CLK goes from 1 to 0, we have inputs of slave
as S=1 & R=0 (instead of S=0 & R=1) and hence final output is set to 1. We again notice a
pulse which occurs much before the edge and still affects the final output.

So we find a situation when a master-slave flip-flop doesn’t work as edge-triggered FF.

Similar problem we’ll face in JK flip-flop as we have a no change condition in both FFs. But
we can realize a edge-triggered FF with D Flip-flop without this problem as:

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Q- Can we implement the D-Flip-flop using MUX?

Ans: Yes, we can. As we can derive a D FF from D latch by following circuit:

So we implement the above circuit to get D ff from MUX as: The following D FF is a falling
edged or negative edged Flip-flop.

And we can implement the rising edge or positive edged flip-flop using negative level
triggered D-LATCH as:

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TIMING PARAMETERS OF A FLIP-FLOP:

There are basically 3 types of factors which affect the working of a flip-flop:

1. SETUP TIME

2. HOLD TIME

3. PROPAGATION TIME

SETUP TIME & HOLD TIME

Setup Time: This is defined as minimum amount of time required for which an input should
be stable just before the clock transition occurs. Suppose we have a positive edged JK flip-
flop and setup time is t= 1ns seconds. If clock pulse with period 5 ns is going from 0 to 1 i.e.
first positive edge is coming at time t=1 ns then both inputs J & K should be stable for 1 ns
from time t=0ns to t=1ns & t=5ns to t=6 ns & t=10 ns to t= 11 ns i.e. J & K should not
change during this period as shown:

Hold Time: This is defined as minimum amount of time required for which an input should
be stable just after the clock transition occurs. Suppose we have a positive edged JK flip-
flop and Hold time is t= 1ns seconds. If clock pulse with period 5 ns is going from 0 to 1 i.e.
first positive edge is coming at time t=1 ns then both inputs J & K should be stable for 1 ns
from time t=1ns to t=2ns & t=5ns to t=6 ns & t=11 ns to t= 12 ns i.e. J & K should not
change during this period as shown:

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And both conditions can be represented as follow and inputs should be stable for at least 2
ns:

Well there are some special timing requirements which must be fulfilled by the input
signal to get a valid output at the output terminal. If any of the above requirements is not
followed and inputs change their value within any of setup time window or hold time
window, then output of the flip-flop can not be predicted and flip-flop is said to enter
in METASTABLE STATE and output can be either zero or one. This whole process is
called METASTABILITY.

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PROPAGATION TIME:

It is defined as the time after the clock transition, required for a flip-flop to generate output.
This is also called CLOCK TO Q delay T clock-to-q.

e.g. Let’s draw the wave forms of inputs and outputs for D FLIP-FLOP which would
illustrate the above discussed:

Maximum Frequency of the clock signal:

To achieve the maximum frequency of the clock signal we can assume to start SETUP time
immediately after the CLK to Q delay is finished.

This would mean that we can have the next positive edge (CLK to Q delay +
SETUP time) after the previous positive edge. And with 50% duty cycle, falling edge
would be right in the middle of positive edges. Hence we get the total minimum time
period and maximum frequency of the clock signal as

QUESTIONS

Q- We are given a D FF which is used as a divide by 2 circuit and specifications of

the flip-flop are as:

T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and circuit is as:

Ans: I’ll recommend drawing the 1st edge of clock and then to mark the various delays
which we require for proper input to reach the flip-flops before the 2nd edge of the clock as:
We know that we have to obey following conditions of setup & propagation time:

To get the minimum delay (maximum frequency of the circuit) , we eliminate the time
between end of propagation time and starting of setup time and we get the clock

time period as:

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QUESTIONS

Q- Find the maximum clock frequency of the following circuit and specifications of
the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and
maximum delay of the combinational circuit is T (c-delay) = 13 ns

Ans: As input to first flip-flop is directly available and hence this doesn’t affect clock
frequency but input to 2nd flip-flop reaches after various delays from the previous edge of
the clock. We the above as follow:

And the complete clock can be represented as follow: c-delay is combinational delay

Digital Logic Design Notes from www.exploreroots.com Page 86

QUESTIONS

Q- Find the maximum clock frequency of the following circuit and specifications of
the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and
maximum delay of the combinational circuit is T (c-delay) = 13 ns and delay of buffer
is T (buf) = 2ns.

Ans: There is a change in the circuit from the previous questions that we have an extra
buffer in the way of clock signal to 2nd flip-flop. Due to this buffer, clock edge reaching
2nd flip-flop delays by 2 ns. Note that we calculate the various delays for input of 2 nd FF wrt
the clock edge of 1st flip-flop. And input going through all the delays should reach before
clock edge reaches the 2nd flip-flop. Let me represent the above in a diagram as follow:

We firstly represent the delays wrt edge of 1st FF as

And the delayed input must reach before the edge reaches 2nd flip-flop

And we know that for 1st FF clock edge can reach anytime as there is direct input available.
Hence we get that

Clock time period is T = T CLK to Q + cdelay + Setup time –clock delay for 2nd FF

= 9 + 13 + 5 – 2 = 25 ns

Digital Logic Design Notes from www.exploreroots.com Page 87

QUESTIONS

Q- Find the maximum clock frequency of the following circuit and specifications of
the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns,
T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold
time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational circuit1 is 13 ns & of
combinational circuit2 is 16ns in the following circuit.

Ans: Now we to take care of following conditions while calculating maximum frequency of
the circuit:

 Inputs of FF1 come directly hence only setup time of FF1 should be satisfied
 Various delays would matter for Inputs of FF2 wrt to the previous edge of FF1
 Various delays would matter for Inputs of FF3 wrt to the previous edge of FF2

Hence we get to know that

If we calculate minimum clock period (Tmin) considering conditions to be fulfilled for edge
of FF1 then Tmin= T1 (setup) = 5 ns

Considering conditions to be fulfilled for edge of FF2 then Tmin= T1 (CLK to Q) +

cdelay1 + setup2 = 9 + 13 + 4 = 26 ns

Considering conditions to be fulfilled for edge of FF3 then Tmin= T2 (CLK to Q) +

cdelay2 + setup3 = 7 + 4 +16 = 27 ns

Now if we take clock period as 5 ns then we’ll not be able to satisfy the condition at clock
edge of FF2 & FF3 (As clock is common for all)

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If we take clock period as 26 ns, then we’ll be satisfying the condition at FF1 & FF2 but
conditions of FF3 would not be satisfied & hence we cannot take this as clock period.

But if we take clock period as 27 ns then we satisfy the condition at every clock edge.

Hence minimum clock period to satisfy every condition is Tmin = 27 and maximum clock
frequency we get is 1/ 27 = 3.7 MHz

The truth table for RS Flip-flop is as follow:

Now let’s draw the K-map and get the equation for output Q. As the Qp and Qp bar are
compliment of each other so we’ll consider only one of those in K-MAP

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CHARACTERISTIC EQUATION OF D FLIP-FLOP:

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The equation we get is

EXCITATION TABLE OF FLIP-FLOPS

Excitation of a flip-flop is actually exact opposite of what a truth table is. The truth table for
the flip-flop gives us the output for the given combination of inputs and present output while
an excitation table gives the input condition for the given output change.

E.g. As in truth table we say for T flip-flop if input T is 1 and previous Q is 0 then we have
output as 1 while in excitation table we are given that present output Q is 0 and new Q is 1
then input T is 1.

Next we write truth table of various flip-flops and then we write their excitation flip-flops.

Digital Logic Design Notes from www.exploreroots.com Page 91

EXCITATION TABLE OF RS Flip-flop:

The truth table of the RS flip-flops is as:

Now to write the excitation table of this flip-flop we first write the various output changes
possible as:

Now we can see from that truth table that to change output from 0 to 0, we can keep
inputs S, R as 0, 0 or 0, 1 and we can write both the combinations as 0, X which means we
just need to keep S=0 and R can have either of two possible values.

Similarly we can note that for output change from 0 to 1, we keep inputs at S=1,
R=0.Similarly we can find the other cases and we get the table as:

Similarly we can find out the excitation tables for other kind of flip-flops as shown next:

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EXCITATION TABLE OF OTHER FFs

JK Flip-flop: The excitation table of JK flip-flop is as:

For output change from 0 to 1 we can either keep inputs J, K as 1, 0 or we can make
use of toggle input combination J=1, K=1 to get compliment of the output.

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CONVERSION OF ONE FLIP-FLOP TO OTHER:

As we have already seen from the way we derived D flip-flop from RS flip-flop or the way
we derived T flip-flop from JK flip-flop or the way we derived JK flip-flop from RS flip-
flop by feeding back outputs that to derive a flip-flop from the other flip-flop we need to
design a combinational arrangement before the given flip-flop to convert the given to work
as required flip-flop. Hence the general diagram to obtain a flip-flop from the given flip-flop
is as:

RS flip-flop to D flip-flop:

Let’s first now derive the D flip-flop from RS flip-flop which we have already done:

Now we need to make a arrangement so that we manipulate input D to inputs R, S such

that we get the same output with RS FF as that of D FF. So we combine the two tables
given above with same outputs in the same row:

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Now we design the combinational circuit to convert D input to SR inputs using K-map as:

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RS flip-flop to JK flip-flop:

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K-map for R input:

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D Flip-flop to RS flip-flop:

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And we get the circuit to convert D to SR FF:

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D to T & T to D FF
Similarly we get the circuits as follow:

D FF to T FF:

T FF to D FF:

Note: We have not shown the clock but we can attach the clock signal to the given FF.

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MEMORY

1-bit Memory Cell: We know that flip-flop can store either zero or one permanently until a
change is made in the inputs. Hence flip-flop would work as 1-bit memory cell.

Registers:

A register is a group of 1- bit memory cells. To make a N-bit register we need N 1-bit memory
cells.

Register with parallel load: We can represent a simple 4-bit register as: We can give the
values to be stored at input and we get that value stored at the next clock pulse.

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But in this circuit we have to maintain the inputs to keep the outputs unchanged as we don’t
have the input condition in D Flip-flop for unchanged output. Hence we modify the above
circuit with an extra

input LOAD which when ‘1’ would mean there is a new input data to be stored and LOAD=0
would mean we have keep the stored data same. The modified circuit is as:

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Shift register:

In this type of register value stored in the register can be either shifted to left or right
depending upon the circuit as:

SERIAL IN SERIAL OUT:

Right shift: Here data is shifted by one bit from left to right with every clock tick.

Left shift: Here data is shifted by one bit from right to left with every clock tick

SERIAL IN PARALLEL OUT: In this type of register we firstly load data serially in the
register. For a 4-it register we’ll need 4 clock cycles to load data and then output comes out
in parallel mode.

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PARALLEL IN SERIAL OUT: In this type of shift registers we first input the Parallel data
by using LOAD=1 and then data is shifted and data comes out serially.

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Ring counter:

This is a special type of register in which 1 moves in the output in the ring i.e. initially output
of 1st FF is 1. On next edge this 1 is transferred to output of 2nd FF while previous output
becomes 0. Similarly on next clock output of 3rd FF becomes 1. Similarly it continuous till
last FF goes 1. After this 1st FF goes 1 goes again and whole procedure is repeated. This
way 1 is moved in a ring as:

i.e.

Clock Q 4 Q3 Q2 Q1

Initially 0001

2nd 0100

3rd 1000

4th 0001

And so on

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Circuit diagram to achieve Ring Counter is as:

To start the Ring counter, we firstly give START=0 and then rightmost FF is set and all
others are reset and hence initial output is 0001

We can also realize Ring counter using JK flip-flop as:

Application: We can use Ring counter in the system where we have to perform different
operations sequentially and repeatedly. Suppose we have to do operations A, B, C & D.
Firstly we have to do A, then B, then C, and then D. after performing all operations we have
to perform operation A and so on. In this case we can use Ring counter to initiate these
operations sequentially.

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Johnson Counter:

While Ring counter, we have connected Q of last to D of 1st FF, but in Johnson Counter we
connect Q bar of last to D of 1st FF as shown below and we also don’t need to connect
preset of 1st FF. This is also called Twisted Ring counter:

And we have outputs has follow:

Clock Q 4 Q3 Q2 Q1

Initially 0000

2nd 0011

3rd 0111

4th 1111

5th 1110

6th 1100

7th 1000

8th 0000

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We can also note that we use only 8 out of 16 possible states and in general we have
used 2n states and hence we have 2n-2n unused states

Q- Design a circuit to transfer data serially from one shift register to other.

Ans: If we have a N-bit shift register then we need only N clock cycles to shift those N-bits
to the other register. If we apply more or less than this many clock cycles then our
operation of shifting would not be as required. Hence we have to give a control pulse which
would control that only N clock cycles are given to the registers. The circuit diagram is as

follow:

If we are to transfer data between 4 bit register then control pulse would be 4 clock cycles
wide as shown so that only 4 clock cycles are passed.

Following table would show the values of two registers at different clock cycles

1101 1001

4th 1101 1101 1

Hence we see that register1 retains its contents and register2 gets the value of register2
which was required.

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ASYNCHRONOUS COUNTERS - MOD-2 counter:

If we see that flip-flop is a mod-2 counter with starting count as 0. If we connect J & K to
HIGH and supply clock to the flip-flop, we’ll see that flip-flop would count pulses 0, then 1
and as it is a MOD-2 counter so it’ll reset and again count from 0.

And the output is as:

Also note that output pulse is of half the original frequency of the clock. Hence we can say
that flip-flop acts as a Divide by 2 circuit.

Ripple counter:

We can attach more flip-flops to make larger counter. We just use more flip-flops in
cascade and give output of first to the clock of 2nd and output of 2nd to clock of 3rdand so on.
This way every flip-flop would divide frequency of the clock by 2 and hence we can obtain a
divide by larger value circuit. Let’s see how we can make larger counters:

And following waveforms would illustrate how the above circuit does counting. It is actually
a MOD-8 counter so it would count from 0 to 7 and then again reset itself as shown:

With every negative edge, count is incremented and when the count reaches 7, next edge
would reset the value to 0.

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Hence we can design a MOD-2n counter using n flip-lops in cascade

Q-Can we design a ripple counter other than MOD-2n?

Ans: Yes we can. For this we’ll first design the counter with value which is multiple of 2 but
greater than the count required. Then we use a combinational circuit to reset the counter
after the required value of count is achieved. Let’s take an example:

Design a MOD-14 counter.

First we design a counter of 2’s multiple greater than 14 which is 16. So we first design a
MOD-16 counter as:

Now we need to design a combinational circuit which would take care that counter is reset
when count value reaches 13. For this we first draw the waveforms as:

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As we have to count till 13 and reset again. We see that when-ever Q4=1, Q3=1 & Q1=1,
when have to reset the value of all the flip-flops so that we get the value of count as 0.
Hence we take NAND of these 3 variables due to which we get a zero when all 3 variables
are 1 and output of NAND gate is connected to all the ACTIVE LOW CLEAR lines to reset
all flip-flops as follow. We also have to make sure that the output of this NAND gate is zero
only after 13.

And now we the output waveforms as:

And we can clearly observe that we have achieved MOD-14 counter as all count values are reset after 13
but in this method we have to observe the output waveforms and then decide the combinational circuit to
reset value after certain count.

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USING K-MAPS TO DESIGN COUNTER

Q- Design MOD-3 ripple counter using (a) Observing outputs (b) K-maps to design
the circuit.

Ans: (a)We can design the MOD 3 counter using 2 FFs as 3 is less than 4 i.e. 2 2 and
greater than 2. We can see directly that as we have to reset the counter only after 2 i.e.
when output is 3 we reset the counter and hence we need to reset only when we have Q0=
1 & Q1=1. Now firstly design MOD-4 counter using 2 FFs and then take NAND of Q0 & Q1
and feed the output to CLEAR of both FFs.

(b) We firstly draw state diagram of the counter required as:

And we have the general circuit to design the other than MOD 2 n then we have the general
circuit as

And now we draw a table to list the different input combinations to Combinational circuit
and their corresponding output as:

0 0 1

0 1 1

1 0 1

1 1 0

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And using K-map as

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And now we draw the table to represent the desired output of the combinational circuit to
reset FFs as:

Q2 Q1 Q0 OUTPUT

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 0

1 1 1 0

QUESTION

Q- Design the ripple counter whose output sequence is represented by the

following state diagram.

Ans: As it is a 3-bit counter hence we firstly arrange 3 FFs and now we design the
combinational circuit to reset the counter at appropriate point.

Q2 Q1 Q0 OUTPUT

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

+ Q1. (Q0bar)

Digital Logic Design Notes from www.exploreroots.com Page 115

= Q2. (Q1 bar) + XOR (Q1, Q0)

OR

Z= Q0. (Q1 bar) + Q1. (Q2bar)

+ Q2. (Q0bar)

And hence can have two types of combinational circuits to achieve the above counter. And
the whole circuit with first combinational circuit as:

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DOWN COUNTER: (Reverse counting)
Here we’ll be counting in reverse order i.e. count would start from 15 to 0 and again value
goes from 0 to 15. We just make a change in the circuit as we give Q bar to the CLK of next
flip-flop or we use positive edged flip-flops and give Q to CLK of next flip-flop.

Or

Or

Consider the following circuit

And we see that this circuit is a UP counter which count from 0 to 7 and then it is reset but
the same circuit can also work as DOWN counter when we take count as combination of
inverted outputs for each FF. i.e. . Hence output count of the above circuit
would go from 7 to 0 and then again it is set to 7.

QUESTION

Q- Design the ripple counter whose output sequence is represented by the

following state diagram.

Ans: As we can see that it is a down counter so we’ll be using Q bar of all flip-flops as clock
to next flip-flops (negative edged FFs). We draw the table as

Q2 Q1 Q0 OUTPUT

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 1

Z= Q2 + Q1

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And the whole circuit is as:

GLITCH:
A glitch is an unwanted pulse which gets generated due to little difference in the delays of
signals. Whenever signals with glitches are used as clock then glitches causes unwanted
triggering of the flip-flop. e.g.

 We can see in the wave-forms given above for MOD-14 counter that there is a
glitch in the Q2 signal which is produced due to delay of AND gate to reset the
FF.
 Also a glitch can be generated when we AND two signals and there is a slight
delay between two signals. Such a combinational circuit is used when we have to
transfer data serially between two registers discussed already and we need limited
number of clock cycles for proper working.

The following circuit was designed to produce enable signal (with 4 clock cycles)

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But due to slight delay in the one of the input signals there is glitch in the output which
would lead to mal-functioning of the circuit.

Synchronous Counter
In synchronous counters we have the same clock signal to all the flip-flops.

MOD-4 Synchronous counter: We discuss here a 2-bit synchronous counter. We have

the circuit for this as:s

We have the initial outputs as Q0=0 & Q1=0. Whenever the first negative clock edge comes
O/P of 1st FF becomes 1 as we have J & K for 1st FF as 1 and hence output of 1st FF
toggles and changes from 0 to 1. But when 1st cock edge had come output of 1st FF was 0.
Hence J & K for 2nd FF for 1st edge are 0. So output of this FF doesn’t change and we get
Q1=0. so the output is (Q1Q0)2= 012.

On the next edge, output of 1st FF changes from 1 to 0 as J & K are always 1 for this FF.
Inputs for 2nd edge for 2nd FF are J=1 & K=1. Hence output changes from 0 to 1. so we get
the count as (Q1Q0)2= 102.

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Similarly on the next edge we’ll get the output count as (Q1Q0)2= 112.

And on the 4th clock edge both the outputs get reset and we get the output as (Q1Q0)2=
002 and again whole procedure is repeated.

We’ll be studying other synchronous counter when we discuss the design of synchronous
circuits later.

COMPARISON B/W SYNCHRONOUS & ASYNCHRONOUS

COUNTERS

Asynchronous Synchronous
The logic circuit of this type of The circuit diagram for type of
counters is simple to design and counter becomes difficult as
Circuit
we feed output of one FF to number of states increase in
clock of next FF the counter
Propagation time delay of this
Propagation time delay of this
type of counter is:
type of counter is :
Tpd = (Delay of 1 FF) + delay of
Propagation Tpd = N * (Delay of 1 FF)
1 gate
Time
which is quiet high
Inclusion of delay of 1 gate
would be illustrated when we
N is number of FFs
design higher counters:
Maximum
And hence operating frequency And hence operating
operating
is Low frequency is Higher
frequency

Digital Logic Design Notes from www.exploreroots.com Page 122

CLOCK SKEW

It is a phenomenon in which there is a difference between the times at which clock signal
reaches different components in synchronous circuits. Or we can say that clock signal from
clock circuitry reaches different components in the circuit at different times.

e.g. If in the circuit given below, CLK signal reaches the two flip-flops at different times then
it is said that CLOCK SKEW exists in the system.

CAUSES: There are basically 2 reasons due to which clock skew exists in the system:

1. Distance: If there is a difference in the distances between the clock circuitry and
different components then clock signal has to travel through different length of
wires, hence clock signal would reach earlier where there is shorter distance and
clock would reach later where there is longer distance.
2. Change in the material of wires: Also if there is a change in the material of
wires then clock signal can travel faster in one wire and slower in other and hence
there would be change at the time at which clock signal reaches different
components.

 Disadvantage: If combinational logic delay is very short or clock skew is large

enough then output of 1st FF would change (hence input of 2nd FF is changed
overriding the previous input) before HOLD time condition for the input of 2nd FF
is satisfied and hence circuit would not work properly due to this HOLD TIME
violation. Or input of 2nd FF change to create SETUP time violations.
 Advantage: We can see in the example given below that due to clock skew,
minimum clock period of the clock is decreased (and hence frequency is
increased).

QUESTION

Q- Find the maximum clock frequency of the above circuit if specifications of

the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) =
9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns.
There is a clock skew of +3ns for 2nd FF in the above circuit.

Ans: We firstly represent the delays wrt edge of 1st FF as

And the delayed input must reach before the edge reaches 2nd flip-flop

The clock skew is basically the delay in clock signal reaching 2nd flip-flop. Hence this is
quiet similar to the previous question of a buffer in the pathway of clock.

Hence Clock time period is T = T CLK to Q + cdelay + Setup time – Clock Skew

= 9 + 13 + 5 – 3 = 24 ns

QUESTIONS

Q- Find the maximum clock frequency of the following circuit if specifications

of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to
Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup)
= 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational
circuit1 is 13 ns & of combinational circuit2 is 16ns in the following circuit.
Also there is problem of clock skew in the system. We also have to identify
the pair of registers between which we need to know the value of clock skew.

Assume value of clock skew between required pair of registers.

Ans: This question is very similar to the question done earlier as we have to fulfill the same
conditions at clock edges. It’s only the clock skew which is going to affect the value of
maximum frequency. We represent everything as:

If now we calculate the minimum time period required considering condition at all FF as
follow, we’ll find:

FF1 Tmin = setup FF1 = 5 ns

FF2 Tmin = T1 CLK to Q + cdelay1 + setup FF2 – clock skew (b/w FF1 & FF2)

= 9 + 13 + 4 – clock skew (b/w FF1 & FF2) = 26 – 3 = 23 ns

FF3 Tmin = T2 CLK to Q + cdelay2 + setup FF3 – clock skew (b/w FF3 & FF2) = 7 +
16 + 4 – 3 = 24 ns

Digital Logic Design Notes from www.exploreroots.com Page 125

Note: We can easily notice that we need the value of clock skew between only
adjacent pair of Flip-flops. We have assumed the value of skew as 3 ns between the
pairs.

And the minimum time period to satisfy every condition at every clock edge is 24 ns

Hence maximum clock frequency of the circuit is Fmax = 1/24 = 4.16 MHz

IMPORTANT: Clock skew is only meaningful between adjacent pair of flip-flops while
it’s meaningless to know about the cock skew between other pair of flip-flops. Hence
in the above case we only need to know the value of clock skew between FF1 & FF2
and FF2 & FF3 while skew between FF1 & FF3 is meaningless.

QUESTIONS

Then 11 = 1011 4 = 0100

Algorithm: For multiplication we first multiply the LSB of 4 (multiplier) with multiplicand and
then shift it towards right. Then we multiply the next bit and then add it to the shifted result.
Again we MULTIPLY, ADD & Shift or if bit of multiplier is 1 then ADD multiplicand and
SHIFT and if bit of multiplier is 0 then ADD zero (or don’t perform ADD but just) SHIFT. We

Digital Logic Design Notes from www.exploreroots.com Page 126

store multiplier in register Q & multiplicand in A and use adder as:

Now I’ll show the contents of shifter at every clock tick if we have to find A* B = 1011 *
0100

1st tick 0 0000 0100 Initial data is stored in

register from inputs

stored

stored

stored

stored

And we get the answer as 001011002

Digital Logic Design Notes from www.exploreroots.com Page 127
Q- Find the maximum clock frequency of the following circuit and
specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK
to Q) = 9ns and delay of other components is T (buf) = 2ns,Â Â T (AND) = 4
ns, T (OR) = 4 ns,Â Â Â Â T (NOT) = 2 ns in the following circuit.

Ans: We first need to calculate the maximum delay of combinational circuit so that proper
input reaches the inputs of 2nd FF.

We take maximum of those hence 6 ns.

Hence Clock time period T =T CLK to Q + cdelay + Setup time â€“clock delay for 2 ndFF = 9
+ 6 + 5â€“2 = 18ns Maximum Clock frequency = F max = 1/18 = 5.55 MHz

Q- Find the maximum clock frequency of the following circuit and

specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) =
4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) =
7ns T3 (setup) = 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of
combinational circuit1 is 13 ns & of combinational circuit2 is 16ns in the
following circuit. And delay of buffer is T (buf) = 2 ns.

Ans: This question is very similar to the question done earlier as we have to fulfill the same
conditions at clock edges it’s only the delay which has been introduced in the path way of
clock signal. We represent everything as:

Digital Logic Design Notes from www.exploreroots.com Page 128

If now we calculate the minimum time period required considering condition at all FF as
follow, we’ll find:

FF3 Tmin = T2 CLK to Q + cdelay2 + setup FF3 – clock delay= 7 + 16 + 4 – 2 =25 ns

As for FF3 we are calculating delays wrt the previous clock edge of FF2 for different
conditions and there is delay of only 2 ns in clock wrt clock at FF2 hence only 2 ns is
subtracted which can also be seen from the diagram.

Note: One can say that there is a total delay of 4 ns for clock of FF3 and hence 4 should be
subtracted but as we are calculating all delays wrt the clock edge of FF2 and the delay
between clocks of FF2 & FF3 is only 2 ns (not 4 ns). Hence 2 is subtracted.

And the minimum time period to satisfy every condition at every clock edge is 25 ns

Digital Logic Design Notes from www.exploreroots.com Page 129

Q- Find the maximum clock frequency of the following circuit and
specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns
T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-
delay) = 13 ns and delay of buffer is T (buf) = 2ns. Delay of OR & inverter is 3
ns & 2 ns respectively.

Ans: The combinational circuit after the 2nd FF doesn’t affect the clock frequency of the
circuit as there is no gated component after that circuit. Hence we represent the delays wrt
edge of 1st FF as

And the delayed input must reach before the edge reaches 2nd flip-flop

And we know that for 1st FF clock edge can reach anytime as there is direct input available.
Hence we get that

Clock time period is T = T CLK to Q + cdelay + Setup time –clock delay for 2nd FF

= 9 + 13 + 5 – 2 = 25 ns

Digital Logic Design Notes from www.exploreroots.com Page 130

Q- Find the maximum clock frequency of the following circuit and
specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 8ns T (CLK
to Q) = 2ns and delay of other components is T (buf) = 2ns, T (AND) = 4 ns, T
(OR) = 4 ns, T (NOT) = 2 ns in the following circuit.(b) Also tell us if there is
HOLD time violation at any of the flip-flops.

Ans: We first need to calculate the maximum delay of combinational circuit so that proper
input reaches the inputs of 2nd FF.

We take maximum of those hence 6 ns.

Hence Clock time period T =T CLK to Q + cdelay + Setup time –clock delay for 2ndFF = 2 +
6 + 5–2 = 11ns Maximum Clock frequency = F max = 1/11 = 9.99 MHz

(b) HOLD TIME:

At 1st FF K input & one input of AND gate for J input is given externally which is supposed
to be held stable for hold time but the other input is a feedback from 2 nd FF and this input
changes only after minimum delay of T = T1 CLK to Q + cdelay + Setup time2 + T2 CLK to
Q + delay of AND gate = 2 + 5 + 6 + 2 + 4 = 19 ns which is greater than Hold time of 1 st FF.
hence hold time condition is satisfied for 1st FF.

At 2nd FF K input changes after minimum delay of T = T2 CLK to Q+ delay of AND gate +
Setup time1 + T1 CLK to Q + delay (inverter) + delay (inverter) = 2 + 4 + 5 + 2 + 2 + 2 = 17
ns i.e. more than Hold time

one J input (o/p of 1st FF) changes after minimum delay of T = T2 CLK to Q+ delay of AND
gate + Setup time1 + T1 CLK to Q + delay (inverter) + delay (OR) = 2 + 4 + 5 + 2 + 2 + 4 =
19 ns i.e. more than Hold time

While other input to J through OR gate is a feed back from o/p of 2 nd FF and changes only
after time T = T2 CLK to Q + delay of AND gate = 6 ns which is less than hold time
(=8ns).

Hence there is a Hold time violation. To correct this we include a buffer gate of 2 ns
delay in the feedback as shown: with this buffer now i/p changes after 8 ns which is
equal to hold time. Hence condition satisfied.

Digital Logic Design Notes from www.exploreroots.com Page 131

Hence we can also note that HOLD time doesn’t depend upon the clock frequency
while SETUP time violation depends upon the clock frequency.

Q-Implement a MOD-8 counter using Parallel-in Parallel-out register and

Ans: We have a 3-bit register with two common inputs CLK & CLEAR for all 3 FFs. So we
initiate the counter we clear all the FFs and then give clock. Whenever count reaches 7
output of adder becomes 000 with carry 1 and carry is ignored and 000 is fed into register.
We have the circuit as:

Digital Logic Design Notes from www.exploreroots.com Page 132

TIMING CIRCUITS

INTRODUCTION

The timing circuits are the special purpose circuits which are generally used in
digital circuits. We have the following important types of timing circuits:

1. 555 Timers are used in timing circuits very often as they are more reliable and lost cost.
We have the two modes of operation of 555 Timer:

 Monostable operation
 Astable operation

2. Schmitt Trigger: This is used to sharpen up falling and rising edges of DATA signal.

Monostable operation:

In monostable operation we have only one state stable and other state unstable. We have a
input named Trigger to the 555 Timer. When we give no trigger timer stays in the stable
state but when we give trigger then timer goes to the other state for a fixed time period and
then goes back to the stable state. The stable state for 555 Timer is LOW state while HIGH
state is unstable state. Hence 555 Timer has a LOW output voltage initially. When we given
trigger then timer output voltage goes from LOW to HIGH and stays HIGH for W time delay
and then resets again.

A Multi-vibrator is 2-state circuit which has either a zero or one or two stable
states. And as in monostable operation of 555 timer we have one stable state, hence we
also call this timer as Monostable Multi-vibrator. Functional diagram of monostable multi-
vibrator is given on next page. In the diagram, as we have three 5 Kohm resistors in series
hence the circuit is called 555 Timer (Triple 5 timer). Due to this arrangement we have
2Vcc/3 voltage at node A and Vcc/3 voltage at node B.

Initially we have output equal to zero i.e. Q’= 0 & Q=1. As Q=1, transistor gets ON and
hence capacitor is discharged and hence S becomes ZERO and R is also ZERO as initial
value of Trigger is Vcc.
Digital Logic Design Notes from www.exploreroots.com Page 133
Hence in stable state

S=0 R=0 output=0 and capacitor C is discharged

When we give a trigger at the input (i.e. a LOW voltage pulse is given for small time), lower
op-amp gives 1 as voltage at –ve terminal becomes less than Vcc/3. Hence R becomes 1
and Q becomes 0 and Q’=1 and output goes HIGH. Now as Q=0, this cuts-off the transistor
and hence capacitor is allowed to charge through resistance R. When capacitor voltage
becomes greater than 2Vcc/3, output of upper op-amp becomes 1 and hence S=1, R=0
which makes Q=1 and Q’=0. And output is again reset. Hence a trigger at the input makes
output as 1 for some time W i.e. a rectangular pulse of width W is obtained.

The value of W is slightly more than the time in which capacitor is charged from 0 to
2Vcc/3. We know that in one time constant RC, capacitor is charged to 63.2% but we need
to charge capacitor to 2Vcc/3 = 66.6%. if we solve the equations then we’ll get

W= 1.1 RC

Digital Logic Design Notes from www.exploreroots.com Page 134

Astable Operation:

In Astable operation, we have no stable states. Hence we say that timer doesn’t stay in any
of the two states indefinitely i.e. vibrates between the two states. Hence we don’t need
trigger in this case. This is also called Astable Multi-vibrator. This is also called free-
running multi-vibrator. When-ever we give power to the timer, we get the rectangular
oscillating output signal.

The following diagram would explain the working of the Astable Multi-vibrator:

Working of this circuit is similar to Monostable multi-vibrator. In this circuit voltage of the
capacitance oscillates between Vcc/3 and 2 Vcc/3.

Suppose initially we have Q=0 & Q’=1. As Q is 0, transistor is turned OFF and hence
capacitor starts charging through R1 + R2. When the voltage of capacitor goes greater than
2 Vcc/3, output of upper Op-amp gets 1 and hence S=1 & R=0 and due to this Q becomes
HIGH and Q’ goes LOW.

Now as we have Q=1 & Q’=0. As Q is 1, transistor is turned ON and hence capacitor starts
discharging through R2. When the voltage of capacitor becomes less than Vcc/3, output of
lower Op-amp gets 1 and hence S=0 & R=1 and due to this Q becomes LOW and Q’ goes
HIGH.

Now again we have Q=0 & Q’=1 and whole procedure is repeated. Hence we get the
oscillating output as illustrated follow:

Digital Logic Design Notes from www.exploreroots.com Page 135

In the figure above W is equal to the time in which capacitor is charged to 2 Vcc/3 from
Vcc/3 and P is equal to the time in which capacitor is discharged from 2Vcc/3 to Vcc/3.
Hence

W= 0.693 (R1+R2) C

P= 0.693 R2 C

So the time period of output is T= 0.693 (R1+2 R2) C

We can vary the duty cycle of output pulse by changing the value of R1 & R2 and duty
cycle is defined as

And frequency of the timer is F= 1/T = 1.44/ (R1+2 R2) C

SCHMITT TRIGGER

As we have generally slow changing DATA signals i.e. DATA signals have slow rising and
falling edges. And use of these signals creates problems in the working of Digital circuits.
Hence to avoid these problems we use SCHMITT TRIGGER to sharpen up the edges of
DATA. The transfer characteristics of this trigger are as follow:

We have only 2 output voltage levels Vo- & Vo+ and there are 2 input voltage thresholds
V1 & V2. the SCHMITT TRIGGER follows the above characteristics i.e. when ever input
voltage is increased from 0, we have the output voltage as Vo- and output remains the
same till input voltage is less than V2. Hence when ever there is an increase in the input
voltage, transition would occur only when input voltage becomes greater than V2.

Digital Logic Design Notes from www.exploreroots.com Page 136

When-ever input voltage is decreased from the high value (>V2), we have the output as
Vo+ and the output remains the same until input voltage becomes less than V1.

Hence behavior of SCHMITT TRIGGER depends on whether input is increasing or

decreasing and trigger is said to give hysteresis of V2 – V1. This is used to eliminate the
effect of noise on the signal. We illustrate this fact using the following example.

Suppose we have the following signal with superimposed noise and we take two cases:
with small hysteresis V2 – V1+ and with large hysteresis V2 – V1— and notice the effect of
SCHMITT TRIGGER

Small hysteresis V2 – V1+: As voltage is less than V1+, hence initial output is Vo-. When the
voltage increases to greater than V2, output jumps suddenly from Vo- to Vo+. Now output
voltage remains same till input voltage drops below V1+. When voltage drops below V1+, we
get the output as Vo-. After some time input voltage again increases beyond V2 and hence
output again jumps to Vo+.

Large hysteresis V2 – V1--: As voltage is less than V1- , hence initial output is Vo-. When the
voltage increases to greater than V2, output jumps suddenly from Vo- to Vo+. Now output
voltage remains same till input voltage drops below V1+. When voltage drops below V1+, we
get the output as Vo-.

Digital Logic Design Notes from www.exploreroots.com Page 137

And we can see that we get a clean square wave for large hysteresis while for small
hysteresis we get many transitions in the output but it is still better than the output without
using SCHMITT TRIGGER.