EEE 51 Exam 1

Electrical and Electronics Engineering Institute

University of the Philippines Diliman
2nd Semester SY 2017 - 2018
Saturday, March 24, 2018 1PM - 4PM
L. Alarcón, M. T. de Leon, R. J. Maestro, C. Santos

Instructions: THINK before you answer. Your score will be based solely on what you have written. Write legibly and avoid
erasures. Anything we cannot understand will be marked wrong. You may use the back of the exam sheets as extra scratch
space, but your final answer, with the correct units, should be placed in the designated areas. DO NOT separate the exam
sheets. All parts (I, II, III, and IV) carry the same weight.

Name:

Student No.:

Encircle one:
Alarcón: THQ (7:00am-8:30am)
de Leon: THR (8:30am-10:00am)
Section: Santos: THU (10:00am-11:30am)
de Leon: THX (2:30pm-4:00pm)
Maestro: WFX (2:30pm-4:00pm)

Scores: Part I:

Part II:

Part III:

Part IV:

Total:

1
Part I:
(12 points) You are tasked to setup the quiescent operating point of all the transistors in the cascoded differential amplifier
below. The transistors are identical, with IS = 5 fA, ! 1, |VA | ! 1, and VCE,sat = 0.2 V. The supply voltage, VCC , is
5 V, and you need to make sure that the collector current of transistor Q5 is 2 mA at a temperature of 300 K. From your
2
trusty notes, you see that the charge of an electron is 1.602 ⇥ 10 19 C, and Boltzmann’s constant is 1.381 ⇥ 10 23 kg ms2 K1
.

VCC VCC

R R

VO VO

VB Q3 Q4 VB

VI Q1 Q2 VI

VC Q5

1. Determine the DC bias voltage VC . (2 points)

VC =

2. Your required output common-mode voltage is half the supply voltage. What is the value of the resistor, R? (2 points)

R=

2
3. You want to get the largest possible symmetric differential output swing from the cascoded differential amplifier, given
that the output common-mode voltage is half the supply voltage. What values would you choose for the DC bias
voltage at the input, VI , and the cascode bias, VB ? (5 points)

VI = VB =

3
4. Instead of trying to maximize output swing, you want to maximize input common-mode range instead. What DC
voltage would you use for VB ? Note that you are still required to maintain the output common-mode voltage at half
the supply voltage. (3 points)

VB =

4
 \ ltl Student f rSectior,

Part II:
Consider the amplifier belorr and the rable oI DC parameters. Assunle tlrat the \.oltage supplf is 3.3[. 8: 1.84Q and
that the circuit is operating at room ternperaturc. (20 points)

\I2 Nr

R LoLT
\ l,l
r)^.-j

\I1 \I3 \i6

+
1i
_\ lt2 t/3 _\ 1l ,\15 it6
0.025r.,, 0.0251/- ' 0.01y-r 0.011.' ' 0.2v-L 0.05y-t
lI ol lmA lr){ lmA 3'rr I ',lrttA J,7rrl
lYcs I r.5 L/ 1 .51', 23V 2.31.' 1.51/ 1.51-
lvos) 1.5li lt' 1.ri5l./ 0.85I', 0.8v
ll{r,l 0.8I. 0.8t,' 1.551,' 1.55I', 0.81/- 0.8,l/

Table 1: Tlansistor Parameters

1. Determine the expression and actual values of the small signal resistances seen by drain terminal and by the source
terminal of trarsistor llt5. (5 points)

r4F1
uf'l i
hr\t52 ftL

1
qrv{rt9r1 f&t
I
.ryr. Yo
,t trD -)
tl
r Pl 4 r:u"
EJ

(ot
r'1tI 4"15,"
/Du J
lt jn
rv{ ft'^
u. Snll' ty! v*,}ho4"t d) a,q,t ll..rti1 Nlpq
yilt V.

Rokrp): l U1 RsQtp\: nb

Rp(ualue): Rs(ualue): r,uKtv

b! ooLi' ls
 2. Ljsing vour ans\rrs iD #1. dras the simplified smal) signal circuil of the anrplifier. Lise smail-signal paraneters
as labels for thc c.oulporents. No need to compute for the actu:rl r.alues. p pointsJ

rD{
t,r^ a-- thpl
+
t5ri ft<

l-ut,

3. Derive an expression and compute for the actual value for the Gr,r of the circ:rtit. (l poi.nts)

tr 1,,^l
r
Y};
\, I
b"5'(
I fuu

rLor^ .' iul AtS

il"+- $r{5,. lt ,
1tt lrfusrwt4
O( fti'
1,t - i,5t fll) , ll,^-Nqrt
l*- '#
I

dqsr- !.r - frJrar . g.e rS

0"t' v [lt*+r* - inl ry nr= -
ilnt(t * t5l
{n^s
rD( l'r t.w Lo

{,rnn ' H) T,h I

: 1"( I

Gy (ezpression)
ttfi>rrw tfl
Gy (ualue\ :
0,lrg rS

l)
 l. Derite iin e\pression all.l conrpute for thc actull ralue for tlr<'/l1r of tltc cir.cuit. // p,rrrrls/

Ur,*
(
I 1,M .t4 ie/ Barx,

I
{-ryl:( tuu
0.s1/b(
Lt/U,l
\.
rtu {i.5tqs(b+ 4trt-ut
FT
r,tr= -ufi = lA*uW,
l*r"t. -T(ipru\ + ly tt*dw
p{ n2Y
lu"t ( t+
h tlw t o( nL
'ry {
W
i4,t,l
nr( tt grr n, t 6,\ nnJ

Rs(e:rpressiort) : W ot I r1,r ,att ftr'f-n, // 'w

ll
#) la..t"t , lLr. o" Ls.
:
Rs(ualue)
2s fi lrJL
5. Derive an expression aDd compute for the actual value for the,,1l,. of the circuit. (l points)

ftu" ' 6, P,,

(
n1/ rc|r,7**r#)
('a" rr\ r2l,b
nr )
r( N4 n{

fi + flrfl'?'orwt w
)

4r,r nfl Nr
Ay(etpression): --v -
rrt
tW r m/ l+ln tu I
W,/
:
Ay (uaLue)
- 1,"(.9
Part III:
In the PMOS differential amplifier circuit below, VDD = 3 V , I1 = 2 mA, and C → ∞. Note also that M1 and M2 are
matched, with VT H,P = −1 V, k = 4 mA
V2 , and λ → 0. (20 points total)

VDD

1 MΩ

I1

vI1 M1 M2 vI2
C
10 kΩ
vO1 vO2

R R

1. If VI1 = VI2 = 1 V , what value of R will result in maximum output swing? (8 points)

R=

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2. If VI1 = VI2 = 1 V and R = 1 kΩ, draw the differential-mode half circuit below and determine the differential-mode
gain. (7 points)

ADM =

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3. If VI1 = VI2 = 1 V and R = 1 kΩ, draw the common-mode half circuit below and determine the common-mode
gain. (7 points)

ACM =

10

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 Narlel Student #: Sectiou:

Palt IV:
The compound BJT amplifier shorvn belorr is to be constructed s'ith .E; : 100Q aad l/cc :5V usiug transistors vith
E: 100 and IA -+ oo. The alnplifler is operated at room temperaturc ard the iDput DC bias yoltage is sel. such that i)
the output DC roltage is at half of the supplf,. ii) the collector current of the 8r is 100x larger than the base current of
Q2, and iii) the base-emitter voltage of Q2 b 0.7V. (20 po.ints total)

Stage 1 Stoge 2

5l' 5t'

r?1

Q2
uourt
tou12
Q1

nL

1. What is the DC collector current of Q2? (2 points)

cz /z
,l
tez= jru = ----:-
t(L
too 2.9V
LLz ' -L
p LezI tot tboJz

t",: 4.4.7d2
^A
2. What should be the value of .R1 such that the conditioDs mentioned arc IJj.et? (2 poi.nts)

Slt ' acr - lgz ltr : rlcc - tJS?z - V a.s'e-

-- loo \2 + fD> - - {*z

'lcc / z
z [o\ IB2-
eI i jg z---..--------_
v<< /z - rlcez
T€r tor (tc:' / p\
- +2.OAt38 rz
Rr= Ta rz
11
3. \\'hat is lhc DC roltage at the collector of Q7'? (1 poht)

Vc1 ls*tr = lwz * Votrrz

= 0. it/ * 2.9v

l'c:t: i. al/

4. The compound anplifier is to be analyzed in the small-signal domain as a cascade of tn'o thevenin equi\,alent two-
port networks with the division of stages as identified in the schematic. Provide the expression for the small-signal
ouput resistance of the first stage to complete the table of tu,o-port parameters. Draw the small signal circuit to
be analyzed in the derivation. (3 points)

Bs
do,rr
lo.r.t
?o,*< - <- oi-O f-'a&
l,Ov,
+
f lrr tbcr floPbot

o
.ti , Y&t' o
1)ol'.t
\(ou : ra,d,
(,- */

O.,i

i c*.
Rr

Parameter Expression for Stage I

Rt tu

Av -9mrRr

Rour Rr

12
 5. Provide the expressions for the small siglal voltage gain aud iDput resistance of the second stage to complete
table of tn'o port parameters. Draq'the snrall signal circuits to be analyzed iu the deriration. Use the alternate
method for deriving the input inrpedalce for bilateral cic[its. (10 poitlts)

.
B 14-'-
1ri4
en ,"*d *
o-rpd l.l
*v .l*. o7+'
-r;4 lia in poa
ryu
Xfo4@ * ro -+Q
g +
(t, ltcr- t' fr:- 1E>
?ii $nz1bc 'lia 1^"uwo
no,^1 4)c,tX

RL L i.. (- { Jr.-

rnuf = tr1. &..

ltlr(,z -- iin rrz
=('=, 6^n*,)- 4
(ra! : Oin * g,rrr lbe3
= rh (t +X,,.,.,/r:) (w)/.\ -t- .
4,: r",,).a_
,
'c1a(r+ ()
Kt)L:4 .^ '- lllk,.?- + ?out 9n '*)( ''39-) a
-' L;4ru* 'U o*t . (a. - zr,rr)6 O*il
;"rO ru-\
afz /
vi" = ,L k1r+ (t+p)n \ ** (ffia
1rr'
t Pr^, , rn, + (,+7)4 "') = Vt'4

Ye*f q2 + (tp)4 \ r)a

f'l ,
\ cep)a )
na6 ( ) P,_

ry> + (t+PP-
Parameter Expression for Stage 2
fuf.
6
Rr,v .", * (,*f)Q * 6a- 4
Ftt
(r+ )A
Av
o. * (rf)Ru

l3
6. Using the tables from the last 2 nunbers. rvrite the expressiol for the overall small signal voltage gail Av,ror:
uoun/rtN in terms of the resistalces and transistor small signal paraneters- The expression should be
written ir a u'ay such that the propagation of the voltagei froru input to output should be the obvious. (2 points)

-2- - I
I
Ro,r1 PprE- I

t +
+
+l +
I
hz'b I rl v*l z
.tri
I fur')i, I
( ;fi tlz 1t
-l

: ( r<2,- + ( Ct ,+
Av,t'or
fo,R' +hz+( (
'74

ll