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http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188


CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
MLB B - PVT B 0003279770 PRODUCTION RELEASED 2014-09-29

LAST_MODIFIED=Mon Sep 29 18:09:18 2014


RADIO_MLB SYNC VER 0.109.0
WIFI_DEV SYNC VER 0.68.0
ROTTERDAM SYNC VER 0.11.0
D D
PDF CSA CONTENTS
TABLE_TABLEOFCONTENTS_HEAD
SYNC MASTER DATE PDF CSA CONTENTS
TABLE_TABLEOFCONTENTS_HEAD
SYNC MASTER DATE PDF CSA CONTENTS
TABLE_TABLEOFCONTENTS_HEAD
SYNC MASTER DATE

1
TABLE_TABLEOFCONTENTS_ITEM
1 TABLE OF CONTENTS N/A N/A 26
TABLE_TABLEOFCONTENTS_ITEM
36 IO: FILTERS N/A N/A 51
TABLE_TABLEOFCONTENTS_ITEM
66 CELL: HB SWITCH RADIO 09/29/2014

2
TABLE_TABLEOFCONTENTS_ITEM
2 BLOCK DIAGRAM: SYSTEM N/A N/A 27
TABLE_TABLEOFCONTENTS_ITEM
37 IO: HOTBAR PADS N/C N/A 52
TABLE_TABLEOFCONTENTS_ITEM
67 CELL: RX DIV (1/2) RADIO 09/29/2014

3 4 BOM TABLES N/A N/A 28 39 IO: BUTTON FLEX CONN N/A N/A 53 68 CELL: RX DIV (2/2) RADIO 09/29/2014

m
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

4
TABLE_TABLEOFCONTENTS_ITEM
5 SOC: MISC & ALIASES N/A N/A 29
TABLE_TABLEOFCONTENTS_ITEM
40 GRAPE: STINGER & CONN N/A N/A 54
TABLE_TABLEOFCONTENTS_ITEM
69 CELL: GPS RADIO 09/29/2014

5
TABLE_TABLEOFCONTENTS_ITEM
6 SOC: MAIN N/A N/A 30
TABLE_TABLEOFCONTENTS_ITEM
41 GRAPE: CUMULUS N/A N/A 55
TABLE_TABLEOFCONTENTS_ITEM
70 CELL: ANT FEEDS & GPS (J82) RADIO 09/29/2014

o
6
TABLE_TABLEOFCONTENTS_ITEM
7 SOC: I/OS N/A N/A 31
TABLE_TABLEOFCONTENTS_ITEM
45 DISPLAY: CONNECTOR N/A N/A 56
TABLE_TABLEOFCONTENTS_ITEM
74 WIFI/BT: J82 ANT INTERFACE WIFI 09/29/2014

7 8 SOC: NAND N/A N/A 32 46 DISPLAY: EDP SUPPORT N/A N/A 57 75 WIFI/BT: WIFI/BT MODULE WIFI 09/29/2014

.c
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

8
TABLE_TABLEOFCONTENTS_ITEM
9 SOC: MIPI, ISP N/A N/A 33
TABLE_TABLEOFCONTENTS_ITEM
47 MESA: SUPPORT N/A N/A 58
TABLE_TABLEOFCONTENTS_ITEM
78 SENSOR: HAMMERHEAD N/A N/A

9 10 SOC: EDP, PCIE N/A N/A 34 48 ROTTERDAM ROTTERDAM 05/13/2014 59 79 CELL: SIM AND ANT SW FILT N/A N/A
C
TABLE_TABLEOFCONTENTS_ITEM

10 11 SOC: DDR N/A


TABLE_TABLEOFCONTENTS_ITEM

35 50 CELL: PROBE PTS & DEBUG CONN RADIO


TABLE_TABLEOFCONTENTS_ITEM

60 81 PMU: ARABELA (1/3) N/A


C

x
N/A 09/29/2014 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

11
TABLE_TABLEOFCONTENTS_ITEM
12 SOC: IO POWER N/A N/A 36
TABLE_TABLEOFCONTENTS_ITEM
51 CELL: BB PMU (1/2) RADIO 09/29/2014 61
TABLE_TABLEOFCONTENTS_ITEM
82 PMU: ARABELA (2/3) N/A N/A

fi
12 13 SOC: SOC POWER AND GND N/A N/A 37 52 CELL: BB PMU (2/2) RADIO 09/29/2014 62 83 PMU: ARABELA (3/3) N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

13
TABLE_TABLEOFCONTENTS_ITEM
14 SOC: CPU, GPU, SRAM POWER N/A N/A 38
TABLE_TABLEOFCONTENTS_ITEM
53 CELL: BASEBAND (1/2) RADIO 09/29/2014 63
TABLE_TABLEOFCONTENTS_ITEM
84 POWER: J82 SPECIFIC N/A N/A

14 39 64

a
16 DDR: CHANNEL 0 AND 1 N/A N/A 54 CELL: BASEBAND (2/2) RADIO 09/29/2014 86 POWER: EXTERNAL SWITCHES N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

15 17 DDR: CHANNEL 2 AND 3 N/A N/A 40 55 CELL: BASEBAND (3/3) RADIO 09/29/2014 65 88 PMU: CHARGER BUCK N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

in
16
TABLE_TABLEOFCONTENTS_ITEM
18 NAND N/A N/A 41
TABLE_TABLEOFCONTENTS_ITEM
56 CELL: RF TXCVR (1/3) RADIO 09/29/2014 66
TABLE_TABLEOFCONTENTS_ITEM
89 POWER: BATTERY CONN N/A N/A

17
TABLE_TABLEOFCONTENTS_ITEM
20 SENSOR: OSCAR N/A N/A 42
TABLE_TABLEOFCONTENTS_ITEM
57 CELL: RF TXCVR (2/3) RADIO 09/29/2014 67
TABLE_TABLEOFCONTENTS_ITEM
90 SOC: DEBUG N/A N/A

18 21 SENSOR: CARBON, PHOS+, MAGN N/A N/A 43 58 CELL: RF TXCVR (3/3) RADIO 09/29/2014 68 91 ALIASES: BB/WLAN/BT N/A N/A

h
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

19
TABLE_TABLEOFCONTENTS_ITEM
22 SENSOR: HALL EFFECT N/A N/A 44
TABLE_TABLEOFCONTENTS_ITEM
59 CELL: QFE DCDC RADIO 09/29/2014 69
TABLE_TABLEOFCONTENTS_ITEM
93 TEST: TPS/HOLES/FIDUCUALS N/A N/A

B 20 27 CAMERA: CAM CONNS N/A 45 60 CELL: 2G PA RADIO 70 95 TEST: EE TP/PP N/A


B

.c
N/A 09/29/2014 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

21
TABLE_TABLEOFCONTENTS_ITEM
28 CAMERA: CAM SUPPORT N/A N/A 46
TABLE_TABLEOFCONTENTS_ITEM
61 CELL: VLB PAD RADIO 09/29/2014 71
TABLE_TABLEOFCONTENTS_ITEM
96 TEST: CELL EE TP/PP N/A N/A

22
TABLE_TABLEOFCONTENTS_ITEM
30 AUDIO: L81 CODEC N/A N/A 47
TABLE_TABLEOFCONTENTS_ITEM
62 CELL: LB PAD RADIO 09/29/2014 72
TABLE_TABLEOFCONTENTS_ITEM
121 POWER: ALIASES N/A N/A
w
23
TABLE_TABLEOFCONTENTS_ITEM
31 AUDIO: HP/DMIC FLEX CONNS N/A N/A 48
TABLE_TABLEOFCONTENTS_ITEM
63 CELL: MB PAD RADIO 09/29/2014 73
TABLE_TABLEOFCONTENTS_ITEM
155 BB/WLAN VOLTAGE ATTRIBUTES N/A N/A

24
TABLE_TABLEOFCONTENTS_ITEM
32 AUDIO: SPEAKER AMPS N/A N/A 49
TABLE_TABLEOFCONTENTS_ITEM
64 CELL: HB PAD RADIO 09/29/2014
w

25
TABLE_TABLEOFCONTENTS_ITEM
35 IO: TRISTAR N/A N/A 50
TABLE_TABLEOFCONTENTS_ITEM
65 CELL: ANTENNA SWITCH RADIO 09/29/2014
w

A A
DRAWING TITLE
SCHEM,MLB-B,X190
DRAWING NUMBER SIZE

Apple Inc. 051-0301 D


SCH AND BOARD P/N R
REVISION

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_HEAD

B.0.0
TABLE_5_ITEM
NOTICE OF PROPRIETARY PROPERTY: BRANCH
DRAWING
051-0301 1 SCH,MLB-B,J82 SCH1 CRITICAL THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
TABLE_5_ITEM

THE POSESSOR AGREES TO THE FOLLOWING: PAGE


820-3633 1 PCBF,MLB-B,J82 PCB1 CRITICAL I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 1 OF 155
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SHEET
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REAR CAMERA ISP0
ISP0_I2C
MIPI0C CSA 27
SPI3
COMPASS PHOSPHOROUS+ GRYO ACCEL
CSA 21 SPI CSA 21 SPI CSA 21 SPI CSA 21 SPI ISP1 FRONT CAMERA
D ISP1_I2C
CSA 27
D
PROX SENSOR MIPI1C

CSA 78 I2C
I2S4 BT MIMO
UART3 WIFI/BT WIFI/BT ANT
TEMP SENSOR
CSA 78 I2C PCIE1 WLAN
UART2 CSA WIFI/BT ANT
HELIUM COEX

m
CSA 78 I2C
CAPRI

OSCAR
NOT ON

SPI (M)
I2C
CELLULAR/

o
GRAPE CSA 41
GPS WIFI-ONLY CONFIG
OSCAR
CSA 20 COEX

.c
PRIMARY CELLULAR ANT
CUMULUS CUMULUS I2C UART
UART8 HSIC0 HSIC DIVERSITY CELLULAR ANT
UART
GPIO IPC
C UART
UART1 UART
GPS ANT C

x
STINGER BASEBAND
USB SIM CARD
CSA 40 I2C

fi
TRISTAR
CSA 35

a
USB1
DISPLAY/ UART2

in
ALS (MIC)
TOUCH PANEL I2C
I2C0 I2C
I2C MESA ALS (AJ)
I2C2 USB2.0 USB0
SPI I2C UART0 UART1

h
UART6 UART0
SPI2 JTAG
I2C1 JTAG
B B
BACKLIGHT
EDP
.c
LPDP SPI1
I2S0
I2S1
SPI
ASP
XSP
MBUS

HP
DIG
w
L81 MIC1
AUDIO CODEC
w

CSA 30 MIC2
RIGHT
BMU AMP
PMU SPEAKER
w

CSA 33
ARABELA BATTERY IO FLEX
CSA 81-83
NC -- DWI1 I2S3
AMP LEFT
HDQ CSA 32
SPEAKER
IRQ UART5 (HDQ) IO FLEX
DWI DWI0
A I2C I2C0 SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

GPIO GPIO
DDR0 DDR1 DDR2 DDR3 FMI0 FMI1 BLOCK DIAGRAM: SYSTEM
DRAWING NUMBER SIZE

Apple Inc. 051-0301 D


REVISION
R
B.0.0
HALL EFF 1 HALL EFF 2 BUTTON FLEX NOTICE OF PROPRIETARY PROPERTY: BRANCH

CSA 22 IO FLEX
CSA 39
NAND FLASH LPDDR3 LPDDR3 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 2 OF 155
http://www.xinxunwei.com TEL:0755-61506416
CSA 16 CSA 17 CSA 18 QQ:1727176051 981775188 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SHEET
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SOC 981775188 TABLE_5_HEAD

Page Notes PART#

343S00016
QTY

1
DESCRIPTION

IC,CAPRI,A1,PROD,ASE
REFERENCE DESIGNATOR(S)

U0600
CRITICAL

CRITICAL
BOM OPTION
TABLE_5_ITEM

Power aliases required by this page:


(NONE) TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


PART NUMBER
Signal aliases required by this page: TABLE_ALT_ITEM

(NONE) 343S00021 343S00016 U0600 IC,CAPRI,A1,PROD,SCK

BOM options provided by this page:

D D
PMU TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_ITEM

343S0675 1 IC,PMU,ARABELA,D2207A0,TOP-AC,FCBGA380 U8100 CRITICAL

SDRAM

m
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_ITEM

333S0803 2 IC,CAPRI,DRAM,10X10MM,FBGA261 U1600,U1700 CRITICAL

TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

o
PART NUMBER
TABLE_ALT_ITEM

333S0804 333S0803 U1600,U1700 ELPIDA DRAM


TABLE_ALT_ITEM

333S00014 333S0803 U1600,U1700 SAMSUNG DRAM

.c
NAND C
C 16GB FLASH CONFIGURATIONS

x
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_ITEM

335S0972 1 TOSHIBA 16GB MLC 1YNM PPN1.5 U1800 CRITICAL 16GB_PROD

fi
TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


PART NUMBER
TABLE_ALT_ITEM

335S1035 335S0972 16GB_PROD U1800 HYNIX 16GB MLC 1YNM PPN1.5

a
64GB FLASH CONFIGURATIONS TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_ITEM

in
335S00011 1 SANDISK 64GB TLC 1YNM PPN1.5 U1800 CRITICAL 64GB_PROD

TABLE_ALT_HEAD

MECHANICAL PARTS PART NUMBER ALTERNATE FOR


PART NUMBER
BOM OPTION REF DES COMMENTS:
TABLE_5_HEAD

TABLE_ALT_ITEM

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 335S00017 335S00011 64GB_PROD U1800 TOSHIBA 64GB TLC 1YNM PPN
TABLE_5_ITEM

806-7118 1 RADIO FENCE X190 PD_FENCE_RADIO CRITICAL MLB_B


TABLE_5_ITEM

h
806-00001 1 AP FENCE X190 PD_FENCE_AP CRITICAL
TABLE_5_ITEM 128GB FLASH CONFIGURATIONS
806-6353 1 GRAPE FENCE X190 PD_FENCE_GRAPE CRITICAL TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_ITEM

335S00012 1 SANDISK 128GB TLC 1YNM PPN1.5 U1800 CRITICAL 128GB_PROD


B B
BARCODE LABEL/EEEE CODES
PART#

825-00067
QTY

1
DESCRIPTION REFERENCE DESIGNATOR(S)

EEEE_FQJ3
CRITICAL

CRITICAL
BOM OPTION

EEEE_MLB_A_16GB
TABLE_5_HEAD

TABLE_5_ITEM
.c PART NUMBER

335S00018
ALTERNATE FOR
PART NUMBER

335S00012
BOM OPTION

128GB_PROD
REF DES

U1800
COMMENTS:
TABLE_ALT_HEAD

TABLE_ALT_ITEM

TOSHIBA 128GB TLC 1YNM PPN


w
EEEE FOR 639-5813 (MLB A 16GB)
TABLE_5_ITEM

825-00067 1 EEEE FOR 639-5814 (MLB A 32GB) EEEE_FQJ0 CRITICAL EEEE_MLB_A_32GB


TABLE_5_ITEM

825-00067 1 EEEE FOR 639-5815 (MLB A 64GB) EEEE_FQJ1 CRITICAL EEEE_MLB_A_64GB


TABLE_5_ITEM

825-00067 1 EEEE FOR 639-5816 (MLB A 128GB) EEEE_FQJ2 CRITICAL EEEE_MLB_A_128GB


w

TABLE_5_ITEM

825-00067 1 EEEE FOR 639-4747 (MLB B 16GB) EEEE_FH54 CRITICAL EEEE_MLB_B_16GB


TABLE_5_ITEM

825-00067 1 EEEE FOR 639-5809 (MLB B 32GB) EEEE_FQHY CRITICAL EEEE_MLB_B_32GB


TABLE_5_ITEM

825-00067 1 EEEE FOR 639-5810 (MLB B 64GB) EEEE_FQHW CRITICAL EEEE_MLB_B_64GB


TABLE_5_ITEM
w

825-00067 1 EEEE FOR 639-5811 (MLB B 128GB) EEEE_FQHV CRITICAL EEEE_MLB_B_128GB

A CKPLUS WAIVE TABLE SYNC_MASTER=N/A SYNC_DATE=N/A A


TABLE_DASHBOARD_INFO PAGE TITLE
CKPLUS RULE EXCEPTIONS REQUIRED
BOM TABLES
SCHEMATIC DEFINED CONSTRAINTS (YES/NO) NO DRAWING NUMBER SIZE

Apple Inc. 051-0301 D


REVISION
R
B.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 4 OF 155
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SHEET
3 OF 73
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BOOT CONFIG ID
72 62 6 5 4 =PP1V8_SOC
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 1
R0510
240 2 JTAG_SOC_SEL OUT 5 69
MASTER: SOC
70 6 IN I2C0_SCL_1V8 MAKE_BASE=TRUE =I2C_SOC2PMU_SCL_1V8 OUT 62

1% =I2C_SOC2TRISTAR_SCL_1V8 OUT 25
TO:
1NOSTUFF 1NOSTUFF 1 1 NOSTUFF
1/32W ARABELA ADDR: 0B0111100X
R0500 R0501 R0502 R0503 MF 70 6 BI I2C0_SDA_1V8 MAKE_BASE=TRUE =I2C_SOC2PMU_SDA_1V8 BI 62 TRISTAR ADDR: 0B0011010X
01005
1.00K 1.00K 1.00K 1.00K =I2C_SOC2TRISTAR_SDA_1V8 BI 25
5% 5% 5% 5%
1/32W 1/32W 1/32W 1/32W
MF MF MF MF
2 01005 2 01005 2 01005 2 01005 NOSTUFF 70 6 I2C1_SCL_1V8 MAKE_BASE=TRUE =I2C_SOC2MESA_SCL_1V8 33
IN OUT
GPIO_BOOT_CFG3 R0550 =I2C_SOC2SPKRAMP_SCL_1V8
6 OUT 240 OUT 24
TO:
MESA EEPROM (MEM) ADDR: 0B1010000X
6 GPIO_BOOT_CFG2 1 2 TP_JTAG_SOC_TRST_L 5 69 I2C1_SDA_1V8 MAKE_BASE=TRUE =I2C_SOC2MESA_SDA_1V8
D 6
OUT
OUT GPIO_BOOT_CFG1 1%
1/32W
OUT 70 6 BI
=I2C_SOC2SPKRAMP_SDA_1V8
BI
BI
33

24
MESA EEPROM (ID) ADDR: 0B1011000X
SPEAKER AMP LEFT ADDR: 0B0110001X
SPEAKER AMP RIGHT ADDR: 0B0110100X D
6 OUT GPIO_BOOT_CFG0 MF
01005

70 6 IN I2C2_SCL_1V8 MAKE_BASE=TRUE =I2C_HP_ALS_SCL_1V8 OUT 23

R0560 =I2C_MIC_ALS_SCL_1V8 OUT 23 TO:


ALS(MIC) ADDR: 0B0101001X
240 ALS(HP) ADDR: 0B1001001X
BOOT_CFG[3:0] MODE S/W READ FLOW
1 2 SOC_TESTMODE OUT 5 69

1% 70 6 BI I2C2_SDA_1V8 MAKE_BASE=TRUE =I2C_HP_ALS_SDA_1V8 BI 23


0000 SPI 1/32W
1. SET GPIO AS INPUT MF =I2C_MIC_ALS_SDA_1V8 23
01005 BI
0001 SPI W/TEST 2. DISABLE PU AND ENABLE PD
CURRENT SETTING ---> 0010 NAND 3. READ SOC_FAST_SCAN_CLK 5
OUT
MAKE_BASE=TRUE
0011 NAND W/TEST
SOC_HOLD_RESET OUT 5
I2C3_SCL_1V8 MAKE_BASE=TRUE =I2C3_SCL_1V8

m
6 IN OUT 70
TO:
PROBE POINTS
SEG: CAN CONNECT TO GROUND. DO NOT FLOAT.
6 BI I2C3_SDA_1V8 MAKE_BASE=TRUE =I2C3_SDA_1V8 BI 70
PPVDD12_UH1_HSIC1 OUT 5

EFUSE SHOULD BE TIED TO GROUND PER SEG


PPVDD18_EFUSE1 OUT 11

o
BOARD ID
72 62 6 5 4 =PP1V8_SOC

.c
1NOSTUFF 1 MLB_A 1 1DEV
R0504 R0505 R0506 R0507
1.00K 1.00K 1.00K 1.00K
5% 5% 5% 5%
1/32W 1/32W 1/32W 1/32W
MF MF MF MF 70 69 68 62 25 10 5 IN RESET_SOC_L MAKE_BASE=TRUE CFSB_SOC OUT 5
2 01005 2 01005 2 01005 2 01005
GPIO_BRD_ID3 CFSB1_SOC
C 6

6
OUT

OUT GPIO_BRD_ID2
OUT 5
C

x
6 OUT GPIO_BRD_ID1
6 OUT GPIO_BRD_ID0

fi
BRD_ID[3-0] S/W READ FLOW R0530
0.00 2
0000 RESERVED 1. SET GPIO AS INPUT 5 IN WDOG_SOC 1 WDOG_SOC2PMU_RESET_IN OUT 62

0%
0001 RESERVED 2. DISABLE PU AND ENABLE PD 1/32W
0010 MLB_B AP 3. READ MF
01005
RDAR://PROBLEM/15529479
0011 MLB_B DEV

a
0100 RESERVED
0101 RESERVED
0110 MLB_A AP
RDAR://PROBLEM/15529479
0111 MLB_A DEV

in
1000 UNUSED
1001 UNUSED
1010 UNUSED
1011 UNUSED
1100 RESERVED
1101 RESERVED

h
B BOARD REVISION B
9

9
OUT
OUT
OUT
OUT
GPIO_BRD_REV0
GPIO_BRD_REV1
GPIO_BRD_REV2
GPIO_BRD_REV3
.c
w
NOSTUFF NOSTUFF NOSTUFF
1
R0523 1R0522 1R0521 1R0520
1.00K 1.00K 1.00K 1.00K
5% 5% 5% 5%
1/32W 1/32W 1/32W 1/32W
MF MF MF MF
2 01005 2 01005 2 01005 2 01005
w

BRD_REV[3-0]

0000 RESERVED
w

0001 RESERVED
S/W READ FLOW
0010 PROTO 1 (BRING UP)
0011 PROTO 1 (LOCAL/CHINA) 1. SET GPIO AS INPUT
0100 PROTO 2 2. ENABLE PU AND DISABLE PD
0101 PRE-EVT 3. READ
0110 EVT
CURRENT SETTING ---> 0111 DVT & PVT
1000 UNUSED

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SOC: MISC & ALIASES


DRAWING NUMBER SIZE

Apple Inc. 051-0301 D


REVISION
R
B.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 5 OF 155
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SHEET
4 OF 73
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ON IN HIBERNATE
VDD1, VDD2, VDDIOD_DDRXCA (VDDCA), VDD12_CKE_DDR0, VDD12_CKE_DDR1

D D
=PP0V95_USB_SOC 72
1 C0630 1 C0631 1 C0632
0.01UF 0.22UF 100PF
10% 20% 5%
PPVDD12_UH1_HSIC1 6.3V 6.3V 16V
4 2 X5R 2 X5R 2 NP0-C0G
01005 01005-1 01005

72 =PP1V2_HSIC_SOC
1 C0610 1 C0611 1 C0612 =PP3V3_USB_SOC 72
1 C0615 1 C0620
0.22UF 0.22UF 0.22UF 0.01UF 100PF
20%
6.3V
20%
6.3V
20%
6.3V 10% 5%
1 C0640 1 C0645 1 C0641
0.01UF 0.22UF 100PF

m
2 X5R 2 X5R 2 X5R 6.3V 16V
2 X5R 2 NP0-C0G 10% 20% 5%
01005-1 01005-1 01005-1 01005 01005 2 6.3V
X5R 2 6.3V
X5R 2 16V
NP0-C0G
01005 01005-1 01005

VDD12_UH1_HSIC1 AM33
SEG: CAN CONNECT TO GROUND. DO NOT FLOAT.

VDD12_UH0_HSIC0 H24

VDDH_USB F23

VDD095_USB J25
VDD33_USB H25
CKPLUS_WAIVE=PWRTERM2GND

o
.c
20MA
U0600

5MA
TMKP88A0-N
FCBGA
13MA
EACH SYM 4 OF 15
OMIT_TABLE

C 71 68

71 68
BI
BI
HSIC_BB_DATA
HSIC_BB_STB
D25
E25
UH1_HSIC0_DATA
UH1_HSIC0_STB
C

x
NC_HSIC1_DATA NO_TEST=TRUE AV38 UH2_HSIC1_DATA
72 62 6 5 4 =PP1V8_SOC ANALOGMUXOUT G35 TP_ANALOGMUXOUT 70
NC_HSIC1_STB NO_TEST=TRUE AU38 UH2_HSIC1_STB
1 1 1 USB_DP B26 USB_SOC_P BI 25 69
R0610 R0611 R0612

fi
JTAG_SOC_SEL U37 JTAG_SEL USB_DM C26 USB_SOC_N
100K 100K 100K 69 4 IN BI 25 69
5% 5% 5% NC_JTAG_SOC_TRTCK NO_TEST=TRUE R36 JTAG_TRTCK
1/32W 1/32W 1/32W
72 62 6 5 4 =PP1V8_SOC MF MF MF 69 4 TP_JTAG_SOC_TRST_L U40 JTAG_TRST*
2 01005 2 01005 2 01005 U36 R0630
1 69 TP_JTAG_SOC_TDO JTAG_TDO
R0634 T41
68.1K2
69 IN JTAG_SOC_TDI JTAG_TDI USB_VBUS F22 USB_VBUS_DETECT_R 1 USB_VBUS_DETECT IN 65
10K USB_VBUS HAS 70K INPUT IMPEDANCE

a
5% 69 25 JTAG_SOC_TMS U38 JTAG_TMS VIN 5.0V MAX 1%
OUT 1/32W
1/32W U41
MF 69 25 OUT JTAG_SOC_TCK JTAG_TCK USB_ID F25 NC_USB_ID NO_TEST=TRUE MF
01005
2 01005
70 69 68 62 25 10 4 IN RESET_SOC_L AR41 RESET*
USB_REXT F24 USB_REXT0

in
1 C0660 POWER-ON RESET 4 IN CFSB_SOC AR39 CFSB
0.01UF FAIL SAFE I/O 4 CFSB1_SOC AN26 CFSB1
IN
10% WDOG AN39 WDOG_SOC OUT 4
10V
2 X5R-CERM 4 IN SOC_HOLD_RESET AN38 HOLD_RESET
0201 XI0 H41 XTAL_SOC_24M_I
TP0600 AM40
TP 1
SOC_TST_CLKOUT TST_CLKOUT XO0 H40 XTAL_SOC_24M_O
ALWAYS-ON 1.8V
TP-P55
4 OUT SOC_FAST_SCAN_CLK AR40 FAST_SCAN_CLK (REQUEST_DFU1_L) HOLD_KEY* AP27 GPIO_BTN_ONOFF_L IN 6 23 62 69

h
69 4 IN SOC_TESTMODE AT39 TESTMODE (REQUEST_DFU2_L) MENU_KEY* AM26 GPIO_BTN_HOME_L IN 6 33 62
R0640 1 PLACE_NEAR=U0600.F24:5MM
1
1.00M2 R0660
200
1% 1%
1/32W 1/32W
MF MF
2 01005
B 01005
B

.c
R06411
1.33K
1% CRITICAL
1/32W
MF Y0600
01005 2 1.60X1.20MM-SM
24.000MHZ-30PPM-9.5PF-60OHM
SOC_24M_O 1 3
NO_TEST=TRUE
CRITICAL
CRITICAL 2 4
1 C0650
1 C0651
w
12PF 12PF
5% 5%
16V 16V
2 CERM 2 CERM
01005 01005
w
w

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SOC: MAIN
DRAWING NUMBER SIZE

Apple Inc. 051-0301 D


REVISION
R
B.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 6 OF 155
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SHEET
5 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 GPIOS


R_RPU AND R_RPD 45 K OHM
V_NOM 1.8V
V_MAX 1.95V
R0700
33 I2S0 LOW JITTER
22 OUT I2S_SOC2CODEC_ASP_MCK 1 2 I2S_SOC2CODEC_ASP_MCK_R H38 I2S0_MCK I2C0_SCL AP36 I2C0_SCL_1V8 OUT 4 6 70
70
PLACE_NEAR=U0600.H38:10MM 5% I2S_SOC2CODEC_ASP_BCLK AR35 I2S0_BCLK
U0600 I2C0_SDA AP34 I2C0_SDA_1V8 NC_SOC_GPIO00 NO_TEST=TRUE AF37 GPIO[0]
1/32W
70 22 OUT TMKP88A0-N BI 4 6 70
U0600
MF I2S_SOC2CODEC_ASP_LRCK AT36 I2S0_LRCK FCBGA NC_SOC_GPIO01 NO_TEST=TRUE AF36 GPIO[1]
01005
70 22 OUT TMKP88A0-N
70 22 IN I2S_CODEC2SOC_ASP_DOUT AN37 I2S0_DIN SYM 6 OF 15 I2C1_SCL AM41 I2C1_SCL_1V8 OUT 4 6 70 70 30 OUT GPIO_SOC2GRAPE_RESET_L AJ41 GPIO[2] FCBGA
70 22 I2S_SOC2CODEC_ASP_DOUT AN36 I2S0_DOUT OMIT_TABLE I2C1_SDA AK36 I2C1_SDA_1V8 4 6 70 62 25 GPIO_TS2SOC2PMU_IRQ (USE INTERNAL PU) AG38
GPIO[3] SYM 5 OF 15
OUT BI IN

D 69 GPIO_DISPLAY_ID1 AM36 I2S1_MCK I2C2_SCL T39 I2C2_SCL_1V8 4 6 70


70 30 IN GPIO_GRAPE2SOC_IRQ_L (USE INTERNAL PU) AH41
NC_SOC_GPIO05 NO_TEST=TRUE AF38
GPIO[4]
GPIO[5]
OMIT_TABLE
TMR32_PWM0 AL38 OSCAR_BIDIR_TIME_SYNC_HOST_IRQ 17
D
OUT OUT BI
70 22 I2S_SOC2CODEC_XSP_BCLK AT38 I2S1_BCLK I2C2_SDA R38 I2C2_SDA_1V8 4 6 70 62 GPIO_PMU2SOC_IRQ_L (USE INTERNAL PU) AG39
GPIO[6] TMR32_PWM1 AM38 NC_TMR32_PWM1 NO_TEST=TRUE
OUT BI IN
70 22 OUT I2S_SOC2CODEC_XSP_LRCK AR38 I2S1_LRCK 62 6 OUT GPIO_SOC2PMU_KEEPACT AG40 GPIO[7] TMR32_PWM2 AL36 NC_TMR32_PWM2 NO_TEST=TRUE

AT40 I2C3_SCL T38 I2C3_SCL_1V8 OUT 4 6


70 22 IN I2S_CODEC2SOC_XSP_DOUT I2S1_DIN NC_SOC_GPIO08 NO_TEST=TRUE AG41 GPIO[8]
AR37 I2C3_SDA R37 I2C3_SDA_1V8 BI 4 6
AE36
70 22 OUT I2S_SOC2CODEC_XSP_DOUT I2S1_DOUT 69 IN GPIO_ALS2SOC_DEVBRD_IRQ_L GPIO[9] UART0_RXD V37 UART_DEBUG2SOC_TX IN 25 69

DWI0_CLK AN35 DWI_SOC2PMU_CLK OUT 62 70 NC_SOC_GPIO10 NO_TEST=TRUE AD36 GPIO[10] UART0_TXD V38 UART_SOC2DEBUG_TX OUT 25 69
I2S2 LOW JITTER
NC_I2S2_MCLK NO_TEST=TRUE H39 I2S2_MCK DWI1_CLK L36 NC_DWI1_CLK NO_TEST=TRUE
68 BI GPIO_BB_IPC AE38 GPIO[11]
NC_I2S2_BCLK NO_TEST=TRUE P37 I2S2_BCLK 28 IN GPIO_BTN_VOL_DOWN_L (USE INTERNAL PU) AF39
GPIO[13] UART1_CTSN N41 UART_BB2SOC_RTS_L IN 68 71

NC_I2S2_LRCK NO_TEST=TRUE M40 I2S2_LRCK DWI0_DO AT35 DWI_SOC2PMU_DO OUT 62 70 28 IN GPIO_BTN_VOL_UP_L (USE INTERNAL PU) AF40
GPIO[12] UART1_RTSN N39 UART_SOC2BB_RTS_L OUT 68 71

NC_I2S2_DIN NO_TEST=TRUE M39 I2S2_DIN DWI1_DO J39 NC_DWI1_DO NO_TEST=TRUE NC_SOC_GPIO14 NO_TEST=TRUE AD37 GPIO[14] UART1_RXD P39 UART_BB2SOC_TX 25 68 71
IN
NC_I2S2_DOUT NO_TEST=TRUE N36 GPIO_SOC2GRAPE_EXT_SW_ON AF41 P40 UART_SOC2BB_TX

m
I2S2_DOUT 30 OUT GPIO[15] UART1_TXD OUT 25 68 71
R0701 4 IN GPIO_BRD_ID3 AD39 GPIO[16] BOARD_ID<3>
33 AJ40 AE39 R41
24 OUT I2S_SOC2SPKRAMP_MCK 1 2 I2S_SOC2SPKRAMP_MCK_R I2S3_MCK 71 68 OUT GPIO_SOC2BB_COREDUMP GPIO[17] UART2_CTSN UART_WLAN2SOC_RTS_L IN 68 70
70 PLACE_NEAR=U0600.AJ40:10MM
5% 70 24 I2S_SOC2SPKRAMP_BCLK AH36 I2S3_BCLK 4 GPIO_BOOT_CFG0 AD38 GPIO[18] BOOT_CFG<0> UART2_RTSN T36 UART_SOC2WLAN_RTS_L 57 68 70
1/32W OUT IN OUT
MF 70 24 OUT I2S_SOC2SPKRAMP_LRCK AK40 I2S3_LRCK NC_SOC_GPIO19 NO_TEST=TRUE AE41 GPIO[19] UART2_RXD R39 UART_WLAN2SOC_TX IN 68 70
01005
70 24 I2S_SPKRAMP2SOC_DOUT AJ38 I2S3_DIN 71 68 GPIO_SOC2BB_WAKE_MODEM AD40 GPIO[20] UART2_TXD R40 UART_SOC2WLAN_TX 57 68 70
IN OUT OUT

o
70 24 OUT I2S_SOC2SPKRAMP_DOUT AK41 I2S3_DOUT 24 OUT GPIO_SOC2SPKRAMP_KEEPALIVE AC37 GPIO[21]
71 68 GPIO_BB2SOC_GPS_SYNC AC38 GPIO[22] UART3_CTSN AP35 UART_BT2SOC_RTS_L 68 70
IN IN
69 GPIO_DISPLAY_ID0 P38 I2S4_MCK 23 GPIO_HP_ALS2SOC_IRQ_L (USE INTERNAL PU) AB36 GPIO[23] UART3_RTSN AT33 UART_SOC2BT_RTS_L 57 68 70
OUT IN OUT
70 68 57 OUT I2S_SOC2BT_BCLK P34 I2S4_BCLK 71 69 68 6 OUT GPIO_SOC2BB_RADIO_ON_L AC36 GPIO[24] UART3_RXD AR34 UART_BT2SOC_TX IN 68 70

I2S_SOC2BT_LRCK P36 SEP’S I2C INTERNAL PULL UPS ARE TOO WEAK (28-55K) GPIO_BOOT_CFG1 AD41 AT34 UART_SOC2BT_TX

.c
70 68 57 OUT I2S4_LRCK 4 IN GPIO[25] BOOT_CFG<1> UART3_TXD OUT 57 68 70

70 68 IN I2S_BT2SOC_DOUT M41 I2S4_DIN SEP_I2C_SCL W36 SEP_I2C0_SCL_1V8 6 69 67 6 IN GPIO_FORCE_DFU AC40 GPIO[26] FORCE_DFU
70 68 57 I2S_SOC2BT_DOUT N38 I2S4_DOUT SEP_I2C_SDA W39 SEP_I2C0_SDA_1V8 6 70 TP_GPIO_DFU_STATUS AC39 GPIO[27] DFU_STATUS UART4_CTSN AG36 UART_ROTTERDAM2SOC_RTS_L 34
OUT OUT IN
SEP_SPI_SCLK V40 NC_SEP_SPI_SCLK NO_TEST=TRUE
4 GPIO_BOOT_CFG2 AC41 GPIO[28] BOOT_CFG<2> UART4_RTSN AG37 UART_SOC2ROTTERDAM_RTS_L 34
IN OUT
SEP_SPI_SSIN V41 NC_SEP_SPI_SSIN NO_TEST=TRUE NC_BOARD_ID4 NO_TEST=TRUE AB38
GPIO[29] BOARD_ID<4> UART4_RXD AH38 UART_ROTTERDAM2SOC_TX 34
IN
SEP_SPI_MISO V36 NC_SEP_SPI_MISO NO_TEST=TRUE GPIO_MIC_ALS2SOC_IRQ_L(USE INTERNAL PU) AB41 GPIO[30] UART4_TXD AH39 UART_SOC2ROTTERDAM_TX
C 4 IN GPIO_BRD_ID2 AL41 SPI0_MISO BOARD_ID<2> SEP_SPI_MOSI W38 NC_SEP_SPI_MOSI NO_TEST=TRUE
23

4
IN
IN GPIO_BOOT_CFG3 AB39 GPIO[31] BOOT_CFG<3>
OUT 34
C
GPIO_BRD_ID1 AJ39 W41 NC_SEP_GPIO0 GPIO_OSCAR2PMU_HOST_WAKE AA36 UART5_RTXD AN34 UART_BATT_HDQ

x
NO_TEST=TRUE
4 IN SPI0_MOSI BOARD_ID<1> SEP_GPIO0 62 17 IN GPIO[32] OUT 62 66

4 GPIO_BRD_ID0 AM39 SPI0_SCLK BOARD_ID<0> 69 68 HSIC_BB2SOC_DEVICE_RDY AA38 GPIO[33]


IN NC_ISP_UART0_RXD IN
AK39 ISP_UART0_RXD AJ36 NO_TEST=TRUE
AA39
NC_SPI0_SSIN NO_TEST=TRUE
SPI0_SSIN 69 68 OUT HSIC_SOC2BB_HOST_RDY GPIO[34]
ISP_UART0_TXD AJ37 NC_ISP_UART0_TXD NO_TEST=TRUE
69 68 IN GPIO_BB2SOC_RESET_DET_L AA37 GPIO[35]
SPI_CODEC_MISO L40 GPIO_CODEC2SOC_IRQ_L (USE INTERNAL PU) Y36

fi
22 IN SPI1_MISO 70 22 IN GPIO[36]
R0702 22 OUT SPI_CODEC_MOSI N34 SPI1_MOSI 69 68 OUT GPIO_SOC2BB_RESET_L AA40 GPIO[37] UART6_RXD V39 UART_ACC2SOC_TX IN 25 70
33 L41
22 OUT SPI_CODEC_SCLK 1 2 SPI_CODEC_SCLK_R SPI1_SCLK UART6_TXD U39 UART_SOC2ACC_TX OUT 25 70
PLACE_NEAR=U0600.L41:10MM
5% 22 SPI_CODEC_CS_L M38 SPI1_SSIN (OPENDRAIN) SOCHOT0 AN41 SOCHOT0_L 6 62 69
1/32W OUT IN
MF (OPENDRAIN) SOCHOT1 AK37 SOCHOT1_L OUT 6 62 UART7_RXD AK38 NC_UART7_RXD NO_TEST=TRUE
01005
33 SPI_MESA_MISO Y37 SPI2_MISO UART7_TXD AL39 NC_UART7_TXD NO_TEST=TRUE
IN

a
R0703 Y38 DISP_VSYNC AP41 DISPLAY_SYNC OUT 30 70
Y39
33 OUT SPI_MESA_MOSI SPI2_MOSI UART8_RXD UART_OSCAR2SOC_TX IN 17 70

SPI_MESA_SCLK 1
33 2 SPI_MESA_SCLK_R AA41 Y40 UART_SOC2OSCAR_TX
33 OUT SPI2_SCLK UART8_TXD OUT 17 70
PLACE_NEAR=U0600.AA41:10MM 5% 33 GPIO_MESA2SOC_IRQ Y41 SPI2_SSIN
1/32W IN
MF
01005

in
70 30 IN SPI_GRAPE_MISO AT37 SPI3_MISO
R0704 70 30 OUT SPI_GRAPE_MOSI AM37 SPI3_MOSI
33 AP39
70 30 OUT SPI_GRAPE_SCLK 1 2 SPI_GRAPE_SCLK_R SPI3_SCLK
PLACE_NEAR=U0600.AP39:10MM
5% 70 30 SPI_GRAPE_CS_L AP38 SPI3_SSIN
1/32W OUT
MF
01005

I2C PULL-UPS

h
72 62 6 5 4 =PP1V8_SOC
BUTTON PULLUPS
1
B R0750 1R0751 1
R0752 1
R0753 1R0754 1
R0755 1
R0756 1
R0757 1
R0740 1
R0741 B

.c
72 62 11 =PP1V8_ALWAYS
2.2K 2.2K 2.2K 2.2K 2.2K 2.2K 2.2K 2.2K 2.2K 2.2K
=PP1V8_S2R_MISC 6 9 66 67 72 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
72 67 66 9 6 =PP1V8_S2R_MISC 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W
MF MF MF MF MF MF MF MF MF MF
=PP1V8_SOC 4 5 6 62 72
2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005

1
R0720 1
R0721 1 1 70 6 4 I2C0_SDA_1V8
100K 100K R0760 R0761 70 6 4 I2C0_SCL_1V8
5% 5% 100K 100K
w
1/32W 1/32W 5% 5% 70 6 4 I2C1_SDA_1V8
MF MF 1/32W 1/32W
2 01005 2 01005 MF MF 70 6 4 I2C1_SCL_1V8
2 01005 2 01005
70 6 4 I2C2_SDA_1V8
70 6 4 I2C2_SCL_1V8
GPIO_BTN_HOME_L 62 6 SOCHOT1_L
62 33 5 I2C3_SDA_1V8
w

69 62 23 5 GPIO_BTN_ONOFF_L 69 62 6 SOCHOT0_L
SEP EEPROM
UNPROGRAMMED P/N: 335S0894
6 4
6 4

6
I2C3_SCL_1V8

SEP_I2C0_SDA_1V8
6 SEP_I2C0_SCL_1V8
w

=PP1V8_EEPROM 72

1 C0790
GPIO_SOC2PMU_KEEPACT 6 62
0.22UF
A1

20%
GPIO_FORCE_DFU 6 67 69
2 6.3V
GPIO_SOC2BB_RADIO_ON_L X5R
6 68 69 71 01005-1
VCC
CRITICAL
NOSTUFF U0790
1 1 1 CAT24C08C4A
R0730 R0731 R0733
A 100K
5%
100K
5%
100K
5% 6 SEP_I2C0_SCL_1V8 B1 SCL
WLCSP
SDA B2 SEP_I2C0_SDA_1V8 6 SYNC_MASTER=N/A SYNC_DATE=N/A A
1/32W 1/20W 1/32W PAGE TITLE
MF MF MF
2 01005 2 201 2 01005 SOC: I/OS
DRAWING NUMBER SIZE
VSS
Apple Inc. 051-0301 D
A2

REVISION
R
B.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 7 OF 155
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SHEET
6 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188

D D

m
72 7 =PP1V8_NAND_SOC

R0800 1 1
R0801
100K 100K

o
5% 5%
1/32W 1/32W
MF MF
01005 2 2 01005

U0600

.c
TMKP88A0-N
FCBGA
SYM 7 OF 15
OMIT_TABLE
70 69 16 ANC0_CE0_L D40 PPN0_CEN[0] PPN1_CEN[0] G36 ANC1_CE0_L 16 69 70
OUT OUT

C NC_ANC0_CE1_L NO_TEST=TRUE D35 PPN0_CEN[1] PPN1_CEN[1] G41 NC_ANC1_CE1_L NO_TEST=TRUE


C
ANC0_AD<0> A37 G38 ANC1_AD<0>

x
70 16 BI PPN0_IO[0] PPN1_IO[0] BI 16 70

70 16 BI ANC0_AD<1> B38 PPN0_IO[1] PPN1_IO[1] G39 ANC1_AD<1> BI 16

70 16 BI ANC0_AD<2> C38 PPN0_IO[2] PPN1_IO[2] E37 ANC1_AD<2> BI 16

70 16 BI ANC0_AD<3> B37 PPN0_IO[3] PPN1_IO[3] E36 ANC1_AD<3> BI 16

ANC0_AD<4> C37 F37 ANC1_AD<4>

fi
70 16 BI PPN0_IO[4] PPN1_IO[4] BI 16

70 16 BI ANC0_AD<5> C39 PPN0_IO[5] PPN1_IO[5] E40 ANC1_AD<5> BI 16

70 16 BI ANC0_AD<6> D39 PPN0_IO[6] PPN1_IO[6] E41 ANC1_AD<6> BI 16

70 16 BI ANC0_AD<7> D36 PPN0_IO[7] PPN1_IO[7] F36 ANC1_AD<7> BI 16

a
70 16 ANC0_ALE A35 PPN0_ALE PPN1_ALE G40 ANC1_ALE 16 70
OUT OUT
70 16 OUT ANC0_CLE B35 PPN0_CLE PPN1_CLE F41 ANC1_CLE OUT 16 70

70 16 OUT ANC0_WE_L A36 PPN0_WEN PPN1_WEN G37 ANC1_WE_L OUT 16 70

70 16 OUT ANC0_RE_L C35 PPN0_REN PPN1_REN F39 ANC1_RE_L OUT 16 70

in
70 16 BI ANC0_DQS C36 PPN0_DQS PPN1_DQS E38 ANC1_DQS BI 16 70

ANC0_ZQ D38 PPN0_ZQ PPN1_ZQ E39 ANC1_ZQ


PLACE_NEAR=U0600.D38:5MM 1 PLACE_NEAR=U0600.E39:5MM
R08401 R0841
240 240
1% 1%
1/32W 1/32W
MF E35 PPN0_VREF PPN1_VREF F35 MF
01005 2 2 01005

h
240 OHM IS CORRECT PER CAPRI DATASHEET
240 OHM IS CORRECT PER CAPRI DATASHEET

B =PP1V8_NAND_SOC
B

.c
7 72

1 1
R0830 C0830
51.1K 0.01UF
1% 10%
1/32W
MF 2 6.3V
X5R
2 01005 01005
VOLTAGE=0.9V
70 PPVREF_ANC_SOC
w
1 1 C0831
R0831
51.1K 0.01UF
1% 10%
1/32W 2 6.3V
X5R
w

MF 01005
2 01005
w

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SOC: NAND
DRAWING NUMBER SIZE

Apple Inc. 051-0301 D


REVISION
R
B.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 8 OF 155
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SHEET
7 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188

D D
72 =PP1V0_MIPI_SOC =PP1V8_MIPI_SOC 72

1 C0906 1 C0910 1 C0915


0.22UF 100PF 1.0UF
20% 5% 20%
2 6.3V
X5R 2 16V
NP0-C0G 2 6.3V
X5R
01005-1 01005 0201-1

VDD10_MIPIC AM31
VDD10_MIPIC AN30
VDD10_MIPIC AN32

VDD18_MIPIC AN28
VDD18_MIPIC AM29

m
26MA 13MA
U0600

o
TMKP88A0-N
FCBGA
SYM 3 OF 15
OMIT_TABLE
70 21 MIPI_CAM_REAR_DATA_P<0> AV33 MIPI0C_DPDATA0 ISP0_SCL AT29 ISP_CAM_REAR_SCL 21
IN OUT

.c
70 21 IN MIPI_CAM_REAR_DATA_N<0> AW33 MIPI0C_DNDATA0 ISP0_SDA AT31 ISP_CAM_REAR_SDA BI 21

70 21 MIPI_CAM_REAR_DATA_P<1> AV32 MIPI0C_DPDATA1


IN
70 21 MIPI_CAM_REAR_DATA_N<1> AW32 MIPI0C_DNDATA1
IN
ISP1_SCL AT32 ISP_CAM_FRONT_SCL OUT 21

C 21

21
IN
IN
MIPI_CAM_REAR_DATA_P<2>
MIPI_CAM_REAR_DATA_N<2>
AV30
AW30
MIPI0C_DPDATA2
MIPI0C_DNDATA2
ISP1_SDA AR28 ISP_CAM_FRONT_SDA BI 21
C

x
SENSOR0_CLK AR31 ISP_CAM_REAR_CLK_R R0910 1 33 2 ISP_CAM_REAR_CLK OUT 21
1/32W 5% 01005 MF
21 IN MIPI_CAM_REAR_DATA_P<3> AV29 MIPI0C_DPDATA3 SENSOR0_RST AT30 ISP_CAM_REAR_SHUTDOWN_L OUT 21 PLACE_NEAR=U0600.AR31:5MM

21 MIPI_CAM_REAR_DATA_N<3> AW29 MIPI0C_DNDATA3


IN
SENSOR1_CLK AP32 ISP_CAM_FRONT_CLK_R R0911 1 33 2 ISP_CAM_FRONT_CLK OUT 21

fi
1/32W 5% 01005 MF
70 21 MIPI_CAM_REAR_CLK_P AV31 MIPI0C_DPCLK SENSOR1_RST AR30 ISP_CAM_FRONT_SHUTDOWN_L 21
PLACE_NEAR=U0600.AP32:5MM
IN OUT
70 21 IN MIPI_CAM_REAR_CLK_N AW31 MIPI0C_DNCLK
MIPI0C_REXT AP30 MIPI0C_REXT
SENSOR0_ISTRB AR32 GPIO_SPKRAMP2SOC_RIGHT_IRQ_L (USE INTERNAL PU)
IN 24
SEG: 4.02K IS CORRECT VALUE
PLACE_NEAR=U0600.AP30:10MM
1 SENSOR0_XSHUTDOWN AR29 GPIO_SPKRAMP2SOC_LEFT_IRQ_L (USE INTERNAL PU)
IN 24
R0920

a
4.02K SENSOR1_ISTRB AP33 GPIO_SOC2ROTTERDAM_DWLD_REQ (USE INTERNAL PD)
OUT 34
1%
1/32W SENSOR1_XSHUTDOWN AN33 GPIO_SOC2ROTTERDAM_EN (USE INTERNAL PU)
OUT 34
MF
01005 2

in
MIPI1C_REXT AP31 MIPI1C_REXT
MIPI1C_DPDATA0 AV37 MIPI_CAM_FRONT_DATA_P<0> IN 21 70

MIPI1C_DNDATA0 AW37 MIPI_CAM_FRONT_DATA_N<0> IN 21 70 SEG: 4.02K IS CORRECT VALUE


PLACE_NEAR=U0600.AP31:10MM
1
R0921
MIPI1C_DPDATA1 AV35 MIPI_CAM_FRONT_DATA_P<1> IN 21
4.02K
MIPI1C_DNDATA1 AW35 MIPI_CAM_FRONT_DATA_N<1> IN 21
1%
1/32W
MF

h
2 01005
MIPI1C_DPCLK AV36 MIPI_CAM_FRONT_CLK_P IN 21 70

MIPI1C_DNCLK AW36 MIPI_CAM_FRONT_CLK_N IN 21 70

B B

.c
w
w
w

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SOC: MIPI, ISP


DRAWING NUMBER SIZE

Apple Inc. 051-0301 D


REVISION
R
B.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 9 OF 155
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SHEET
8 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188


72 =PP0V95_PCIE_SOC =PP1V8_PCIE_SOC 72
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
C1096 C1097 C1092 C1093 C1094 C1095 1 C1041 1 C1046 1 C1040 1 C1049 1 C1050
1UF 1UF 1UF 1UF 1UF 1UF 0.22UF 0.01UF 56PF 56PF 0.22UF
CERM 4V CERM 4V CERM 4V CERM 4V CERM 4V CERM 4V 20% 10% 5% 5% 20%
0402 20% 0402 20% 0402 20% 0402 20% 0402 20% 0402 20% 6.3V
2 X5R 6.3V
2 X5R 6.3V
2 NP0-C0G 6.3V
2 NP0-C0G 6.3V
2 X5R
1 3 1 3 1 3 1 3 1 3 1 3 01005-1 01005 01005 01005 01005-1

2 4 2 4 2 4 2 4 2 4 2 4

R1090
VOLTAGE=1.2V
0.00 2
D 72 =PP1V0_LPDP_SOC
PP1V2_PCIE_PLL_SOC_FILT 1
0%
=PP1V2_PLL_SOC 11 72 D
1 C1090 1 C1091 1/32W
56PF 0.22UF MF
1 01005
C1055 1 C1045 5% 20%
1.0UF 56PF 6.3V
2 NP0-C0G 2 6.3V
X5R
20% 5% 01005 01005-1
2 6.3V
X5R
6.3V
2 NP0-C0G
0201-1 01005

H22
H23
J21
J23

G26
J26
H29
K30

VDD095_VP01_PCIE J27

VDD095_VP23_PCIE K29

8MA VDDA10_REFCLK_PCIE L28

VDD18_VPH01_PCIE K27

VDD18_VPH23_PCIE J28

VDDA12_PLL_PCIE L27
LPDP_VDDA10
LPDP_VDDA10
LPDP_VDDA10
LPDP_VDDA10

VDD095_VPTX0_PCIE
VDD095_VPTX1_PCIE
VDD095_VPTX2_PCIE
VDD095_VPTX3_PCIE
L35 SWD_OSCAR_CLK_1V8

m
D23 ULPI_DATA[0] OUT 17 70
32 BI EDP_AUX_P LPDP_AUX_P L37
E23 ULPI_DATA[1] SWD_OSCAR_IO_1V8 BI 17 70
32 BI EDP_AUX_N LPDP_AUX_N K38
ULPI_DATA[2] GPIO_BRD_REV2 IN 4

70 32 EDP_DATA_P<0> C22 LPDP_TX0P ULPI_DATA[3] J34 GPIO_SOC2DEVBRD_S3E_RESET2_L 69


OUT OUT
70 32 EDP_DATA_N<0> B22 LPDP_TX0N ULPI_DATA[4] M37 GPIO_SOC2WLAN_WAKE 68 70
OUT IN

8.5MA
24MA 21MA 45MA 26MA ULPI_DATA[5] M36 GPIO_SOC2BT_WAKE
70 32 EDP_DATA_P<1> B23 LPDP_TX1P EACH EACH EACH IN 57 68 70

o
OUT OMIT_TABLE L38 GPIO_BRD_REV3
A23 ULPI_DATA[6] IN 4
70 32 OUT EDP_DATA_N<1> LPDP_TX1N U0600 L34
ULPI_DATA[7] GPIO_SOC2AJ_HS3_SHUNT_EN OUT 23

EDP_DATA_P<2> C24 TMKP88A0-N


70 32 OUT LPDP_TX2P FCBGA K34
B24 ULPI_CLK GPIO_SOC2AJ_HS4_SHUNT_EN OUT 23
70 32 OUT EDP_DATA_N<2> LPDP_TX2N SYM 8 OF 15 M34
ULPI_DIR GPIO_BRD_REV1 IN 4

.c
70 32 EDP_DATA_P<3> B25 LPDP_TX3P ULPI_NXT K41 GPIO_BRD_REV0 4
OUT IN
70 32 EDP_DATA_N<3> A25 LPDP_TX3N ULPI_STP L39 GPIO_SOC2DEVBRD_S3E_WAKE 69
PLACE_NEAR=U0600.F21:10MM OUT OUT
R10231 1 C1060 LPDP_CAL_DRV_OUT F21 LPDP_CAL_DRV_OUT TOUCH CLK +/-100PPM -->
CLK32K_OUT K39 CLK_SOC2GRAPE_32K OUT 30 69 70
240 100PF G23 (+/-30PPM FREQUENCY ACCURACY, +/-70PPM FOR JITTER)
RDAR://PROBLEM//16438437 1% 5% LPDP_CAL_VSS_EXT LPDP_CAL_VSS_EXT
1/32W 6.3V
2 CERM CPU_SLEEP_STATUS AN40 NC_CPU_SLEEP_STATUS NO_TEST=TRUE
MF
C 01005 2 01005 NC_PCIE_RX0_P
NC_PCIE_RX0_N
NO_TEST=TRUE

NO_TEST=TRUE
E29
F29
PCIE_RX0_P
PCIE_RX0_M
EDP_HPD P41 EDP_HPD IN 32 C

x
B29 (12MHZ TO EXT NVME CTL) NAND_SYS_CLK J35 CLK_SOC2DEVBRD_PCIE_24MHZ OUT 69
NC_PCIE_TX0_P NO_TEST=TRUE
PCIE_TX0_P
NC_PCIE_TX0_N NO_TEST=TRUE C29
PCIE_TX0_M
PERST# FOR LANE 0 IS GPIO[39]
NC_PCIE_CLK0_P NO_TEST=TRUE A32 PCIE_REF_CLK0_P
PCIE_WLAN2SOC_TX_P

fi
70 68 IN B32
NC_PCIE_CLK0_N NO_TEST=TRUE
PCIE_REF_CLK0_M
70 68 IN PCIE_WLAN2SOC_TX_N NC_PCIE_CLKREQ0 NO_TEST=TRUE J41 PCIE_CLKREQ0*

PLACE_NEAR=U0600.A28:11MM
(PCIE_WLAN2SOC_TX_P) D28 PCIE_RX1_P
70 68 57 OUT PCIE_SOC2WLAN_TX_P 0.1UF1 2 C1022 (PCIE_WLAN2SOC_TX_N) E28 PCIE_RX1_M
20% 4V 01005 X5R

a
0.1UF1 C1023 PCIE_SOC2WLAN_TX_C_P A28 PCIE_TX1_P
70 68 57 OUT PCIE_SOC2WLAN_TX_N 2 70

20% 4V 01005 X5R 70 PCIE_SOC2WLAN_TX_C_N B28 PCIE_TX1_M


PLACE_NEAR=U0600.B28:11MM
WIFI
PCIE_SOC2WLAN_CLK_C_P B33 PCIE_REF_CLK1_P PERST# FOR LANE 1 IS GPIO[43]
PLACE_NEAR=U0600.B33:8MM C33
C1024 PCIE_SOC2WLAN_CLK_C_N PCIE_REF_CLK1_M

in
70 68 57 OUT PCIE_SOC2WLAN_CLK_P 0.1UF1 2
72 67 66 6 =PP1V8_S2R_MISC 20% 4V 01005 X5R (PCIE_WLAN2SOC_CLKREQ_L) J40 PCIE_CLKREQ1* (1.8V)
1 70 68 57 OUT PCIE_SOC2WLAN_CLK_N 0.1UF1 2 C1025
R1020 20% 4V 01005 X5R NC_PCIE_RX2_P NO_TEST=TRUE D30 PCIE_RX2_P
1.00K PLACE_NEAR=U0600.C33:8MM
NO_TEST=TRUE E30
5% NC_PCIE_RX2_N PCIE_RX2_M
1/32W
MF A30
2 01005
NC_PCIE_TX2_P NO_TEST=TRUE
PCIE_TX2_P
70 68 PCIE_WLAN2SOC_CLKREQ_L NC_PCIE_TX2_N NO_TEST=TRUE B30 PCIE_TX2_M
IN

h
NC_PCIE_CLK2_P NO_TEST=TRUE D32 PCIE_REF_CLK2_P
NC_PCIE_CLK2_N NO_TEST=TRUE E32 PCIE_REF_CLK2_M

69 PCIE_DEVBRD2SOC_CLKREQ_L J38 PCIE_CLKREQ2*


IN
B B

.c
NC_PCIE_RX3_P NO_TEST=TRUE E31 PCIE_RX3_P
NC_PCIE_RX3_N NO_TEST=TRUE F31
PCIE_RX3_M

NC_PCIE_TX3_P NO_TEST=TRUE B31 PCIE_TX3_P


NC_PCIE_TX3_N NO_TEST=TRUE C31 PCIE_TX3_M

NC_PCIE_CLK3_P NO_TEST=TRUE E33 PCIE_REF_CLK3_P


NC_PCIE_CLK3_N NO_TEST=TRUE F33 PCIE_REF_CLK3_M
w
NC_PCIE_CLKREQ3 NO_TEST=TRUE K36 PCIE_CLKREQ3*

NC_PCIE_REF_CK01_P NO_TEST=TRUE G27 PCIE_REF_PAD_CLK01_P


NC_PCIE_REF_CK01_N NO_TEST=TRUE G28
PCIE_REF_PAD_CLK01_M
INTERNAL REF IS USED
G30
w

SEG: OK TO FLOAT REF_PAD_CLK NC_PCIE_REF_CK23_P NO_TEST=TRUE


PCIE_REF_PAD_CLK23_P J36
G29 PCIE_PERST0* NC_PCIE_PERST0 NO_TEST=TRUE
NC_PCIE_REF_CK23_N NO_TEST=TRUE
PCIE_REF_PAD_CLK23_M J37
PCIE_PERST1* PCIE_SOC2WLAN_RESET_L OUT 68 70

PCIE_RESREF01 J31 PCIE_RESREF01 PCIE_PERST2* H36 PCIE_SOC2DEVBRD_RESET_L 69


OUT 1
NC_PCIE_RESREF23 NO_TEST=TRUE H31
PCIE_RESREF23 PCIE_PERST3* H37 NC_PCIE_PERST3 NO_TEST=TRUE R1022
100K
5%
w

SEG: UNUSED RESREFS CAN FLOAT 1/32W


MF
CORRECT VALUE FOR CAPRI CAPRI DATASHEET 0. 2 01005
PLACE_NEAR=U0600.J31:10MM
FOR UNUSED PCIE LINKS, THE PCIE_TX_P/M PINS MAY BE LEFT FLOATING
R10211 BUT THE RESPECTIVE VPTX SUPPLY SHALL BE CONNECTED
200
1%
1/32W
MF
01005 2

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SOC: EDP, PCIE


DRAWING NUMBER SIZE

Apple Inc. 051-0301 D


REVISION
R
B.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 10 OF 155
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SHEET
9 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

70 14

70 14
OUT
OUT
DDR0_CA<0>
DDR0_CA<1>
A15
B15
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188
DDR0_CA[0]
DDR0_CA[1]
U0600
TMKP88A0-N
DDR1_CA[0]
DDR1_CA[1]
E21
D20
DDR1_CA<0>
DDR1_CA<1>
OUT
OUT
14 70

14 70
70 15 OUT DDR2_CA<0>
DDR2_CA<1>
AW22
AV22
DDR2_CA[0]
DDR2_CA[1]
U0600 DDR3_CA[0]
DDR3_CA[1]
AW15
AW16
DDR3_CA<0>
DDR3_CA<1>
OUT 15 70

C15 E20
70 15 OUT TMKP88A0-N OUT 15 70
70 14 OUT DDR0_CA<2> DDR0_CA[2] FCBGA DDR1_CA[2] DDR1_CA<2> OUT 14 70
70 15 DDR2_CA<2> AU22 DDR2_CA[2] FCBGA DDR3_CA[2] AV16 DDR3_CA<2> 15 70
OUT OUT
DDR0_CA<3> D16 DDR0_CA[3] SYM 1 OF 15 DDR1_CA[3] B20 DDR1_CA<3> AT23 AU16
70 14 OUT OUT 14 70
70 15 OUT DDR2_CA<3> DDR2_CA[3] SYM 2 OF 15 DDR3_CA[3] DDR3_CA<3> OUT 15 70
DDR0_CA<4> A14 DDR0_CA[4] OMIT_TABLE DDR1_CA[4] A20 DDR1_CA<4> AW23 OMIT_TABLE AW17
70 14 OUT OUT 14 70
70 15 OUT DDR2_CA<4> DDR2_CA[4] DDR3_CA[4] DDR3_CA<4> OUT 15 70
DDR0_CA<5> A11 DDR0_CA[5] DDR1_CA[5] A17 DDR1_CA<5> AW26 AW20
70 14 OUT OUT 14 70
70 15 OUT DDR2_CA<5> DDR2_CA[5] DDR3_CA[5] DDR3_CA<5> OUT 15 70
70 14 OUT DDR0_CA<6> C11 DDR0_CA[6] DDR1_CA[6] C17 DDR1_CA<6> OUT 14 70
70 15 DDR2_CA<6> AU26 DDR2_CA[6] DDR3_CA[6] AU20 DDR3_CA<6> 15 70
OUT OUT
DDR0_CA<7> D12 DDR0_CA[7] DDR1_CA[7] D17 DDR1_CA<7> AT27 AT21
70 14 OUT OUT 14 70
70 15 OUT DDR2_CA<7> DDR2_CA[7] DDR3_CA[7] DDR3_CA<7> OUT 15 70 72 11 =PP1V2_VDDIOD_SOC
DDR0_CA<8> A10 DDR0_CA[8] DDR1_CA[8] A16 DDR1_CA<8> AW27 AW21
70 14 OUT OUT 14 70
70 15 OUT DDR2_CA<8> DDR2_CA[8] DDR3_CA[8] DDR3_CA<8> OUT 15 70
DDR0_CA<9> B10 B16 DDR1_CA<9> 1 1

D
70 14 OUT DDR0_CA[9] DDR1_CA[9] OUT 14 70
70 15 OUT DDR2_CA<9> AV27 DDR2_CA[9] DDR3_CA[9] AV21 DDR3_CA<9> OUT 15 70
1 C1194
0.1UF
R1194
1%
4.7K
1 C1196
0.1UF
R1196
4.7K
1%
D
DDR0_CK_P B12 DDR0_CK[0] DDR1_CK[0] B18 DDR1_CK_P 20% 1/32W 20% 1/32W
70 14 OUT OUT 14 70
70 15 OUT DDR2_CK_P AV25 DDR2_CK[0] DDR3_CK[0] AV19 DDR3_CK_P OUT 15 70 6.3V
6.3V MF 2 X5R-CERM MF
DDR0_CK_N A12 DDR0_CKB[0] DDR1_CKB[0] A18 DDR1_CK_N DDR2_CK_N DDR3_CK_N 2 X5R-CERM
70 14 OUT OUT 14 70
70 15 OUT
AW25 DDR2_CKB[0] DDR3_CKB[0] AW19 OUT 15 70
01005 2 01005 01005 2 01005
NC_DDR0_CK<1> NO_TEST=TRUE D13 DDR0_CK[1] DDR1_CK[1] D18 NC_DDR1_CK<1> NO_TEST=TRUE
NC_DDR2_CK<1> NO_TEST=TRUE AU25 DDR2_CK[1] DDR3_CK[1] AU19 NC_DDR3_CK<1> NO_TEST=TRUE
PPVREF_DDR0_DQ_SOC 10 PPVREF_DDR1_DQ_SOC 10
NC_DDR0_CKB<1> NO_TEST=TRUE C12 DDR0_CKB[1] DDR1_CKB[1] C18 NC_DDR1_CKB<1> NO_TEST=TRUE
NC_DDR2_CKB<1> NO_TEST=TRUE AT26 DDR2_CKB[1] DDR3_CKB[1] AT20 NC_DDR3_CKB<1> NO_TEST=TRUE VOLTAGE=0.6V
VOLTAGE=0.6V

70 14 OUT DDR0_CKE<0> B14 DDR0_CKE[0] DDR1_CKE[0] D19 DDR1_CKE<0> OUT 14 70 DDR2_CKE<0> AV23 AV17 DDR3_CKE<0>
70 15 OUT DDR2_CKE[0] DDR3_CKE[0] OUT 15 70
1 1
NC_DDR0_CKE<1> NO_TEST=TRUE E13 DDR0_CKE[1] DDR1_CKE[1] E18 NC_DDR1_CKE<1> NO_TEST=TRUE
NC_DDR2_CKE<1> NO_TEST=TRUE AR24 DDR2_CKE[1] DDR3_CKE[1] AR20 NC_DDR3_CKE<1> NO_TEST=TRUE 1 C1195 R1195 1 C1197 R1197
RESET_SOC_L D14 DDR0_CKEIN DDR1_CKEIN C19 RESET_SOC_L 10 25 62 68 69 70
AT25 AT19 0.1UF 4.7K 0.1UF 4.7K
70 69 68 62 25 10 5 4 IN IN 4
5 69 68 62 25 10 5 4 IN RESET_SOC_L DDR2_CKEIN DDR3_CKEIN RESET_SOC_L IN 4 5 10 25 62 68 69 70
20% 1% 20% 1%
70 1/32W 1/32W
6.3V 6.3V
2 X5R-CERM MF 2 X5R-CERM MF
70 14 OUT DDR0_CSN<0> D15 DDR0_CSN[0] DDR1_CSN[0] F20 DDR1_CSN<0> OUT 14 70
70 15 DDR2_CSN<0> AT24 DDR2_CSN[0] DDR3_CSN[0] AT18 DDR3_CSN<0> 15 70
01005 2 01005 01005 2 01005
OUT OUT
NC_DDR0_CSN<1> NO_TEST=TRUE E14 DDR0_CSN[1] DDR1_CSN[1] E19 NC_DDR1_CSN<1> NO_TEST=TRUE
NC_DDR2_CSN<1> NO_TEST=TRUE AR23 DDR2_CSN[1] DDR3_CSN[1] AR19 NC_DDR3_CSN<1> NO_TEST=TRUE

m
DDR0_DM<0> E6 DDR0_DM[0] DDR1_DM[0] U2 DDR1_DM<0> DDR2_DM<0> AL2 AR11
70 14 OUT OUT 14 70
70 15 OUT DDR2_DM[0] DDR3_DM[0] DDR3_DM<0> OUT 15 70
DDR0_DM<1> E5 DDR0_DM[1] DDR1_DM[1] U5 DDR1_DM<1> DDR2_DM<1>
70 14 OUT OUT 14 70
70 15 OUT
AJ5 DDR2_DM[1] DDR3_DM[1] AV10 DDR3_DM<1> OUT 15 70
DDR0_DM<2> B5 W5 DDR1_DM<2> 1 1
70 14 OUT DDR0_DM[2] DDR1_DM[2] OUT 14 70
70 15 OUT DDR2_DM<2> AL5 DDR2_DM[2] DDR3_DM[2] AV8 DDR3_DM<2> OUT 15 70 1 C1184 R1184 1 C1186 R1186
DDR0_DM<3> H5 DDR0_DM[3] DDR1_DM[3] R2 DDR1_DM<3> DDR2_DM<3> AJ2 AR13 4.7K 4.7K
70 14 OUT OUT 14 70
70 15 OUT DDR2_DM[3] DDR3_DM[3] DDR3_DM<3> OUT 15 70 0.1UF 1% 0.1UF 1%
20% 1/32W 20% 1/32W

o
2 6.3V
X5R-CERM MF 2 6.3V
X5R-CERM MF
DDR0_DQ<0> F10 DDR0_DQ[0] DDR1_DQ[0] AA3 DDR1_DQ<0> DDR2_DQ<0> AR3 AP7
70 14 BI BI 14 70
70 15 BI DDR2_DQ[0] DDR3_DQ[0] DDR3_DQ<0> BI 15 70 01005 2 01005 01005 2 01005
70 14 BI DDR0_DQ<1> E10 DDR0_DQ[1] DDR1_DQ[1] AA2 DDR1_DQ<1> BI 14 70 DDR2_DQ<1> AR2 DDR2_DQ[1] DDR3_DQ[1] AR7 DDR3_DQ<1>
D10 AA1
70 15 BI BI 15 70 PPVREF_DDR2_DQ_SOC 10 PPVREF_DDR3_DQ_SOC 10
70 14 BI DDR0_DQ<2> DDR0_DQ[2] DDR1_DQ[2] DDR1_DQ<2> BI 14 70
70 15 DDR2_DQ<2> AR1 DDR2_DQ[2] DDR3_DQ[2] AT7 DDR3_DQ<2> 15 70
VOLTAGE=0.6V VOLTAGE=0.6V
BI BI
DDR0_DQ<3> F9 DDR0_DQ[3] DDR1_DQ[3] Y3 DDR1_DQ<3> AP3 AP8
70 14 BI BI 14 70
70 15 BI DDR2_DQ<3> DDR2_DQ[3] DDR3_DQ[3] DDR3_DQ<3> BI 15 70

.c
1 1
70 14 BI DDR0_DQ<4> D9 DDR0_DQ[4] DDR1_DQ[4] Y1 DDR1_DQ<4> BI 14 70
70 15 BI DDR2_DQ<4> AP1 DDR2_DQ[4] DDR3_DQ[4] AT8 DDR3_DQ<4> BI 15 70
1 C1185 R1185 1 C1187 R1187
DDR0_DQ<5> E8 DDR0_DQ[5] DDR1_DQ[5] W2 DDR1_DQ<5> AN2 AR9 0.1UF 4.7K 0.1UF 4.7K
70 14 BI BI 14 70
70 15 BI DDR2_DQ<5> DDR2_DQ[5] DDR3_DQ[5] DDR3_DQ<5> BI 15 70
20% 1% 20% 1%
DDR0_DQ<6> D8 DDR0_DQ[6] DDR1_DQ[6] W1 DDR1_DQ<6> 6.3V 1/32W 6.3V 1/32W
70 14 BI BI 14 70
70 15 BI DDR2_DQ<6> AN1 DDR2_DQ[6] DDR3_DQ[6] AT9 DDR3_DQ<6> BI 15 70 2 X5R-CERM MF 2 X5R-CERM MF
DDR0_DQ<7> F7 DDR0_DQ[7] DDR1_DQ[7] V3 DDR1_DQ<7> 01005 2 01005 01005 2 01005
70 14 BI BI 14 70
70 15 BI DDR2_DQ<7> AM3 DDR2_DQ[7] DDR3_DQ[7] AP10 DDR3_DQ<7> BI 15 70
DDR0_DQ<8> F4 DDR0_DQ[8] DDR1_DQ[8] T6 DDR1_DQ<8> AH6 AU11
70 14 BI BI 14 70
70 15 BI DDR2_DQ<8> DDR2_DQ[8] DDR3_DQ[8] DDR3_DQ<8> BI 15 70

C 70 14 BI DDR0_DQ<9> E3 DDR0_DQ[9] DDR1_DQ[9] R5 DDR1_DQ<9> BI 14 70


70 15 BI DDR2_DQ<9> AG5 DDR2_DQ[9] DDR3_DQ[9] AV12 DDR3_DQ<9> BI 15 70 C
DDR0
DDR1

DDR0_DQ<10> C3 DDR0_DQ[10] DDR1_DQ[10] R4 DDR1_DQ<10>

DDR2
DDR3
70 14 BI BI 14 70 DDR2_DQ<10> AG4 DDR2_DQ[10] DDR3_DQ[10] AW12 DDR3_DQ<10>

x
70 15 BI BI 15 70
DDR0_DQ<11> F2 DDR0_DQ[11] DDR1_DQ[11] P6 DDR1_DQ<11> DDR2_DQ<11> AF6 AU13 DDR3_DQ<11>
70 14 BI
DDR0_DQ<12> D3 DDR0_DQ[12] DDR1_DQ[12] P4 DDR1_DQ<12>
BI 14 70
70 15 BI
DDR2_DQ<12> AF4
DDR2_DQ[11] DDR3_DQ[11]
AW13 DDR3_DQ<12>
BI 15 70
ONCE ROUTED SEG NEEDS TO CHECK PI OF *_VREF_DQ0
70 14

70 14
BI
BI DDR0_DQ<13> F1 DDR0_DQ[13] DDR1_DQ[13] N6 DDR1_DQ<13>
BI
BI
14 70

14 70
70 15 BI
DDR2_DQ<13> AE6
DDR2_DQ[12] DDR3_DQ[12]
AU14 DDR3_DQ<13>
BI 15 70
AND *_VREF_DQ1 BEING TIED TOGETHER
70 15 BI DDR2_DQ[13] DDR3_DQ[13] BI 15 70
70 14 BI DDR0_DQ<14> E1 DDR0_DQ[14] DDR1_DQ[14] N5 DDR1_DQ<14> BI 14 70 DDR2_DQ<14> AE5 AV14 DDR3_DQ<14>
DDR2_DQ[14] DDR3_DQ[14]

fi
70 15 BI BI 15 70
70 14 BI DDR0_DQ<15> D2 DDR0_DQ[15] DDR1_DQ[15] N4 DDR1_DQ<15> BI 14 70 DDR2_DQ<15> AE4 AW14 DDR3_DQ<15>
70 15 BI DDR2_DQ[15] DDR3_DQ[15] BI 15 70
DDR0_DQ<16> C9 DDR0_DQ[16] DDR1_DQ[16] AC6 DDR1_DQ<16> AR6 AT4
70 14 BI BI 14 70
70 15 BI DDR2_DQ<16> DDR2_DQ[16] DDR3_DQ[16] DDR3_DQ<16> BI 15 70
70 14 BI DDR0_DQ<17> B9 DDR0_DQ[17] DDR1_DQ[17] AC5 DDR1_DQ<17> BI 14 70 DDR2_DQ<17> AR5 AU4 DDR3_DQ<17> 72 10 =PP1V2_S2R_DDR_SOC
70 15 BI DDR2_DQ[17] DDR3_DQ[17] BI 15 70
70 14 BI DDR0_DQ<18> A9 DDR0_DQ[18] DDR1_DQ[18] AC4 DDR1_DQ<18> BI 14 70 DDR2_DQ<18> AR4 AV4 DDR3_DQ<18> 1
70 15 BI DDR2_DQ[18] DDR3_DQ[18] BI 15 70 1 C1190 R1190 1
70 14 BI DDR0_DQ<19> C8 DDR0_DQ[19] DDR1_DQ[19] AB6 DDR1_DQ<19> BI 14 70
70 15 BI DDR2_DQ<19> AP6 DDR2_DQ[19] DDR3_DQ[19] AU5 DDR3_DQ<19> BI 15 70 0.1UF 10K 1 C1192 R1192
0.1UF 10K

a
DDR0_DQ<20> A8 DDR0_DQ[20] DDR1_DQ[20] AB4 DDR1_DQ<20> 20% 1%
70 14 BI BI 14 70
70 15 BI DDR2_DQ<20> AP4 DDR2_DQ[20] DDR3_DQ[20] AW5 DDR3_DQ<20> BI 15 70 6.3V 1/32W 20% 1%
B7 AA5 2 X5R-CERM 6.3V
70 14 BI DDR0_DQ<21> DDR0_DQ[21] DDR1_DQ[21] DDR1_DQ<21> BI 14 70 DDR2_DQ<21> AN5 DDR2_DQ[21] DDR3_DQ[21] AV6 DDR3_DQ<21> 01005
MF 2 X5R-CERM 1/32W
70 15 BI BI 15 70
2 01005 01005
MF
70 14 BI DDR0_DQ<22> A7 DDR0_DQ[22] DDR1_DQ[22] AA4 DDR1_DQ<22> BI 14 70
70 15 DDR2_DQ<22> AN4 DDR2_DQ[22] DDR3_DQ[22] AW6 DDR3_DQ<22> 15 70
2 01005
BI BI
70 14 BI DDR0_DQ<23> C6 DDR0_DQ[23] DDR1_DQ[23] Y6 DDR1_DQ<23> BI 14 70 DDR2_DQ<23> AM6 DDR2_DQ[23] DDR3_DQ[23] AU7 DDR3_DQ<23> PPVREF_DDR0_CA_SOC 10
J4 P3
70 15 BI BI 15 70 PPVREF_DDR1_CA_SOC 10
DDR0_DQ<24> DDR0_DQ[24] DDR1_DQ[24] DDR1_DQ<24> DDR2_DQ<24> AH3 AP14 DDR3_DQ<24> VOLTAGE=0.6V

in
70 14 BI BI 14 70 VOLTAGE=0.6V
70 15 BI DDR2_DQ[24] DDR3_DQ[24] BI 15 70
70 14 BI DDR0_DQ<25> H3 DDR0_DQ[25] DDR1_DQ[25] N2 DDR1_DQ<25> BI 14 70 DDR2_DQ<25> AG2 AR15 DDR3_DQ<25>
1 C1191 1
R1191 1
DDR0_DQ<26> G3 N1 DDR1_DQ<26>
70 15 BI DDR2_DQ[25] DDR3_DQ[25] BI 15 70
0.1UF 10K
1 C1193 R1193
70 14 BI DDR0_DQ[26] DDR1_DQ[26] BI 14 70
70 15 DDR2_DQ<26> AG1 DDR2_DQ[26] DDR3_DQ[26] AT15 DDR3_DQ<26> 15 70
20% 1% 0.1UF 10K
BI BI 6.3V
DDR0_DQ<27> J2 DDR0_DQ[27] DDR1_DQ[27] M3 DDR1_DQ<27> AF3 AP16 2 X5R-CERM 1/32W 20% 1%
70 14 BI BI 14 70
70 15 BI DDR2_DQ<27> DDR2_DQ[27] DDR3_DQ[27] DDR3_DQ<27> BI 15 70
01005 MF 2 6.3V 1/32W
DDR0_DQ<28> G2 DDR0_DQ[28] DDR1_DQ[28] M1 DDR1_DQ<28> 2 01005 X5R-CERM MF
70 14 BI BI 14 70 DDR2_DQ<28> AF1 DDR2_DQ[28] DDR3_DQ[28] AT16 DDR3_DQ<28> 01005
J1 L3
70 15 BI BI 15 70
2 01005
70 14 BI DDR0_DQ<29> DDR0_DQ[29] DDR1_DQ[29] DDR1_DQ<29> BI 14 70
70 15 DDR2_DQ<29> AE3 DDR2_DQ[29] DDR3_DQ[29] AP17 DDR3_DQ<29> 15 70
BI BI
DDR0_DQ<30> H1 DDR0_DQ[30] DDR1_DQ[30] L2 DDR1_DQ<30> AE2 AR17
70 14 BI BI 14 70
70 15 BI DDR2_DQ<30> DDR2_DQ[30] DDR3_DQ[30] DDR3_DQ<30> BI 15 70
DDR0_DQ<31> G1 L1 DDR1_DQ<31>

h
70 14 BI DDR0_DQ[31] DDR1_DQ[31] BI 14 70
70 15 DDR2_DQ<31> AE1 DDR2_DQ[31] DDR3_DQ[31] AT17 DDR3_DQ<31> 15 70
BI BI

DDR0_DQS_P<0> D7 DDR0_PDQS[0] DDR1_PDQS[0] V1 DDR1_DQS_P<0> AM1 DDR2_PDQS[0]


70 14 BI BI 14 70
70 15 BI DDR2_DQS_P<0> DDR3_PDQS[0] AT10 DDR3_DQS_P<0> BI 15 70
70 14 BI DDR0_DQS_N<0> D6 DDR0_NDQS[0] DDR1_NDQS[0] U1 DDR1_DQS_N<0> BI 14 70 DDR2_DQS_N<0> AL1 DDR2_NDQS[0] DDR3_NDQS[0] AT11 DDR3_DQS_N<0> 1 1
70 15 BI BI 15 70 1 C1180 R1180 1 C1182 R1182
B 0.1UF 10K 0.1UF 10K
B

.c
DDR0_DQS_P<1> D4 DDR0_PDQS[1] DDR1_PDQS[1] T4 DDR1_DQS_P<1> 20% 1% 20% 1%
70 14 BI BI 14 70
70 15 BI DDR2_DQS_P<1> AH4 DDR2_PDQS[1] DDR3_PDQS[1] AW11 DDR3_DQS_P<1> BI 15 70 6.3V 1/32W 6.3V 1/32W
D5 DDR0_NDQS[1] 2 X5R-CERM 2 X5R-CERM
70 14 BI DDR0_DQS_N<1> DDR1_NDQS[1] U4 DDR1_DQS_N<1> BI 14 70 DDR2_DQS_N<1> AJ4 DDR2_NDQS[1] DDR3_NDQS[1] AW10 DDR3_DQS_N<1> 01005
MF
01005
MF
70 15 BI BI 15 70
2 01005 2 01005

DDR0_DQS_P<2> A6 DDR0_PDQS[2] DDR1_PDQS[2] Y4 DDR1_DQS_P<2> AM4 DDR2_PDQS[2] PPVREF_DDR2_CA_SOC 10 PPVREF_DDR3_CA_SOC


70 14 BI BI 14 70
70 15 BI DDR2_DQS_P<2> DDR3_PDQS[2] AW7 DDR3_DQS_P<2> BI 15 70
VOLTAGE=0.6V VOLTAGE=0.6V
10

DDR0_DQS_N<2> A5 DDR0_NDQS[2] DDR1_NDQS[2] W4 DDR1_DQS_N<2>


70 14 BI BI 14 70
70 15 BI DDR2_DQS_N<2> AL4 DDR2_NDQS[2] DDR3_NDQS[2] AW8 DDR3_DQS_N<2> BI 15 70
1 1
1 C1181 R1181 1 C1183 R1183
DDR0_DQS_P<3> G4 DDR0_PDQS[3] DDR1_PDQS[3] P1 DDR1_DQS_P<3> AH1 DDR2_PDQS[3] 0.1UF 10K 0.1UF 10K
DDR3_PDQS[3] AT14
w
70 14 BI BI 14 70
70 15 BI DDR2_DQS_P<3> DDR3_DQS_P<3> BI 15 70 20% 1% 20% 1%
G5 DDR0_NDQS[3] 6.3V 6.3V
70 14 BI DDR0_DQS_N<3> DDR1_NDQS[3] R1 DDR1_DQS_N<3> BI 14 70
70 15 DDR2_DQS_N<3> AJ1 DDR2_NDQS[3] DDR3_NDQS[3] AT13 DDR3_DQS_N<3> 15 70
2 X5R-CERM 1/32W
MF 2 X5R-CERM 1/32W
MF
BI BI
01005 01005
2 01005 2 01005
10 PPVREF_DDR0_CA_SOC A13 DDR0_VREF_CA DDR1_VREF_CA A19 PPVREF_DDR1_CA_SOC 10
10 PPVREF_DDR2_CA_SOC AW24 DDR2_VREF_CA DDR3_VREF_CA AW18 PPVREF_DDR3_CA_SOC 10
DDR0_ZQ_CA_SOC C13 DDR0_ZQ_CA DDR1_ZQ_CA F18 DDR1_ZQ_CA_SOC AU24 DDR2_ZQ_CA
10 10
10 DDR2_ZQ_CA_SOC DDR3_ZQ_CA AU18 DDR3_ZQ_CA_SOC 10
w

PPVREF_DDR0_DQ_SOC H10 DDR0_VREF_DQ0 DDR1_VREF_DQ0 AA7 PPVREF_DDR1_DQ_SOC


10 10
10 PPVREF_DDR2_DQ_SOC AL7 DDR2_VREF_DQ0 DDR3_VREF_DQ0 AN9 PPVREF_DDR3_DQ_SOC 10
L6 DDR0_VREF_DQ1 DDR1_VREF_DQ1 R7 AG7 DDR2_VREF_DQ1 DDR3_VREF_DQ1 AN15

DDR0_ZQ_DQ0_SOC G9 DDR0_ZQ_DQ0 DDR1_ZQ_DQ0 AA6 DDR1_ZQ_DQ0_SOC


10 10
10 DDR2_ZQ_DQ0_SOC AL6 DDR2_ZQ_DQ0 DDR3_ZQ_DQ0 AP9 DDR3_ZQ_DQ0_SOC 10
DDR0_ZQ_DQ1_SOC M6 DDR0_ZQ_DQ1 DDR1_ZQ_DQ1 R6 DDR1_ZQ_DQ1_SOC AG6 DDR2_ZQ_DQ1
10 10 DDR2_ZQ_DQ1_SOC DDR3_ZQ_DQ1 AP15 DDR3_ZQ_DQ1_SOC
w

10 10

=PP1V2_S2R_DDR_SOC F13 VDD12_CKE_DDR0 VDD12_CKE_DDR1 F17 =PP1V2_S2R_DDR_SOC AP24 VDD12_CKE_DDR2


72 10 10 72
72 10 =PP1V2_S2R_DDR_SOC VDD12_CKE_DDR3 AP19 =PP1V2_S2R_DDR_SOC 10 72

C1101 1 1 C1100 C1102 1 1 C1103


0.22UF 0.22UF 0.22UF 0.22UF
20% 20% 20% 20%
6.3V 2 SEG: OK TO FLOAT CK, CKB, CKE AND CSN PINS 2 6.3V 6.3V 6.3V
X5R X5R X5R 2 SEG: OK TO FLOAT CK, CKB, CKE AND CSN PINS 2 X5R
01005-1 01005-1 01005-1 01005-1

A DDR0_ZQ_CA_SOC 10 DDR1_ZQ_CA_SOC 10 DDR2_ZQ_CA_SOC 10 DDR3_ZQ_CA_SOC 10 SYNC_MASTER=N/A SYNC_DATE=N/A A


DDR0_ZQ_DQ0_SOC 10 DDR1_ZQ_DQ0_SOC 10 PAGE TITLE
DDR2_ZQ_DQ0_SOC 10 DDR3_ZQ_DQ0_SOC 10
DDR0_ZQ_DQ1_SOC 10 DDR1_ZQ_DQ1_SOC 10 DDR2_ZQ_DQ1_SOC 10 DDR3_ZQ_DQ1_SOC 10 SOC: DDR
DRAWING NUMBER SIZE
1
R1100 1R1102 1R1104 1
R1101 1R1103 1R1105 1 Apple Inc. 051-0301 D
240 240 240 240 240 240
R1106 1R1107 1R1108 1
R1109 1R1110 1R1111 REVISION
240 240 240 240 240 240 R
1%
1/32W
1%
1/32W
1%
1/32W
1%
1/32W
1%
1/32W
1%
1/32W 1%
1/32W
1%
1/32W
1%
1/32W
1%
1/32W
1%
1/32W
1%
1/32W
B.0.0
MF MF MF MF MF MF MF MF MF MF MF MF NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 11 OF 155
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SHEET
10 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188


PLACE_NEAR=U0600.H21:13MM
XW12A0 R1290
SHORT-10L-0.5MM-SM VOLTAGE=1.2V
G12 3.5MA EACH AF16
VOLTAGE=1.2V 0.00 2
72 11 10 =PP1V2_VDDIOD_SOC 1 2 PP1V2_VDDIOD_DDR01CA VDDIOD_DDR01CA VDDA12_PLL_CPU PP1V2_PLL_SOC_FILT 1 =PP1V2_PLL_SOC 9 11 72
G14 U0600 H21 0%
D 1 C1260
1.0UF
1 C1261
1.0UF
1 C1262
1.0UF
1 C1265
0.47UF
1 C1266
0.47UF
1 C1267
0.47UF
1 C1268
0.22UF
1 C1269
0.22UF
G16
VDDIOD_DDR01CA TMKP88A0-N LPDP_VDDA12_PLL
VDDIOD_DDR01CA FCBGA VDDA12_PLL_MIPIT AP29
1 C1290
0.01UF
10%
1 C1291
0.22UF
20%
1/32W
MF
01005
D
20% 20% 20% 20% 20% 20% 20% 20% G18 VDDIOD_DDR01CA SYM 11 OF 15
VOLTAGE=6.3V
2 X5R
VOLTAGE=6.3V
2 X5R
VOLTAGE=6.3V
2 X5R
VOLTAGE=4V
2 CERM-X5R-1
VOLTAGE=4V
2 CERM-X5R-1
VOLTAGE=4V
2 CERM-X5R-1
VOLTAGE=6.3V
2 X5R VOLTAGE=6.3V 2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R
2 X5R G20 VDDIOD_DDR01CA OMIT_TABLE 01005 01005-1
0201-1 0201-1 0201-1 201 201 201 01005-1 01005-1 VDDA18__SOC1_TSADC M32
H13 VDDIOD_DDR01CA
VDDA18_SOC0_TSADC W18
H15 VDDIOD_DDR01CA
H17 VDDIOD_DDR01CA VDDA18_CPU_TSADC0 AF18
1MA
XW12C0 H19 AH12
SHORT-10L-0.5MM-SM VOLTAGE=1.2V VDDIOD_DDR01CA VDDA18_CPU_TSADC1
72 11 10 =PP1V2_VDDIOD_SOC 1 2 PP1V2_VDDIOD_DDR23CA AM17 VDDIOD_DDR23CA VDDA18_CPU_TSADC2 AE12
AM19 VDDIOD_DDR23CA VDDA18_CPU_TSADC3 AG18 =PP1V8_VDDIO18_SOC 11 72
1 C1270 1 C1271 1 C1272 1 C1275 1 C1276 1 C1277 1 C1278 1 C1279 AM21
1.0UF 1.0UF 1.0UF 0.47UF 0.47UF 0.47UF VDDIOD_DDR23CA
0.22UF 0.22UF AM25 1 C1238
20%
VOLTAGE=6.3V
20%
VOLTAGE=6.3V
20%
VOLTAGE=6.3V
20%
VOLTAGE=4V
20%
VOLTAGE=4V
20%
VOLTAGE=4V 20% 20% VDDIOD_DDR23CA 1 C1235 1 C1236 1 C1237
0.22UF

m
2 X5R 2 X5R 2 X5R 2 CERM-X5R-1 2 CERM-X5R-1 2 CERM-X5R-1 VOLTAGE=6.3V
2 X5R
VOLTAGE=6.3V
2 X5R AN18 AB35 0.22UF 0.22UF 0.22UF
0201-1 0201-1 0201-1 201 201 201 VDDIOD_DDR23CA VDDIO18_GRP1 20% 20% 20% 20%
01005-1 01005-1 AN20 AD35 2 VOLTAGE=6.3V
VDDIOD_DDR23CA VDDIO18_GRP1 2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R X5R
AN22 AF35 01005-1 01005-1 01005-1 01005-1
VDDIOD_DDR23CA VDDIO18_GRP1
AN24 VDDIOD_DDR23CA GPIO, UART, DWI, VDDIO18_GRP1 AH35
AM23 I2C, I2S, SPI, AK35
VDDIOD_DDR23CA FAIL SAFE, TIMER, VDDIO18_GRP1
AM11 MISC, ISP_UART0, AL34
72 11 10 =PP1V2_VDDIOD_SOC VDDIOD_DDRDQ SEP, JTAG, VDDIO18_GRP1

o
AM13 CLK32K_OUT, AM35 =PP1V8_VDDIO18_SOC 11 72
VDDIOD_DDRDQ ULPI, PCIE GPIO VDDIO18_GRP1
C1200 1
AM15 VDDIOD_DDRDQ VDDIO18_GRP1 K35 CRITICAL
15UF 30MA C1240 1 C1242 1 C1243 1 C1244 1 C1245 1 C1246 1 C1247 1 C1248 1 C1249 1
20% AM9 VDDIOD_DDRDQ VDDIO18_GRP1 M35
VOLTAGE=4V 4.3UF 1.0UF 1.0UF 1.0UF 0.47UF 0.47UF 0.22UF 0.22UF 8.2PF
CERM 2 AA8 VDDIOD_DDRDQ VDDIO18_GRP1 P35 20% 20% 20% 20% 20% 20% 20% 20% +/-0.5PF
0402 VOLTAGE=4V VOLTAGE=6.3V VOLTAGE=6.3V VOLTAGE=6.3V VOLTAGE=4V VOLTAGE=4V VOLTAGE=6.3V VOLTAGE=6.3V 50V

.c
AB5 VDDIOD_DDRDQ VDDIO18_GRP1 T35 X5R-CERM 2 X5R 2 X5R 2 X5R 2 CERM-X5R-1 2 CERM-X5R-1 2 X5R 2 X5R 2 C0G-CERM 2
0610 0201-1 0201-1 0201-1 201 201 01005-1 01005-1 201
AM7 VDDIOD_DDRDQ VDDIO18_GRP1 V35
AN10 VDDIOD_DDRDQ VDDIO18_GRP1 Y35
AN12 VDDIOD_DDRDQ 3MA VDDIO18_GRP0 AM28
CRITICAL CRITICAL AN14 ISP[0|1]_I2C,
C1203 1 C1204 1 VDDIOD_DDRDQ SENSOR[0|1] L1290
C 4.3UF
20%
4.3UF
20%
AN16
AB7
VDDIOD_DDRDQ
VDDIOD_DDRDQ VDDIO18_PPN H32
120-OHM-25%-250MA-0.5DCR
1 2 =PP1V8_XTAL_SOC
C

x
VOLTAGE=4V VOLTAGE=4V 72
X5R-CERM 2 X5R-CERM 2 AN8 VDDIOD_DDRDQ 75MA VDDIO18_PPN H33
0610 0610 01005 PLACE_NEAR=U0600.H35:5MM
AP2 VDDIOD_DDRDQ VDDIO18_PPN H34 C1280 1
AP5 VOLTAGE=1.8V
0.22UF
VDDIOD_DDRDQ H35 20%
AR16 1MA VDDIO18_XTAL 69 PP1V8_XTAL VOLTAGE=6.3V
VDDIOD_DDRDQ X5R 2

fi
AR8 AM27 01005-1
VDDIOD_DDRDQ 1MA VDDIO18_AON
C1205 1 C1206 1 C1207 1 C1208 1 C1209 1 AV13 VDDIOD_DDRDQ
VDD18_EFUSE1 AL35 PPVDD18_EFUSE1
1.0UF 1.0UF 1.0UF 1.0UF 1.0UF AV5 VDDIOD_DDRDQ CKPLUS_WAIVE=PWRTERM2GND
4
20% 20% 20% 20% 20% EFUSE SHOULD BE TIED TO GROUND PER SEG
VOLTAGE=6.3V VOLTAGE=6.3V VOLTAGE=6.3V VOLTAGE=6.3V VOLTAGE=6.3V B8 VDDIOD_DDRDQ VDD_ANA_PLL0 V19 =PP1V8_ALWAYS 6 62 72
X5R 2 X5R 2 X5R 2 X5R 2 X5R 2
0201-1 0201-1 0201-1 0201-1 0201-1 E2 VDDIOD_DDRDQ VDD_ANA_PLL1 AA18
E9 U19 C1281 1

a
VDDIOD_DDRDQ 21MA VDD_ANA_PLL2
AD7
0.22UF
VDDIOD_DDRDQ VDD_ANA_PLL4 V18 20%
VOLTAGE=6.3V
G10 VDDIOD_DDRDQ VDD_ANA_PLL5 Y18 X5R 2
01005-1
G8 VDDIOD_DDRDQ
C1210 1 C1211 1 C1212 1
H11 VDDIOD_DDRDQ

in
1.0UF 1.0UF 1.0UF PLACE_NEAR=U0600.V19:11MM
20% 20% 20% AF2 VDDIOD_DDRDQ R1291
VOLTAGE=6.3V VOLTAGE=6.3V VOLTAGE=6.3V
X5R 2 X5R 2 X5R 2 H2 VDDIOD_DDRDQ
VOLTAGE=1.2V 0.00 2
0201-1 0201-1 0201-1 PP1V2_ANA_PLL_SOC_FILT 1 =PP1V2_PLL_SOC 9 11 72
H7 VDDIOD_DDRDQ 0%
H9 1 C1296 1 C1297 1 C1298 1/32W
VDDIOD_DDRDQ 1 C1299 MF
J8 0.22UF 0.01UF 0.01UF 8.2PF 01005
VDDIOD_DDRDQ 20% 10% 10% +/-0.5PF
K7 VDDIOD_DDRDQ 2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R
VOLTAGE=6.3V
2 X5R 50V
2 C0G-CERM
L8 01005-1 01005 01005 201

h
C1220 1 C1221 1 C1222 1 C1223 1 C1224 1 VDDIOD_DDRDQ
0.47UF 0.47UF 0.47UF 0.47UF 0.47UF M2 VDDIOD_DDRDQ
20% 20% 20% 20% 20% M7
VOLTAGE=4V VOLTAGE=4V VOLTAGE=4V VOLTAGE=4V VOLTAGE=4V VDDIOD_DDRDQ
CERM-X5R-1 2 CERM-X5R-1 2 CERM-X5R-1 2 CERM-X5R-1 2 CERM-X5R-1 2 AF5 V7
201 201 201 201 201 VDDIOD_DDRDQ VDDIOD_DDRDQ
N8 W8
B VDDIOD_DDRDQ VDDIOD_DDRDQ
B

.c
P5 VDDIOD_DDRDQ VDDIOD_DDRDQ Y2
P7 VDDIOD_DDRDQ VDDIOD_DDRDQ Y7
R8 VDDIOD_DDRDQ VDDIOD_DDRDQ AF7
C1225 1 C1226 1 C1227 1 T7 VDDIOD_DDRDQ VDDIOD_DDRDQ AH7
0.47UF 0.47UF 0.47UF U8 AK7
20% 20% 20% VDDIOD_DDRDQ VDDIOD_DDRDQ
VOLTAGE=4V VOLTAGE=4V VOLTAGE=4V
CERM-X5R-1 2 CERM-X5R-1 2 CERM-X5R-1 2
201 201 201
w
C1230 1 C1231 1 C1232 1
0.22UF 0.22UF 100PF
w

20% 20% 5%
VOLTAGE=6.3V VOLTAGE=6.3V 25V 2
X5R 2 X5R 2 C0G
01005-1 01005-1 0201
w

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SOC: IO POWER
DRAWING NUMBER SIZE

TABLE_ALT_HEAD

Apple Inc. 051-0301 D


PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: REVISION
PART NUMBER R
TABLE_ALT_ITEM
REFDES FOR ALTERATIVE TABLE B.0.0
138S0702 138S0657 QTY 22 RDAR://PROBLEM/8837828 C1203,C1204,C1240, C1305-C1308, C1404-C1409,C1464-C1469,C1445,C1446 NOTICE OF PROPRIETARY PROPERTY: BRANCH
TABLE_ALT_ITEM

THE INFORMATION CONTAINED HEREIN IS THE


138S0702 138S0657 QTY 22 RDAR://PROBLEM/8837828 C1602,C1603,C1642,C1643, C1702,C1703,C1742,C1743 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 12 OF 155
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SHEET
11 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 A1


A21
VSS
VSS
U0600 VSS
VSS
AD8
AE11
AK3
AK30
VSS
VSS
U0600 VSS
VSS
AT6
AU1
D31
D33
VSS
VSS
U0600 VSS
VSS
K2
K20
R27
R29
VSS
VSS
U0600 VSS
VSS
W9
Y10
TMKP88A0-N TMKP88A0-N TMKP88A0-N TMKP88A0-N
A22 VSS FCBGA VSS AE13 AK32 VSS FCBGA VSS AU10 D34 VSS FCBGA VSS K22 R3 VSS FCBGA VSS Y12
A24 VSS SYM 12 OF 15 VSS AE17 AK34 VSS SYM 13 OF 15 VSS AU12 D37 VSS SYM 14 OF 15 VSS K24 R31 VSS SYM 15 OF 15 VSS Y14
A26 VSS OMIT_TABLE VSS AE19 AK4 VSS OMIT_TABLE VSS AU15 E11 VSS OMIT_TABLE VSS K26 R33 VSS OMIT_TABLE VSS Y16
72 =PP0V95_SOC A27 AE21 AK5 AU17 E12 K28 R35 Y20
VSS VSS VSS VSS VSS VSS VSS VSS
CRITICAL CRITICAL CRITICAL CRITICAL A29 AE23 AK6 AU21 E15 K3 R9 Y22
1 C1305 1 C1306 1 C1307 1 C1308 VSS VSS VSS VSS VSS VSS VSS VSS
4.3UF 4.3UF 4.3UF 4.3UF A3 VSS VSS AE25 AK8 VSS VSS AU23 E16 VSS VSS K32 T1 VSS VSS Y24
20% 20% 20% 20% AL10 VDD_SOC VDD_SOC J32
4V 4V 4V 4V U0600 A31 VSS VSS AE27 AL11 VSS VSS AU27 E17 VSS VSS K37 T10 VSS VSS Y26
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM AL14 VDD_SOC K11
TMKP88A0-N VDD_SOC
D 0610 0610 0610 0610
AL18
AA10
VDD_SOC FCBGA VDD_SOC AA20
A33
A34
VSS
VSS
VSS
VSS
AE29
AE31
AL13
AL17
VSS
VSS
VSS
VSS
AU28
AU29
E22
E24
VSS
VSS
VSS
VSS
K4
K40
T12
T14
VSS
VSS
VSS
VSS
Y28
Y30
D
VDD_SOC SYM 10 OF 15 VDD_SOC K13 A39 AE33 AL19 AU3 E26 K5 T16 Y32
AA12 VSS VSS VSS VSS VSS VSS VSS VSS
VDD_SOC OMIT_TABLE VDD_SOC K15 A41 AE35 AL21 AU30 E27 K6 T18
AC18 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC K17 AA11 AE37 AL23 AU31 E34 K8 T2 VSS_SENSE M26 TP_SOC_VSS_SENSE 70
CRITICAL CRITICAL CRITICAL T19 VSS VSS VSS VSS VSS VSS VSS
1 1 1 VDD_SOC VDD_SOC K19 AA13 AE40 AL25 AU32 E4 L11 T20
C1320 C1321 C1322 T21 VSS VSS VSS VSS VSS VSS VSS VSS_CPU_SENSE AC13 TP_SOC_VSS_CPU_SENSE 70
1.0UF 1.0UF 1.0UF VDD_SOC VDD_SOC K21 AA15 AE7 AL27 AU33 E7 L13 T22
20% 20% 20% T23 VSS VSS VSS VSS VSS VSS VSS
6.3V 6.3V 6.3V VDD_SOC VDD_SOC K23 AA17 AE9 AL29 AU34 F11 L15 T24
2 X5R 2 X5R 2 X5R T34 VSS VSS VSS VSS VSS VSS VSS
0201-1 0201-1 0201-1 VDD_SOC VDD_SOC K25 AA19 AF10 AL3 AU35 F12 L17 T26
T9 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC K31 AA21 AF12 AL31 AU36 F14 L19 T28
U10 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC K33 AA23 AF14 AL33 AU37 F15 L21 T3
U12 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC K9 AA25 AF20 AL37 AU39 F16 L23 T30
VSS VSS VSS VSS VSS VSS VSS

m
U14 VDD_SOC VDD_SOC AA22
CRITICAL CRITICAL CRITICAL AA27 VSS VSS AF22 AL40 VSS VSS AU41 F19 VSS VSS L25 T32 VSS
U16 VDD_SOC VDD_SOC L10
1 C1323 1 C1324 1 C1325 AA29 VSS VSS AF24 AL9 VSS VSS AU6 F26 VSS VSS L31 T37 VSS
1.0UF 1.0UF 1.0UF U18 VDD_SOC VDD_SOC L12
20% 20% 20% AA31 VSS VSS AF26 AM10 VSS VSS AU8 F27 VSS VSS L33 T40 VSS
6.3V 6.3V 6.3V AC20 VDD_SOC VDD_SOC L14
2 X5R 2 X5R 2 X5R AA33 VSS VSS AF28 AM12 VSS VSS AU9 F28 VSS VSS L4 T5 VSS
0201-1 0201-1 0201-1 U20 VDD_SOC VDD_SOC L16 AA35 VSS VSS AF30 AM14 VSS VSS AV11 F3 VSS VSS L5 T8 VSS
U22 VDD_SOC VDD_SOC L18 AA9 AF32 AM16 AV15 F30 L7 U11

o
V11 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC L20 AB1 AF34 AM18 AV18 F32 L9 U13
V13 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC L22

SOC PD PARTITIONS)
AB10 VSS VSS AF8 AM2 VSS VSS AV2 F34 VSS VSS M10 U15 VSS
V15 VDD_SOC VDD_SOC L24 AB12 VSS VSS AG21 AM20 VSS VSS AV20 F38 VSS VSS M12 U17 VSS
CRITICAL CRITICAL V17 VDD_SOC VDD_SOC L26
1 C1330 1 C1331 AB14 VSS VSS AG23 AM22 VSS VSS AV24 F40 VSS VSS M14 U21 VSS

.c
V21 VDD_SOC VDD_SOC L30
0.47UF 0.47UF AB16 VSS VSS AG25 AM24 VSS VSS AV26 F5 VSS VSS M16 U23 VSS
20% 20% V23 VDD_SOC VDD_SOC AB17
4V 4V AB18 AG27 AM30 AV28 F6 M18 U25
2 CERM-X5R-1 2 CERM-X5R-1
V9 VSS VSS VSS VSS VSS VSS VSS
201 201 VDD_SOC VDD_SOC L32 AB2 AG29 AM32 AV34 F8 M20 U27
W10 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC M11 AB20 AG3 AM34 AV40 G11 M22 U29
AC22 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC M13 AB22 AG31 AM5 AV7 G13 M24 U3
W12 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC M15
C W14
VDD_SOC
VDD_SOC VDD_SOC M17
AB24
AB26
VSS
VSS
VSS
VSS
AG33
AG35
AM8
AN11
VSS
VSS
VSS
VSS
AV9
AW1
G15
G17
VSS
VSS
VSS
VSS
Y8
M30
U31
U33
VSS
VSS
C

x
W16 VDD_SOC M19

4.0A MAX,
VDD_SOC AB28 AG9 AN13 AW28 G19 M4 U35
1 C1340 1 C1341 1 C1345 W20 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC M21 AB3 AH10 AN17 AW3 G21 M5 U6
0.22UF 0.22UF 100PF W22 VSS VSS VSS VSS VSS VSS VSS
20% 20% 5% VDD_SOC VDD_SOC M23 AB30 AH14 AN19 AW34 G22 M8 U7
2 6.3V 2 6.3V 2 16V Y11 VSS VSS VSS VSS VSS VSS VSS
X5R X5R NP0-C0G VDD_SOC VDD_SOC M27 AB32 AH16 AN21 AW39 G24 N11 U9
01005-1 01005-1 01005 VSS VSS VSS VSS VSS VSS VSS

fi
Y13 VDD_SOC VDD_SOC AB19 AB34 VSS VSS AH18 AN23 VSS VSS AW41 G25 VSS VSS N13 V10 VSS
Y15 VDD_SOC VDD_SOC M29
0.904V - 0.996V, AB37 VSS VSS AH2 AN25 VSS VSS AW9 G31 VSS VSS N15 V12 VSS
Y17 VDD_SOC VDD_SOC M31 AB40 VSS VSS AH20 AN27 VSS VSS B11 G32 VSS VSS N17 V14 VSS
Y19 VDD_SOC VDD_SOC M33 AB8 VSS VSS AH22 AN29 VSS VSS B13 G33 VSS VSS N19 V16 VSS
AD17 VDD_SOC VDD_SOC M9 AC1 VSS VSS AH24 AN3 VSS VSS B17 G34 VSS VSS N21 V2 VSS
Y21 VDD_SOC VDD_SOC N10

a
AC11 VSS VSS AH26 AN31 VSS VSS B19 G6 VSS VSS N23 V20 VSS
Y23 VDD_SOC VDD_SOC N12 Y5 VSS VSS AH28 AN6 VSS VSS B2 G7 VSS VSS N27 V22 VSS
Y34 VDD_SOC VDD_SOC N14 AC17 VSS VSS AH30 AN7 VSS VSS B21 H12 VSS VSS N29 V24 VSS
Y9 VDD_SOC VDD_SOC N16 AC19 VSS VSS AH32 AP11 VSS VSS B27 H14 VSS VSS N3 V26 VSS
AD19 VDD_SOC VDD_SOC N18 AC2 AH37 AP12 B34 H16 N31 V28

in
AD21 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC N20
(VDD_SOC,

AC21 VSS VSS AH40 AP13 VSS VSS B36 H18 VSS VSS N33 V30 VSS
AD23 VDD_SOC VDD_SOC AB21 AC23 VSS VSS AH5 AP18 VSS VSS B4 H20 VSS VSS N35 V32 VSS
AD34 VDD_SOC VDD_SOC N22 AC25 VSS VSS AH8 AP20 VSS VSS B40 H26 VSS VSS N37 V34 VSS
AE18 VDD_SOC VDD_SOC P11 AC27 VSS VSS AJ11 AP21 VSS VSS B6 H27 VSS VSS N40 V4 VSS
AE20 VDD_SOC VDD_SOC P13 AC29 VSS VSS AJ13 AP22 VSS VSS C1 H28 VSS VSS N7 V5 VSS
AA14 VDD_SOC VDD_SOC P15 AC3 VSS VSS AJ17 AP23 VSS VSS C10 H30 VSS VSS N9 V6 VSS
AE22 VDD_SOC VDD_SOC P17

h
AC31 VSS VSS AJ19 AP25 VSS VSS C14 H4 VSS VSS P10 V8 VSS
AF23 VDD_SOC VDD_SOC P19 AC33 VSS VSS AJ21 AP26 VSS VSS C16 H6 VSS VSS P12 W11 VSS
AH23 VDD_SOC VDD_SOC P21 AC35 VSS VSS AJ23 AP28 VSS VSS C20 H8 VSS VSS P14 W13 VSS
AH34 VDD_SOC VDD_SOC P23 AC7 VSS VSS AJ25 AP37 VSS VSS C21 J11 VSS VSS P16 W15 VSS
AK23 VDD_SOC VDD_SOC P9
B AC9 AJ27 AP40 C23 J13 P18 W17
B

.c
AL24 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC R10 AD1 AJ29 AR10 C25 J15 P2 W19
AL26 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC AB23 AD10 AJ3 AR12 C27 J17 P20 W21
AL28 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC R12 AD12 AJ31 AR14 C28 J19 P22 W23
AL30 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC R14 AD16 AJ33 AR18 C30 J29 P24 W25
AL32 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC R16 AD18 AJ35 AR21 C32 J3 P26 W27
AA16 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC R18 AD2 AJ6 AR22 C34 J30 P28 W29
J10 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC R20 AD20 AJ7 AR25 C4 J33 P30 W3
w
J12 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC R22 AD22 AJ9 AR26 C41 J5 P32 W31
J14 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC T11 AD24 AK1 AR27 C5 J6 P8 W33
J16 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC T13 AD26 AK12 AR33 C7 J7 R11 W35
J18 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC T15 AD28 AK16 AR36 D11 J9 R13 W37
J20 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC T17 AD3 AK18 AT12 D21 K1 R15 W40
w

J22 VSS VSS VSS VSS VSS VSS VSS


VDD_SOC VDD_SOC L29 AD30 AK2 AT2 D22 K10 R17 W6
J24 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC M28 AD32 AK22 AT22 D24 K12 R19 W7
VSS VSS VSS VSS VSS VSS VSS
VDD_SOC_SENSE M25 AD4 VSS VSS AK24 AT28 VSS VSS D26 K14 VSS VSS R21
AD5 VSS VSS AK26 AT3 VSS VSS D27 K16 VSS VSS R23
AD6 VSS VSS AK28 AT5 VSS VSS D29 K18 VSS VSS R25
w

70 62 PPVDD_SOC_SOC_SENSE
VOLTAGE=0.95V

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SOC: SOC POWER AND GND


DRAWING NUMBER SIZE

Apple Inc. 051-0301 D


REVISION
R
B.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 13 OF 155
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SHEET
12 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188


72 =PPVDD_CPU
CRITICAL CRITICAL =PPVDD_GPU 72
1 C1400 1 C1401 C1405 C1406 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
15UF 15UF 7.5UF 7.5UF AB11 VDD_CPU VDD_GPU AA26 1 C1460 1 C1461 1 C1464 1 C1465 1 C1466 1 C1467 1 C1468 1 C1469
20% 20% 20% 20% U0600
4V 4V AD15 AA28 15UF 15UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF
2 4V
CERM 2 4V
CERM CERM CERM VDD_CPU TMKP88A0-N VDD_GPU 20% 20% 20% 20% 20% 20% 20% 20%
0402 0402 0402 0402 AD9 VDD_CPU FCBGA VDD_GPU AC34 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V
1 3 1 3 CERM CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM
AE10 VDD_CPU SYM 9 OF 15 VDD_GPU AD25 0402 0402 0610 0610 0610 0610 0610 0610
AE14 VDD_CPU OMIT_TABLE VDD_GPU AD29
2 4 2 4
D AE16
AE8
VDD_CPU
VDD_CPU
VDD_GPU
VDD_GPU
AD31
AE26
D
AF13 AE28 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
VDD_CPU VDD_GPU 1 C1470 1 C1471 1 C1472 1 C1473 1 C1474 1 C1475
AF15 VDD_CPU VDD_GPU AE32 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL AF17 AE34 20% 20% 20% 20% 20% 20%
C1410 C1411 C1412 C1413 C1414 C1415 C1416 VDD_CPU VDD_GPU 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
4.3UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF AF19 VDD_CPU VDD_GPU AF25 0201-1 0201-1 0201-1 0201-1 0201-1 0201-1
20% 20% 20% 20% 20% 20% 20% AB15 AF29
4V 4V 4V 4V 4V 4V 4V VDD_CPU VDD_GPU
CERM CERM CERM CERM CERM CERM CERM AF21 AA32
0402 0402 0402 0402 0402 0402 0402 VDD_CPU VDD_GPU
1 3 1 3 1 3 1 3 1 3 1 3 1 3 AF9 VDD_CPU VDD_GPU AF31
AG10 VDD_CPU VDD_GPU AG26 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
2 4 2 4 2 4 2 4 2 4 2 4 2 4 AG12 AG28 1 C1480 1 C1481 1 C1482 1 C1483 1 C1484 1 C1485
VDD_CPU VDD_GPU
AG14 AG32 0.47UF 0.47UF 0.47UF 0.47UF 0.47UF 0.47UF

m
VDD_CPU VDD_GPU 20% 20% 20% 20% 20% 20%
AG17 VDD_CPU VDD_GPU AG34 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
0204 0204 0204 0204 0204 0204
AG20 AH25

CPU0-2 AND CPUB)


VDD_CPU VDD_GPU
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL AG22 AH29
C1420 C1421 C1422 C1423 C1424 C1425 C1426 VDD_CPU VDD_GPU
1UF 1UF 1UF 1UF 1UF 1UF 1UF AG8 VDD_CPU VDD_GPU AH31
20% 20% 20% 20% 20% 20% 20% AH11 AJ26
4V 4V 4V 4V 4V 4V 4V VDD_CPU VDD_GPU
CERM CERM CERM CERM CERM CERM CERM

o
GPU LOGIC)
0402 0402 0402 0402 0402 0402 0402 AB9 VDD_CPU VDD_GPU AJ28 1 C1490 1 C1491 1 C1492 1 C1493 1 C1495 1 C1496
1 3 1 3 1 3 1 3 1 3 1 3 1 3 AH13 VDD_CPU VDD_GPU AA34 0.22UF 0.22UF 0.22UF 0.22UF 100PF 56PF
20% 20% 20% 20% 5% 5%
AH15 VDD_CPU VDD_GPU AJ32 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
16V
2 NP0-C0G
6.3V
2 NP0-C0G
2 4 2 4 2 4 2 4 2 4 2 4 2 4 AH17 AJ34 01005-1 01005-1 01005-1 01005-1 01005 01005
VDD_CPU VDD_GPU
AH19 AK25

.c
VDD_CPU VDD_GPU
AH21 AK29

13.4A MAX,
VDD_CPU VDD_GPU

8.0A MAX,
AH9 VDD_CPU VDD_GPU AK31
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL AJ10 N28
C1430 C1431 C1432 C1433 C1434 C1435 C1436 VDD_CPU VDD_GPU
1UF 1UF 1UF 1UF 1UF 1UF 1UF AJ12 VDD_CPU VDD_GPU N32
20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V AJ14 VDD_CPU VDD_GPU P25
C 1
CERM
0402
3 1
CERM
0402
3 1
CERM
0402
3 1
CERM
0402
3 1
CERM
0402
3 1
CERM
0402
3 1
CERM
0402
3
AJ16 VDD_CPU VDD_GPU P29 C
AC12 AB25

x
0.775V - 1.05V,
VDD_CPU VDD_GPU

0.80V - 1.05V,
AJ18 VDD_CPU VDD_GPU P31
2 4 2 4 2 4 2 4 2 4 2 4 2 4 AJ20 R26
VDD_CPU VDD_GPU
AJ22 VDD_CPU VDD_GPU R28
AJ8 R32

fi
VDD_CPU VDD_GPU
AK11 VDD_CPU VDD_GPU R34
CRITICAL CRITICAL AK13 T25
C1437 C1438 VDD_CPU VDD_GPU
1UF 1UF
C1439 1
AK15 T29
220PF VDD_CPU VDD_GPU
20% 20% 10% AK17 T31
4V 4V VDD_CPU VDD_GPU

(VDD_GPU
(VDD_CPU
CERM CERM 10V
0402 0402 X7R-CERM 2 AK19 U26
VDD_CPU VDD_GPU

a
01005
1 3 1 3 AK21 VDD_CPU VDD_GPU U28
AC14 VDD_CPU VDD_GPU AB29
2 4 2 4 AK9 U32
VDD_CPU VDD_GPU
AL12 VDD_CPU VDD_GPU U34

in
AL16 VDD_CPU VDD_GPU V25
AL20 VDD_CPU VDD_GPU V29
AL22 VDD_CPU VDD_GPU V31
AL8 VDD_CPU VDD_GPU W26
AC16 VDD_CPU VDD_GPU W28
AC8 VDD_CPU VDD_GPU W32
AD11 VDD_CPU VDD_GPU W34

h
AD13 VDD_CPU VDD_GPU Y25
VOLTAGE=1.1V
70 62 PPVDD_CPU_SOC_SENSE AB13 VDD_CPU_SENSE VDD_GPU AB31
VDD_GPU Y29
VDD_GPU Y31
B B

.c
VDD_GPU AC26
VDD_GPU AC28
VDD_GPU AC32
VOLTAGE=1.1V
VDD_GPU_SENSE N26 PPVDD_GPU_SOC_SENSE 62 70

CPU AND GPU SRAM)


VDD_SRAM AG30
VDD_SRAM AH27
VDD_SRAM AH33
w
VOLTAGE=3.3V
70 62 PPVDD_SRAM_SOC_SENSE N25 VDD_SRAM_SENSE VDD_SRAM AJ15
72 =PPVDD_SRAM AA24 VDD_SRAM VDD_SRAM AJ24
CRITICAL CRITICAL CRITICAL CRITICAL AA30 VDD_SRAM VDD_SRAM AJ30
C1451 C1452 C1453 C1454 AB27 AK10
7.5UF 7.5UF 4.3UF 4.3UF VDD_SRAM VDD_SRAM
20% 20% 20% 20% AB33 VDD_SRAM VDD_SRAM AK14
4V 4V 4V 4V
w

CERM CERM CERM CERM AC10 VDD_SRAM VDD_SRAM AK20


0402 0402 0402 0402

3.4A MAX,
1 3 1 3 1 3 1 3 AC15 VDD_SRAM VDD_SRAM AK27
AC24 VDD_SRAM VDD_SRAM AK33
2 4 2 4 2 4 2 4 AC30 VDD_SRAM VDD_SRAM AL15
AD14 VDD_SRAM VDD_SRAM N24
w

AD27 VDD_SRAM VDD_SRAM N30


CRITICAL CRITICAL AD33 VDD_SRAM VDD_SRAM P27

0.95V - 1.05V,
C1455 C1456 AE15 P33
1UF 1UF VDD_SRAM VDD_SRAM
20% 20% AE24 VDD_SRAM VDD_SRAM R24
4V 4V
CERM CERM AE30 VDD_SRAM VDD_SRAM R30
0402 0402
1 3 1 3 AF11 VDD_SRAM VDD_SRAM T27
AF27 VDD_SRAM VDD_SRAM T33
2 4 2 4 AF33 VDD_SRAM VDD_SRAM U24

A AG11
AG13
VDD_SRAM VDD_SRAM U30
V27 SYNC_MASTER=N/A SYNC_DATE=N/A A
(VDD_SRAM

VDD_SRAM VDD_SRAM
PAGE TITLE
AG15 VDD_SRAM VDD_SRAM V33
CRITICAL AG16 VDD_SRAM VDD_SRAM W24 SOC: CPU, GPU, SRAM POWER
1 C1457 1 C1459 AG19 VDD_SRAM VDD_SRAM W30 DRAWING NUMBER SIZE
1.0UF
20% 5%
100PF AG24 VDD_SRAM VDD_SRAM Y27
Apple Inc. 051-0301 D
2 6.3V
X5R 2 16V
NP0-C0G VDD_SRAM Y33
R
REVISION
0201-1 01005 B.0.0
TABLE_ALT_HEAD NOTICE OF PROPRIETARY PROPERTY: BRANCH
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: THE INFORMATION CONTAINED HEREIN IS THE
PART NUMBER PROPRIETARY PROPERTY OF APPLE INC.
TABLE_ALT_ITEM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
138S00006 138S0835 ? C1410, ECT RDAR://PROBLEM/16040051 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 14 OF 155
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SHEET
13 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
70 10

70 10

70 10
IN
IN
IN
DDR1_CA<0>
DDR1_CA<1>
DDR1_CA<2>
H18
H19
J18
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188
DDR0_CA[0] OMIT_TABLE
DDR0_CA[1]
DDR0_CA[2]
U1600
BGA-1
DDR1_CA[0]
DDR1_CA[1]
DDR1_CA[2]
V17
W17
V16
DDR0_CA<0>
DDR0_CA<1>
DDR0_CA<2>
IN
IN
IN
10 70

10 70

10 70
72 15 14 =PP1V2_DDR_VDDQ

J19 DRAM W16 CRITICAL CRITICAL CRITICAL CRITICAL


70 10 IN DDR1_CA<3> DDR0_CA[3] DDR1_CA[3] DDR0_CA<3> IN 10 70

DDR1_CA<4> K19 (1 OF 3) W15 DDR0_CA<4>


C1600 1 C1601 1 C1602 1 C1603 1 C1605 1 C1606 1 C1607 1 C1608 1
DDR0_CA[4] DDR1_CA[4] 15UF 15UF 4.3UF 4.3UF 1.0UF 1.0UF 1.0UF 1.0UF

CAPRI-DRAM
70 10 IN IN 10 70

70 10 IN DDR1_CA<5> R18 DDR0_CA[5] DDR1_CA[5] V10 DDR0_CA<5> IN 10 70


20% 20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 6.3V 2 6.3V 2 6.3V 2 6.3V 2
DDR1_CA<6> R19 W10 DDR0_CA<6> CERM 2 CERM 2 X5R-CERM 2 X5R-CERM 2 X5R X5R X5R X5R
70 10 IN DDR0_CA[6] DDR1_CA[6] IN 10 70 0402 0402 0610 0610 0201-1 0201-1 0201-1 0201-1
70 10 IN DDR1_CA<7> T19 DDR0_CA[7] DDR1_CA[7] W9 DDR0_CA<7> IN 10 70

70 10 IN DDR1_CA<8> T20 DDR0_CA[8] DDR1_CA[8] Y9 DDR0_CA<8> IN 10 70

70 10 IN DDR1_CA<9> U18 DDR0_CA[9] DDR1_CA[9] V8 DDR0_CA<9> IN 10 70

D 70 10 IN DDR1_CK_P M19 DDR0_CK DDR1_CK W13 DDR0_CK_P IN 10 70


D
DDR1_CK_N N19 DDR0_CKB DDR1_CKB W12 DDR0_CK_N
70 10 IN IN 10 70
C1609 1 C1610 1 C1611 1 C1615 1 C1616 1 C1619 1
70 10 IN DDR1_CKE<0> L19 DDR0_CKE[0] DDR1_CKE[0] W14 DDR0_CKE<0> IN 10 70 100PF 0.47UF 0.47UF 0.1UF 0.1UF 100PF
L18 V14 5% 20% 20% 20% 20% 5%
NC_DRAM_DDR1_CKE<1> DDR0_CKE[1] DDR1_CKE[1] NC_DRAM_DDR0_CKE<1> 25V 4V 4V 6.3V 6.3V 16V
NO_TEST=TRUE NO_TEST=TRUE C0G 2 CERM-X5R-1 2 CERM-X5R-1 2 X5R-CERM 2 X5R-CERM 2 NP0-C0G 2
0201 201 201 01005 01005 01005
SEG: OK TO FLOAT CKE AND CS PINS SEG: OK TO FLOAT CKE AND CS PINS

70 10 IN DDR1_CSN<0> L20 DDR0_CS[0] DDR1_CS[0] Y14 DDR0_CSN<0> IN 10 70

NC_DDR1_CS<1> NO_TEST=TRUE K20 DDR0_CS[1] DDR1_CS[1] Y15 NC_DDR0_CS<1> NO_TEST=TRUE

70 10 IN DDR1_DM<0> L3 DDR0_DM[0] DDR1_DM[0] C14 DDR0_DM<0> IN 10 70

70 10 DDR1_DM<1> N2 DDR0_DM[1] DDR1_DM[1] B12 DDR0_DM<1> 10 70 POR CAPS 6/11/2013

m
IN IN
70 10 DDR1_DM<2> G2 DDR0_DM[2] DDR1_DM[2] B18 DDR0_DM<2> 10 70
IN IN
70 10 DDR1_DM<3> T4 DDR0_DM[3] DDR1_DM[3] D9 DDR0_DM<3> 10 70
IN IN
72 15 =PP1V8_S2R_DDR AA19 OMIT_TABLE A10
A1 OMIT_TABLE F20
H3 C17 B13 U1600 A12
70 10 BI DDR1_DQ<0> DDR0_DQ[0] DDR1_DQ[0] DDR0_DQ<0> BI 10 70
CRITICAL A18 U1600 F21
H4 D17 1 1 1 1 1 C2 CAPRI-DRAM A15
70 10 BI DDR1_DQ<1> DDR0_DQ[1] DDR1_DQ[1] DDR0_DQ<1> BI 10 70 C1620 C1625 C1626 C1628 C1629 BGA-1
A2 CAPRI-DRAM G1
DDR1_DQ<2> J2 B16 DDR0_DQ<2> 15UF 1UF 1UF 1.0UF 1.0UF C3 A16

o
70 10 BI DDR0_DQ[2] DDR1_DQ[2] BI 10 70
20% 10% 10% 20% 20% DRAM A20 BGA-1 G18
J3 C16 4V 6.3V 6.3V 6.3V 6.3V G19 A19 DRAM
70 10 BI DDR1_DQ<3> DDR0_DQ[3] DDR1_DQ[3] DDR0_DQ<3> BI 10 70 CERM 2 CERM 2 CERM 2 X5R 2 X5R 2 (2 OF 3) A21 G20
J4 D16 0402 402 402 0201-1 0201-1 M2 B14 (3 OF 3)
70 10 BI DDR1_DQ<4> DDR0_DQ[4] DDR1_DQ[4] DDR0_DQ<4> BI 10 70 A3 G21
J5 E16 P18 VDD1 C19
70 10 BI DDR1_DQ<5> DDR0_DQ[5] DDR1_DQ[5] DDR0_DQ<5> BI 10 70 A4 H2
DDR1_DQ<6> K2 B15 V11 C21
70 10 BI DDR0_DQ[6] DDR1_DQ[6] DDR0_DQ<6> BI 10 70 A5 J20

.c
DDR1_DQ<7> W20 D4
70 10 BI
K3 DDR0_DQ[7] DDR1_DQ[7] C15 DDR0_DQ<7> BI 10 70 A6 K5
DDR1_DQ<8> P3 C11 W21 D6
70 10 BI DDR0_DQ[8] DDR1_DQ[8] DDR0_DQ<8> BI 10 70 A8 L5
DDR1_DQ<9> P4 D11 DDR0_DQ<9>
C1634 1 C1635 1 C1636 1 C1639 1
Y19 E12
70 10 BI DDR0_DQ[9] DDR1_DQ[9] BI 10 70
100PF 0.1UF 0.1UF 100PF VDDQ AA1 M20
DDR1_DQ<10> Y5 E17
R2 DDR0_DQ[10] DDR1_DQ[10] B10 DDR0_DQ<10> 5% 20% 20% 5%
AA2 M3
DDR0
DDR1

70 10 BI BI 10 70 25V 6.3V 6.3V 16V


DDR1_DQ<11> R3 C10 C0G 2 X5R-CERM 2 X5R-CERM 2 NP0-C0G 2 Y6 F1
70 10 BI DDR0_DQ[11] DDR1_DQ[11] DDR0_DQ<11> BI 10 70 0201 01005 01005 01005 AA3 N20
C 70 10 BI DDR1_DQ<12>
DDR1_DQ<13>
R4
R5
DDR0_DQ[12]
DDR0_DQ[13]
DDR1_DQ[12]
DDR1_DQ[13]
D10
E10
DDR0_DQ<12>
DDR0_DQ<13>
BI 10 70
AA18
F3
H5
AA6 P2 C
AA7 R20

x
70 10 BI BI 10 70
T2 B9 AA20 J1
70 10 BI DDR1_DQ<14> DDR0_DQ[14] DDR1_DQ[14] DDR0_DQ<14> BI 10 70 B1 T5
T3 72 15 14 =PP1V2_S2R_DDR AA21 K1
70 10 BI DDR1_DQ<15> DDR0_DQ[15] DDR1_DQ[15] C9 DDR0_DQ<15> BI 10 70 B11 U1
E2 B20 CRITICAL CRITICAL CRITICAL AA4 L2
70 10 BI DDR1_DQ<16> DDR0_DQ[16] DDR1_DQ[16] DDR0_DQ<16> BI 10 70
C1646 1 B17 VSS VSS U20
DDR1_DQ<17> E3 C20 DDR0_DQ<17>
C1640 1 C1642 1 C1643 1 C1645 1
AA5 N1
DDR0_DQ[17] DDR1_DQ[17] 1UF B2 V18

fi
70 10 BI BI 10 70
15UF 4.3UF 4.3UF 1UF 10% B3 N5
70 10 BI DDR1_DQ<18> E4 DDR0_DQ[18] DDR1_DQ[18] D20 DDR0_DQ<18> BI 10 70
20%
4V
20%
4V
20%
4V
10%
6.3V 6.3V B21 V19
CERM 2 X5R-CERM 2 X5R-CERM 2 CERM 2 CERM 2 B4 R1
70 10 DDR1_DQ<19> E5 DDR0_DQ[19] DDR1_DQ[19] E20 DDR0_DQ<19> 10 70 402 C1 V5
BI BI 0402 0610 0610 402
F2 B19 E13 W4
70 10 BI DDR1_DQ<20> DDR0_DQ[20] DDR1_DQ[20] DDR0_DQ<20> BI 10 70 C13 V6
E21
70 10 BI DDR1_DQ<21> F4 DDR0_DQ[21] DDR1_DQ[21] D19 DDR0_DQ<21> BI 10 70 C4 V7
F5 E19 M5
70 10 BI DDR1_DQ<22> DDR0_DQ[22] DDR1_DQ[22] DDR0_DQ<22> BI 10 70 VDD2 D1 W1

a
DDR1_DQ<23> G5 E18 DDR0_DQ<23> P20
70 10 BI DDR0_DQ[23] DDR1_DQ[23] BI 10 70 D2 W18
DDR1_DQ<24> U2 B8 DDR0_DQ<24> V20
70 10 BI DDR0_DQ[24] DDR1_DQ[24] BI 10 70
C1648 1 C1649 1 C1655 1 C1656 1 C1659 1 D21 W5
DDR1_DQ<25> V2 B7 DDR0_DQ<25> V21
70 10 BI DDR0_DQ[25] DDR1_DQ[25] BI 10 70 1.0UF 1.0UF 0.1UF 0.1UF 100PF D3 W6
20% 20% 20% 20% 5% W19
70 10 DDR1_DQ<26> V3 DDR0_DQ[26] DDR1_DQ[26] C7 DDR0_DQ<26> 10 70 6.3V 6.3V 6.3V 6.3V 16V D5 W7
BI BI X5R 2 X5R 2 X5R-CERM 2 X5R-CERM 2 NP0-C0G 2
V4 D7 Y11
DDR1_DQ<27> DDR0_DQ<27>

in
70 10 BI DDR0_DQ[27] DDR1_DQ[27] BI 10 70 0201-1 0201-1 01005 01005 01005 E1 Y1
W2 B6 Y18
70 10 BI DDR1_DQ<28> DDR0_DQ[28] DDR1_DQ[28] DDR0_DQ<28> BI 10 70 E14 Y10
Y20
70 10 BI DDR1_DQ<29> W3 DDR0_DQ[29] DDR1_DQ[29] C6 DDR0_DQ<29> BI 10 70 E15 Y12
Y3 B5 Y21
70 10 BI DDR1_DQ<30> DDR0_DQ[30] DDR1_DQ[30] DDR0_DQ<30> BI 10 70 E6 Y13
70 10 DDR1_DQ<31> Y4 DDR0_DQ[31] DDR1_DQ[31] C5 DDR0_DQ<31> 10 70 E7 Y16
BI BI
72 15 14 =PP1V2_S2R_DDR H20
E9 Y2
K4 DDR0_PDQS[0] K18
70 10 BI DDR1_DQS_P<0> DDR1_PDQS[0] D15 DDR0_DQS_P<0> BI 10 70 CRITICAL F18 Y7
C1660 1 C1665 1 C1666 1 C1668 1 C1669 1 M18

h
70 10 DDR1_DQS_N<0> L4 DDR0_NDQS[0] DDR1_NDQS[0] D14 DDR0_DQS_N<0> 10 70 F19 Y8
BI BI
15UF 1UF 1UF 1.0UF 1.0UF N18
20% 10% 10% 20% 20%
4V 6.3V 6.3V 6.3V 6.3V T18
70 10 DDR1_DQS_P<1> N4 DDR0_PDQS[1] DDR1_PDQS[1] D12 DDR0_DQS_P<1> 10 70 CERM 2 CERM 2 CERM 2 X5R 2 X5R 2
BI BI
N3 DDR0_NDQS[1] 0402 402 402 0201-1 0201-1 V12 VDDCA
70 10 BI DDR1_DQS_N<1> DDR1_NDQS[1] C12 DDR0_DQS_N<1> BI 10 70
V13
B B

.c
G3 DDR0_PDQS[2] V15
70 10 BI DDR1_DQS_P<2> DDR1_PDQS[2] C18 DDR0_DQS_P<2> BI 10 70
V9
70 10 BI DDR1_DQS_N<2> G4 DDR0_NDQS[2] DDR1_NDQS[2] D18 DDR0_DQS_N<2> BI 10 70
Y17

70 10 BI DDR1_DQS_P<3> U4 DDR0_PDQS[3] DDR1_PDQS[3] D8 DDR0_DQS_P<3> BI 10 70 C1674 1 C1675 1 C1676 1 C1679 1

DDR1_DQS_N<3> U3 DDR0_NDQS[3] DDR0_DQS_N<3> 100PF 0.1UF 0.1UF 100PF


70 10 BI DDR1_NDQS[3] C8 BI 10 70
5% 20% 20% 5%
25V 6.3V 6.3V 16V
C0G 2 X5R-CERM 2 X5R-CERM 2 NP0-C0G 2
0201 01005 01005 01005
PPVREF_DDR1_CA_DRAM P19 DDR0_VREF_CA DDR1_VREF_CA W11
w
14 PPVREF_DDR0_CA_DRAM 14

14 PPVREF_DDR1_DQ_DRAM M4 DDR0_VREF_DQ DDR1_VREF_DQ D13 PPVREF_DDR0_DQ_DRAM 14

DDR1_ZQ_DRAM U19 DDR0_ZQ DDR1_ZQ W8 DDR0_ZQ_DRAM


1 1
R1698 R1699
w

240 DDR0 AND DDR1 WERE SWAPPED INTENTIONALLY FOR ROUTING 240
1% 1%
1/32W 1/32W
MF MF
2 01005 2 01005
w

72 15 14 =PP1V2_S2R_DDR
72 15 14 =PP1V2_DDR_VDDQ
1 1
1
R1690 1
R1692 R1694 R1696
10K
1 C1694 10K
1 C1696
4.7K 1 C1690 4.7K 1 C1692 1% 0.1UF 1% 0.1UF
1% 0.1UF 1% 0.1UF 1/32W 20% 1/32W 20%
A 1/32W
MF
2 01005
20%
6.3V
2 X5R-CERM
1/32W
MF
2 01005
20%
6.3V
2 X5R-CERM
MF
2 01005
6.3V
2 X5R-CERM
01005
MF
2 01005
6.3V
2 X5R-CERM
01005 SYNC_MASTER=N/A SYNC_DATE=N/A A
01005 01005 PAGE TITLE

VOLTAGE=0.6V VOLTAGE=0.6V
VOLTAGE=0.6V
PPVREF_DDR1_CA_DRAM 14
VOLTAGE=0.6V
PPVREF_DDR0_CA_DRAM 14
DDR: CHANNEL 0 AND 1
PPVREF_DDR1_DQ_DRAM 14 PPVREF_DDR0_DQ_DRAM 14
DRAWING NUMBER SIZE

1 1
1
R1695 1 C1695
1
R1697 1 C1697 Apple Inc. 051-0301 D
R1691 1 C1691 R1693 1 C1693 10K 0.1UF 10K 0.1UF REVISION
4.7K 0.1UF 4.7K 0.1UF 1% 20% R
1% 20% 1% 20%
1%
1/32W
20%
6.3V
2 X5R-CERM
1/32W
MF
6.3V
2 X5R-CERM B.0.0
1/32W
MF 2 6.3V
X5R-CERM
1/32W
MF 2 6.3V
X5R-CERM
MF
01005 2 01005
01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH
01005 01005 2 01005
2 01005 2 01005 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 16 OF 155
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SHEET
14 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
70 10

70 10

70 10
IN
IN
IN
DDR3_CA<0>
DDR3_CA<1>
DDR3_CA<2>
H18
H19
J18
http://www.xinxunwei.com TEL:0755-61506416 QQ:1727176051 981775188
DDR0_CA[0] OMIT_TABLE
DDR0_CA[1]
DDR0_CA[2]
U1700
BGA-1
DDR1_CA[0]
DDR1_CA[1]
DDR1_CA[2]
V17
W17
V16
DDR2_CA<0>
DDR2_CA<1>
DDR2_CA<2>
IN
IN
IN
10 70

10 70

10 70
72 15 14
=PP1V2_DDR_VDDQ

J19 DRAM W16 CRITICAL CRITICAL CRITICAL CRITICAL


70 10 IN DDR3_CA<3> DDR0_CA[3] DDR1_CA[3] DDR2_CA<3> IN 10 70

DDR3_CA<4> K19 (1 OF 3) W15 DDR2_CA<4>


C1700 1 C1701 1 C1702 1 C1703 1 C1705 1 C1706 1 C1707 1 C1708 1
DDR0_CA[4] DDR1_CA[4] 15UF 15UF 4.3UF 4.3UF 1.0UF 1.0UF 1.0UF 1.0UF

CAPRI-DRAM
70 10 IN IN 10 70

70 10 IN DDR3_CA<5> R18 DDR0_CA[5] DDR1_CA[5] V10 DDR2_CA<5> IN 10 70


20% 20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 6.3V 2 6.3V 2 6.3V 2 6.3V 2
DDR3_CA<6> R19 W10 DDR2_CA<6> CERM 2 CERM 2 X5R-CERM 2 X5R-CERM 2 X5R X5R X5R X5R
70 10 IN DDR0_CA[6] DDR1_CA[6] IN 10 70 0402 0402 0610 0610 0201-1 0201-1 0201-1 0201-1
70 10 IN DDR3_CA<7> T19 DDR0_CA[7] DDR1_CA[7] W9 DDR2_CA<7> IN 10 70

70 10 IN DDR3_CA<8> T20 DDR0_CA[8] DDR1_CA[8] Y9 DDR2_CA<8> IN 10 70

70 10 IN DDR3_CA<9> U18 DDR0_CA[9] DDR1_CA[9] V8 DDR2_CA<9> IN 10 70

D 70 10 IN DDR3_CK_P M19 DDR0_CK DDR1_CK W13 DDR2_CK_P IN 10 70


D
DDR3_CK_N N19 DDR0_CKB DDR1_CKB W12 DDR2_CK_N
70 10 IN IN 10 70
C1709 1 C1710 1 C1711 1 C1715 1 C1716 1 C1719 1
70 10 IN DDR3_CKE<0> L19 DDR0_CKE[0] DDR1_CKE[0] W14 DDR2_CKE<0> IN 10 70 220PF 0.47UF 0.47UF 0.1UF 0.1UF 100PF
L18 V14 10% 20% 20% 20% 20% 5%
NC_DRAM_DDR3_CKE<1> DDR0_CKE[1] DDR1_CKE[1] NC_DRAM_DDR2_CKE<1> 10V 4V 4V 6.3V 6.3V 16V
NO_TEST=TRUE NO_TEST=TRUE X7R-CERM 2 CERM-X5R-1 2 CERM-X5R-1 2 X5R-CERM 2 X5R-CERM 2 NP0-C0G 2
01005 201 201 01005 01005 01005
SEG: OK TO FLOAT CKE AND CS PINS SEG: OK TO FLOAT CKE AND CS PINS

70 10 IN DDR3_CSN<0> L20 DDR0_CS[0] DDR1_CS[0] Y14 DDR2_CSN<0> IN 10 70

NC_DDR3_CS<1> NO_TEST=TRUE K20 DDR0_CS[1] DDR1_CS[1] Y15 NC_DDR2_CS<1> NO_TEST=TRUE

70 10 IN DDR3_DM<0> L3 DDR0_DM[0] DDR1_DM[0] C14 DDR2_DM<0> IN 10 70

70 10 DDR3_DM<1> N2 DDR0_DM[1] DDR1_DM[1] B12 DDR2_DM<1> 10 70

m
IN IN
70 10 DDR3_DM<2> G2 DDR0_DM[2] DDR1_DM[2] B18 DDR2_DM<2> 10 70
IN IN
70 10 DDR3_DM<3> T4 DDR0_DM[3] DDR1_DM[3] D9 DDR2_DM<3> 10 70
IN IN
72 14 =PP1V8_S2R_DDR AA19 OMIT_TABLE A10 A1 OMIT_TABLE F20
H3 C17 B13 U1700 A12 A18 F21
70 10 BI DDR3_DQ<0> DDR0_DQ[0] DDR1_DQ[0] DDR2_DQ<0> BI 10 70
CRITICAL U1700
H4 D17 1 1 1 1 1 C2 CAPRI-DRAM A15 A2 G1
70 10 BI DDR3_DQ<1> DDR0_DQ[1] DDR1_DQ[1] DDR2_DQ<1> BI 10 70 C1720 C1725 C1726 C1728 C1729 BGA-1
CAPRI-DRAM
DDR3_DQ<2> J2 B16 15UF 1UF 1UF 1.0UF 1.0UF C3 A16 A20 BGA-1 G18
DDR2_DQ<2>

o
70 10 BI DDR0_DQ[2] DDR1_DQ[2] BI 10 70
20% 10% 10% 20% 20% DRAM
J3 C16 4V 6.3V 6.3V 6.3V 6.3V G19 A19 A21 DRAM G20
70 10 BI DDR3_DQ<3> DDR0_DQ[3] DDR1_DQ[3] DDR2_DQ<3> BI 10 70 CERM 2 CERM 2 CERM 2 X5R 2 X5R 2 (2 OF 3)
J4 D16 0402 402 402 0201-1 0201-1 M2 B14 A3 (3 OF 3) G21
70 10 BI DDR3_DQ<4> DDR0_DQ[4] DDR1_DQ[4] DDR2_DQ<4> BI 10 70
J5 E16 P18 VDD1 C19 A4 H2
70 10 BI DDR3_DQ<5> DDR0_DQ[5] DDR1_DQ[5] DDR2_DQ<5> BI 10 70

DDR3_DQ<6> K2 B15 V11 C21 A5 J20


70 10 BI DDR0_DQ[6] DDR1_DQ[6] DDR2_DQ<6> BI 10 70

.c
DDR3_DQ<7> W20 D4
70 10 BI
K3 DDR0_DQ[7] DDR1_DQ[7] C15 DDR2_DQ<7> BI 10 70 A6 K5
DDR3_DQ<8> P3 C11 W21 D6 A8 L5
70 10 BI DDR0_DQ[8] DDR1_DQ[8] DDR2_DQ<8> BI 10 70

DDR3_DQ<9> P4 D11 DDR2_DQ<9>


C1734 1 C1735 1 C1736 1 C1739 1
Y19 E12 AA1 M20
70 10 BI DDR0_DQ[9] DDR1_DQ[9] BI 10 70
100PF 0.1UF 0.1UF 100PF VDDQ
DDR3_DQ<10> Y5 E17
R2 DDR0_DQ[10] DDR1_DQ[10] B10 DDR2_DQ<10> 5% 20% 20% 5% AA2 M3
DDR0
DDR1

70 10 BI BI 10 70 25V 6.3V 6.3V 16V


DDR3_DQ<11> R3 C10 C0G 2 X5R-CERM 2 X5R-CERM 2 NP0-C0G 2 Y6 F1 AA3 N20
70 10 BI DDR0_DQ[11] DDR1_DQ[11] DDR2_DQ<11> BI 10 70 0201 01005 01005 01005
C 70 10 BI DDR3_DQ<12>
DDR3_DQ<13>
R4
R5
DDR0_DQ[12]
DDR0_DQ[13]
DDR1_DQ[12]
DDR1_DQ[13]
D10
E10
DDR2_DQ<12>
DDR2_DQ<13>
BI 10 70
AA18
F3
H5
AA6
AA7
P2
R20
C

x
70 10 BI BI 10 70
T2 B9 AA20 J1 B1 T5
70 10 BI DDR3_DQ<14> DDR0_DQ[14] DDR1_DQ[14] DDR2_DQ<14> BI 10 70
T3 72 15 14 =PP1V2_S2R_DDR AA21 K1
70 10 BI DDR3_DQ<15> DDR0_DQ[15] DDR1_DQ[15] C9 DDR2_DQ<15> BI 10 70 B11 U1
E2 B20 CRITICAL CRITICAL CRITICAL AA4 L2 B17 VSS VSS U20
70 10 BI DDR3_DQ<16> DDR0_DQ[16] DDR1_DQ[16] DDR2_DQ<16> BI 10 70
C1746 1
DDR3_DQ<17> E3 C20 DDR2_DQ<17>
C1740 1 C1742 1 C1743 1 C1745 1
AA5 N1 B2 V18
DDR0_DQ[17] DDR1_DQ[17] 1UF

fi
70 10 BI BI 10 70
15UF 4.3UF 4.3UF 1UF 10% B3 N5
70 10 BI DDR3_DQ<18> E4 DDR0_DQ[18] DDR1_DQ[18] D20 DDR2_DQ<18> BI 10 70
20%
4V
20%
4V
20%
4V
10%
6.3V 6.3V B21 V19
CERM 2 X5R-CERM 2 X5R-CERM 2 CERM 2 CERM 2 B4 R1
70 10 DDR3_DQ<19> E5 DDR0_DQ[19] DDR1_DQ[19] E20 DDR2_DQ<19> 10 70 402 C1 V5
BI BI 0402 0610 0610 402
F2 B19 E13 W4 C13 V6
70 10 BI DDR3_DQ<20> DDR0_DQ[20] DDR1_DQ[20] DDR2_DQ<20> BI 10 70
E21
70 10 BI DDR3_DQ<21> F4 DDR0_DQ[21] DDR1_DQ[21] D19 DDR2_DQ<21> BI 10 70 C4 V7
F5 E19 M5 D1 W1
70 10 BI DDR3_DQ<22> DDR0_DQ[22] DDR1_DQ[22] DDR2_DQ<22> BI 10 70 VDD2

a
DDR3_DQ<23> G5 E18 DDR2_DQ<23> P20 D2 W18
70 10 BI DDR0_DQ[23] DDR1_DQ[23] BI 10 70

DDR3_DQ<24> U2 B8 DDR2_DQ<24> V20 D21 W5


70 10 BI DDR0_DQ[24] DDR1_DQ[24] BI 10 70
C1748 1 C1749 1 C1755 1 C1756 1 C1759 1
DDR3_DQ<25> V2 B7 DDR2_DQ<25> V21 D3 W6
70 10 BI DDR0_DQ[25] DDR1_DQ[25] BI 10 70 1.0UF 1.0UF 0.1UF 0.1UF 100PF
20% 20% 20% 20% 5% W19
70 10 DDR3_DQ<26> V3 DDR0_DQ[26] DDR1_DQ[26] C7 DDR2_DQ<26> 10 70 6.3V 6.3V 6.3V 6.3V 16V D5 W7
BI BI X5R 2 X5R 2 X5R-CERM 2 X5R-CERM 2 NP0-C0G 2
V4 D7 Y11 E1 Y1
DDR3_DQ<27> DDR2_DQ<27>

in
70 10 BI DDR0_DQ[27] DDR1_DQ[27] BI 10 70 0201-1 0201-1 01005 01005 01005
W2 B6 Y18 E14 Y10
70 10 BI DDR3_DQ<28> DDR0_DQ[28] DDR1_DQ[28] DDR2_DQ<28> BI 10 70
Y20
70 10 BI DDR3_DQ<29> W3 DDR0_DQ[29] DDR1_DQ[29] C6 DDR2_DQ<29> BI 10 70 E15 Y12
Y3 B5 Y21 E6 Y13
70 10 BI DDR3_DQ<30> DDR0_DQ[30] DDR1_DQ[30] DDR2_DQ<30> BI 10 70

70 10 DDR3_DQ<31> Y4 DDR0_DQ[31] DDR1_DQ[31] C5 DDR2_DQ<31> 10 70 E7 Y16


BI BI
72 15 14 =PP1V2_S2R_DDR H20 E9 Y2
K4 DDR0_PDQS[0] K18
70 10 BI DDR3_DQS_P<0> DDR1_PDQS[0] D15 DDR2_DQS_P<0> BI 10 70 CRITICAL F18 Y7
C1760 1 C1765 1 C1766 1 C1768 1 C1769 1 M18

h
70 10 DDR3_DQS_N<0> L4 DDR0_NDQS[0] DDR1_NDQS[0] D14 DDR2_DQS_N<0> 10 70 F19 Y8
BI BI
15UF 1UF 1UF 1.0UF 1.0UF N18
20% 10% 10% 20% 20%
4V 6.3V 6.3V 6.3V 6.3V T18
70 10 DDR3_DQS_P<1> N4 DDR0_PDQS[1] DDR1_PDQS[1] D12 DDR2_DQS_P<1> 10 70 CERM 2 CERM 2 CERM 2 X5R 2 X5R 2
BI BI
N3 DDR0_NDQS[1] 0402 402 402 0201-1 0201-1 V12 VDDCA
70 10 BI DDR3_DQS_N<1> DDR1_NDQS[1] C12 DDR2_DQS_N<1> BI 10 70
V13
B B

.c
G3 DDR0_PDQS[2] V15
70 10 BI DDR3_DQS_P<2> DDR1_PDQS[2] C18 DDR2_DQS_P<2> BI 10 70
V9
70 10 BI DDR3_DQS_N<2> G4 DDR0_NDQS[2] DDR1_NDQS[2] D18 DDR2_DQS_N<2> BI 10 70
Y17

70 10 BI DDR3_DQS_P<3> U4 DDR0_PDQS[3] DDR1_PDQS[3] D8 DDR2_DQS_P<3> BI 10 70 C1774 1 C1775 1 C1776 1 C1779 1

DDR3_DQS_N<3> U3 DDR0_NDQS[3] DDR2_DQS_N<3> 100PF 0.1UF 0.1UF 100PF


70 10 BI DDR1_NDQS[3] C8 BI 10 70
5% 20% 20% 5%
25V 6.3V 6.3V 16V
C0G 2 X5R-CERM 2 X5R-CERM 2 NP0-C0G 2
0201 01005 01005 01005
PPVREF_DDR3_CA_DRAM P19 DDR0_VREF_CA DDR1_VREF_CA W11
w
15 PPVREF_DDR2_CA_DRAM 15

15 PPVREF_DDR3_DQ_DRAM M4 DDR0_VREF_DQ DDR1_VREF_DQ D13 PPVREF_DDR2_DQ_DRAM 15

DDR3_ZQ_DRAM U19 DDR0_ZQ DDR1_ZQ W8 DDR2_ZQ_DRAM


1 1
R1798 R1799
w

240 240
1% DDR2 AND DDR3 WERE SWAPPED INTENTIONALLY FOR ROUTING 1%
1/32W 1/32W
MF MF
2 01005 2 01005
w

72 15 14 =PP1V2_S2R_DDR
72 15 14 =PP1V2_DDR_VDDQ