VLSI Eng CMOS Process 20100210 PDF

EC31004 VLSI Engineering (Spring 2009-10) Spring 2009-10
EC31004 VLSI Engineering Notes

Filename: VLSI_Eng_CMOS_Process_<date>.doc
Content
1. CMOS inverter: device perspective ........................................................................................................................5
1.1. Fabrication steps ...............................................................................................................................................6
1.1.1. Photolithography or Lithography ...............................................................................................................6
1.1.2. Oxidation..................................................................................................................................................10
1.1.3. Poly-Si deposition ....................................................................................................................................12
1.1.4. Ion-implantation .......................................................................................................................................12
1.1.5. Metallization ............................................................................................................................................13
1.1.6. Forming a transistor (NMOSFET) ...........................................................................................................26
1.1.7. Isolation methods .....................................................................................................................................32
1.1.8. Shallow Trench Isolation (STI) process ...................................................................................................33
1.2. MOS Capacitor ...............................................................................................................................................39
1.2.1. MOS capacitor with gate-voltage .............................................................................................................41
2. CMOS inverter: circuit perspective.......................................................................................................................47
2.1. Static input-output transfer curve characterization .........................................................................................48
2.1.1. Noise-margin and noise-immunity ...........................................................................................................51
Last updated: 10 Feb 2010 (working document)
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2.1.2. Input impedance of receiver gate .............................................................................................................54

2.1.3. Output impedance of driver gate ..............................................................................................................55
2.1.4. The regenerative property ........................................................................................................................56
2.1.5. Fan-in .......................................................................................................................................................58
2.1.6. Fan-out .....................................................................................................................................................59
2.1.7. Directivity ................................................................................................................................................60
2.2. CMOS inverter dynamic characterization.......................................................................................................61
2.2.1. Output voltage swing ...............................................................................................................................62
2.2.2. Propagation delay, rise-time and fall-time................................................................................................63
2.2.3. Power-dissipation .....................................................................................................................................67
3. MOS FET: I-V characteristics ..............................................................................................................................71
3.1. Depletion or cut-off region of operation .........................................................................................................71
3.2. Active region of operation ..............................................................................................................................72
3.3. Saturation region of operation ........................................................................................................................76
3.3.1. Channel length modulation ......................................................................................................................79
3.3.2. Threshold voltage variation......................................................................................................................83
3.3.3. Velocity saturation effect .........................................................................................................................85
3.4. Transconductance of MOS device ..................................................................................................................88
3.5. On-resistance of MOS device .........................................................................................................................89
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3.6. Capacitance in MOS device............................................................................................................................91

4. CMOS Inverter: I-V characteristics ....................................................................................................................100
4.1. Static output-high voltage (VOH) and output-low voltage (VOL) ...................................................................100
4.2. Inverter switching threshold voltage.............................................................................................................100
4.3. Static input-high voltage (VIH) and output-low voltage (VIL) .......................................................................102
4.4. Switching time..............................................................................................................................................105
4.4.1. High-to-low switching time....................................................................................................................105
4.4.2. Low-to-high switching time ...................................................................................................................111
4.4.3. Maximum switching frequency..............................................................................................................113
4.4.4. Propagation delay...................................................................................................................................114
4.4.5. RC modelling .........................................................................................................................................117
4.4.6. CMOS inverter capacitance: estimation of COUT ....................................................................................118
4.5. Design of inverter .........................................................................................................................................120
4.5.1. Symmetrical inverter design...................................................................................................................120
4.5.2. Equal-sized MOSFET inverter design....................................................................................................121
4.5.3. Design of inverter for load .....................................................................................................................122
4.6. Various single-ended inverter / inverting amplifier configurations ..............................................................124
4.6.1. Push-pull inverter / inverting amplifier ..................................................................................................124
4.6.2. Inverter / inverting amplifier using NMOS driver..................................................................................129
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1. CMOS inverter: device perspective
Gate oxide
Poly-Si Gate
W
Source Drain Field-Oxide (SiO2)

n+ n+
L
p substrate
Bulk or Body
Figure 1-1. Cross-section of an N-channel enhancement MOSFET (LOCOS fabrication process)
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1.1. Fabrication steps
1.1.1. Photolithography or Lithography
 Photo-mask / mask:
o High-quality glass containing opaque (chromium) patterns
o Masks having patterns are created at the very end of the design phase using CAD tool  mask
generation / ‘tape-out’
o Each reticle (die-reticle) of mask (which is meant for single instance of IC) repeated two-
dimensionally across the entire Si wafer surface
 Photoresist / resist:
o Polymer sensitive to UV light
o Positive photresist dissolves when exposed to UV light
o Negative photoresist hardens when exposed to UV light
 Etching:
o Reactive Ion Etching: Gaseous mixture to remove material which are not covered by the photoresist
6
Figure 1-2. (a) SiO2 is grown on Si substrate by oxidation process and (b) SiO2 layer is covered with
photoreist or resist
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Figure 1-3. positive photoreist is selectively removed
8
Figure 1-4. Exposed SiO2 is chemically etched away
9
Figure 1-5. Photoresist is dissolved away to leave an etched pattern on Si
1.1.2. Oxidation
1.1.2.1. Thermal Oxidation
 Dry oxidation at elevated temperature

o 900 – 1100 degree C
o Si + O2  SiO2
o Slower process compared to wet oxidation
 Wet oxidation using steam
o Si + 2H2O  SiO2 + 2H2
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o Faster oxide growing process compared to dry oxidation

o Lower quality oxide than dry oxidation
 For both dry / wet oxidation:

o Oxidation process slows down as the SiO2 thickness increases
o Growing thick-oxide or Field-Oxide (FOX) becomes a slow / costly step
o Reduction of volume when SiO2 is created
 NSi  5 x 1022 / cm3 and NSiO2  2.3 x 1022 / cm3
 For a given area of Silicon, depth increase of 2.3/5 = 45 %
1.1.2.2. CVD (Chemical Vapour Decomposition) Oxidation
 Chemically deposited SiO2: Does not consume substrate Si

o SiH4 + 2O2  SiO2 + 2H2O
o At 1000 deg C
o Insulation between Metal interconnect layers
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1.1.3. Poly-Si deposition
 Poly-Si or Poly deposition:

o SiH4  Si (poly-crystalline) + 2H2
o Used as the Gate material of the MOSFETs and as the interconnects between the Gates
o In addition Metal Silicide (e.g. Tungsten silicide (WSi2) or Titanium silicide (TiSi2)) are used to
improve conductivity of Poly-Si interconnects
 In pre-VLSI era, Al used to be the gate-material
o Al gate had problems in miniaturization  improved by the use of Poly-Si (an additional interconnect
layer without introducing metallization)
1.1.4. Ion-implantation
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 Accelerated n-type (Arsenic, As or Phosphorus, P) or p-type (Boron, B) ions are impinged on Si substrate
o Ions are stopped by Si crystal structure  damage of the Si structure
o Thermal annealing diffuses the implanted ions and repairs the Substrate Si structure (the regular
geometric arrangement of atoms) by substituting Si atoms with implanted ions at the implanted sites.
1.1.5. Metallization
 Interconnect layers:
o Depending on the fabrication process, 4 to 8 metal interconnect layers
o Al interconnect (easier to deposit at relatively lower temperature and adheres well on SiO2)
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o Cu interconnect as an alternative (difficult integration process compared to Al) offering higher

conductivity
 Metallization example:
Figure 1-6. An NMOS transistor (STI process shown)
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Figure 1-7. Metal-1 depostion
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Figure 1-8. Metal-1 etching for forming all Metal-1 layer interconnects
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Figure 1-9. Inter-layer SiO2 deposition for isolating Metal-1 and Metal-2 layers
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Figure 1-10. Via etching for connecting Metal-1 interconnects to Metal-2 interconnects at required locations
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Figure 1-11. Metal-2 layer deposition
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Figure 1-12. Metal-2 etching to form all interconnects in Metal-2 layer (Note: Metal-2 interconnect routing
is kept in perpendicular direction to w.r.t. Metal-1 interconnect routing for reducing inter-layer stray cap.)
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Figure 1-13. Inter-layer SiO2 deposition for isolating Metal-2 layer and the higher layer
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Figure 1-14. Via etching for connecting Metal-2 interconnects to higher-layer interconnects at required
locations
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Figure 1-15. higher-layer metal deposition
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Figure 1-16. higher-layer interconnect etching (in perpendicular direction to adjacent metal layers)
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Figure 1-17. Top dielectric and passivation layer and die-pad opening (showing 3-Metal process as example)
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1.1.6. Forming a transistor (NMOSFET)
Figure 1-18. Field-Oxide isolation areas are formed first, within which exposed islands are available for
forming the NMOSFETs
Figure 1-19. Forming thin gate-oxide (SiO2) and the poly-Si gate: step - 1
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- Poly-Si
- SiO2 (Thin-OX)
- SiO2 (Field Oxide)
- Si substrate (p-type)
Poly-Si (Gate)
- SiO2 (Thin-OX)
- SiO2 (Field Oxide)
- Si substrate (p-type)
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Figure 1-23. Forming Drain and Source regions using n+ diffusion
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Figure 1-24. Insulating the Poly-Si Gate and poly-Si interconnects before metal contacts to active areas can
be formed
Figure 1-25. Forming metal contacts to active-areas
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Figure 1-26. CMOS IC: side view (shown to relative scale)
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1.1.7. Isolation methods
 LOCOS: LOCAL Oxidation of Si

o Used to be most common
o Oxide encroachment into the width of the FETs (one of the drawbacks)
 STI: Shallow Trench Isolation
o Newer and more complex fabrication steps than LOCOS
Figure 1-27. NMOS and PMOS FETs using Field-Oxide (FOX) isolation in LOCOS process
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Figure 1-28. NMOS and PMOS FETs using trench isolation in STI process
 Silicon wafer
o Crystalline Si
o With current technology, 200mm (8-inch) wafers are common
o To prevent CMOS latch up, heavy doping of the substrate
o Epitaxy layer is lightly doped (helps forming buried layer in BJT / BiCMOS process)
1.1.8. Shallow Trench Isolation (STI) process
 Si wafer as starting material
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 Forming epitaxial layer on native wafer

 Isolation processing and defining Field region
 Threshold (VT) adjustment ion-implants: nFET and pFET threshold adjustment separately
 Gate oxidation
 Poly-Si deposition and gate formation
 Single type of gate for earlier CMOS technology: either n+ or p+ for a process
 Dual-gate (both p+ and n+ types) for recent technology
 Source and Drain implantation
 Contacts and metallization
 Metal-Silicide (e.g. TiSi2 or WSi2 or TaSi2) materials for good ohmic contacts to Gate and Drain/Source
 Via and multi-layer interconnects
o Al in older technology
o Cu in newer technology (more difficult fabrication steps than with Al)
o Current technology: upto 8 metal layers
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Figure 1-29. STI process: Pad-oxide growth and Nitride deposition
Figure 1-30. STI process: Pad-oxide removal and shallow-trench etchting
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Figure 1-31. STI process: SiO2 deposition (or Poly)
Figure 1-32. STI process: After oxide and nitride removal
Figure 1-33. STI process: After oxide and nitride removal
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Figure 1-34. Top-view and channel-length side-view and channel-width side-view of NMOS FET
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Figure 1-35. Layout, cross-section and circuit-diagram of CMOS inverter

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1.2. MOS Capacitor
 Si + O2  SiO2
o SiO2 : insulator
o Resistivity = 1012 ohm-cm
o Die-electric constant,  = 3.97 0, where 0 = 8.854 F/cm2
Figure 1-36. Cross-section of MOS capacitor

 For parallel plate capacitors
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 Electrical field, E = V / d [in V/cm], where d = plate separation

 Stored charge, Q = C V [in Coulomb]
o C =  A / d, where A = area of the plate,  = dielectric constant (in F/cm)
 For MOS gate-to-channel capacitor per unit area (assuming all charge in surface of Si)
o COX = OX / XOX [in F / cm2]
o Smaller XOX is desired for greater electric field – enhances the ‘field-effect’ of the MOSFET
o Typically (present manufacturing technology), XOX ≤ 100 Angstrom (1 Angstrom = 1E-10 m)
 Example: XOX = 80 Angstrom

o COX = 4.32 E-7 F/cm2
Suppose the area of the Gate-metal = 1 um x 1um
C = COX A = 4.32 fF (femto-farad)  per um2 value for 80 angstrom XOX case
o Suppose V = 1V
Stored charge, Q = 4.32 Coulomb [C]
No. of electrons
= Q / e, where e = 1.602 E-19 Coulomb
= 2.7 E+4 electrons ~ 104 electrons  per um2 per Volt gate-voltage value for 80 angstrom XOX case
o No. of electrons as field-induced carrier are not that many
Noise consideration is important
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 In pure (intrinsic) Si, n = p = ni2 = 1.45 E+10 cm-3, at 300K
1.2.1. MOS capacitor with gate-voltage
+VG
V(x)
poly-Si Gate VG
VOX + xOX
- X=0
+ S= QS/COX
S
- p (NA) Si
E(x) = dV(x)/dx
x
Surface charge, QS
Figure 1-37. MOS capacitor voltage distribution

 Field-effect due to the application of VG, VG > 0
o VG = VOX + S, S = the surface potential [in V]
o Surface charge density, QS = COX S [ in C/cm3 ]
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0 < +VG < VTn
V(x)
poly-Si Gate VG
VOX + xOX
- X=0
+ - - - - - - S
S
- p (NA) Si
E(x) = -dV(x)/dx
x
Ionized acceptors
Bulk charge, QB S= QS/COX QB/COX
Figure 1-38. At the on-set of inversion in MOS capacitor

 For 0 < VG < VTn (depletion mode)
o Bulk-charge or depletion charge (QB) build-up because of the acceptors atoms ionized with electrons
o Immobile charges
o QB = - sqrt(2q Si NA S)
 In depletion mode, charge in the surface (QS) made up entirely by the bulk-charge, QS  QB
o S = QS / COX = sqrt(2q Si NA S) / COX
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0 < +VG < VTn Excess (inversion

layer) electron, Qn
V(x)
poly-Si Gate VG
VOX + xOX
- - - - - - - - - - - X=0
+ - - - - - - S
S
- p (NA) Si
E(x) = dV(x)/dx
x
Ionized acceptors
Bulk charge, QB S= QS/COX = (QB+ Qn)/COX
Figure 1-39. On-set of inversion in MOS capacitor
 For VG = VTn (on-set of inversion) and VG > VTn

o Inversion layer build-up  mobile electrons (Qn)
o QS = Q B + Qn
 Current will now flow if potential applied across the inversion layer (y-dimension, along the channel length)
o Current density, J(y) = E(y),
where, conductivity,  = n qn + p qp, Qn = q n, p = 0
n  1360 cm2 / V-sec and p  480 cm2 / V-sec
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o [ Analysis of J(y) will be discussed in I-V characteristics of MOSFET]
 At on-set of inversion Qn  0 and QS = QB

o The threshold value of the surface potential (S) needed to form this layer
 2 | F | = 2 (kT/q) ln(NA / ni), where
F = the bulk Fermi potential
kT/q = thermal voltage  25mv at 300K
ni2 = intrinsic carrier density  1.45 E+10 / cm3
 VOX = | QB | / COX = sqrt(2q Si NA (2 | F |) ) / COX
 The ideal value of threshold voltage, VTn (ideal)
= VG at (Qn = 0) condition
= S + VOX, at (Qn = 0) condition
= (2 | F |) + sqrt(2q Si NA (2 | F |) ) / COX
 Flat-band voltage, QFB (modification factor into VTn)
o Trapped charge (per unit area) inside the oxide, QOX
o Fixed charge (per unit area) at the Oxide-silicon surface, Qf
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o Work-function difference between Gate material and Substrate material, G - S

 - (kT/q) ln(NA ND, poly / ni2) for n-poly gate and p-substrate
 - (kT/q) ln(NA, poly / NA) for n-poly gate and p-substrate
o VFB = (G - S) – (Qf / COX) – (QOX / COX)
= a value characterized by the fabrication process, usually a negative value
 Modified VTn = VTn (ideal) + VFB
= ((2 | F |) + sqrt(2q Si NA (2 | F |) ) / COX ) + VFB
may become a negative value
o Threshold adjustment implant (into the substrate) is given to adjust the value for VTn, DI
= No. of implanted ions / cm2
o Threshold adjusted VTn
= ((2 | F |) + sqrt(2q Si NA (2 | F |) ) / COX ) + VFB  (qDI / COX)
 Typical working VTn for 3.3V process ~ 0.7 V
o Body bias effect on VTn
o Source-to-Body reverse-bias effectively increases the depletion charge, QB
o Modified QB = sqrt(2q Si NA (2 | F | + VSBn) )
 VTn under body-bias
= ((2 | F |) + sqrt(2q Si NA (2 | F | + VSBn) ) / COX ) + VFB  (qDI / COX)
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o VTn =  ( sqrt(2 | F | + VSBn) - sqrt(2 | F |) ), where

o Body-bias factor,  = sqrt(2q Si NA) / COX
 VTn = VT0n + VTn
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2. CMOS inverter: circuit perspective
V DD
S
G
D
V IN V O UT
D
G
S
V SS
Figure 2-1. CMOS inverter schematic
 NMOS, PMOS: 4 terminal devices

 Meaning of the direction of arrow in symbol
 Symbol of enhancement device
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2.1. Static input-output transfer curve characterization
VOUT
Gain = ∞
RIN = ∞
ROUT = 0
NMH = VDD/2 = NML
VIN
Figure 2-2. Input-output transfer-curve of inverter as an ideal switch
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Figure 2-3. CMOS inverter static characterization bench
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Figure 2-4. Static input-output transfer curve of inverter in general

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2.1.1. Noise-margin and noise-immunity
 Static noise-margin
o NMH = VOH – VIH
o NML = VIL - VOL
 VID = VIH - VIL (single-ended i/p for CMOS)
 VOD = VOH - VOL (single-ended o/p for CMOS)
o Noise-margin is resistive/current load dependant
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Figure 2-5. Reduction in noise-margin based on load-current
 Noise sources: supply noise, cross talk noise, offset voltage, etc
 Cross-talk: capacitive coupling and inductive coupling between two neighbouring wires
52
v(t)
i(t)
Figure 2-6. Capacitive-coupling and inductive-coupling
 Supply-noise:
VDD
o Effect on VOH of the driver gate

Figure 2-7. Power-supply noise
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 Offset-error example:
VDD
VDD
Figure 2-8. Offset-error due to additional resistance in current return path (GND)
o Effect on VOL (dynamic value, when circuit is switching) of driver gate
 For good noise immunity, the signal swing (= VOH - VOL) and the noise margins (NMH and NML) have to be
greater than the combined impact of fixed sources of noise
2.1.2. Input impedance of receiver gate
 Ideally, input impedance of the receiver should be infinity

 Practically:
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o The gate resistance of the driven device is finite

o MOS gate-capacitance of the driven gate
2.1.3. Output impedance of driver gate
 Ideally, the output impedance of the driver should be zero

 Practically:
o Drain-to-Source resistance of the “ON” device of the driving gate
o MOS gate-capacitance of the driven gate
o O/p capacitance of the “ON” device and the “OFF” device of the driving gate
o The interconnect-resistance, and capacitance appear as the loads
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2.1.4. The regenerative property
v0 v1 v2 v3 v4 v5 v6
3
V (v)
v0
1
v1 v2
-1
0 2 4 6 8 10
t (ns)
Figure 2-9. Regenerative property of a logic gate

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v0 v1 v2 v3 v4 v5 v6
v1 = f(v0)  v1 = finv(v2)
v3 f(v) finv(v)
v1
sqrt(
v3
finv(v) f(v)
v2 v0 v0 v2
Regenerative Gate Non-regenerative Gate
 Requirement to be regenerative:
o Transfer-curve must have a transient region with a gain (absolute value) > 1
o Gain > 1 region is surrounded by two valid regions, where the gain < 1.
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 Regenerative gate has two stable operating points.

 Non-regenerative gate has one stable operating point.
2.1.5. Fan-in
 Fan-in of a gate: the number of inputs to the gate

 The more the number of inputs,
o The larger the total area of the gates (increase in the number of transistors to realize the gate)
o The slower the switching of the gate (increase in the parasitic caps of parallel connection nodes of the
transistor, and increase in the series resistance of series-connected transistors)
Figure 2-10. Fan-in of a NAND gate
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2.1.6. Fan-out
Figure 2-11. Fan-out of an Inverter gate
 Fan-out of a gate: the number of receiver/driven gates connected to the output of the driving gate
o The larger the fan-out of the gate, the slower the output switching
 To improve the current drive capability
o Transistor may have to be up-sized
o One or more buffer / inverter may have to be inserted between the driver-gate and the driven-gate.
(Recall regenerative property) to improve (1) voltage-swing (2) rise-time and fall-time
 Example of large fan-out path: Clock-tree within an IC
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2.1.7. Directivity
 Ideally, changes in an output level should not affect unchanging inputs of the same gate: unidirectional
 Capacitive coupling between inputs and outputs exits in real circuit
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2.2. CMOS inverter dynamic characterization
Figure 2-12. CMOS inverter dynamic characterization bench using programmable switched current-load
61
Figure 2-13. Alternative dynamic characterization bench for CMOS inverter
2.2.1. Output voltage swing
 Output voltage-swing, VOD = VOH - VOL
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 Input sensitivity for switching (in saturated region), VID = VIH - VIL
 For noise-immunity in ac-coupled switching operation, VOD > VID
VOUT (V)
VOD VOD (V)
ILOAD (A)
VIN (V)
VID (V)
Figure 2-14. Alternative dynamic characterization bench for CMOS inverter
2.2.2. Propagation delay, rise-time and fall-time
2.2.2.1. Definitions
63
V in
50%
tpHL tpLH
V out
90%
50%
10% t
tf tr
Figure 2-15. Rise-time, fall-time and propagation delay
2.2.2.2. RC-modelling of the inverter output
64
R
vIN
vOUT
CL
Figure 2-16. RC modeling of the inverter output loading for tPD estimation and tR, tF estimation
 RC modeling:
o vOUT(t) = VOD (1 – exp(–t/)), where  = RC
o t = –  ln(1 – x), where x = vOUT(t) / VOD, 0 ≤ x ≤ 1
o t2 – t1 = –  ln( (1 – x2) / (1– x1) )
o Example:
for 10% - 90% time, x2 = 90% and x1 = 10%
for 0% - 50% time, x2 = 50% and x1 = 0%
 Propagation delay, tPD

= time taken to reach 50% of the of peak-to-peak o/p swing
65
= ln (2)  = 0.69 RC
 Rise-time, tR
= Time taken to reach 90% of the of peak-to-peak o/p swing from the 10%
= ln(9)  = 2.2 RC
 Fall-time, tF
= Time taken to reach 10% of the of peak-to-peak o/p swing from the 90%
= ln(9)  = 2.2 RC
2.2.2.3. Propagation delay estimation using ring-oscillator configuration
66
v0 v1 v2 v3 v4 v5
v0 v1 v5
Figure 2-17. Ring-oscillator for determination of propagation delay
 Time-period of oscillation, T = 2 * tPD * N, where N = an odd number
2.2.3. Power-dissipation
 Instantaneous power: p(t) = v(t) i(t) = Vsupply i(t)

 Peak power: Ppeak = Vsupply ipeak
o Used for sizing-up the current-supply-path (VDD) and current-return-path (GND) interconnects
o Used for setting the current compliance in the supply equipment or power-source
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R
vIN
vOUT
CL
 Energy supplied from a voltage-source to the RC network while charging =

T 2 T 2 T 2 VOH
 dv 
Ein   pin (t )dt   vin t iin t dt   VDD  C L out dt  VDD C L  dv
2
out  VDD C LVOH  C LVDD
0 0 0  dt  0
o T = the clock period

o Assuming VOH is able to reach VDD after charging, the energy supplied from the source during the
charging of CL is independent of the R
 Energy stored at CL from a voltage-source to the RC network while discharging =
T 2 T 2 T 2 VOH
 dv  1 1
 pCL (t )dt   vout t iCL t dt   0 out out 2 L OH 2 CLVDD
2 2
EC L  vout  C L out dt  C L v dv  C V 
0 0 0  dt 
o T = the clock period
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o Assuming VOH is able to reach VDD after charging, the energy stored by CL after the charging of CL is
independent of the R
o Half the energy supplied from the source is lost within the resistor during charging
T 2 T 2
 dvout  1 1
 v R t iR t dt   
 DD out L
2 2
ECL  V  v  C  dt  C V V
L DD OH  C V
L OH  C LVDD
0 0  dt  2 2
o Upon application of 0V at the input, (1/2) CL VDD2 stored in the resistor gets dissipated in the resistor
Average power:
1 T Vsupply
isupply t dt
T
T 0 
 Pavg  p (t ) dt 
0
T
 Used for determining battery-life for portable power-source
 Used for determining heat dissipation requirement
 Three components of power [in Watt]:

o Leakage power within driver (static component)
= VDD ILEAKAGE
o Power due to charging/discharging of load through output-resistance (dynamic component)
= CL VOD2 fCLOCK P01
69
where, P01 = average switching activity per clock-period, 0 ≤ P01 ≤ 1,

VOD  VDD (for CMOS, almost rail-to-rail swing)
o Device short-circuit power within driver during the switching activity (dynamic component)
= tSC VDD IPEAK fCLOCK P01
where, tSC = fraction of clock-period time VDD to GND path shorted through the transistor-stack,
P01 = average switching activity per clock-period, 0 ≤ P01 ≤ 1,
 Average Power dissipation [in Watt]
= CL VDD2 fCLOCK P01 + tSC VDD IPEAK fCLOCK P01 + VDD ILEAKAGE
 Power-Delay Product (PDP) = Pavg  tp
 Average energy dissipated for every clock-period, E [in Joule]

= CL VDD2 P01 + tSC VDD IPEAK P01 + VDD ILEAKAGE / fCLOCK
 Energy-Delay Product (EDP) = E  tp
70
3. MOS FET: I-V characteristics
3.1. Depletion or cut-off region of operation
Figure 3-1. NMOS FET in depletion region of operation

71
3.2. Active region of operation
 After the on-set of strong inversion:
72
Figure 3-2. NMOS FET in active region of operation
 The electron inversion layer mobile charge, Qn(y) [charge per unit area under the gate at y, 0  y  L]
= - [(VGSn – VTn) – V(y)] COX, where VGSn > VTn
Electric field, E(y) = -dV(y)/dy
 Two conditions necessary to establish a current flow:
o VGSn > VTn  Excess charge (inversion layer charge formation)
o VDSn > 0  Creation of an electric field across the mobile-charge (inversion) layer
 A drift current caused by the electron movement through the channel
 Channel acting as an nonlinear resistor
73
Figure 3-3. Analysis of channel current flow
 Consider the small segment of length dy along the channel
74
 ID = – vn(y) Qn(y) W
where,
o vn(y) = the drift velocity of electrons under the field E(x) established along the length (average value
of electric field = –VDS / L) [ L / s ]
vn(y) = – n E(y) = – n dV/dy
 n = surface electron mobility  approx. half of bulk electron mobility
o W = width of the channel [ m ]
o Qn(y) = charge underneath the gate-oxide per unit length [ C / m ]
Qn(y) = COX (VGS – VT – V(y))
 ID = [n dV/dy ] [ COX (VGS – VT – V(y)) ] W
 IDn dy (where, y=0 to y=L) = (n COX) W  [(VGSn – VTn) – V(y)]) dV (where, V(y=0)=0 to V(y=L)=VDSn)
 IDn = (n COX) (W/L) [(VGSn – VTn) – VDSn/2]) VDS
o Process transconductance, k’n = n COX [in A/V2]
o Device transconductance, n = k’n (W/L) [in A/V2]
75
3.3. Saturation region of operation
 Peak value of IDn w.r.t. VDSn

o IDn / VDSn = 0 = n [(VGSn – VTn) – VDSn])
o VDSn, SAT = VGSn – VTn
o IDn, SAT = n/2 (VGSn – VTn)2
 IDn does not decrease below IDn, SAT in real device, when VDSn > VDSn, SAT
 Channel pinch-off
o Qn(y=L) = 0  Channel-depth compressed to minimal thickness
o Inversion-layer height at y=L is minimal to maintain the IDn = IDn, SAT
o ‘Overdrive voltage’ = VGSn - VTn
o ‘Aspect ratio’ = W/L
76
Figure 3-4. For a fixed value of VGS, IDn vs. VDSn curve
77
Figure 3-5. Channel pinch-off in NMOS FET
78
3.3.1. Channel length modulation
Figure 3-6. Channel length modulation in NMOS FET
 For VDSn  VDSn, SAT, weak dependence on VDSn

79
o LSAT  L  pinch-off point moves toward source

L / LSAT = 1 +  (VDSn – VDSn,SAT), where  is in V-1
o  is empirically determined
o  used often in analog CMOS design  1 / ( IDn) = AC output impedance looking into the Drain
o IDn = n/2 (VGSn – VTn)2 (1 +  VDSn)
80
Figure 3-7. I-V curve for NMOS FET
81
Figure 3-8. I-V curve for NMOS FET with channel-length modulation w.r.t. VDSn
 ‘Overdrive voltage’ = VGSn - VTn

 sqrt( IDn )
= sqrt( n/2 (VGSn – VTn)2 (1 +  VDSn) )
 sqrt( n/2) (VGSn – VTn), for   0
82
sqrt(IDn)
(sub-threshold / (active)
VGSn
cut-off) VTn
Figure 3-9. NMOS FET saturation characteristics
3.3.2. Threshold voltage variation
3.3.2.1. Body-bias effect
 On-set of strong inversion when surface potential induced 2|F| = 2 * (kT/q) ln (NA / ni)
83
o F = Fermi potential, where

(kT/q) = 26 mV at 300K, ni = 1.5 x 1010 cm-3
For NA  1016, 2|F|  0.7 V
 Depletion-layer charge when Source = GND or 0V, and Body/Substrate = GND or 0V,
QB0 = [ 2 q NA si (2 |F|) ]1/2
VT0 = The threshold voltage required to sustain a QB0 amount of depletion-charge underneath the channel
(and maintain the strong-inversion layer electrons)
 Depletion-layer charge when Source > 0V, Body/Substrate = GND or 0V,
QB = [ 2 q NA si (VSB + 2 |F|) ]1/2
VT becomes higher since a higher gate-voltage required to sustain a larger amount of depletion-charge
underneath the channel
 Empirical device-modelling for VT:
VT = VT0 +  [ (VSB + 2 |F|)1/2 - (2 |F|)1/2 ]
Process parameters:
VT0 = Device threshold voltage [V]
 = Body-bias coefficient [V1/2]
84
3.3.2.2. Drain induced barrier lowering
 Threshold voltage decrease at a higher VDS bias  DIBL

 Expansion of the space-charge (QB) underneath the channel because of VDS > 0
This space-charge is not sustained by applied VGS (but by VDS)  lower VGS potential required to create
strong-inversion
 Pronounced effect for lower L (short-channel)
3.3.3. Velocity saturation effect
 Velocity-saturation of charge-carriers at high VDS

o Electron/hole mobility increases at slower rate at high electric field
o High electric-field for small L (below L=2 um)  short-channel effect
o Saturation velocity for hole and electron, vsat  107 cm/s
o For 0.25 um process, a VDS = 2V will take the MOSFET into velocity saturation region
 The drift-velocity, vn(y)
= n E(y) / [ 1 + E(y) / Ecrit ], for E(y) < Ecrit
= vsat for E(y) >= Ecrit
Ecrit = 2 vsat / n , and Ecrit lies within 1 V/um to 5 V/um
85
Figure 3-10. Velocity saturation of electron drifting under applied electric field along the channel
 Active-region operation:
IDn = (n / [ 1 + VDS / (Ecrit L)]) COX (W/L) [(VGSn – VTn) – VDSn/2]) VDS
For large L (long-channel device), [ 1 + VDS / (Ecrit L) ] approaches to 1
86
 Saturation-region operation:
IDn,SAT = (n / [ 1 + VDSn,SAT / (Ecrit L) ]) COX (W/L) [(VGSn – VTn) – VDSn,SAT/2] VDSn,SAT
where VDSn,SAT = (VGSn – VTn) / [ 1 + (VGSn – VTn) / (Ecrit L) ]
IDn
Identical VGSn
Long-channel
Short-channel
VDSn,SAT VGSn - VTn

VDSn
Figure 3-11. Velocity saturation effect on drain current for NMOS device
 IDn,SAT vs VGSn turns into a linear curve from quadratic when VGSn >> VTn
87
Simplifying the velocity-saturation:

 Approximation:
vn(y) = n E(y) for E(y) < Ecrit
= n Ecrit = vsat for E(y) > Ecrit
 Active-region operation:
IDn = n COX (W/L) [(VGSn – VTn) – VDSn/2]) VDS  identical to long-channel MOSFET
 Saturation-region operation:
IDn,SAT = n COX (W/L) [(VGSn – VTn) – VDSn,SAT/2] VDSn,SAT
where VDSn,SAT  L ECrit
3.4. Transconductance of MOS device
 In saturated region, MOS device behaving like a current source, where value of the current is governed by
the gate-bias (VGSn)
 Change in the current-value of this current source w.r.t. the change in the gate-bias  transconductance
 Transconductance, gm = IDn / VGSn
= [(n/2) (VGSn – VTn)2] / VGSn
= n (VGSn – VTn)
88
 Rewriting gm in terms of IDn

also, gm = sqrt (2 n IDn)
and, gm = 2 IDn / (VGSn – VTn)
 Extending into the linear region, gm

= [(n/2) [2(VGSn – VTn) – VDSn]) VDSn] / VGSn
= n VDSn
3.5. On-resistance of MOS device
 IDn = (n/2) [2(VGSn – VTn) – VDSn]) VDSn

 For VDSn << 2(VGSn – VTn)
IDn  n (VGSn – VTn) VDSn
 Large-signal resistance looking into the drain, Rn = VDSn / IDn
Rn = 1 / [n (VGSn – VTn) ]  Use for calculation of rise-time, fall-time (Assumption: charging / discharging
spending most of the part in non-saturation)
 On-resistance RON in linear region (looking into the drain)
89
Figure 3-12. Linear operation in deep non-saturation (‘triode’) region for the square-law model
Alternative modeling of average resistance value:

 Ravg(V2,V1)  [ Ron(V2) + Ron(V1)] / 2  Valid for linear charging/discharging behaviour
90
 Example: 50% of VDD for tPD estimation:

Ravg(VDD, VDD/2) = [ VDD / [IDn,SAT (1+  VDD)] + (VDD/2) / [IDn,SAT (1+  VDD)] ] / 2
3.6. Capacitance in MOS device
Figure 3-13. Large-signal charge-storage in MOSFET

91
Leff
Mask L
FOX
encroachment
Mask W
Weff
LD Gate
Figure 3-14. Top-view of overlap Gate-Drain and Gate-Source capacitance in MOSFET
92
Figure 3-15. Gate-Source and Gate-Drain overlap capacitance in MOSFET
93
Figure 3-16. Gate-Bulk overlap capacitance in MOSFET
 Gate-to-channel capacitance, C2
= Weff (L – 2 LD) COX = Weff (Leff) COX
 Gate-to-Drain capacitance and Gate-to-Source capacitance, C1 = C3
 COX (LD) Weff
= (CGSO) Weff or (CGDO) Weff
94
 Gate-to-Bulk capacitance, C5
= CGBO (Leff)
 Bulk-to-Channel depletion capacitance across the reverse-bias junction, C4
 OFF / Satutration / Non-saturation:

o Transistor Off:
 CGB = C2 + 2 C5 = COX Weff Leff + CGBO Leff
 CGS = C1  COX Weff LD = CGSO Weff
 CGD = C3  COX Weff LD = CGDO Weff
o Transistor in Saturation:
 CGB = 2 C5 = CGBO Leff
 CGS = C1 + (2/3) C2 = COX Weff (LD + 0.67 Leff)
= CGSO Weff + 0.67 COX Weff Leff
 CGD = C3 + (1/3) C2 = CGDO Weff + 0.33 COX Weff Leff biased near saturation/non-saturation pt.
CGD  COX Weff LD = CGDO Weff when biased well into saturation
 While using the transistor in small-signal amplification w/ constant-current source (ID,SAT) biase
o Transistor in Non-saturation
 While using the transistor as a switch  most part of the charging/discharging happening
using non-saturation current
95
 CGB = 2 C5 = CGBO Leff

 CGS = C1 + (1/2) C2 = COX Weff (LD + 0.5 Leff)
= CGSO Weff + 0.5 COX Weff Leff
 CGD = C3 + (1/2) C2 = COX Weff (LD + 0.5 Leff)
= CGDO Weff + 0.5 COX Weff Leff
96
Figure 3-17. Drain / Source geometry: the bottom capacitance and the sidewall capacitance
 Bulk-to-Drain depletion capacitance across the reverse-bias junction, CBD

 Bulk-to-Source depletion capacitance across the reverse-bias junction, CBS
97
 Bottom surface capacitance for Drain-to-Bulk surface,

Cbot = Cj0 W X,
where, WD and XD are the geometry of the Drain
Cj0 = bottom capacitance per unit area under zero reverse bias
 Sidewall surface capacitance for Drain to Bulk surface,
Cside = Cjsw 2(W + X),
where, WD and XD are the geometry of the Drain
Cjsw = sidewall capacitance per unit length under zero reverse bias
 CBD (zero-bias) = Cj0 W X + Cjsw 2(W + X)
 CBS (zero-bias) = Cj0 W X + Cjsw 2(W + X)
 Average LTI value when bias-value is varying from V1 to V2, of CBD
= 1 / (V2 – V1) Cj(V) dV, integrated from V1 to V2
 General model for Cj(V) = Cj0 / (1 + V / 0)m
where,
0m = built-in potential across the junction
Cj0 = capacitance value when the junction has zero-bias applied across it
m = 0.5  approximation for bottom, m = 0.33  approximation for sidewall
98
 Under the reverse bias VR,

CBD (VR) = Cj0 W X / (1 + VR/0) 0.5 + Cjsw 2(W + X) / sqrt(1 + VR/0sw) 0.33
 Average LTI value when bias-value is varying from V1 to V2, of CBD
CBD (V1, V2)
= 1 / (V2 – V1) Cj(VR) dVR
= Cj0 W X K0.5(V1, V2) + Cjsw 2(W + X) K0.33(V1, V2)
where,
K0.5(V1, V2) = 0 / [0.5 (V2- V1)] [(1 + V2/0) 0.5 - (1 + V1/0) 0.5]
K0.33(V1, V2) = 0 / [0.67 (V2- V1)] [(1 + V2/0) 0.67 - (1 + V1/0) 0.67]
Note: in general, Km(V1, V2) = 0 / [(1-m) (V2- V1)] [(1 + V2 /0) (1-m) - (1 + V1/0) (1-m)]
 Also,
CBS (V1, V2) = Cj0 W X K0.5(V1, V2) + Cjsw 2(W + X) K0.33(V1, V2)
 If V1 = 0V, V2 = VDD
K0.5(0V, VDD) = (2 0 / VDD) [(1 + VDD/0) 1/2 - 1]
K0.33(0V, VDD) = ((3/2) 0 / VDD)[ (1 + VDD/0) 2/3 - 1]
 CBS (0V, VDD) = Cj0 W X K0.5(0V, VDD) + Cjsw 2(W + X) K0.33(0V, VDD)
 CBD(0V, VDD) = Cj0 W X K0.5(0V, VDD) + Cjsw 2(W + X) K0.33(0V, VDD)
99
4. CMOS Inverter: I-V characteristics
4.1. Static output-high voltage (VOH) and output-low voltage (VOL)
 The largest value of VOUT : VOH

o VOUT = VDD - VSDp
o VSDp = 0 V, when IDp = 0
o VOH = VDD
 The smallest value of VOUT : VOL
o VOUT = VDSn
o VDSn = 0 V, when IDn = 0
o VOL = 0 V
 Output voltage-swing (single-ended VOD) = VOH - VOL
4.2. Inverter switching threshold voltage
 Midpoint voltage, VI, where VOUT = VIN = VI

 VGSn = VDSn = VI
VDSn > VGSn - VTn  NMOS in saturation
100
 VSGp = VSDp = VDD - VI

VSDp > VSGp - |VTp|  PMOS in saturation
 IDn, SAT = IDp, SAT
(n/2) (VGSn – VTn)2 = (p/2) (VDD - VI – |VTp|)2
 VI = [VDD - |VTp| + sqrt(n / p) VTn ] / (1 + sqrt(n / p))
 Process variation on VI
 Note: if we want to set the VI to VDD/2, then

o (VDD/2 - |VTp| ) = sqrt(n / p) (VDD/2 - VTn )
o sqrt(p) (VDD/2 - |VTp| ) = sqrt(n) (VDD/2 - VTn )
101
Figure 4-1. Switching threshold dependency on n and p
4.3. Static input-high voltage (VIH) and output-low voltage (VIL)
 On the voltage-transfer-curve, dVOUT / dVIN = -1

o VIL : NMOS is saturated and PMOS is non-saturated
o VIH : NMOS is non-saturated and PMOS is saturated
102
 VIL calculation:
o IDn (sat) = IDp (non-sat)
(n/2) (VGSn – VTn)2 = (p/2) [2(VSGp– |VTp|) – VSDp]) VSDp
o (n/2) (VIN – VTn)2 = (p/2) [2((VDD - VIN) – |VTp|) – (VDD – VOUT)]) (VDD – VOUT)
o IDn(VIN) = IDp(VIN, VOUT)
Taking differentials,
(dIDn/dVIN) dVIN = (IDp/VIN) dVIN + (IDp/VOUT) dVOUT
o dVOUT/ dVIN = [ (dIDn/dVIN) - (IDp/VIN) ] / (IDp/VOUT)
dVOUT/ dVIN = -1, at VIN = VIH
o VIN ( 1 + n / p) = 2 VOUT – VDD - |VTp| + (n / p) VTn
 VIL is obtained solving the above (highlighted) simultaneous equations in terms of VIN and VOUT,
where the first equation is of quadratic form and the second equation is of linear form
 VIH calculation:
o (n/2) [ 2(VIN – VTn) - VOUT ] VOUT = (p/2) (VDD - VIN – |VTp|)2
o IDp(VIN) = IDn(VIN, VOUT)
o dVOUT/ dVIN = [ (dIDp/dVIN) - (IDn/VIN) ] / (IDn/VOUT)
dVOUT/ dVIN = -1, at VIN = VIH
103
o VIN ( 1 + p / n) = 2 VOUT + VTn + (p / n) (VDD - |VTp| )

 VIH is obtained solving the above (highlighted) simultaneous equations in terms of VIN and VOUT,
where the first equation is of quadratic form and the second equation is of linear form
104
4.4. Switching time
4.4.1. High-to-low switching time
Figure 4-2. Sub-circuit for tHL analysis
 IDn = - COUT dVOUT/dt
105
o Assumptions:
Step-input voltage, VIN = VDD
Linear time-invariant (LTI) model for COUT
 At the beginning portion of the discharge (t  0)
o VGSn = VDD
o VOUT(t=0)  VDD  NMOS is saturated
dVOUT  n
o I Dn  COUT  VDD  VTn 2
dt 2
 A linear decay in VOUT(t) until VOUT(t) = (VDD - VTn)
 The smaller the COUT, the faster the decay
 The higher the n, the faster the decay
dVOUT
dt  COUT
 n
VDD  VTn 2
2
 Integrating from t=0, and using the lower boundary condition VOUT(t=0) = VDD
VOUT t   VDD
t  COUT
n
VDD  VTn 2
2
106
n
VDD  VTn 2
2
 VOUT (t )  VDD  t , where 0  t  t0
COUT
 Let t = t0, so that VOUT(t = t0) = (VDD - VTn)  Entry into non-saturation from saturation
o VOUT(t = t0) = (VDD - VTn) = VDD – [ n/2 (VDD – VTn)2 / COUT ] t0
COUT
t0  VTn
 n 2
 2 VDD  VTn  
o
 Toward the end of the discharge (t  t0)

dVOUT  n
o I Dn  COUT  2VDD  VTn   VDSn VDSn
dt 2
dVOUT  n
o  COUT  2VDD  VTn   VOUT VOUT
dt 2
dVOUT n
 dt
o
VOUT  2VDD  VTn VOUT 2COUT
dVOUT dV  V  V 
 OUT  n DD Tn dt
 2VDD  VTn  VOUT
o
VOUT COUT
o Integrate from t0 to t with lower boundary condition for integration: VOUT(t0) = VDD - VTn
107
  VOUT  2VDD  VTn    n VDD  VTn  t

VOUT
ln
o    
  t t0
  VOUT VDD VTn C OUT
 VOUT  2VDD  VTn  VDD  VTn    n VDD  VTn 

ln 
    t  t0 
o
 VOUT VDD  VTn   2VDD  V 
Tn  C OUT
 VOUT  2VDD  VTn   t  t0 

ln   
o
  VOUT  n
COUT
The time-constant of discharge,  n  Rn COUT 
 n VDD  VTn 
1
R 
where, n
 n VDD  VTn   non-saturation on-resitance value
VOUT  2VDD  VTn  t t0   n
e
o  VOUT
VOUT  2VDD  VTn  t t0   n
e
o  VOUT
o  
VOUT 1  e t t0   n  2VDD  VTn 
108
2e   t  t 0  /  n
VOUT (t )  VDD  VTn  
o
1  e  t  t 0  /  n
 Combining saturation and non-saturation discharging,
High-to-low switching time = time taken from V1 = (0.9 VDD) to V0 = (0.1 VDD),
 v VDD VTn
dVOUT (t )
v V0
dVOUT (t ) 
t HL   COUT   COUT  
 v V1
I Dn , SAT v VDD VTn Dn , Non  SAT 
I 
VDD VTn
 
VOUT t  V1  VDD  VTn 
v VDD VTn
dVOUT (t )  
   
n  
n
 v V1
I Dn , SAT  VDD  VTn  
2
VDD  VTn 2
 2 V1 2
109
v V0
dVOUT (t ) 1 V0  dVOUT dVOUT 

v VDD VTn
I Dn , Non  SAT  n VDD  VTn  VDD VTn VOUT  2VDD  VTn  VOUT 
   
  VOUT  2VDD  VTn  

V0
1
 ln 
 n VDD  VTn    VOUT VDD VTn
 1  V  2VDD  VTn  VDD  VTn  

  ln 0  
 n VDD  VTn   V0 VDD  VTn   2VDD  VTn  
1  2VDD  VTn   V0 
  ln 
 n VDD  VTn   V0 
 t HL  s n n
 V  V0   2VDD  VTn  
sn  2  Tn   ln   1 , where V = 0.1 V and V = V - V = 0.9 V
VDD  VTn   
0 DD 1 DD 0 DD
V0
110
4.4.2. Low-to-high switching time
Figure 4-3. Sub-circuit for tLH analysis
 IDp = - COUT dVOUT/dt

o Assumptions:
 Step-input voltage, VIN = 0V
o Linear time-invariant (LTI) model for COUT
 At the beginning of the charge (t  0)
111
o VOUT(t=0)  0 PMOS is saturated
dVOUT  p
o I Dp  COUT
dt

2
VDD  VTp  2
p
2
V DD  VTp 
2
o VOUT (t )  t
COUT
 A linear charging in VOUT(t) until VOUT(t) = (VDD - |VTp|)
 The smaller the COUT, the faster the decay
 The higher the p, the faster the decay
o Let t = t1, so that VOUT(t = t1) = |VTp|  Entry into non-saturation from saturation
o VOUT(t = t1) = [ p/2 (VDD – |VTp|)2 / COUT ] t1 = |VTp|
o t1 = |VTp| COUT / [ p/2 (VDD – |VTp|)2 ]
o VOUT(t) = [ p/2 (VDD – |VTp|)2 / COUT ] t , where 0  t  t1
 Toward the end of the charge (t  t1)
o IDp = - COUT dVOUT/dt = (p/2) [2(VDD – |VTp|) – VDSp]) VDSp
 t t1  /  p

VOUT (t )  VDD  VDD  VTp   2e
 t  t1  /  p
o
1 e
112
 The time-constant of charge, p

COUT
 p  R p COUT 
 
 p VDD  VTp , where
1
Rp 
 
 p VDD  VTp  non-saturation on-resistance value
 Combining saturation and non-saturation charging,
High-to-low switching time = time taken from V0 = (0.1 VDD) to V1 = (0.9 VDD),
t LH  s p p
 VTp  V0
s p  2

  ln 

 2 VDD  VTp  
 1
VDD  VTp   V0  , with V0 = 0.1 VDD and V1 = 0.9 VDD
 
4.4.3. Maximum switching frequency
 fMAX = 1 / (tLH + tHL)

= 1 / (sp p + sn n)
113
Figure 4-4. Output wafeforms below fMAX and above fMAX
4.4.4. Propagation delay
 tp = (tpHL + tpLH) / 2
114
 v VDD VTn
dVOUT (t )
v VDD 2
dVOUT (t ) 
t pHL   COUT   COUT  

 v VDD
I Dn , SAT I
v VDD VTn Dn , Non  SAT 
VDD VTn
 
VOUT t 
v VDD VTn
dVOUT (t )   VTn
   
n  
n
o v VDD
I Dn , SAT  VDD  VTn  
2
VDD  VTn 2
 2 VDD 2
v VDD 2
dVOUT (t ) 1 VDD 2  dVOUT dVOUT 

v VDD VTn
I Dn , Non  SAT  n VDD  VTn  VDD VTn VOUT  2VDD  VTn  VOUT 
   
VDD 2
1   VOUT  2VDD  VTn  
 ln 
 n VDD  VTn    VOUT VDD VTn
 VDD 
  2VDD  VTn  
o 
1
 ln 2 
VDD  VTn 

 n VDD  VTn   VDD VDD  VTn   2VDD  VTn  
 
 2 
1  4VDD  VTn  
  ln  1
 n VDD  VTn   VDD 
115
 tpHL = sn’ n, where,
COUT
 n  RnCOUT 
 n VDD  VTn 
2VTn  4VDD  VTn  

 ln   1
'
sn 
VDD  VTn  VDD 
 tpLH = sp’ p , where
COUT
 p  R p COUT 

 p VDD  VTp 
'
sp 
2 VTp
 ln 

 4 VDD  VTp 

 1
VDD  VTp  VDD 
 
116
Figure 4-5. Step-input and output wafeforms showing propagation delay
4.4.5. RC modelling
 tHL = t0.1 – t0.9

= n ln ( VDD / 0.1VDD) - n ln ( VDD / 0.9VDD)
= n ln(9)
 tLH = t0.9 – t0.1
= p ln(9)
117
 fMAX = 1/ [ln(9) (n + p)]  0.45 / (n + p)

 tpHL = n ln (VDD / 0.5 VDD)
= n ln(2)
 tpLH = p ln (VDD / 0.5 VDD)
= p ln(2)
 tp = 0.5 ( tpHL + tpLH )  0.347 (n + p)
4.4.6. CMOS inverter capacitance: estimation of COUT
Figure 4-6. CMOS inverter capacitance : estimating COUT
118
 Objective: Linear time-invariant (LTI) modelling of COUT for design/analysis of switching-time

 COUT = CINT + CLOAD
 Internal capacitance of the driver during o/p switching,
CINT = (CGDn + CGDp) + (CDBn + CDBp)
 Load capacitance to the driver o/p,
CLOAD = CLINE + CFO
 CGD  CGDO Weff + 0.5 COX Weff Leff
 Average value (during charging/discharging between VOH and VOL) of the depletion capacitance, CDB
CBD (VOL, VOH) = Cj0 W X K0.5(VOL, VOH) + Cjsw 2(W + X) K0.33(VOL, VOH)
where,
Km(VOL, VOH) = 0 / [(1-m) (VOH - VOL)] [(1 + VOH /0) (1-m) - (1 + VOL/0) (1-m)]
W and X are the geometry of the Drain
 Assuming VOL = 0V and VOH = VDD
CBD (0, VDD) = (2 0 / VDD) [ (1 + VDD / 0)0.5 – 1] + (3 0 / 2 VDD) [ (1 + VDD / 0sw)0.67 – 1]
119
 Interconnect line capacitance, CLINE = (OX / XINT) w D

XINT = thickness of the oxide between the line and the substrate
w = width of the interconnect
D = distance of the interconnect
 Fan-out capacitance, CFO = NFO (CGn + CGp)

where, NFO = fan-out of the driving gate
CGn = COX Wn Ln (geometric lengths are used)
CGp = COX Wp Lp (geometric lengths are used)
4.5. Design of inverter
4.5.1. Symmetrical inverter design
 VI = VDD/2
 If VTn  |VTp|
o  n  p
 (W/L)p = (kn’ / kp’) (W/L)n
o VIL = (1/4) [VTn + (3/4) VDD]
120
o VIH = (1/4) [(5/2)VTn - VDD]

 Also,
VIL + VIH = VDD
Noise margin, VNMH = VNML = (1/4) [VTn + (3/4) VDD]
tLH = tHL
Figure 4-7. CMOS inverter: symmetric design
4.5.2. Equal-sized MOSFET inverter design
 n / p = kn’ / kp’
 VI = [VDD - |VTp| + sqrt(kn’ / kp’) VTn ] / (1 + sqrt(kn’ / kp’))
121
o VI < 0.5 VDD, for VTn  |VTp|

o VNMH > VNML
o tLH > tHL
Figure 4-8. CMOS inverter: equal-sized MOSFET design
4.5.3. Design of inverter for load
 tHL = (sn nINT) + (sn nL) = (sn Rn) CINT + (sn Rn) CL
 tLH = (sp pINT) + (sp pL) = (sp Rp) CINT + (sp Rp) CL
122
o CL and the required tHL and tLH are the design specifications
o Wn, Ln, Wp, Rp are the design variables
Figure 4-9. CMOS inverter: switching time vs. load capacitance
 nL = CL / [ kn’(W/ L)n (VDD - VTn)]

 pL = CL / [ kp’(W/ L)p (VDD - VTp)]
123

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EC31004 VLSI Engineering (Spring 2009-10) Spring 2009-10

EC31004 VLSI Engineering Notes

2.1.2. Input impedance of receiver gate .............................................................................................................54

3.6. Capacitance in MOS device............................................................................................................................91

1. CMOS inverter: device perspective

Source Drain Field-Oxide (SiO2)

Figure 1-1. Cross-section of an N-channel enhancement MOSFET (LOCOS fabrication process)

Last updated: 10 Feb 2010 (working document)

1.1. Fabrication steps

1.1.1. Photolithography or Lithography

Last updated: 10 Feb 2010 (working document)

Last updated: 10 Feb 2010 (working document)

Figure 1-3. positive photoreist is selectively removed

Last updated: 10 Feb 2010 (working document)

Figure 1-4. Exposed SiO2 is chemically etched away

Last updated: 10 Feb 2010 (working document)

Figure 1-5. Photoresist is dissolved away to leave an etched pattern on Si

1.1.2.1. Thermal Oxidation

 Dry oxidation at elevated temperature

Last updated: 10 Feb 2010 (working document)

o Faster oxide growing process compared to dry oxidation

 For both dry / wet oxidation:

1.1.2.2. CVD (Chemical Vapour Decomposition) Oxidation

 Chemically deposited SiO2: Does not consume substrate Si

Last updated: 10 Feb 2010 (working document)

1.1.3. Poly-Si deposition

 Poly-Si or Poly deposition:

Last updated: 10 Feb 2010 (working document)

Last updated: 10 Feb 2010 (working document)

o Cu interconnect as an alternative (difficult integration process compared to Al) offering higher

Figure 1-6. An NMOS transistor (STI process shown)

Last updated: 10 Feb 2010 (working document)

Figure 1-7. Metal-1 depostion

Last updated: 10 Feb 2010 (working document)

Last updated: 10 Feb 2010 (working document)

Last updated: 10 Feb 2010 (working document)

Last updated: 10 Feb 2010 (working document)

Figure 1-11. Metal-2 layer deposition

Last updated: 10 Feb 2010 (working document)

Last updated: 10 Feb 2010 (working document)

Last updated: 10 Feb 2010 (working document)

Last updated: 10 Feb 2010 (working document)

Figure 1-15. higher-layer metal deposition

Last updated: 10 Feb 2010 (working document)

Last updated: 10 Feb 2010 (working document)

Last updated: 10 Feb 2010 (working document)

1.1.6. Forming a transistor (NMOSFET)

Last updated: 10 Feb 2010 (working document)

Last updated: 10 Feb 2010 (working document)

Last updated: 10 Feb 2010 (working document)

Figure 1-23. Forming Drain and Source regions using n+ diffusion

Last updated: 10 Feb 2010 (working document)

Figure 1-25. Forming metal contacts to active-areas

Last updated: 10 Feb 2010 (working document)

Figure 1-26. CMOS IC: side view (shown to relative scale)

Last updated: 10 Feb 2010 (working document)

1.1.7. Isolation methods

 LOCOS: LOCAL Oxidation of Si

Last updated: 10 Feb 2010 (working document)

1.1.8. Shallow Trench Isolation (STI) process

 Si wafer as starting material

Last updated: 10 Feb 2010 (working document)

 Forming epitaxial layer on native wafer