Act 17300

Chapter 1
Second Order Filters

Analog Communication Trainer
1-1: Curriculum Objectives

 
1. To understand the basic theory of filters.
2. To design and implement the second order low-pass filters.
3. To design and implement the second order high-pass filters.
4. To design and implement the second order bandpass filters.
5. To design and implement the second order band reject filters.
1-2: Curriculum Theory

Filters are ubiquitous in telecommunication systems. The function of
filters is to remove the unwanted signal and reserve the wanted signal at
frequency domain. Normally filters can be classified into three different
classifications: If discriminated by filtering range, then there are four types
which are low-pass filter (LPF), high-pass filter (HPF), bandpass filter (BPF)
and band reject filter BRF). Figure 1-1 shows the frequency responses of
low-pass, high-pass, bandpass and band-reject filters.
If discriminated by the frequency response of passband area, then
there are two popular types, which are Butterworth filter and Chebyshev
filter, as shown in figure 1-2. Butterworth filter is also known as maximally
1－2
Chapter 1 Second Order Filters
flat filter since no ripple is permitted in its passband. However, ripple is
appeared at the inner part of stopband and the attenuation of transition band
is not sharp enough. Chebyshev filter is also known as equal ripple filter
since the ripple is equally in its passband. There are no ripples in the
stopband and the attenuation of transition band is sharper than Butterworth
filter.
H ( j ) H ( j )
f f
fo fo
(a) Low-pass filter (b) High-pass filter
H ( j ) H ( j )
BW BW
f f
fo fo
(c) Bandpass filter (d) Band-reject filter
Figure 1-1 Frequency responses of ideal filters.
Ripples
H ( j ) H ( j )
Ripples
f f
(a) Butterworth filter (b) Chebyshev filter
Figure 1-2 Frequency responses of Butterworth and Chebyshev filters.
1－3
If discriminated by components, then there are two types, which are
active filter and passive filter. Early days, filter is formed by resistors,
capacitors and inductors, so this type of filter is called passive filter. Recent
years, active components such as operation amplifier (OP) are generally
used; therefore we called this type of filter as active filter. The advantages of
active filter are as below:
1. After special circuit arrangement, the transfer function provides property
of inductor, therefore it can replace inductor components.
2. Since operation amplifier (OP) has high input impedance and low output
impedance, so the isolation is very good and can easily be used for series
application.
3. Active components have function of amplifying, hence active filter also
provides gain.
In the experiments, we will introduce the implementation of second
order low-pass filter, high-pass filter, bandpass filter and bandstop filter.
Normally the cut-off frequency of a filter is determined by the frequency
with an attenuation of 3 dB.
1-1 Second Order Low-pass Filter
The purpose of low-pass filter is to enable low frequency signal pass
through and high frequency signal attenuate. Figure 1-3 shows the inverting
1－4
integrator or Miler integrator circuit, its transfer function is:
1 1
 
Vout ( S ) 
 SC  RC   0 (1-1)
Vin ( S ) R S S
Where
1
o 
RC
From equation (1-1), we know that the Miller integrator circuit is the
first order low-pass filter. If we want to design the second order active
low-pass filter, we need two Miller integrator circuits and an inverting
amplifier.
Figure 1-4 shows the block diagram of the second order active
low-pass filter. It is comprised by two Miller integrator circuits, a unit gain
inverting amplifier and an adder. Assume that the output of the adder is A(s),
then the transfer function is
o 1 
A (S)  KVin (S)  ( )A(S)  (( o ) 2 )A (S)
S Q S
 1   
A (S) 1  ( o )  ( o ) 2   KVin (S)
 Q S S 
o 2  KVin (S)
Vout (S)  ( ) A(S)  ( o ) 2
S S 1  1 ( o )  ( o ) 2
Q S S
1－5
R
Input
Vin A Output
Vout
Figure 1-3 Miller integrated circuit.
1
1
Q
Input K o o
(Vin )  
S
 -1
A(S) S
Output
(Vout )
Figure 1-4 Block diagram of second order active low-pass filter.
Simplify the above equation, we get
Vout (S) Ko2

 (1-2)
Vin (S)  
S2   0  S  02
Q
Equation (1-2) is the standard equation of the second order active
low-pass filter, if we follow the block diagram to design the circuit, we can
obtain the second order low-pass filter.
Figure 1-5 shows the circuit diagram of the second order active
low-pass filter, which is based on the block diagram in figure 1-4. We
combine the adder and the first Miller integrator circuit by replacing an OP
(U1). So we can save an OP, but the calculation of the circuit parameters will
1－6
be more complicated. If we assume
C1  C 2  C
R6  R5  R4
Then the transfer function can be expressed as
R3 1
Vout (S) R1 R 3R 4C 2

Vin (S) S2  1 S  1
CR 2 R 3R 4C 2
R3 1
R1 R 3R 4 C 2
 (1-3)
R 3R 4 1 1
S2  S
R 2 C R 3R 4 R 3R 4C 2
R3
R 2 10 k 15 k
C1 10 nF
C2
R1 12 V
R
(I/P) 6
R 10 nF
13 4
7.5 k
6 R5 15 k
14 15 k
12
7 10
5 15 k
12 V 8
U1:B
U1 : A 9
U1 : LM 348 U1:C
LPF O/P
Figure 1-5 Circuit diagram of second order active low-pass filter.
1－7
Compare equations (1-2) and (1-3), we obtain
R3
K (1-4)
R1
1
0  (1-5)
C R 3R 4
R2
Q (1-6)
R 3R 4
From the circuit diagram at figure 1-5, R1, R2, R3, C1 and U1 : A not
only comprise a Miler integrator circuit, but also have the function of
weighted summer. The objective is to multiply an individual weight for
input signal and the output signal of U1 : C . After that make a summation
on input signal and the output signal of U1 : C . R4, C2 and U1 : B
comprise a Miler integrator circuit; R5, R6 and U1 : C comprise an
inverting amplifier. According to the theory of network composition, this
circuit satisfies the conditions of Butterworth, therefore the curve for
frequency response at passband area is very smooth with no ripple.
1-2 Second Order High-pass Filter
The frequency response of second orders high-pass filter is just the
reverse of second order low-pass filter. The objective is to enable high
frequency signal pass through and attenuate low frequency signal. Figure
1-6 is the block diagram of high-pass filter. It is constructed by two Miler
1－8
integrator circuits, an inverting amplifier and two adders. We can obtain the
transfer function as
Vout (S) KS 2
 (1-7)
Vin (S)  
S 2   0  S   02
 Q 
The above function is the standard function of high-pass filter. We can
design and obtain the circuit of second order high-pass filter by following
the function from the block diagram.
Q K
1Q
o
KQ o
 
Input
(Vin )  -1 
S S
K Output
(Vout )
Figure 1-6 Block diagram of second order high-pass filter.
R7
15 k
R3
15 k
C1
R5 C2
R1 2.2 nF
I/P R4 15 k 2.2 nF
2
7.5 k R6 12 V
1 15 k 6
3 7 9
U1 : A 15 k
5 8
R2 U1 : LM348 U1 : B 1
0 12 V
7.5 k
U1 : C
HPF O/P
Figure 1-7 Circuit diagram of second order high-pass filter.
1－9
Figure 1-7 is the circuit diagram of second order high-pass filter, which
is based on the block diagram of figure 1-6. The first adder and the first Miler
integrator circuit are combined and replaced by U1 : A . The second adder
and inverting amplifier is replaced by U1 : B . Then we can save two
operation amplifiers, but for the circuit parameters, the calculation will
become more complicated. We assume
C1  C 2  C
R7  R6  R5
Then the transfer function is
R5 2 R5  1 R2 
 S    
Vout (S) R2 CR 2  R 3 R 1R 4 
 (1-8)
Vin (S) 1 1
S2  S
R 3C R 4 R 5C 2
If assume R 1R 4  R 2 R 3 ,
Then
R5 2
 S
Vout (S) R2

Vin (S) S2  1 S  1
R 3C R 4 R 5C 2
R5 2

S
R2
 (1-9)
R 4R 5 S 1
S2   
R3 C R 4 R 5 R 4 R 5C 2
1－10
Compare equations (1-7) and (1-9), we obtain
R5
K  (1-10)
R2
1
o  (1-11)
C R 4R 5
R3
Q  (1-12)
R 4R 5
From figure 1-7, R1, R3, R7, C1 and U1 : A not only comprise a Miler
integrator circuit, but also have the function of weighted summer. The
objective is to multiply an individual weight for input signal and the output
signal of U1 : C . After that make a summation on input signal and the
output signal of U1 : C . R2, R4, R5 and U1 : B comprise a weighted
summer circuit, which can multiply an individual weight for input signal
and the output signal of U1 : A . After that make a summation on input
signal and the output signal of U1 : A . R6, C2 and U1 : C comprise a Miler
integrator circuit. This circuit also satisfies the conditions of Butterworth,
because of its pole overlapping, therefore the curve for frequency response
at passband area is very smooth with no ripple.
1-3 Second Order Bandpass Filter
The objective of bandpass filter is to make a certain low and high
frequency signal attenuate, but enable a certain frequency band signal pass
1－11
through. From Figure 1-8, we can see that the characteristic curve is a
combination of low-pass and high-pass filters. The bandpass filter consists
of a f 3dB  f 2 low-pass filter and a f 3dB  f1 high-pass filter. Moreover,
the center frequency is f o  f1  f 2 and 3 dB frequency band ( BW3dB ) is
f2  f 1 .
Voltage
Gain
(dB) BW
3 dB 3 dB
HPF LPF
f1 fo f2 Frequency (Hz)
Figure 1-8 Frequency response of bandpass filter.
1
1
Q
Input K o o
(Vin )  
S
 -1
S
Output
(Vout )
Figure 1-9 Block diagram of second order active bandpass filter.
1－12
Figure 1-9 shows the block diagram of the second order active
bandpass filter, which consists of two Miller integrator circuits, a unit gain
inverting amplifier and an adder. The transfer function is expressed as
Vout (S) KSo

 (1-13)
Vin (S)  
S 2   0  S  02
 Q
bandpass filter, if we follow the block diagram to design the circuit, we can
obtain the second order bandpass filter.
R3
R 2 10 k 15 k
C1
C2
R1
10 nF R
6
(I/P) 13 R4 10 nF
7.5 k :
U1 R5
A 14 6 15 k
15 k :
12 U1
:LM34 B 7 10 :
U1 5 15 k U1
8 C 8
9
(BPF O/P)
Figure 1-10 Circuit diagram of second order active bandpass filter.
Figure 1-10 is the circuit diagram of the second order active bandpass
filter, which is based on the block diagram in figure 1-9. We combine the
adder and the first Miller integrator circuit by replacing an OP ( U1 : A ). So
1－13
we can save an OP, but the calculation of the circuit parameters will be more
complicated. If we assume
C1  C 2  C
R6  R5  R 4
Then the transfer function can be expressed as
R 3R 4 1
 S
Vout (S) R1 R 3R 4 C
 (1-14)
Vin (S) R 3R 4 1 1
S 
2
S
R2 C R 3R 4 R 3R 4C 2
Comparing equations (1-13) and (1-14), we get
R 3R 4
K (1-15)
R1
1
0  (1-16)
C R 3R 4
R2
Q (1-17)
R 3R 4
In figure 1-10, R1 , R 2 , R 3 , C1 and U1 : A not only comprise a
Miller integrator circuit, but also provide the function of weighted summer.
The objective is to multiply a weighted to the input signal and output signal
of U1 : C , respectively, after that sum the input signal and output signal of
U1 : C . R 4 , C 2 and U1 : B comprise a Miller circuit. R 5 , R 6 and
1－14
U1 : C comprise an unit gain inverting amplifier. This circuit satisfies the
conditions of Butterworth filter, therefore, there is no ripple permitted in the
passband and the frequency response is very flat.
1-4 Second Order Band Reject Filter
The objective of bandstop filter is to make a certain low and high
frequency signal pass through, but disable a certain frequency band signal
pass through. On the other words, if a circuit rejects a finite frequency band
that does not include zero (DC) and infinite frequency, then it is known as
band reject filter. Thus band reject filter is specified by two stopband
frequencies to set the frequency band as shown in figure 1-11. From figure
1-11, we can see that the characteristic curve is a combination of low-pass
and high-pass filters. The band reject filter consists of a f 3dB  f1 low-pass
filter and a f 3dB  f 2 high-pass filter. Moreover, the center frequency is
f o  f1  f 2 and 3 dB frequency band ( BW3dB ) is f 2  f 1 .
Figure 1-12 shows the block diagram of the second order active band
reject filter, which consists of a low-pass filter, high-pass filter and an adder.
Let the output of the low-pass filter be VLPF(S) and the output of the
high-pass filter be VHPF(S). Then the transfer function is expressed as
Vout (S)  (K1  VLPF  K 2  VHPF )

(1-18)
 Vin (S)(K1  TLPF  K 2  THPF )
1－15
where
TLPF (S) : The standard transfer function of low-pass filter.
THPF (S) : The standard transfer function of high-pass filter
K 1 and K 2 : The weight of the linear adder.
Substitute TLPF (S) and THPF (S) by using equation (1-2) and
equation (1-7), then equation (1-18) can be rewritten as
Vout (S) K 2S2  K1o2

 K (1-19)
Vin (S)  
S2  S o   o2
 Q
Voltage
Gain
(dB) BW
3 dB 3 dB
LPF HPF
f1 fo f2 Frequency (Hz)
Figure 1-11 Frequency response of band reject filter.
1－16
band reject filter, if we follow the block diagram to design the circuit, we
can obtain the second order bandpass filter. Therefore, practically, we just
need to sum the outputs of figure 1-5 and figure 1-7 by using the adder in
figure 1-13, where K1  K 2  1 , then equation (1-19) can be rewritten as
Vout (S) S2  o2

 K (1-20)
Vin (S)  
S2  S o   o2
 Q
LPF
 K1

Input Output
( Vin ) ( Vout )
 K2
HPF
Figure 1-12 Block diagram of second order active band reject filter.
R1 R3
LPF I/P
10 k 10 k
R2
HPF I/P
10 k A 741 BRF O/P
Figure 1-13 Circuit diagram of second order active band reject filter.
1－17
All the above-mentioned circuits are second order filters. By
comparing their transfer functions, we know that the order of the filters is
determined by the denominator. If the order of the denominator is higher
than the order of the numerator, then the filter is a low-pass filter. On the
other hand, if the order of the denominator is smaller than the order of the
numerator, then the filter is a high-pass filter. For higher levels filter, we
can series the mentioned circuits to obtain the required efficiency (Only
the components’ values need to redesign for satisfying the coefficient of
Butterworth or Chebyshev filter). In this experiment, the IC that we use is
LM348 package with four operation amplifiers (A741). The unit gain
bandwidth is about 1 MHz, therefore same as A741, it is not desirable at
high frequency response. Then for experiment of second order high-pass
filter, we change the IC to LM318. The unit gain bandwidth is about 15
MHz, so we can improve the high frequency response.
1－18
1-3: Experiment Items
Experiment 1: Second order active low-pass filter
1. Refer to the circuit in figure 1-5 or figure ACS1-1 on ACT-17300-01

module. Let J1 and J2 be short circuit, J3 and J4 be open circuit, i.e.
C1  C 3  10 nF .
2. At the input port, input 500 mV amplitude, 10 Hz sine wave frequency.

Then by using oscilloscope, observe on the output signal port (LPF O/P)
and record the measured result in table 1-1.
3. The input amplitude remains, change the frequency to 30 Hz, 50 Hz,

70 Hz, 100 Hz, 300 Hz, 500 Hz, 700 Hz, 1 kHz, 3 kHz, 5 kHz, 7 kHz
and 10 kHz. Then by using oscilloscope, observe on the output signal
port (LPF O/P) and record the measured results in table 1-1.
4. Find the voltage gain of each frequency and records the measured results
in table 1-1.
5. From the data in table 1-1, sketch and label the voltage gain in Bode
plots in figure 1-14.
6. Let J3 and J4 be short circuit, J1 and J2 be open circuit, i.e. change C1

and C2 to C3 and C4, which C 3  C 4  3.3 nF .
7. Repeat step 2 to step 5 and record the measured results in table 1-2 and
figure 1-15.
1－19
Experiment 2: Second order active high-pass filter

C1  C 2  2.2 nF .

Then by using oscilloscope, observe on the output signal port (HPF
O/P) and record the measured result in table 1-3.
3. The input amplitude remains, change the frequency to 100 Hz, 300
Hz, 500 Hz, 700 Hz,1 kHz, 3 kHz, 5 kHz, 7 kHz, 10 kHz, 30 kHz, 50
kHz and 100 kHz. Then by using oscilloscope, observe on the output
signal port (HPF O/P) and record the measured results in table 1-3.
4. Find the voltage gain of each frequency and record the measured
results in table 1-3.

and C2 to C3 and C4, which C 3  C 4  1 nF .
figure 1-17.
1－20
Experiment 3: Second order active bandpass filter

C1  C 2  10 nF .

Then by using oscilloscope, observe on the output signal port (BPF O/P)
3. The input amplitude remains, change the frequency to 30 Hz, 50 Hz, 70

Hz, 100 Hz, 300 Hz, 500 Hz, 700 Hz, 1 kHz, 3 kHz, 5 kHz, 7 kHz and
10 kHz. Then by using oscilloscope, observe on the output signal port
(BPF O/P) and record the measured results in table 1-5.
4. Find the voltage gain of each frequency and record the measured results
in table 1-5.

and C2 to C3 and C4, which C 3  C 4  3.3 nF .
figure 1-19.
1－21
Experiment 4: Second order active band reject filter
1. Refer to the block diagram in figure 1-12, by using the low-pass filter in
figure 1-5, the high-pass filter in figure 1-7, the adder in figure 1-13 to
sum the low-pass and high-pass filters. Or refer to figure ACS1-1 and
ACS1-2 on ACT-17300-01 module.
2. At figure ACS1-1, let J1 and J2 be short circuit, J3 and J4 be open

circuit, i.e. C1  C 2  10 nF ; At figure ACS1-2, let J1 and J2 be short
circuit, J3 and J4 be open circuit, i.e. C1  C 2  2.2 nF .
3. Connect the input ports of figure ACS1-1 and figure ACS1-2 together.
Connect the LPF O/P of the low-pass filter in figure ACS1-1 to the LPF
I/P of the linear adder in figure ACS1-2; Connect the HPF O/P of the
high-pass filter in figure ACS1-2 to the HPF I/P of the linear adder in
figure ACS1-2.

Then by using oscilloscope, observe on the output signal port (BRF O/P)
5. The input amplitude remains, change the frequency to 50 Hz, 70 Hz,

100 Hz, 300 Hz, 500 Hz, 700 Hz, 1 kHz, 3 kHz, 5 kHz, 7 kHz, 10 kHz,
30 kHz, 50 kHz, 70 kHz and 100 kHz. Then by using oscilloscope,
observe on the output signal port (BRF O/P) and record the measured
6. Find the voltage gain of each frequency and record the measured results
in table 1-7.
1－22
8. At figure ACS1-1, let J3 and J4 be short circuit, J1 and J2 be open

circuit, i.e. C1  C 2  3.3 nF ; At figure ACS1-2, let J3 and J4 be short
circuit, J1 and J2 be open circuit, i.e. C1  C 2  1 nF .
figure 1-21.
1－23
1-4: Measured Results
Table 1-1 Measured results of second order low-pass filter. ( C1  C 2  10 nF )
Input Signal
Frequency 10 30 50 70 100 300 500 700 1k 3k 5k 7k 10k
(Hz)
Output Signal
Amplitude
(mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
Figure 1-14 Bode plots of voltage gain versus frequency.
1－24
Table 1-2 Measured results of second order low-pass filter. ( C 3  C 4  3.3 nF )
Input Signal
Frequency 10 30 50 70 100 300 500 700 1k 3k 5k 7k 10k
(Hz)
Output Signal
Amplitude
(mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1－25
Table 1-3 Measured results of second order high-pass filter. ( C1  C 2  2.2 nF )
Input Signal
Frequency 70 100 300 500 700 1k 3k 5k 7k 10k 30k 50k 100k
(Hz)
Output Signal
Amplitude
(mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1－26
Table 1-4 Measured results of second order high-pass filter. ( C 3  C 4  1 nF )
Input Signal
Frequency 70 100 300 500 700 1k 3k 5k 7k 10k 30k 50k 100k
(Hz)
Output Signal
Amplitude
(mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1－27
Table 1-5 Measured results of second order bandpass filter. ( C1  C 2  10 nF )
Input Signal
Frequency 10 30 50 70 100 300 500 700 1k 3k 5k 7k 10k
(Hz)
Output Signal
Amplitude
(mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1－28
Table 1-6 Measured results of second order bandpass filter. ( C 3  C 4  3.3 nF )
Input Signal
Frequency 10 30 50 70 100 300 500 700 1k 3k 5k 7k 10k
(Hz)
Output Signal
Amplitude
(mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1－29
Table 1-7 Measured results of second order band reject filter.
( C1  C 2  10 nF for LPF; C1  C 2  2.2 nF for HPF)
Input Signal
30 50 70 100 300 500 700 1k
Frequency (Hz)
Output Signal
Amplitude (mV)
Voltage Gain
(dB)
Input Signal
3k 5k 7k 10 k 30 k 50 k 70 k 100 k
Frequency (Hz)
Output Signal
Amplitude (mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1－30
Table 1-8 Measured results of second order band reject filter.
( C1  C 2  3.3 nF for LPF; C1  C 2  1 nF for HPF)
Input Signal
30 50 70 100 300 500 700 1k
Frequency (Hz)
Output Signal
Amplitude (mV)
Voltage Gain
(dB)
Input Signal
3k 5k 7k 10 k 30 k 50 k 70 k 100 k
Frequency (Hz)
Output Signal
Amplitude (mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1－31
1-5: Problems Discussion
1. According to the signal selection of filter, filters can be divided into

how many types?
2. Compare the Butterworth filter and Chebyshev filter.
3. Describe the advantages of using OP to design the filter.
4. Try to derive the standard transfer function in equation (1-7) of the

second order high-pass filter.
5. Try to derive the standard transfer function in equation (1-13) of the

second order bandpass filter.
6. Refer to equations (1-5), (1-11) and (1-16), in order to change the

bandwidth of the filters, describe which components need to be
changed easily.
7. Refer to the standard transfer functions in equations (1-2) and (1-7),

discuss the relationship between the filters and the order of numerator
and denominator.
8. In figure 1-5, how to adjust the C1 and C2 in order to increase the 3 dB

frequency?
9. In figure 1-7, how to adjust the C1 and C2 in order to decrease the 3 dB

frequency?
1－32
Chapter 2
RF Oscillators
1. To understand the basic theory of oscillators.
2. To design and implement the Colpitts and Hartley oscillators.
3. To design and implement the crystal and voltage controlled

oscillators.
4. To understand the measurement and calculation of the output

frequency of oscillators.
Nowadays, wireless communication is widely used and expanded
rapidly. Therefore, RF oscillator becomes one of the important members in
wireless communications. The characteristic of oscillator is that it can
produce sinusoidal wave or square wave at output terminal without any
input signal. So oscillator becomes an important role no matter for
modulated signals or carrier signals. In this chapter, we will focus on the
theory of feedback oscillators and the design and implementation of
different kinds of oscillators. Besides, we can also learn to measure and
calculate the output frequency of oscillators in this chapter.
2－2
Chapter 2 RF Oscillators
2-1 The Operation Theory of Oscillators
Figure 2-1 shows the basic block diagram of the oscillator circuit. It
includes an amplifier and a resonator, which comprise the positive feedback
network. When we switch on the power, the circuit will produce noise. The
noise will be amplified by the amplifier, and pass through a resonator circuit
which has filter function. At last what’s left is the signal in the passband.
The unwanted signal is filtered by the resonator. So the pass through signal
will then send to the input port of amplifier and combine to the original
signal, which their phases are same and will be amplified again. In figure
2-1, the transfer function can be expressed as
Vo ( j) A( j)
A f ( j)   (2-1)
Vi ( j) 1  A( j)( j)
The definition of open loop gain is
L( j)  A( j)( j)
Using Barkhausen principle, we know the oscillation condition is
L( jo )  A( jo )( jo )  1 (2-2)
Therefore, we can obtain a specific corner frequency o to ensure
that the open loop gain L( jo ) is equal to 1, and the phase must be 0o ,
that is
2－3
A ( jo )( jo )  1 (2-3)
arg[A( jo )( jo )]  0o (2-4)

Amplifier Gain
Vs
Vi A( j) Vo
Vf Feedback Network
( j)
Figure 2-1 Basic block diagram of oscillator circuit.
From the above mention, in order to satisfy equations (2-3) and (2-4),
we should make sure that the product of the feedback factor and the
amplifier gain is 1. Meanwhile, the total summation of the phases is zero
after feedback. Therefore, figure 2-1 can be changed to figure 2-2 for
different structures of amplifier.
Non-inverting Amplifier
Vs
Vi A ( j) Vo
Vf 0o
( j)
Inverting Amplifier
Vs
Vi A ( j) Vo
Vf 180 o
( j)
Figure 2-2 Oscillator circuits comprised by non-inverting and inverting amplifier.
2－4
2-2 Colpitts and Hartley Oscillators
Figure 2-3 shows the basic structure of LC feedback oscillator which
Z1 , Z 2 and Z3 represent inductance or capacitance components. Figure
2-4 is a small signal equivalent circuit for LC feedback oscillator. From
figure 2-4, we get
( Z 2  Z 3 ) || Z1 Z2
A    ( A )  
ro  ( Z 2  Z 3 ) || Z1 Z 2  Z 3
(2-5)
Z1  Z 2
 ( A ) 
ro ( Z1  Z 2  Z 3 )  Z1 ( Z 2  Z 3 )
Let Zi  jX i , where Z L  jX L  jL ; Z C  jX C  j(1 / C ) ,
substitute into equation (1-5), we get
( jX 1 )  ( jX 2 )
A    ( A ) 
ro  ( jX 1  jX 2  jX 3 )  jX 1 ( jX 2  jX 3 )
(2-6)
A  X1  X 2

ro  j( X1  X 2  X 3 )  X1 ( X 2  X 3 )
From equation (2-4), we know that the A is real number, therefore, the first
condition for LC feedback oscillator to oscillate is
X1  X 2  X 3  0 (2-7)
Since equation (2-3) A( jo )  ( jo )  1 , then
A  X1  X 2 X
A ( j  o )  ( j  o )   A 2 1
 X1  ( X 2  X 3 ) X1
2－5
So, the second condition is
X1
A (2-8)
X2
Vo
-A
z2 z1
z3
Figure 2-3 Feedback oscillator diagram.
ro Vo
Vi  AVi
z3
z1
z2
Figure 2-4 Small signal equivalent circuit for LC feedback oscillator.
From the above-mentioned terms, we can make a conclusion: The
basic diagram of an oscillator includes an amplifier and a resonator to form
a feedback network. When we switch on the power, the circuit will produce
2－6
noise. The noise will be amplified by the amplifier, and pass through a
resonator circuit which has filter function. At last what’s left is the signal in
the passband. The unwanted signal is filtered by the resonator. So the pass
through signal will then send to the input port of amplifier and combine with
the original signal, which their phases are same and be amplified again. This
is how the oscillation been formed. On the other hand, base on Barkhausen
oscillation principle, the first and second conditions inform us:
1. Since the voltage gain of the amplifier is real number, therefore Z1 and
Z2 are same components with same reactance and Z3 is another
component with different reactance.
2. The voltage gain, A of the amplifier must be greater than the ratio of Z1
and Z2.
Figure 2-5 shows three common types of oscillators, which are
Colpitts, Hartley and Clapp. If we combine the oscillators with transistor by
utilizing either common gate mode, common drain mode or common source
mode, then there are many types of oscillators mode for selection.
Figure 2-6 is the AC equivalent circuit of Colpitts oscillator. The
parallel LC resonant circuit links between the base and collector of transistor.
So part of the voltage come from the voltage divider formed by C1 and C2,
and feedback to the base of the transistor. R represents the total summation
of output resistor, load resistor together with the equivalent resistor of the
inductor and capacitor of a transistor.
2－7
(a) Colpitts Oscillator (b) Hartley Oscillator (c) Clapp Oscillator
Figure 2-5 Three common types of oscillators.
Output
R C1
L
C2
Figure 2-6 AC equivalent circuit of Colpitts oscillator.
If the operation frequency is low, then we can ignore the internal
junction capacitance of the transistor. Hence, from equation (2-7), the
oscillation frequency of Colpitts oscillator is
1 1
X1  X 2  X 3     o L  0
oC1 o C2
1
fo  (Hz) (2-9)
CC
2 L 1 2
C1  C 2
We need to consider the conditions of Colpitts oscillator. The voltage gain of
A of the amplifier is g m R . Then, from equation (2-8), we know that
condition of oscillation is
2－8
1

X1 oC1 C2
A  
X2  1 C1
oC2
C2
gmR  (2-10)
C1
Figure 2-7 is the circuit diagram of Colpitts oscillator. R1, R2, R3 and
R4 provide operation bias to transistor, C1 is coupling capacitor, C2 is bypass
capacitor, C3, C4 and L1 comprise a resonant circuit for selecting suitable
operation frequency.
+12V
R1 R3
22 k 2k Output
C1 TP1 Q1
2N3904 C3
1 nF 1 nF
L1
R2 27 uH
10 k
R4 C2
1k 100 nF
C4
15 nF
Figure 2-7 Circuit diagram of Colpitts oscillator.
Output
R L1
L2
Figure 2-8 AC equivalent circuit of Hartley oscillator.
2－9
Figure 2-8 is the AC equivalent circuit of Hartley oscillator. Same as
Colpitts oscillator, the parallel LC resonant circuit connects between the
base and collector of the transistor, the difference is part of the voltage come
from the voltage divider formed by L1 and L2, and feedback to the base of
the transistor. R represents the total summation of output resistor, load
resistor together with the equivalent resistor of the inductor and capacitor of
a transistor.
If the operation frequency is low, then we can ignore the internal
junction capacitance of the transistor. Therefore from equation (2-19), the
oscillation frequency can be obtained as
1
X1  X 2  X 3  o L1  o L 2  0
o C
1
f0  ( Hz ) (2-11)
2 L1  L 2 C
Similarly, from equation (2-20), we can obtain the condition of
oscillation as
X1 o L1 L1
A  
X 2 o L 2 L 2
L1
gmR  (2-12)
L2
2－10
Figure 2-9 is circuit diagram of Hartley oscillator. R1, R2 and R3
provide the operation bias to transistor, C1 is coupling capacitor, C2 is
bypass capacitor, C3, L1 and L2 comprise a resonant circuit for selecting
suitable operation frequency.
+12V
R1
Output
C1
Q1
L1
R2 C3
R3 C2
L2
Figure 2-9 Circuit diagram of Hartley oscillator.
2-3 Crystal Oscillator
In order to get better frequency stability, it is obvious that we have to
choose a high Q circuit when designing the oscillator circuits, such as
transistors with piezoelectric effect, for example, quartz, ceramic and so on.
These transistors are usually used to design the oscillator circuits with high
stability due to the reason that the loss of the transistors is very low and the
Q value of the transistors is very high and stable.
Crystals are tri-dimensional structure. It is a mechanical oscillator,
which has various types of oscillation. A crystal is a device that is usually
2－11
made by cutting a pure quartz crystal in a very thin slice and then plating the
faces with a conductor in order to make an electrical connection. The
property that makes the crystal useful in designing the oscillator is the
piezoelectric effect. When the crystal is excited by the voltage, it will cause
a deformation of the quartz material and produce various types of oscillation.
In addition, we can choose specific oscillation type and high order harmonic
via different product process of crystals. Figure 2-10 shows the equivalent
circuit and the impedance characteristic of crystal. In figure 2-10, the
parallel capacitor C p is the static capacitor in the range about 7 ~ 10 pF.
The series capacitor Cs and inductor L correspond to the disposal
sequence and mass of the crystal. Generally, the value of Cs is about 0.05
pF, and L is about 10 H. The internal loss is represented by resistor r,
which mainly comes from plating, brace of the crystal and the impedance
caused by inner-friction or leads etc. Since the Q value of crystal is very
high, therefore, r seems to be very small, only few ohms. Besides, we also
can get the series or parallel resonant frequency, respectively. In figure 2-10,
we have
1
fs  (2-13)
2 LCs
1
fp  (2-14)
CC
2 L s p
Cs  C p
2－12
Zx Z  r (Q 2  1)
Cs Cp
r
r
f
fs fp
(a) Equivalent circuit of crystal (b) Characteristic curve of impedance

Figure 2-10 Equivalent circuit of crystal and the characteristic curve of impedance.
Since C p  140 Cs , then the difference between fs and f p is around
0.36 %.
Cs
f p  (1  )f s (2-15)
2Cp
Crystal always plays a role as the parallel or series resonant circuit in
oscillator circuit. Due to the high Q value of crystals, the stability of
oscillation frequency can be higher than using the general inductors and
capacitors. If crystal is used in a parallel resonant circuit, then it is called as
the parallel mode crystal oscillator, as shown in figure 2-11(a). In the
oscillation circuit with parallel mode, the crystal can be seen as an inductor.
On the other hand, if the crystal is operated in series resonant circuit, then it
is called as the series mode crystal oscillators as shown in figure 2-11(b). In
the oscillation circuit with series mode, the crystal can be seen as a capacitor.
Besides, the design of crystal oscillator is similar to the design methods
2－13
without using crystals. However, we should pay more attention to design the
bias circuit for the reason that the DC signal may not pass through the
crystal.
C1 C1
'
X tal L
X ' tal
C2 C2
(a) Parallel mode crystal oscillator circuit (b) Series mode crystal oscillator circuit
Figure 2-11 Circuit structures of crystal oscillator
+12V
R2
270
C4
R1 100 pF
22 k
X'tal 輸出
C 2 680 pF
6 MHz
C1 TP1
R3 C3
51 680 pF
Figure 2-12 Circuit diagram of the Colpitts crystal oscillator.
Figure 2-12 is the circuit diagram of the Colpitts crystal oscillator. The
operating bias of the transistor is provided by R1 , R 2 and R 3 . Moreover,
C1 and C 2 are the external parallel capacitors added on the crystal. The
values that we choose should be higher until the parasitic capacitor can be
2－14
neglected. The bypass capacitor and coupled capacitor are denoted as C3
and C 4 , respectively. The oscillation frequency of this circuit is decided by
the frequency of the crystal oscillator we used.
2-4 Voltage Controlled Oscillator
Voltage controlled oscillator is an oscillator circuit that the output
frequency can be varied by voltage. The main design concepts and methods
are similar to the LC feedback oscillator as mentioned before. However, the
only difference is that we use varactor diode, which the capacitance can be
varied by the voltage to replace the original capacitor. Therefore, we may
not discuss the theory of the oscillator but we will focus on the theory of the
varactor diode.
Varactor diode or tuning diode is mainly used for changing the
capacitance value of oscillator. The objective is to let the output frequency
of oscillator can be adjusted or tunable, therefore varactor diode dominates
the tunable range of the whole voltage controlled oscillator. Varactor diode
is a diode, which its capacitance can be varied by adding a reverse bias
voltage to pn junction. When reverse bias voltage increases, the depletion
region becomes wide, this will cause the capacitance value decreases;
nevertheless when reverse bias voltage decreases, the depletion region will
be reduced, this will cause the capacitance value increases. Varactor diode
also can be varied by the amplitude of AC signal.
2－15
Figure 2-13 is the capacitance analog diagram of varactor diode. When
a varactor diode without bias voltage, the concentration will be differed
from minor carriers at pn junction. Then these carriers will diffuse and
become depletion region. The p type depletion region carries electron
positive ions, then the n type depletion region carries negative ions. We can
use parallel plate capacitor to obtain the expression as shown as follow
A
C (2-16)
d
where
  11.8 o (dielectric constant of silicon)
o  8.85  1012
A: the cross section area of capacitor.
d: the width of depletion region.
When reverse bias voltage increases, the width of depletion region d
will increase but the cross section area A remains same, therefore the
capacitance value would be reduced. On the other hand, the capacitance
value will increase voltage when reverse bias decreases.
Varactor diode can be equivalent to a capacitor series a resistor (Rs)
and an inductor (Ls) as shown in figure 2-14. From figure 2-14, Cj is the
junction capacitor of semiconductor, which only exits in pn junction. Rs is
2－16
the sum of bulk resistance and contact resistance of semiconductor material,
which is related to the quality of varactor diode (generally below a few
ohm). Ls is the equivalent inductor of bounding wire and semiconductor
material.
Figure 2-20 is the circuit diagram of voltage controlled oscillator by
using the structure of Clapp oscillator in figure 2-10(c). R1 , R 2 and R 3
provide the operating bias voltage of the transistor. C 2 , C3 , L1 , CV1 and
C V 2 comprise the resonant circuit to select a proper operation frequency.
Finally, C1 is the bypass capacitor and C 4 is the coupled capacitor.

PN Junction
- - +
+
- +
P - + N
- +
- +
Depletion Region
_
_ _ _ +
+ + +
_ _ _
+ + +
_ _
+ +
Parallel Plate Capacitor Dielectric
Figure 2-13 Capacitance analog diagram of varactor diode.
CV Cj Rs
(a) Circuit symbol (b) Equivalent circuit
Figure 2-14 Circuit symbol and equivalent circuit diagram of varactor diode.
2－17
+12V
L1 R2
100 uH
270
+12V
C4
CV1 R1 100 pF
1SV55 22 k
Output
VR 1 Vt C2
5k 680 pF
CV2 C1
1SV55 100 nF R3 C3
680 pF
Figure 2-15 Circuit diagram of voltage controlled oscillator.
2－18

 
Experiment 1: Colpitts and Hartley oscillators
1. To implement the circuit as shown in figure 2-7 which L1  27 H ,

C3  1 nF , C 4  15 nF or refer to figure ACS2-1 on ACT-17300-01
module. Let J1 and J2 be short circuit, J3 and J4 be open circuit.
2. Switch the oscilloscope to AC channel, then observe on the output

signal port ( O / P ) and the feedback port (TP1) of the oscillator. Then,
record the signal waveforms and frequencies in table 2-1.
3. To implement the circuit as shown in figure 2-9 which L 2  220 H ,

L 3  100 H , C 5  10 nF or refer to figure ACS2-1 on
ACT-17300-01 module. Let J3 and J4 be short circuit, J1 and J2 be

open circuit.

2－19
Experiment 2: Crystal and voltage controlled oscillator
1. To implement the circuit as shown in figure 2-12, which

C 2  C 3  680 pF , Xtal  6 MHz or refer to figure ACS2-2 on
ACT-17300-01 module. Let J2 be short circuit, J1 be open circuit.

3. To implement the circuit as shown in figure 2-15, which

C 2  C3  680 pF , L1  100 H , CV1  CV2  1SV55 or refer to
figure ACS2-2 on ACT-17300-01 module. Let J1 be short circuit, J2 be
open circuit.
4. Adjust the variable resistor, VR1 , so that the DC voltage (Vt) of the
varactor diode is varied from the values in table 2-3.

signal port ( O / P ) and record the measured results in table 2-3.
6. According to the data in table 2-3, sketch the characteristic curve with
frequency versus voltage in figure 2-16.
2－20

 
Table 2-1 Measured results of Colpitts and Hartley oscillator.
Components
Values of Colpitts Output Signal Waveforms
Oscillator
O/P
L1 :
C3 :
C4 :
TP1
Theoretical value fo =
Measured value fo =
Components
Values of Hartley Output Signal Waveforms
Oscillator
O/P
L2 :
L3 :
C5 :
TP1
Measured value fo =
2－21
Table 2-2 Measured results of crystal oscillator.
Components Values of Hartley Oscillator

Output Signal
Waveforms
C2 : ; C3 : ; Xtal1 :
(O/P)
Measured value fo =
TP1
Measured value fo =
2－22
Table 2-3 Measured results of voltage controlled oscillator.
Input DC Bias
3 4 5 6 7 8 9 10 11 12
( Vt )
Output Signal
Frequency
(MHz)
Output Signal
Frequency (MHz)
Input DC
Bias
3 4 5 6 7 8 9 10 11 12 (Vt )
Figure 2-16 Characteristic curve of frequency versus voltage.
2－23

 
1. Describe the conditions of oscillation that the oscillator can operate in a
proper way.
2. Describe the conditions of oscillation that the Colpitts oscillator and

Hartley oscillator can operate in a proper way.
3. Try to design a Hartley oscillator as shown in figure 2-9 with 5 MHz

output frequency, then find the values of C3 , L1 and L 2 .
4. Briefly describe the advantages of crystal oscillator.
5. Briefly describe the design concepts of voltage controlled oscillators.
2－24
Chapter 3
AM Modulator
1. To understand the basic theory of amplitude modulation (AM).
2. To understand the waveform and frequency spectrum of AM

modulator, also calculate the percentage of modulation.
3. To design and implement the AM modulator by using

transistor.
4. To design and implement the AM modulator by balanced

modulator.
5. To understand the measurement and adjustment of AM

modulator.
In amplitude modulation (AM), we utilize the amplitude of audio
signal to modulate the amplitude of carrier signal, which means that the
amplitude of carrier signal will be varied with amplitude of audio signal.
The waveform of AM modulation is shown in figure 3-1 and its block
diagram is shown in figure 3-2. In figure 3-2, we know that in order to
generate the AM signal, we just need to add a DC signal with the audio
signal, and then multiply the added signal with the carrier signal.
3－2
Chapter 3 AM Modulator
Am Ac
Audio Signal Carrier Signal

E max
E min
Amplitude Modulated Signal
Figure 3-1 Signal waveform of amplitude modulation.
Audio
AM Output
Signal Input
DC Level Carrier Signal
Figure 3-2 Block diagram of AM modulator.
Let the audio signal be A m cos (2 f m t ) and carrier signal be
A c cos (2 f c t ) , then the amplitude modulation can be expressed as
x AM (t )   ADC  Am cos (2 f m t )Ac cos (2 f c t )
 ADC Ac 1  m cos (2 f m t )cos (2 f c t) (3-1)
Where
3－3
m  A m / A DC .
A DC : DC signal magnitude.
A m : Audio signal amplitude.
A C : Carrier signal amplitude.
f m : Audio signal frequency.
f C : Carrier signal frequency.
m: Modulation index or depth of modulation.
From equation (3-1), we notice that the variation of the magnitude
A DC Ac 1  m cos(2 f m t ) of the carrier signal can be controlled by
parameter “m”. This means that we can change the magnitude of the audio
signal (Am) or DC signal (ADC) to control the level or depth of the carrier
signal. Therefore, this parameter “m” is known as the modulation index.
Besides, we can also rewrite equation (3-1) as
A DC A C m  cos  2( f c  f m ) t   cos  2(f c  f m ) t  

1
x AM ( t ) 
2
 A D C A C cos 2 f c t  (3-2)
The first term represents double sideband signals; the second term
represents carrier signal. From equation (3-2), we can sketch the frequency
spectrum of amplitude modulation as shown in figure 3-3. Since the audio
3－4
signal is hidden in the double sidebands and the carrier signal does not
contain any message, therefore the power is consumed in carrier during
transmission of amplitude modulation signal. For this reason, the
transmission efficiency of AM modulation is lower than double sidebands
suppressed carrier (DSB-SC) modulation but its demodulation circuit is
much simpler.
ADC  Ac
0.5m  ADC  Ac 0.5m  ADC  Ac
f
fc  fm fc fc  fm
Figure 3-3 Frequency spectrum of amplitude modulation signal.
There is an important parameter “m” in equation (3-1) called
modulation index or depth of modulation. Normally it is represented in
percentage, so we also call modulation percentage. Modulation index is an
important parameter in equation (3-1). The definition is as follow
Audio signal amplitude A

m  100 %  m  100 % (3-3)
DC signal magnitude A DC
Generally, the magnitude of DC signal is not easy to measure;
therefore we express the modulation index in another form
3－5
E max  E min
m  100 % (3-4)
E max  E min
Where E max and E min as shown in figure 3-1 are E max  A C  A m and
E min  A C  A m .
We know that at amplitude modulation, the audio signal is hidden in
the double sidebands, so if the double sideband signals are getting stronger,
the transmission efficiency is getting better. From equation (3-2), we know
that the double sideband signals are proportional to the modulation index.
Thus the larger the modulation index, the better the transmission efficiency.
Normally modulation index is smaller or equal to 1. If greater than 1,
we call it over modulation, as shown in figure 3-4. Figure 3-4 shows the
waveforms of the over modulation. In figure 3-4, we can see that the
variation of carrier signal is no longer a sinusoidal wave. It is rather a
distorted sinusoidal wave, therefore, this kind of AM signal is unable to
demodulate and recover to the original by using the envelop detection in
next chapter.
Emax
Emin
Figure 3-4 Waveforms of the over modulation.
3－6
As we know that the AM modulator can be implemented by using a
multiplier. However, in electronics circuit, the multiplier is constructed by
the nonlinear characteristics of active component. Therefore, in this chapter,
we will discuss the design of AM modulator by using a single transistor and
balanced modulator.
3-1 Transistor AM Modulator
The circuit diagram of transistor AM modulator is shown in figure 3-5.
In figure 3-5, the audio signal ( A m cos (2 f m t ) ) will pass through a
transformer and send into the base of the transistor. The carrier signal
( A c cos (2 f c t ) ) also passes through a transformer and sends into the
emitter of the transistor. These two signals will form a small amount of
small signal voltage difference at the base and emitter of the transistor. The
small signal voltage difference is
Vbe  Vb  Ve  A m cos(2f m t )  A c cos(2f c t ) (3-5)
Then at the collector of the transistor, this voltage difference will
produce a small signal collector current as
I c  I s e Vbe VT
(3-6)
Expand equation (3-6) by Taylor’s expansion, then we get
I c  aVbe  bVbe
2
(3-7)
3－7
+12 V
C2 C4
100 nF 10 uF
L1
R1 100 uH
120 k C3
TP2 AM
Signal
Audio C1 TP1 Output
Signal
Q1 1 nF
TR1 R3
Input 100 nF 3904 3k3
TP3
R2
5k6
VR1
TR2
Carrier 500
Signal
Input
Figure 3-5 Circuit diagram of transistor AM modulator.
In equation (3-7), we notice that after the audio signal and the carrier
signal input into the base and collector of the transistor, we can obtain
cos 2 (2 f m t ) , cos 2 (2 f c t ) and cos (2 f m t )  cos (2 f c t ) signals at the
collector. Then we utilize the filter to obtain the modulated AM signal
cos (2 f m t )  cos (2 f c t ) . In figure 3-5, the inductor L1, capacitor C3 and
resistor R3 comprise a high-pass filter, which is used to obtain the modulated
AM signal. Capacitor C1 is the coupling capacitor. Capacitor C2 and C3 are
the bypass capacitors. Resistors R1 and R2 are the bias resistors. Variable
resistor VR1 is used to change the operation point of the transistor and it also
used to control the magnitude of the carrier, which inputs into the collector
of the transistor. Therefore, it can adjust the output signal waveform of the
modulator.
3－8
3-2 MC1496 AM Modulator
The main different between the design of AM modulator by using
balanced modulator and the transistor is that we can use the theory of
balanced modulator to cancel out the unwanted harmonics signals, which is
produced by the nonlinear characteristic of the transistor, then the remain
signal is the AM signal. In this chapter, we utilize the balanced modulator
(MC1496) to implement the AM modulator.
Follow the variation of input signal frequency, the balanced modulator
(MC1496) can become a frequency multiplier, AM modulator or double
sidebands suppressed carrier modulator (DSB-SC Modulator). Its input
signal, output signal and circuit characteristics are shown in table 3-1.
Table 3-1 Three different types of modulation signal produced by different signals
frequency of balanced modulator.
Input Carrier Input Audio Output Balanced Circuit

Signal Signal Modulator Characteristics
Frequency
fc fc 2f c
Multiplier
Amplitude
fc fm fc , fc  f m , fc  f m
Modulator
DSB-SC
fc fm fc  fm , fc  fm
Modulator
3－9
Figure 3-6 is the internal circuit diagram of MC1496, where D1, R1, R2,
R3, Q7 and Q8 comprise an electric current source, which can supply DC
bias current for Q5 and Q6. Q5 and Q6 comprise a differential combination to
drive the dual differential amplifiers constructed by Q1, Q2, Q3 and Q4. Pin 1
and 4 are the inputs of audio signal, after that this signal will be amplified
by the differential amplifier, which is comprised by Q5 and Q6. Pin 8 and 10
are the inputs of carrier signal. Then the amplified audio signal will multiply
by the carrier signal at the dual differential amplifiers constructed by Q1, Q2,
Q3 and Q4. Finally, the output signals can be obtain at the collectors of Q1,
Q2, Q3 and Q4, respectively. The resistor between pins 2 and 3 controls the
gain of the balanced modulator; the resistor of pin 5 determines the
magnitude of bias current for amplifier.
(12)

Output

Q1 Q2 Q3 Q4 (6)
Carrier (10)
Signal 
Input 
(8) Q5 Q6
(4)
Audio 
Signal
Input (2)
 Gain
(1) Q7 Adjustment
Terminal
Bias Q8 (3)
Adjustment
(5) D1
Terminal
R2 R3
R1 500
(14) 500
500
V
Figure 3-6 Internal circuit diagram of MC1496.
3－10
Figure 3-7 is the circuit diagram of AM modulator. We can see that the
carrier signal and audio signal belong to single ended input. The carrier
signal input from pin 10 and the audio signal input from pin 1. Therefore R8
determine the gain of the whole circuit and R9 determine the magnitude of
bias current. If we adjust the variable resistor VR1 or change the input
amplitude of audio signal, then we can control the percentage modulation of
AM modulator.
C3 R7 1 k
+12 V
100 uF
+
R4 C5 C8
VR2
10 k 100 nF 100 uF
1k
Carrier TP1 8
Signal R9 R11
Input R5 3k9 3k9
C2 100 C6
100 uF TP2 100 nF
10 6 AM
Audio + TP5 Output
C1 TP3 MC1496
Signal Signal
1 Balanced 12
Input
100 nF Modulator TP6 C7
R1 100 nF
10 k TP4 TP7
4 5
R2 R3 R6 R10
VR1 14
100 6k8
100 k 10 k 100
R8
-12 V
100
+
C4 Z1
100 uF 5V
Figure 3-7 Circuit diagram of amplitude modulation by utilizing MC1496.
3－11
Experiment 1: Transistor AM modulator
1. Refer to the circuit diagram in figure 3-5 or figure ACS3-1 on

ACT-17300-02 module.
2. At audio signal input port (Audio I/P), input 100 mV amplitude, 1 kHz sine
wave frequency; at carrier signal input port (Carrier I/P), input 300 mV
amplitude, 500 kHz sine wave frequency.
3. By using oscilloscope, observe on output signal waveforms of AM

output port (AM O/P). Adjust VR1 so that the modulated AM signal is
the maximum without distortion. Then records the measured results in
table 3-2.
4. By using oscilloscope, observe on output signal waveforms of the base

(TP1) and collector (TP3) of the transistor. Then record the measured
5. By using oscilloscope, observe on output signal waveforms of the

mixing (TP2) of the transistor. Then record the measured results in
table 3-2.
6. By using spectrum analyzer, observe on the frequency spectrum of AM

O/P and TP2. Then record the measured results in table 3-2.
7. Substitute the measured results into equation (3-4), find the modulation
percentage and record in table 3-2.
3－12
8. According to the input signals in table 3-2, repeat step 4 to 7 and record
the measured results in table 3-2.
Experiment 2: MC1496 AM modulator

Experiment 2-1: Observe on the variation of AM modulator
by changing the amplitude and frequency
of audio signal

ACT-17300-02 module. Let J1 be short circuit, J2 be open circuit; i.e.
R 10  6.8 k .

output ports (AM O/P1 and AM O/P2). Adjust VR2 so that the signal at
AM O/P1 is the maximum without distortion. Adjust VR1 so that the
modulation index of the AM signal reaches 50 %. Then records the
measured results in table 3-4.
4. By using oscilloscope, observe on output signal waveforms of the pin 1

(TP3), pin 4 (TP4), pin 8 (TP1),and pin 10 (TP2) of the balanced
modulator. Then record the measured results in table 3-4.
3－13

mixing (TP5 and TP6) of the balanced modulator and the bias operation
point (TP7). Then record the measured results in table 3-4.

O/P1, AM O/P2, TP5 and TP6. Then record the measured results in
table 3-4.
9. Let J1 be open circuit and J2 be short circuit, i.e. change the resistor R10
= 6.8 k to R12 = 3.3 k. Repeat step 2 to step 8 and record the

by changing the amplitude and frequency
of carrier signal

ACT-17300-02 module. Let J1 be open circuit, J2 be short circuit; i.e.
R12 = 3.3 k.
3－14

output ports (AM O/P1 and AM O/P2). Adjust VR2 so that the signal at
AM O/P1 is the maximum without distortion. Adjust VR1 so that the

(TP3), pin 4 (TP4), pin 8 (TP1), and pin 10 (TP2) of the balanced

mixing (TP5 and TP6) of the balanced modulator and the bias operation
point (TP7). Then record the measured results in table 3-7.

O/P1, AM O/P2, TP5 and TP6. Then record the measured results in
table 3-7.
3－15

by changing the variable resistor VR1

R12 = 3.3 k.

output ports (AM O/P1 and AM O/P2). Adjust VR1 so that the

O/P1 and AM O/P2. Then record the measured results in table 3-9.
3－16

by changing the variable resistor VR2

R12 = 3.3 k.

output ports (AM O/P1 and AM O/P2). Adjust VR1 so that the
modulation index of the AM signal reaches 50 %.
4. Adjust VR2 so that the resistance are 0 , 5 k and 10 k, the others
remain. Then record the measured results in table 3-10.
3－17

Table 3-2 Observe on the variation of amplitude modulation by changing the
amplitude of audio signal. (fm = 1 kHz, fc = 500 kHz, Vc = 300 mV)
Output Signal Audio Signal Amplitudes

Ports 100 mV 150 mV
AM O/P
TP1
TP3
TP2
AM O/P
Output Signal
Spectrums
TP2
Output Signal
Spectrums
E max  E max 
Modulation
Index E min  E min 
m % m %
3－18

frequency of audio signal. (Vm = 100 mV, fc = 500 kHz, Vc = 300 mV)
Output Signal Audio Signal Frequencies

Ports 100 Hz 400 Hz
AM O/P
TP1
TP3
TP2
AM O/P
Output Signal
Spectrums
TP2
Output Signal
Spectrums
E max  E max 
Modulation
m % m %
3－19

amplitude of audio signal. (fm = 1 kHz, fc = 500 kHz, Vc = 300 mV, R10 =
6.8 k)

Ports 600 mV 300 mV
AM O/P1
AM O/P2
TP3
TP4
3－20

amplitude of audio signal. (Continue) (fm = 1 kHz, fc = 500 kHz, Vc = 300
mV, R10 = 6.8 k)

Ports 600 mV 300 mV
TP1
TP2
TP5
TP6
3－21

amplitude of audio signal. (Continue) (fm = 1 kHz, fc = 500 kHz, Vc =
300 mV, R10 = 6.8 k)
Output Audio Signal Amplitudes

Signal Ports 600 mV 300 mV
TP7
AM O/P1
Output
Signal
Spectrums
AM O/P2
Output
Signal
Spectrums
TP5
Output
Signal
Spectrums
TP6
Output
Signal
Spectrums
E max  E max 
Modulation
m % m %
3－22

amplitude of audio signal. (fm = 1 kHz, fc = 500 kHz, Vc = 300 mV, R12 =
3.3 k)

Ports 600 mV 300 mV
AM O/P1
AM O/P2
TP3
TP4
3－23

amplitude of audio signal. (Continue) (fm = 1 kHz, fc = 500 kHz, Vc = 300
mV, R12 = 3.3 k)

Ports 600 mV 300 mV
TP1
TP2
TP5
TP6
3－24

300 mV, R12 = 3.3 k)

TP7
AM O/P1
Output
Signal
Spectrums
AM O/P2
Output
Signal
Spectrums
TP5
Output
Signal
Spectrums
TP6
Output
Signal
Spectrums
E max  E max 
Modulation
m % m %
3－25

frequency of audio signal. (Vm = 600 mV, fc = 500 kHz, Vc = 300 mV, R12
= 3.3 k)

Ports 1 kHz 2 kHz
AM O/P1
AM O/P2
TP3
TP4
3－26

frequency of audio signal. (Continue) (Vm = 600 mV, fc = 500 kHz, Vc =
300 mV, R12 = 3.3 k)

Ports 1 kHz 2 kHz
TP1
TP2
TP5
TP6
3－27

300 mV, R12 = 3.3 k)

TP7
AM O/P1
Output
Signal
Spectrums
AM O/P2
Output
Signal
Spectrums
TP5
Output
Signal
Spectrums
TP6
Output
Signal
Spectrums
E max  E max 
Modulation
m % m %
3－28

amplitude of carrier signal. (Vm = 600 mV, fm = 1 kHz, fc = 500 kHz, R12
= 3.3 k)
Output Signal Carrier Signal Amplitudes

Ports 200 mV 300 mV
AM O/P1
AM O/P2
TP3
TP4
3－29

amplitude of carrier signal. (Continue) (Vm = 600 mV, fm = 1 kHz, fc =
500 kHz, R12 = 3.3 k)
Output Signal Carrier Signal Amplitudes

Ports 200 mV 300 mV
TP1
TP2
TP5
TP6
3－30

amplitude of carrier signal. (Continue) (Vm = 600 mV, fm = 1 kHz, fc =
500 kHz, R12 = 3.3 k)
Output Carrier Signal Amplitudes

TP7
AM O/P1
Output
Signal
Spectrums
AM O/P2
Output
Signal
Spectrums
TP5
Output
Signal
Spectrums
TP6
Output
Signal
Spectrums
E max  E max 
Modulation
m % m %
3－31

frequency of carrier signal. (Vm = 600 mV, fm = 1 kHz, Vc = 300 mV, R12
= 3.3 k)
Output Signal Carrier Signal Frequencies

Ports 500 kHz 1 MHz
AM O/P1
AM O/P2
TP3
TP4
3－32

frequency of carrier signal. (Continue) (Vm = 600 mV, fm = 1 kHz, Vc =
300 mV, R12 = 3.3 k)
Output Signal Carrier Signal Frequencies

Ports 500 kHz 1 MHz
TP1
TP2
TP5
TP6
3－33

frequency of carrier signal. (Continue) (Vm = 600 mV, fm = 1 kHz, Vc =
300 mV, R12 = 3.3 k)
Output Carrier Signal Frequencies

Signal Ports 500 kHz 1 MHz
TP7
AM O/P1
Output
Signal
Spectrums
AM O/P2
Output
Signal
Spectrums
TP5
Output
Signal
Spectrums
TP6
Output
Signal
Spectrums
E max  E max 
Modulation
m % m %
3－34
Table 3-9 Observe on the variation of amplitude modulation by changing the variable
resistor VR1. (Vm = 600 mV, fm = 1 kHz, Vc = 300 mV, fc = 500 kHz, R12 =
3.3 k)
Modulation Output Signal Output Signal Modulation

Index Waveforms Spectrums Percentages
E max 
AM
O/P1 E min 
m= %
30 %
E max 
AM
O/P2 E min 
m= %
E max 
AM
O/P1 E min 
m= %
50 %
E max 
AM
O/P2 E min 
m= %
E max 
AM
O/P1 E min 
m= %
110 %
E max 
AM
O/P2 E min 
m= %
3－35

variable resistor VR2. (Vm = 600 mV, fm = 1 kHz, Vc = 300 mV, fc = 500
kHz, R12 = 3.3 k)
Magnitudes of
Output Signal Output Signal Modulation
Variable
Waveforms Spectrums Percentages
Resistor VR2
E max 
AM
O/P1 E min 
m= %
0
E max 
AM
O/P2 E min 
m= %
E max 
AM
O/P1 E min 
m= %
5 k
E max 
AM
O/P2 E min 
m= %
E max 
AM
O/P1 E min 
m= %
10 k
E max 
AM
O/P2 E min 
m= %
3－36

 
1. Explain the objectives of the transistor Q1 in figure 3-5.
2. Explain the objectives of the inductor L1, capacitor C3 and resistor R3 in

figure 3-5.
3. Explain the objectives of the variable resistor VR1 in figure 3-7.
4. Refer to figure 3-7, if we let J2 be short circuit, J1 be open circuit, i.e. R10
changes to R12, which its value is 6.8 k changed to 3.3 k. Then
describe the variation of the DC bias current of MC1496.
5. Refer to figure 3-7, if we adjust the magnitude of the variable resistor VR2
from small to large, then describe the variation of the output signal of AM
modulator.
6. When modulation index, m = 50 % and 110 %, what are the ratio of Emax
and Emin?
3－37
3－38
Chapter 4
AM Demodulator
1. To understand the theory of amplitude demodulation.
2. To design and implement the diode detection amplitude

demodulator.
3. To design and implement the product detection amplitude

demodulator.
4. To understand the measurement and adjustment of AM

demodulator.
From Chapter 3, we know that the amplitude modulation signal
utilizes the amplitude of audio signal to modulate high frequency carrier
signal. Therefore, when we receive the amplitude modulation signal, we
need to restore the audio signal. Figure 4-1 is the theory diagram of
amplitude modulation. Normally detector can be classified as synchronous
detector and asynchronous detector. We will discuss these two types of
detectors in this chapter.
4－2
Chapter 4 AM Demodulator
4-1 Diode Detector for Amplitude Demodulation
Since amplitude modulation signal utilizes audio signal to modulate
carrier signal, which means the variation of carrier signal amplitude is
followed by the change of audio signal amplitude. Hence the objective of
amplitude demodulator is to take out the variation envelop detection from
modulated AM signal. Figure 4-2 is the block diagram of diode detector.
This circuit is a typical asynchronous detector. It rectifies the modulated AM
signal and obtains a positive half wave signal. After that the signal will pass
through a low-pass filter and obtain an envelop detection. Then get rid of the
DC signal, the audio signal will be recovered. If the input signal of the diode
detector is the over modulated AM signal, as shown in figure 4-2 then we
are unable to recover the distorted signal to the audio signal by the diode
detector. As for the over modulated AM signal, we need to use the product
detector to demodulate this kind of signal, which will be discussed in next
section.
AM
Demodulator
Modulated AM Signal Audio Signal
Figure 4-1 Theory diagram of amplitude demodulator.
4－3
Modulated AM Signal
Low-pass
Rectifier DC Block Audio Signal
Filter
Over Modulated AM Signal
Figure 4-2 Block diagram of diode detector.
R2 2k2
R4 4k7
R1 +12 V
AM
R3 +12 V D1
Signal C3
Input 1k uA741 1N4004
TP3 R5 TP4 100 nF
Audio
Signal
TP1 1k LM318
Output
-12 V TP2 1k
-12 V C1 C2 R6
10 nF 10 nF 4k7
Amplifier Diode Detector
Figure 4-3 Circuit diagram of diode detector.
Figure 4-3 is the circuit diagram of diode detector, in which resistors
R1, R2, R3, R4, U1 and U2 form two groups of inverting amplifiers to amplify
the input signal, the amplified rate is 10 times of the original signal; Diode
D1 is the rectifier diode which can make the amplitude modulation signal
become a positive half wave signal; Capacitors C1, C2 and resistors R5, R6
comprise a low-pass filter to remove the envelop detection signal of audio
signal which includes the DC level; then finally the objective of C3 is to
block the DC level and we can obtain a pure audio signal at output port.
4－4
4-2 Product Detector for Amplitude Demodulation
The AM demodulator can be implemented by utilizing a balanced
modulator. We call this type of modulator as synchronous detector or
product detector. Figure 4-4 is the block diagram of product detector. In
figure 4-4, we notice that the design of product detector is to multiply the
modulated AM signal by the synchronized carrier signal in AM modulator.
Let x AM ( t ) be the modulated AM signal, x c ( t ) be the carrier signal, i.e.:
x AM ( t )  A DC  1  m cos (2 f m t ) A c cos (2 f c t ) (4-1)
x c ( t )  A c cos (2 f c t ) (4-2)
When these two signals input into two different ports of balanced
modulator, then the output signal of the balanced modulator is as follow
x out (t )  kx c (t ) x AM (t )
 k A DC A c2  1  m cos (2f m t )cos2 (2f c t )
k A DC A c2 k A DC A c2
  m cos (2f m t )
2 2
k A DC A c2
  1  m cos (2f m t)cos2 (2f c t) (4-3)
2
Where k represents the gain of the balanced modulator, in equation
(4-3), the first term is the DC signal, second term is the audio signal and
third term is the second harmonic of modulated AM signal. If we can take
4－5
out the second term from xout (t) by using the low-pass filter as shown in
figure 4-4, then we can obtain the exact demodulated AM signal or audio
signal.
Modulated Audio
AM signal LPF
Signal
Input Output
Carrier Signal
Figure 4-4 Block diagram of product detector.
Figure 4-5 is the circuit diagram of product detector. Variable resistor
VR1 controls the input magnitude of carrier signal; variable resistor VR2
controls the input magnitude of modulated AM signal; then the output
signal of MC1496 is located at pin 12. C 7 , C 9 and R 8 comprise a
low-pass filter which can remove the unwanted third term of equation
(4-3), i.e. second harmonic of amplitude modulated signal. The DC signal,
which is the first term of equation (4-3), can be blocked by C10. Therefore
the signal that we obtain at output port will be:
k A DC A c2
x out ( t )  m cos (2 f m t ) (4-4)
2
Equation (4-4) represents the audio signal or in other words the
original modulated AM signal can be taken out via product detector.
4－6
These two types of detectors have their own advantages and
disadvantages. As for diode detector, which is asynchronous detector, its
circuit is simple but the performances are not as better as product detector.
However for product detector, which is synchronous detector, it has good
performances but the circuit is more complicated than diode detector.
Further more it also requires synchronous for both carrier signal and
amplitude modulated signal (same frequency and same phase), otherwise it
will affect the quality of the output signal.
R2 1 k R4 2 k
+12 V
+
C4 C8
C1 R1 VR3
10 k 100 uF
100 nF 1k
100 nF
TP1 8
R6 R7
VR1 R3 2k 2k
100 k C3 1k
Carrier 100 nF
Signal
TP2
10 MC1496 6 TP5 C10
Input C2 R8
TP3 Balanced TP6 TP7 2u2 F Audio
AM 1 Modulator 12 + Signal
Output
+
Signal 100 nF 1k
C6
Input 2u2 F C7 C9
R5 1 nF 1 nF
VR2 TP4 10 k
100 k 4
5
C5 14
100 nF
Figure 4-5 Circuit diagram of product detector.
4－7
Experiment 1: Diode detector

ACT-17300-02 module. Let J1 be short circuit and J2 be open circuit to
produce the modulated AM signal as the signal source in this
experiment.
3. Adjust VR1 so that the modulation index of the AM signal is the

maximum. Adjust VR2 so that the signal at AM O/P1 is 250 mVP-P.
4. Connect the output signal of the AM modulator (AM O/P1) to the input
port (AM I/P) of diode detector in figure 4-3 or figure ACS4-1 on
5. By using oscilloscope and switching to DC channel, observe on the first

stage (TP1) and second stage (TP2) amplified signal waveforms. Then
record the measured results in table 4-1.
6. By using oscilloscope, observe on the output signal waveforms of the

rectifier (TP3). Then record the measured results in table 4-1.

low-pass filter (TP4) and the demodulated AM output port (Audio O/P).
Then record the measured results in table 4-1.
4－8
8. According to the input signals in table 4-1, repeat step 4 to step 7 and
Experiment 2: Product detector

Experiment 2-1: Observe on the variation of AM demodulator
by changing the amplitude and frequency of
audio signal

experiment.
3. Adjust VR1 so that the modulation index of the AM signal is 50 %.
port (AM I/P) of product detector in figure 4-5 or figure ACS4-2 on
ACT-17300-02 module. At the same time, also connect the carrier
signal input port (Carrier I/P) of the product detector with the same
carrier signal in AM modulator.
5. By using oscilloscope, observe on the output signal waveforms of

product detector (Audio O/P). Adjust VR1 and VR2 so that the signal at
4－9
Audio O/P is optimum without distortion. Adjust VR3 so that the signal
at Audio O/P is the maximum without distortion.
6. By using oscilloscope, observe on the output signal waveforms of AM

I/P, Carrier I/P and Audio O/P. Then record the measured results in
table 4-3.


multiplier (TP5 and TP6) of the balanced modulator and the low-pass
filter (TP7). Then record the measured results in table 4-3.
Experiment 2-2: Observe on the variation of AM demodulator

by changing the amplitude and frequency of
carrier signal

experiment.
4－10
3. By using oscilloscope, observe on the output signal waveform of

modulated AM signal (AM O/P1). Adjust VR1 so that the modulation
index of the AM signal is 50 %.
port (AM I/P) of product detector in figure 4-5 or figure ACS4-2 on
ACT-17300-02 module. At the same time, also connect the carrier
signal input port (Carrier I/P) of the product detector with the same
carrier signal in AM modulator.

product detector (Audio O/P). Adjust VR1 and VR2 so that the signal at
Audio O/P is optimum without distortion. Adjust VR3 so that the signal
at Audio O/P is the maximum without distortion.
6. By using oscilloscope, observe on the output signal waveforms of AM

I/P, Carrier I/P and Audio O/P. Then record the measured results in
table 4-5.


multiplier (TP5 and TP6) of the balanced modulator and the low-pass
filter (TP7). Then record the measured results in table 4-5.
4－11
4－12


AM I/P
TP1
TP2
TP3
TP4
Audio O/P
4－13

Output Audio Signal Frequencies

Signal Ports 3 kHz 6 kHz
AM I/P
TP1
TP2
TP3
TP4
Audio O/P
4－14


AM I/P
Carrier I/P
Audio O/P
TP3
TP4
4－15

300 mV)

TP1
TP2
TP5
TP6
TP7
4－16

Output Audio Signal Frequencies

Signal Ports 3 kHz 6 kHz
AM I/P
Carrier I/P
Audio O/P
TP3
TP4
4－17

300 mV)

TP1
TP2
TP5
TP6
TP7
4－18

amplitude of carrier signal. (fm = 2 kHz, Vm = 600 mV, fc = 500 kHz)

AM I/P
Carrier I/P
Audio O/P
TP3
TP4
4－19

amplitude of carrier signal. (Continue) (fm = 2 kHz, Vm = 600 mV, fc =
500 kHz)

TP1
TP2
TP5
TP6
TP7
4－20

frequency of carrier signal. (fc = 2 kHz, Vm = 600 mV, Vc = 300 mV)
Output Carrier Signal Frequencies

AM I/P
Carrier I/P
Audio O/P
TP3
TP4
4－21

frequency of carrier signal. (Continue) (fc = 2 kHz, Vm = 600 mV, Vc =
300 mV)
Output Cariier Signal Frequencies

TP1
TP2
TP5
TP6
TP7
4－22

 
1. By using diagram, explain the reasons why the diode detector is
unable to recover the over modulated AM signal to the original audio
signal.
2. Refer to figure 4-3, explain the results if we connect the output of AM

modulator to the diode detector without the two-stage amplifier, what
will be the results?
3. Refer to figure 4-3, describe the functions of low-pass filter in diode

detector. And also explain what kinds of components comprise the
low-pass filter.
4. Refer to figure 4-5, explain the results if the carrier signal and
modulated AM signal are asynchronous.
5. Refer to figure 4-5, explain the objectives of VR1 and VR2.
6. Refer to figure 4-5, explain the objectives of C7, C9 and R8.
7. Refer to figure 4-5, explain the objectives of VR3 and R5.
4－23
Chapter 5
DSB-SC and SSB

Modulator
1. To understand the operation theory of double sideband

suppressed carrier (DSB-SC) modulator and single sideband
(SSB) modulator.
2. To understand the waveforms and frequency spectrum of

DSB-SC and SSB modulators.
3. To design and implement the DSB-SC and SSB modulators.
4. To understand the measurement and adjustment of DSB-SC

and SSB modulators.

5-1 The Operation Theory of DSB-SC and SSB
Modulator
Figure 5-1 shows the waveforms of the amplitude modulation (AM).
Let the audio signal be A m cos (2 f m t ) and carrier signal be
A c cos (2 f c t ) , then the amplitude modulation can be expressed as
X AM  [A DC  A m cos(2f m t )]A c cos(2f c )

(5-1)
 A DC A c [1  m cos(2f m t )] cos(2f c t )
5－2
Chapter 5 DSB-SC and SSB Modulator
Am Ac
Audio Signal Carrier Signal

E max
E min
Amplitude Modulated Signal
Figure 5-1 Signal waveform of amplitude modulation.
where
m  A m / A DC .
A DC : DC signal magnitude.
A m : Audio signal amplitude.
A C : Carrier signal amplitude.
f m : Audio signal frequency.
f C : Carrier signal frequency.
m: Modulation index or depth of modulation.
We can rewrite equation (5-1) as
5－3
x AM ( t )  A DC A C m cos  2( f c  f m ) t   cos  2(f c  f m ) t 

1
2 (5-2)
 A D C A C cos 2 f c t 
The first term represents the double sideband signals; the second term
represents the carrier signal. From equation (5-2), we can sketch the
frequency spectrum of amplitude modulation as shown in figure 5-2(a).
Since the AM signal is hidden in the double sidebands and the carrier signal
does not contain any signal, therefore the power is consumed in carrier
during transmission of amplitude modulation signal. The double sideband
suppressed carrier (DSB-SC) modulation means the term
A DC A C cos(2f C t ) equals to zero, therefore, it can suppress the carrier
signal and only left the double sideband. We can use the DSB-SC
modulation to obtain the SSB modulation. We utilize two DSB-SC
modulators and let the phase difference between the two audio signals and
carrier signals be 90 degree, i.e. (DSB  SC) Q and (DSB  SC) I , as
shown in equation (5-3) and (5-4).
(DSB SC) P  cos2(f C  f m )t  cos2(f C  f m )t (5-3)
( DSB  SC ) Q  cos 2(f C  f m ) t  cos 2(f C  f m ) t (5-4)
Equations (5-3) and (5-4) show that both (DSB  SC) Q and
( DSB  SC) I signals connect to the adder, then we can obtain USSB or
LSSB signal at the output port.
5－4
X LSSB  (DSB  SC) I  (DSB  SC) Q
 cos 2(f C  f m ) t (5-5)
X LSSB  (DSB  SC) I  (DSB  SC) Q
 cos 2(f C  f m ) t (5-6)
Figure 5-2(a) is the frequency spectrum of AM signal. We can see that
the frequency spectrum consists of three kinds of signals, which are f c  f m ,
f c and f c  f m . The output voltage of fc is higher than the other two signals,
therefore, the carrier signal does not contain any signal, and the power is
consumed in carrier during transmission of amplitude modulation signal.
Figure 5-2(b) is the frequency spectrum of DSB-SC signal. We can see that
the frequency spectrum consists of two kinds of signals, which are f c  f m
and f c  f m . These two kinds of signals consists of the transmission signal,
therefore, by using this type of modulation, the power will not consume in
the carrier. Besides, as a result of the audio signal is hidden in the double
sideband, so, the stronger the double sideband signal, the transmission
efficiency will be better. From equation (5-2), we notice that the larger the
modulation index, the better the transmission efficiency. Generally, the
modulation index is smaller or equal to 1. If the modulation index is greater
than 1, we call this situation as over modulation. Figure 5-2(c) and figure
5-2(d) are the frequency spectrum of SSB signal. We can see that the
5－5
frequency spectrum consists of either f c  f m signal or f c  f m signal.
Therefore, during transmission, the power consumption of SSB modulation
is less than DSB-SC modulation. From the above-mentioned discussion, we
know that the sequence of power consumption of the three different types of
modulation is AM > DSB-SC > SSB.
x AM ( f )
A DC A c
0 .5 mA DC A c 0 .5 mA DC A c
f (Hz)
(a) Frequency spectrum of AM.
x AM (f )
0.5mADCA c 0.5mA DCA c
f (Hz)
(b) Frequency spectrum of DSB-SC.
x AM (f )
0.5mADCA c
f (Hz)
(c) Frequency spectrum of SSB.
5－6
x AM (f )
0.5mA DCA c
f (Hz)
fc  fm fc f c  fm
(d) Frequency spectrum of SSB.
Figure 5-2 Different frequency spectrums of AM modulation.
Audio Balanced DSB-SC Modulation

Signal Modulator Output
Carrier Signal
Figure 5-3 Block diagram of DSB-SC modulation.
5-2 Implementation of DSB-SC Modulator
DSB-SC modulation is a kind of AM modulation, therefore, we can
utilize the structure of AM modulator to implement the DSB-SC modulator.
Figure 5-3 is the block diagram of DSB-SC modulator. We utilize balanced
modulator MC1496 to design the DSB-SC modulated signal. Figure 5-4 is
the internal circuit diagram of MC1496, where D1, R1, R2, R3, Q7 and Q8
5－7
comprise an electric current source, which can supply DC bias current for
Q5 and Q6. Q5 and Q6 comprise a differential combination to drive the dual
differential amplifiers constructed by Q1, Q2, Q3 and Q4. Pin 1 and 4 are the
inputs of audio signal; Pin 8 and 10 are the inputs of carrier signal. The
resistor between pins 2 and 3 controls the gain of the balanced modulator;
the resistor of pin 5 determines the magnitude of bias current for amplifier.
(12)

Output

Q1 Q2 Q3 Q4 (6)
Carrier (10)
Signal 
Input 
(8) Q5 Q6
(4)
Audio 
Signal
Input (2)
 Gain
(1) Q7 Adjustment
Terminal
Bias Q8 (3)
Adjustment
(5) D1
Terminal
R2 R3
R1 500
(14) 500
500
V
Figure 5-4 Internal circuit diagram of MC1496.
Figure 5-5 is the circuit diagram of AM modulator. We can see that the
carrier signal and audio signal belong to single ended input. The carrier
signal is inputted from pin 10 and the audio signal is inputted from pin 1.
Therefore R8 determine the gain of the whole circuit and R9 determine the
5－8
magnitude of bias current. If we adjust the variable resistor VR1 or change
the input amplitude of audio signal, then we can control the percentage
modulation of amplitude modulation, which means we can adjust the output
become the DSB-SC modulation. By adjusting variable resistor VR2, we can
control the magnitude of the output amplitude, which is also the gain.
R7
1k 1k
+12
V
R3 C3 R8 1 k
0.1uF
R10 R11
3.9 k 3.9 k
C1 R4 2 3 DSB-SC
Carrier 51 8
0.1uF 6 Signal
Signal C4
10 Output
Input 0.1uF
MC1496
Audio C2
1 12
Signal
0.1uF 4
Input 14 5
R1 R2 R5 R6
10 k 10 k 300 1k
R9
50 k 6.8 k
VR1
5 V
Figure 5-5 Circuit diagram of DSB-SC modulation by utilizing MC1496.
5-3 Implementation of SSB Modulator
From equations (5-5) and (5-6), we know that the SSB modulator is
the combination of two DSB-SC modulators. Figure 5-6 is the block
diagram of SSB modulator, where the phase difference of each audio signal
and carrier signal of the two DSB-SC modulators is 90 degree (i.e. 90
degree phase difference between TP1 and TP2, and 90 degree phase
5－9
difference between TP3 and TP4). In figure 5-6, the block of the quadrature
phase shift and the phase shift represent the phase shifter. The circuit
diagram of phase shifter is shown in figure 5-7. By adjusting the variable
resistor, we can control the phase difference between the input and output
phase. The circuits of balanced modulator 1 and balanced modulator 2 are
similar to the circuit diagram in figure 5-5. Then the output terminals of the
two balanced modulators, which are TP5 and TP6 will be added by the
linearity adder, then we can obtain the modulated SSB signal. The circuit
diagram of the linearity adder is shown in figure 5-8. We utilize oscilloscope
or spectrum analyzer to observe TP5 and adjust VR1 of the balanced
modulator 1, so that the output is the modulated DSB-SC signal. By
adjusting the variable resistor VR2, we can control the gain of the DSB-SC
modulator so that the output amplitude is maximum without distortion.
Similarly, we utilize oscilloscope or spectrum analyzer to observe TP6 and
adjust VR1 of the balanced modulator 2, so that the output is the modulated
DSB-SC signal. By adjusting the variable resistor VR2, we can control the
gain of the DSB-SC modulator so that the output amplitude is maximum
without distortion. Finally, we use the spectrum analyzer to observe the
output signal terminal is whether the modulated SSB signal. If the frequency
spectrum is not true, we can adjust the variable resistor of the quadrature
phase shift.
5－10
TP1 TP5
Balance
Modulator 1 DSB Q
Quadrature Phase Signal
TP3
Phase
Shifter
45 45 Phase Linear
Phase Shift Adder
Audio Carrier  45 SSB
I/P Shifter I/P O/P
 45
TP4
In Phase Signal Balance DSB I

Modulator 2
DSB-SC
TP2 TP6 O/P
Figure 5-6 Block diagram of SSB modulator.
R2
10 k
R1 1 nF
C2 +12
10 k V
Signal uA741
Signal
Input Port Output Port
C1 -12 V
Phase 100 k
adjustment 100 pF
Figure 5-7 Circuit diagram of phase shifter.
5－11
R4
100 k
R1
+12 V
100 k
DSB Q
uA741
SSB
DSB I O/P
R2
100 k -12 V
R3
47 k
Figure 5-8 Circuit diagram of linearity adder.
5－12
Experiment 1: DSB-SC modulator

1. To implement a DSB-SC modulator as shown in figure 5-5 or refer to
figure ACS5-1 on ACT-17300-03 module.
2. At the audio signal input port (Audio I/P), input a 300 mV amplitude and
1 kHz sine wave frequency. Next at the carrier signal input port (Carrier
I/P), input a 300 mV amplitude and 100 kHz sine wave frequency.
3. By using oscilloscope, observe on both the audio signal output ports TP1
and TP2 at the same time. Next adjust variable resistor “QPS” so that the
phase difference between TP1 and TP2 is 90. Then record the measured
results in table 5-1. By using oscilloscope, observe on both the carrier
signal output ports TP3 and TP4 at the same time. Next adjust variable
resistor “Phase Adjust” so that the phase difference between TP3 and TP4
is 90. Then record the measured results in table 5-1.

DSB  SC Q modulation output port (TP5). Next adjust variable resistor
VR1 (gain adjustment) so that the output amplitude is maximum without

distortion, and also adjust variable resistor VR3 (modulation index
adjustment) so that the center level of upper peak and lower peak are 0 V
or the modulation index is 100 %. Finally, record the measured results in
table 5-2.
5. Change the oscilloscope to spectrum analyzer, observe on the output

signal waveforms of TP5 and record the measured results in table 5-2.
5－13

DSB  SC I modulation output port (TP6). Next adjust variable resistor
adjustment) so that the center level of upper peak and lower peak are 0 V
or the modulation index is 100 %. Finally, record the measured results in
table 5-3.

8. According to the input signals in table 5-4, repeat step 3 and record the
9. According to the input signals in table 5-4, repeat steps 4 and 5, then
observe on TP6 and the DSB  SC I output port (DSB-SC O/P). Finally,
observe on TP6 and the DSB  SC I output port (DSB-SC O/P). Finally,
5－14
Experiment 2: SSB modulator
1. To implement a SSB modulator as shown in figure 5-6 or refer to figure

ACS5-1 on ACT-17300-03 module.
2. At the audio signal input port (Audio I/P), input a 300 mV amplitude
and 1 kHz sine wave frequency. Next at the carrier signal input port
(Carrier I/P), input a 300 mV amplitude and 200 kHz sine wave
frequency.
and TP2 at the same time. Next adjust variable resistor “QPS” so that the
phase difference between TP1 and TP2 is 90. Then record the measured
results in table 5-10. By using oscilloscope, observe on both the carrier
signal output ports TP3 and TP4 at the same time. Next adjust variable
resistor “Phase Adjust” so that the phase difference between TP3 and
TP4 is 90. Then record the measured results in table 5-10.


adjustment) so that the center level of upper peak and lower peak are 0
V or the modulation index is 100 %. Finally, record the measured results
in table 5-11.

5－15

adjustment) so that the center level of upper peak and lower peak are 0
V or the modulation index is 100 %. Finally, record the measured results
in table 5-12.

8. By using oscilloscope, observe on the output signal waveforms of SSB

modulation output port (SSB O/P), then record the measured results in
table 5-13.
9. By using spectrum analyzer, observe on the output signal waveforms of

SSB modulation output port (SSB O/P), then record the measured results
in table 5-13.
5－16

Table 5-1 Measured results of phase adjustment.
(Audio I/P Vp = 300 mV, f = 1 kHz; Carrier I/P Vp = 300 mV, f = 100 kHz)
TP1
and
TP2
TP3
and
TP4
5－17
Table 5-2 Measured results of modulated DSB-SC signal (TP5).
Oscilloscope
Spectrum
Analyzer
5－18
Oscilloscope
Spectrum
Analyzer
5－19
Table 5-3 Measured results of modulated DSB-SC signal (TP6). (Continue)
Oscilloscope
Spectrum
Analyzer
5－20
TP1
and
TP2
TP3
and
TP4
5－21
Oscilloscope
Spectrum
Analyzer
5－22
Oscilloscope
Spectrum
Analyzer
5－23
Table 5-6 Measured results of modulated DSB-SC signal (DSB-SC O/P). (Continue)
Oscilloscope
Spectrum
Analyzer
5－24
TP1
and
TP2
TP3
and
TP4
5－25
Oscilloscope
Spectrum
Analyzer
5－26
Oscilloscope
Spectrum
Analyzer
5－27
Table 5-9 Measured results of modulated DSB-SC signal (DSB-SC O/P). (Continue)
Oscilloscope
Spectrum
Analyzer
5－28
TP1
and
TP2
TP3
and
TP4
5－29
Oscilloscope
Spectrum
Analyzer
5－30
Oscilloscope
Spectrum
Analyzer
5－31
Table 5-13 Measured results of SSB modulation signal ( SSB O/P ).
( Audio I/P Vp = 300 mV, f = 1 kHz; Carrier I/P Vp = 300 mV, f = 200 kHz )
Oscilloscope
Spectrum
Analyzer
5－32

 
1. Explain the definitions of DSB-SC modulation and SSB modulation.
2. Explain the reasons that why the audio signal and the carrier signal need
phase shifter to produce the orthogonal signal.
3. Explain the advantages and disadvantages of DSB-SC modulation and

SSB modulation.
4. Explain the output signal waveform of SSB O/P, if the phase difference of
DSB - SC Q and DSB - SC I is same. (Refer to the measured results from
oscilloscope and spectrum analyzer in table 5-13)
5－33
5－34
Chapter 6
DSB-SC and SSB

Demodulators
1. To understand the operation theory of double sideband

suppressed carrier (DSB-SC) demodulator and single
sideband (SSB) demodulator.
2. To design and implement the DSB-SC and SSB demodulators.
3. To measure and adjust the DSB-SC and SSB demodulators.
6-1 The Operation Theory of DSB-SC and SSB

Demodulator
When the modulated signal is recovered to the original audio signal,
the procedure is known as demodulation. In this chapter, we will discuss the
operation theory of DSB-SC and SSB demodulator.
Assume that a DSB-SC signal is X DSSC ( t )  m( t ) cos(2f C t ) , where
m(t) represents the audio signal or the low frequency signal. If this signal is
multiplied by 2 cos(2f C t ) , then we get
y D  kX DSSC ( t )2 cos(2f C t )
 m( t ) cos(2f C t )2 cos(2f C t ) (6-1)
 0.5m( t )[cos(4f C t )  1]
6－2
Chapter 6 DSB-SC and SSB Demodulator
By using Fourier Transform on equation (6-1), we can rewrite the
expression as
YD  0.5M (f ){0.5[(f  2f C )  (f  2f C )  (f )}

(6-2)
 0.5M (f )  0.25[ M (f  2f C )  M (f  2f C )]
When YD(f) pass through a low-pass filter, which its frequency
bandwidth equals or greater than the frequency bandwidth of m(t), but
smaller than 2fc, then the only term left in equation (6-2) is
X D (f )  0.5M (f ) (6-3)
By using Fourier Transform on equation (6-3), we get
x D ( t )  0 .5 m ( t ) (6-4)
From equations (6-1) to (6-3), we know that the synchronous
demodulator in figure 6-1 can recover the m(t) signal from the DSB-SC
signal.
yD (t )
Balanced
x DSSC ( t ) LPF x D (t)
Modulator
Carrier Signal
Figure 6-1 Block diagram of synchronous demodulator.
6－3
On the other hand, if we consider the phase difference (t) between the
carrier signals of the demodulator and modulator, then this situation will
cause the signal distortion and the demodulator is unable to recover the
original audio signal.
y D ( t )  kx DSSC ( t )2 cos(2f C t  ( t ))
 km( t ) cos(2f C t )2 cos(2f C t  ( t )) (6-5)
 0.5m( t )[cos(4f C t  ( t ))  cos(( t ))]
When yD(f) pass through a low-pass filter, which its frequency
bandwidth equals or greater than the frequency bandwidth of m(t), but
smaller than 2fc, then we get
x D ( t )  0.5m( t ) cos(( t )) (6-6)
In equation (6-6), if the phase difference (t) is a constant, then it will
cause attenuation on the amplitude. However, if the phase difference (t) is
a time domain function, then the signal will critically distort and unable to
recover to the original audio signal.
As for the SSB signal, it can be divided into upper SSB signal and
lower SSB signal. The expressions are as follow
x USSB ( t )  DSB P  DSB Q

(6-7)
 2 cos 2(f C  f m ) t
6－4
or
x LSSB ( t )  DSB P  DSB Q

(6-8)
 2 cos 2(f C  f m ) t
where
DSB P  k cos(2f m t ) cos(2f C t )
DSBQ  k sin(2f m t ) sin(2f C t )
f C : frequency of carrier signal.
f m : frequency of audio signal.
k: gain of the multiplier or mixer.
If equations (6-7) and (6-8) is multiplied 2 cos(2f C t ) , then we get
y DU ( t )  kx USSB ( t )[2 cos(2f C t )]
 0.5[2 cos 2(f C  f m ) t ][2 cos(2f C t )] (6-9)
 cos(2f m t )  cos 2(2f C  f m ) t
or
y DL ( t )  kx LSSB ( t )[2 cos(2f C t )]
 0.5[2 cos 2(f C  f m ) t ][2 cos(2f C t )] (6-10)
 cos(2f m t )  cos 2(2f C  f m ) t
6－5
When yDU(t) or yDL(t) pass through a low-pass filter, which its
frequency bandwidth equals or greater than the frequency bandwidth of m(t),
but smaller than 2fc, then we get
x D ( t )  cos(2f m t ) (6-11)
From equations (6-7) to (6-11), we know that the synchronous
demodulator in figure 6-2 can recover the m(t) signal from the SSB signal.
On the other hand, if we consider the phase difference (t) between the
carrier signals of the demodulator and modulator, then this situation will
cause the signal distortion and the demodulator is unable to recover the
original audio signal.
y DU ( t )  kx USSB ( t )[2 cos(2f C t  ( t ))]
 0.5[2 cos 2(f C  f m ) t ][2 cos(2f C t  ( t ))] (6-12)
 cos(2f m t  ( t ))  cos[2(2f C  f m ) t  ( t )]
or
y DL ( t )  kx LSSB ( t )[2 cos(2f C t  ( t ))]
 0.5[2 cos 2(f C  f m ) t ][2 cos(2f C t  ( t ))] (6-13)
 cos(2f m t  ( t ))  cos[2(2f C  f m ) t  ( t )]
Therefore, when yDU(t) pass through the low-pass filter, then we get
6－6
x USSB ( t ) y DU ( t )
Balanced
LPF x D (t )
x LSSB ( t ) Modulator y DL ( t )
Carrier Signal
Figure 6-2 Block diagram of synchronous demodulator.
x D ( t )  cos(2f m t  ( t ))
(6-14)
 cos(2f m t ) cos(( t ))  sin(2f m t ) sin(( t ))
Or when yDL(t) pass through the low-pass filter, then we get
x D ( t )  cos(2f m t  ( t ))
(6-15)
 cos(2f m t ) cos(( t ))  sin( 2f m t ) sin(( t ))
From equations (6-14) and (6-15), we know that if the phase
difference between the carrier signals of the demodulator and modulator
equals to each other, then x D ( t )  cos(2f m t ) . This situation indicates that
the audio signal can be recovered. If the phase difference is not zero, then
we notice that the demodulated signal will distort and unable to recover to
the original audio signal.
6－7
6-2 Implementation of DSB-SC and SSB Demodulator
From the above-mentioned discussion, we utilize the balanced
modulator to implement the DSB-SC and SSB synchronous detectors.
Assume that xAM(t) be the modulated DSB-SC and SSB signal, xc(t) be the
carrier signal, then
x c ( t )  A c cos (2 f c t ) (6-17)
When these two signals input into two differential ports of balanced
modulator, then the output signal of the balanced modulator is as follow
x out (t )  kx c ( t )  x AM ( t )
k A DC A c2 k A DC A c2 (6-18)
  m cos (2f m t )
2 2
k A DC A c2
  1  m cos (2f m t)cos2 (2f c t)
2
Where k represents the gain of the balanced modulator. The first term
is the DC signal, second term is the audio signal and third term is the second
harmonic of modulated AM signal. If we can take out the second term from
xout (t), then we can obtain the exact demodulated DSB-SC and SSB signals
or audio signal.
6－8
Figure 6-3 is the circuit diagram of synchronous product detector.

Variable resistor VR1 controls the input magnitude of carrier signal; variable
resistor VR2 controls the input magnitude of modulated AM signal; then
the output signal of MC1496 is located at pin 12. Capacitors C7, C9 and
resistor R9 comprise a low-pass filter which can remove the unwanted third
term of equation (6-18), i.e. second harmonic of modulated AM signal.
Since the active low-pass filter provides gain, so, the objective of the
low-pass filter is to prevent attenuation on the output signal due to the RC
circuit. The DC signal, which is the first term of equation (6-18), can be
blocked by C10. Therefore the signal that we obtain at output port will be
k A DC A c2
x out ( t )  m cos (2 f m t ) (6-19)
2

original modulated AM signal can be taken out via product detector.
R2 R4
1k 1k
+12 V
C1 R1 C4 R 51 k
100 nF 1k 100 nF C8
R7 R8 100 nF
C2 8 2 3 2k 2k
VR1 R3
10
Carrier100 k 1k 6
100 nF TP1
I/P MC1496
DSB-SC or SSB C3100 nF
1 Balanced +12V
I/P R9
Modulator TP2
12 + C10
1k Audio
C9 uA741
VR 2
14
100 nF O/P
+ 10 nF
100 k 4 5 C6 C7 -12V
2 u2F 100 nF
C5 R6 R11
100 nF R10
10 k
10 k +12 V 10 k
Figure 6-3 Circuit diagram of synchronous product detector.
6－9
Experiment 1: Product detector of DSB-SC demodulator
1. To implement a DSB-SC modulator as shown in figure 5-5 or refer to

figure ACS5-1 on ACT-17300-03 module to produce the modulated
DSB-SC signal source.
2. To implement a product detector of DSB-SC demodulator as shown in

figure 6-3 or refer to figure ACS6-1 on ACT-17300-03 module. Then let
J1 be short circuit and J2 be open circuit.
3. At the audio signal input port (Audio I/P) in figure ACS5-1, input a 300
mV amplitude and 1 kHz sine wave frequency. Then at the carrier signal
input port (Carrier I/P) in figure ACS5-1, input a 300 mV amplitude and
200 kHz sine wave frequency.
and TP2 in figure ACS5-1 at the same time. Next adjust variable resistor
“QPS” so that the phase difference between TP1 and TP2 is 90. Then
by using oscilloscope, observe on both the carrier signal output ports
TP3 and TP4 in figure 5-1 at the same time. Next adjust variable resistor
“Phase Adjust” so that the phase difference between TP3 and TP4 is 90.

VR1 (gain adjustment) so that the output amplitude of the carrier signal
is maximum without distortion, and also adjust variable resistor VR3
6－10
(modulation index adjustment) so that the center level of upper peak and
lower peak are 0 V or the modulation index is 100 %. By using
oscilloscope again, observe on the output signal waveforms of
lower peak are 0 V or the modulation index is 100 %.
6. Connect the modulated DSB-SCI signal (DSB-SCI O/P) in figure

ACS5-1 to the input terminal (DSB-SC/SSB I/P) of the product detector
in figure ACS6-1. At the same time, input the same carrier signal in
figure ACS5-1 to the carrier signal input port (Carrier I/P) in figure
ACS6-1.

product detector (Audio O/P) in figure ACS6-1. Next adjust variable
resistors VR1 and VR2, so that the output amplitude is the maximum
without distortion. Finally, record the output signal waveforms of the
product detector TP1, TP2 and the demodulated signal (Audio O/P) in
table 6-1.
8. Let J1 be open circuit and J2 be short circuit. Then repeat step 7 and
6－11
Experiment 2: Product detector of SSB demodulator
1. To implement a SSB modulator as shown in figure 5-6 or refer to figure

ACS5-1 on ACT-17300-03 module to produce the modulated SSB signal
source.
2. To implement a product detector of SSB demodulator as shown in figure

6-3 or refer to figure ACS6-1 on ACT-17300-03 module. Then let J1 be
short circuit and J2 be open circuit.
3. At the audio signal input port (Audio I/P) in figure ACS5-1, input a 300
mV amplitude and 2 kHz sine wave frequency. Then at the carrier signal
input port (Carrier I/P) in figure ACS5-1, input a 300 mV amplitude and
200 kHz sine wave frequency.
and TP2 in figure ACS5-1 at the same time. Next adjust variable resistor
“QPS” so that the phase difference between TP1 and TP2 is 90. Then
by using oscilloscope, observe on both the carrier signal output ports
TP3 and TP4 in figure 5-1 at the same time. Next adjust variable resistor
“Phase Adjust” so that the phase difference between TP3 and TP4 is 90.

lower peak are 0 V or the modulation index is 100 %. By using
6－12
oscilloscope again, observe on the output signal waveforms of

lower peak are 0 V or the modulation index is 100 %.
6. Connect the modulated SSB signal (SSB O/P) in figure ACS5-1 to the
input terminal (DSB-SC/SSB I/P) of the product detector in figure
ACS6-1. At the same time, input the same carrier signal in figure
ACS5-1 to the carrier signal input port (Carrier I/P) in figure ACS6-1.

product detector (Audio O/P) in figure ACS6-1. Next adjust variable
resistors VR1 and VR2, so that the output amplitude is the maximum
without distortion. Finally, record the output signal waveforms of the
product detector TP1, TP2 and the demodulated signal (Audio O/P) in
table 6-3.
8. Let J1 be open circuit and J2 be short circuit. Then repeat step 7 and
6－13

Table 6-1 Measured results of DSB-SC demodulator.
(J1 be short circuit, J2 be open circuit)
TP1
TP2
Audio
O/P
6－14
Table 6-2 Measured results of DSB-SC demodulator.
(J1 be open circuit, J2 be short circuit)
TP1
TP2
Audio
O/P
6－15
Table 6-3 Measured results of SSB demodulator.
(J1 be short circuit, J2 be open circuit)
TP1
TP2
Audio
O/P
6－16
Table 6-4 Measured results of SSB demodulator.
(J1 be open circuit, J2 be short circuit)
TP1
TP2
Audio
O/P
6－17
1. Explain the demodulation of the DSB-SC and SSB signals.
2. If the phase difference of the carrier signal in the synchronized

demodulator and the carrier signal in the modulator is different, then
explain what the results will be.
3. Explain the functions of low-pass filter in the synchronized demodulator.

And also explain what the output waveform will be, if the low-pass filter
is neglected.
6－18
Chapter 7
FM Modulator
1. To understand the characteristics of varactor diodes.
2. To understand the operation theory of voltage controlled

oscillator (VCO).
3. To design and implement the frequency modulator by using the

voltage controlled oscillator.
4. To design and implement the frequency modulator by using

MC4046.
5. To design and implement the frequency modulator by using

LM566.
7-1 The Operation Theory of FM Modulation
In frequency modulation (FM), we utilize the amplitude of audio signal to
7－2
Chapter 7 FM Modulator
modulate the frequency of carrier signal. The transmitted high and low
frequency signals will follow the received audio signal, which has different
frequency that keeps on changing. The frequency modulation can be
expressed as
x FM ( t )  A c cos ( t )  A c cos [ 2 f c t  2 f   x ( ) d ] (7-1)
If x ()  A m cos (2 f m  ) ,
Then
f Am
x FM ( t )  A c cos [ 2 f c t  sin (2 f m t )]
fm
= A c cos [ 2 f c t   sin (2 f m t )] (7-2)
Where
t  : Instantaneous modulated frequency.
f c : Carrier frequency.
f m : Modulating frequency or audio signal frequency.
: Modulation index,   A m (f  / f m ) .
f  : Frequency deviation.
7－3
Frequency deviation of FM x FM ( t ) is shown as below
1 d 1 d
f  ( t )  [ 2 f c t   sin (2 f m t ) ]
2 dt 2 dt
 f c  f m  cos (2 f m t )  f c  A m  f   cos (2 f m t ) (7-3)
From equation (7-3), we know that when the amplitude of modulating
signal changes, the frequency of FM will change too, and it uses the center
point of carrier frequency to achieve frequency deviation. From Carson’s rule,
the bandwidth (BW) of modulated signal can be expressed as
 A f 
BW  2(  2)  f m  2 m   2   f m  2 (A m f   2f m )
 fm 
If the FM signal is the largest amplitude and largest frequency (i.e. Am=1
and f m =W), then the bandwidth of FM can be simplified as
BW  2 (f   W )
7-2 Varactor Diode
Varactor diode is also called tuning diode. Varactor diode is a diode,
which its capacitance can be varied by adding a reverse bias voltage to the pn
junction. When reverse bias voltage increases, the depletion region becomes
wide, this will cause the capacitance value decreases; nevertheless when
7－4
reverse bias voltage decreases, the depletion region will be reduced, this will
cause the capacitance value increases. Varactor diode also can be varied from
the amplitude of AC signal. If an AC signal is added to a varactor diode, the
variation of capacitance of varactor diode will follow the amplitude of
modulating signal.
Figure 7-1 is the analog diagram of capacitance of varactor diode. When
a varactor diode does not have bias, the concentration will be different from
minor carriers at pn junction. Then these carriers will diffuse and become
depletion region. The p type depletion region carries electron positive ions,
then the n type depletion region carries negative ions. We can use parallel
plate capacitor to represent the depletion region.
PN Junction
+
- ++
N
P
+
+
+
Depletion Region
_ _ +
_ _ _ + + +
_ _ _ + + +
_ + +
Parallel Board
Substract
Figure 7-1 Analog diagram of capacitance of varactor diode.
7－5
The transition capacitance pn junction of the plates can be expressed as
A
C (7-4)
d
Where
  11.8  o (dielectric constant of Silicon).
 o  8.85x10 12 .
A : The PN junction area.
d : Depletion width.
When reverse bias voltage increases, the width of depletion region d will
increase but the cross section area A remains, therefore the capacitance value
would be reduced. On the other hand, the capacitance value will increase
when reverse bias voltage decreases.
Varactor diode can be equivalent to a capacitor series a resistor (Rs) and
an inductor (Ls) as shown in figure 7-2. From figure 7-2, Cj is the junction
capacitor of semiconductor, which only exits in pn junction. Rs is the sum of
bulk resistor and contact resistor of semiconductor material, which is related
to the quality of varactor diode (generally below a few ohm). Ls is the
7－6
equivalent inductor of bounding wire and semiconductor material.
Tuning ratio, TR is the ratio of capacitance value under two different
biases for varactor diode. The expression is shown as follow
Cj RS
Figure 7-2 Equivalent circuit diagram varactor diode.
CV2
TR  (7-5)
C V1
Where
TR : Tuning ratio.
C V1 : The capacitance value of varactor diode at V1 .
C V 2 : The capacitance value of varactor diode at V2 .
From this experiment, the characteristics of the varactor diode 1SV55 is
shown as below
C 3V  42 pF (The capacitance of varactor diode at bias 3 V ).
TR  2.65 (3 V ~ 30 V).
7－7
VCC
16
Phase 2 Phase Comp. 1
3 Comp. Out
Comp. In 13 Phase Comp. 2
1
14 Phase Out
Signal In
1 Comp.
Phase Pulses 2
4 VCO Out
6 CLA
VCO In 9 VCO 7
CLB
11 Max. Freq.
Demodulator 10 12 Min. Freq.
Out
8 5
GND INH
Figure 7-3 Block diagram of MC4046.
7-3 Implementation of FM Modulator by Using PLL

MC4046
MC4046 is the phase locked loop (PLL) integrated circuit. Figure 7-3 is
the internal structure diagram of MC4046. Pin 1, pin 10 and pin 15 are in N.C.
mode. Pin 5 is the input of INH, which is situated in low voltage level. The
VCO oscillation frequency of MC4046 is determined by the input voltage at
pin 9, the capacitances at pin 6 and pin 7, the resistances at pin 11 and pin 12.
7－8
Figure 7-4 is the circuit diagram of FM modulator by using MC4046. By
adjusting the variable resistor VR1 (DC level), we can control the output
frequency at pin 4, which is the frequency fo; capacitor C2, resistor R6 and R7
determine the oscillation frequency of fo; capacitor C2 and resistor R6

determine the maximum frequency of fo; capacitor C2 and resistor R7
determine the minimum frequency of fo, i.e. the modulation bandwidth.
R4
10 k
+12V
C1 R1 +12 V
A u di o
+
uA741 9 16
I/ P 10 k
100 nF -
+12V -12 V
R5 6
C2 4046 4 FM
7
R 2 4 k7 VCO O/P
10 nF 11
20 k
12
V R1 3 5 8
R6
10 k 56 k R7
R 100 k
3
20 k
Figure 7-4 Circuit diagram of MC4046 FM modulator.
7-4 Implementation of FM Modulator by Using VCO

LM566
LM566 is voltage-controlled oscillator integrated circuit. Figure 7-5 is
the internal structure diagram of LM566. Figure 7-6 shows the circuit
diagram of FM modulator by using LM566. We let SW1 be open circuit, and
7－9
the circuit is a voltage-controlled oscillator. The output signal frequency is
controlled by C3, VR1 and audio signal input terminal voltage. C2 is used to
eliminate parasitic oscillation. If C3 and VR1 remain a constant, then the
output signal frequency and the voltage difference between pin 8 and pin 5
( V8  V5 ) is proportional. In another words, when input signal voltage ( V5 )
increases, the voltage difference ( V8  V5 ) between pin 8 and pin 5 will
decrease, the output signal frequency will decrease as well. But, when input
signal voltage ( V5 ) decreases, the frequency of output signal will increase.
Another factor that affects the output signal frequency is VR 1  C 3 value, the
output signal frequency and VR 1  C 3 inverse proportionally. When the
VR 1  C 3 value is getting larger, the output signal frequency is getting lower.
But when the VR 1  C 3 value is getting smaller then the output signal
frequency is getting higher. From figure 7-6, when we short circuit SW1, then
R1 and R2 provide a DC bias voltage as the DC level of input audio signal.
The center frequency (fo) can be adjusted by using VR1. If audio signal input
terminal is inputted with an AC signal, the VCO output signal frequency will
follow the change of the input audio signal voltage, which the FM signal is
deviated.
7－10
GND 1 8 Vcc
Schmitt Trigger
Timing
2 7
Capacitor
Square Wave 3 Current Timing

6
Output Source Resistor
Triangle Modulation
Wave Output 4 5
Input
Figure 7-5 Internal structure diagram of LM566.
+5V
VR1
R1 5k
3 k3 8
FM
6 3
O/P
C2 LM566
C1 R3
10 nF VCO 4 k7
Audio 5
I/P R2 1 7
100 nF
8 k2 C3
DC
I/P 100 nF
-5V
Figure 7-6 Circuit diagram of LM566 FM modulator.
7－11
7-3: Experiment
Experiment 1: MC4046 FM modulator


modulated FM signal (FM O/P). Adjust variable resistor VR1 so that the
output signal is 20 kHz square wave. Then record the measured results in
table 7-1.
3. At the audio signal input port (Audio I/P), input 300 mV amplitude and 1
kHz sine wave frequency. By using oscilloscope, observe on the output
signal waveforms of FM O/P, then record the measured results in table
7-2.
7－12
Experiment 2: LM566 FM modulator

2. Let J1 be short circuit, i.e. the circuit is the FM modulator. J3 be short

circuit and J2 be open circuit, i.e. the selected capacitor is C4 = 10 nF.
Adjust variable resistor VR1 so that the frequency at the modulated FM
output port (FM O/P) is 20 kHz square wave. Then record the measured
3. At the audio signal input port (Audio I/P), input 300 mV amplitude and 1
kHz sine wave frequency. By using oscilloscope, observe on the output
signal waveforms of FM O/P, then record the measured results in table
7-4.
7－13

Table 7-1 Measured results of MC4046.
FM O/P
7－14
Table 7-2 Measured results of MC4046 FM modulator.
(f = 1 kHz, Vm = 300 mV)
FM O/P
7－15
Table 7-2 Measured results of MC4046 FM modulator. (Continue)
(f = 1 kHz, Vm = 300 mV)
FM O/P
7－16
Table 7-3 Measured results of LM566.
FM O/P
7－17
Table 7-4 Measured results of LM566 FM modulator.
(f = 1 kHz, Vm = 300 mV)
FM O/P
7－18
Table 7-4 Measured results of LM566 FM modulator. (Continue)
(f = 1 kHz, Vm = 300 mV)
FM O/P
7－19
1. Describe the operation theory of FM modulation.
2. Explain the implementation of FM modulator by using MC4046.
3. Explain the implementation of FM modulator by using LM566.
7－20
Chapter 8
FM Demodulator
1. To understand the operation theory of phase locked loop.
2. To understand the basic characteristics of MC4046 phase

locked loop.
3. To understand the basic characteristics of LM565 phase

locked loop.
4. To design and implement the FM demodulator by using

MC4046.
5. To design and implement the FM demodulator by using

LM565.

Frequency demodulator is also called frequency discriminator, which
can convert the variation of frequency to the variation of linear voltage.
8－2
Chapter 8 FM Demodulator
Normally we use FM to AM conversion circuit, balanced discriminator
circuit, phase-shift discriminator circuit and PLL synthesizer for the FM
demodulator. In this chapter, we will introduce the phase locked loop
frequency demodulator and FM to AM conversion discriminator.
8-1 The Operation Theory of Phase Locked Loop
Phase locked loop or PLL is a feedback circuit. In the feedback loop, the
feedback signal will lock the output signal frequency and phase with the same
frequency and phase of the input signal. So, for wireless communication, if
the frequency of the carrier signal deviates during transmission, then the PLL
in the receiver will operate and lock the carrier signal. In this experiment,
there are two types of using PLL, and the first type is demodulator, which is
used for demodulation by following the variation of phase and frequency. The
second is the carrier frequency tracking which is used to track the changes of
the frequency of the carrier signal and synchronize the oscillation.
Normally, phase locked loop can be divided into 3 sections, there are
1. Phase detector (PD)
2. Low-pass filter (LPF)
3. Voltage controlled oscillator (VCO)
8－3
From figure 8-1, the function of phase detector is to receive input signal
and VCO signal, then the two signals are compared by phase detector and
provided an output signal, which is a pulse signal. After that this signal is then
sent to a low-pass filter to remove the unwanted signal and left the DC
voltage.
Signal Vi Phase Vd Low-pass Ka

Input Detector K d Filter Singal
Amplifier Output
Vo
VCO Ko
Figure 8-1 Block diagram of phase locked loop.
This DC voltage can be used to control the output signal frequency of
VCO. Figure 8-1 is the block diagram of phase-locked loop, where
K d = The gain of phase detector ( Volts / Radian ).
Ｋａ = The gain of amplifier ( Volt / Volt ).
Ｋｏ = The gain of VCO ( kHz / Volt ).
ＫＬ = Kd Ka Ko = The gain of closed loop ( kHz / Radian ).
We use a simple circuit to explain the basic concept of phase detector.
8－4
From figure 8-2(a) shows the phase difference between two input signals is
the smallest, so the output signal pulse width is the narrowest. Then figure
8-2(b) shows the phase difference between two input signals is larger than
figure 8-2(a), so the output signal pulse width is wider than figure 8-2(a).
Figure 8-2(c) shows the phase difference between two input signals is the
largest and therefore the output signal pulse width is the widest. If this three
output signals pass through the low-pass filter to remove the AC signal, then
the magnitude of DC voltage in figure 8-2 is as follow: 1. figure 8-2(c) has the
highest DC voltage, 2. figure 8-2(b) is the second higher, and 3. figure 8-2(a)
is the lowest. The relation of DC voltage and the phase difference of A, B
input signals is shown in figure 8-2(d).
8－5
Input A
XOR Output
Input B
A
Input
B
Output
(a) (b) (c)
DC
Output
Signal
(V)
Input Signal
Phase Difference
0 90 180 270 360
(d)
Figure 8-2 Theory of phase detector.
From figure 8-3, assume that the free-running frequency of a VCO is set
to 1 kHz (assume the bias voltage is 2 V). If inputting a signal A is below 1
kHz and a signal B is higher than 1 kHz. From figure 8-3, we found that,
when input signal A frequency lower than the free-running frequency of VCO,
then the output of low-pass filter will receive a lower voltage level (assume is
1 V), this lower voltage level will adjust the oscillation frequency of VCO, so
that the oscillation frequency will decrease until the frequency of output
signal of VCO and the frequency of signal A equal to each other. When input
signal B frequency is higher than the basic frequency of VCO, the output
terminal of low-pass filter will receive a higher voltage (assume is 3 V), so
8－6
that the oscillation frequency of VCO will increase until the frequency of
output signal of VCO and the frequency of signal B equal to each other.
Normally the time needed for VCO locked frequency is very short. The
above-mentioned discussion is only the description of the concept, however,
practically; the circuit of phase detector is quite difficult and complicated.
Signal A Small DC
980Hz Voltage
XOR Output
VCO
1 kHz Large DC
XOR Voltage
Signal B
Output
1.2 kHz
1mS 1mS Low-pass Filter
Figure 8-3 Theory of locked frequency.
8-2 The Basic Characteristics of PLL LM565
(1) Free-running frequency
Figure 8-4 is a LM565 phase locked loop circuit diagram, from figure
8-4, when input terminal does not input any signal, the output signal
frequency of VCO is called free-running frequency. Where C 2 is timing
capacitor, VR1 is timing variable resistor, the free-running frequency (fo) of
LM565 is decided by C2 and VR1.
1
Free-running frequency: f o  (8-1)
3.7 VR 1 C 2
8－7
33.6f o
Closed loop gain: K L  K d K a K o  (8-2)
Vc
Where Vc = Total voltage supply = Vcc  ( Vcc )  5  (5)  10 V
+5V
6 10
C1
1 uF
Signal Vi 2 C3
Input Phase Vd R3 0.1 uF
Amp. Signal
3 Detector
R1 Ka 7 Output
0.68 k 3.6 k
5
Kd
SW1 C4
VCO 0.001uF
Ko LM565
4 Vo
R2
0.68 k
1 9 8
C2
0.1uF VR1
5K
5V +5V
Figure 8-4 LM565 phase locked loop.
(2) Locked Range
When phase-locked loop circuit is at already-locked situation, assume
the input signal frequency (fi) slowly move away from fo, when fi reaches at a
certain frequency, the PLL will leave the locked situation. At this moment,
the maximum frequency difference for frequency fi and fo is called
locked-range (refer to figure 8-5). The locked-range of LM565 is
8 fo
fL  (8-3)
VC
8－8
(3) Captured Range
At the beginning, PLL is at not locked situation, and then let the input
signal frequency fi slowly move close to fo, when fi reaches at a certain
frequency, PLL will be at already-locked situation. Then at this moment, the
frequency difference between fi and fo is called captured range (refer to
Figure 8-5). LM565 captured range is
 1  2  f L
fc    (8-4)
 2  3.6  10  C 2
3
fL fL
fc fc
f Lh
fi
f L1 f Cl fo fch Hz
Figure 8-5 Lock range and capture range diagram.
8-3 Implementation of FM demodulator by Using

LM565 PLL
Figure 8-4 is the circuit diagram of LM565 phase-locked loop, we can
use this circuit as a FM demodulator. When the input signal frequency
increases, then the output signal voltage decrease. However, when the input
signal frequency decreases, the output signal voltage will increase, therefore,
8－9
we can utilize the relationship between the voltage of PLL and frequency to
design the FM demodulator.
LM565 phase detector and VCO are designed in the IC package, this
VCO and LM566 are the same. The free-running frequency fo of VCO is
decided by the external C2 and VR1. The low-pass filter is comprised by the
internal resistor R3 at pin 7 and external capacitor C3. The objective of
capacitor C4, which is connected between pins 7 and 8 is to reduce the
parasitic oscillation.
Audio Signal
Input d Envelop DC
xFM(t) dt Detector Output
Blocked
Figure 8-6 Block diagram of FM to AM frequency discriminator.
8-4 Basic Characteristics of PLL MC4046
(1) Free-running frequency
Figure 8-6 is a MC4046 phase locked loop circuit diagram. From figure
8-6, when input terminal does not input any signal, the output signal
frequency of VCO is called free-running frequency. Where C 2 is timing
8－10
capacitor, VR1 is timing variable resistor, the free-running frequency (fo) of
MC4046 is decided by C2 and VR1.
1
Free-running frequency: f o  (8-5)
VR 1 C 2
(2) Locked Range
When phase-locked loop circuit is at already-locked situation, assume
the input signal frequency (fi) slowly move away from fo, when fi reaches at a
certain frequency, the PLL will leave the locked situation. At this moment,
the maximum frequency difference for frequency fi and fo is called
locked-range (refer to figure 8-5). The locked-range of MC4046 is
2fL = fmax - fmin (8-6)
(3) Captured Range
At the beginning, PLL is at not locked situation, and then let the input
signal frequency fi slowly move close to fo, when fi reaches at a certain
frequency, PLL will be at already-locked situation. Then at this moment, the
frequency difference between fi and fo is called captured range (refer to
Figure 8-5). The captured range of MC4046 is
1 2  f L
2f c    (8-7)
   R 1 R 2  C1 
8－11
+12 V
2 16 3 VCO
R1 9 4
4 k7 O/P
6
R2 C2 7
4046
PLL
680 10 nF 11 4 Audio
C1 12
3 5 8
O/P
10 nF R3
56 k VR1
100 k
Figure 8-6 Circuit diagram of MC4046 PLL.
8-5 Implementation of FM demodulator by

Using MC4046 PLL
Figure 8-6 is the circuit diagram of MC4046 phase-locked loop, which
its functions are similar to LM565, we can use this circuit as a FM
demodulator. When the input signal frequency increases, then the output
signal voltage decrease. However, when the input signal frequency decreases,
the output signal voltage will increase, therefore, we can utilize the
relationship between the voltage of PLL and frequency to design the FM
demodulator.
As a result of the demodulated audio signal consists of noise signal,
therefore, we utilize the low-pass filter in figure 8-7 to remove all the
unwanted signals. Capacitors C1, C2, resistors R1, R2, R3, R4 and A741
comprise an active low-pass filter. This structure is a voltage controlled
8－12
voltage source (VCVS) low-pass filter. The expression of the gain is
R4
Av  1 (8-8)
R1
Cutoff frequency is
1
fo  (8-9)
2 R 2 R 3C1C 2
If R 2  R 3  R and C1  C 2  C , then
1
fo  (8-10)
2RC
R 4 1 k5
R1
1 k5 +12 V
Audio
uA741
O/P
C1 R 2 -12 V
1 nF 10 k
Audio
I/P R3 C2
1 k5 1 nF
8－13
Experiment 1: LM565 FM demodulator
Experiment 1-1: Basic characteristics of LM565

2. Let J2 be short circuit and J3 be open circuit, i.e. C2 = 100 nF. Let J1 be
open circuit, i.e. SW1 be open circuit.
3. Adjust the variable resistor VR1, then measure the maximum ( f oh ) and
minimum ( f ol ) free-running frequencies (refer to figure 8-5) at the VCO
output port (VCO O/P). Then record the measured results in table 8-1.
4. Adjust the variable resistor VR1 so that the free-running frequency of

VCO O/P ( f o ) is 2 kHz.
5. Let J1 short circuit, and at the input port, input 0.25 V amplitude and 2
kHz square wave frequency.
6. By using oscilloscope, observe on the demodulated output port (Audio

O/P). Slightly increase the input signal frequency until the output signal
frequency of Audio O/P is unable to lock input signal. Then record the
signal frequency f Lh at this moment in table 8-1.
8－14
7. Readjust the input signal frequency to the free-running frequency ( f o ) of

PLL. Then decrease the input signal frequency until the output signal
frequency of Audio O/P is unable to lock input signal. Then record the
input signal frequency f Ll at this moment in table 8-1.
8. By using equation f L  (f Lh  f Ll ) / 2 , then calculate the locked range.
9. Increase the input signal frequency so that the output signal frequency of
Audio O/P is unable to lock the input signal. Then slightly decrease the
input signal frequency until the Audio O/P locks the input signal. Then
observe on the input signal frequency f Ch and record the measured
10. Decrease the input signal frequency so that the output signal frequency of
Audio O/P is unable to lock the input signal. Then slightly increase the
input signal frequency until the Audio O/P locks the input signal. Then
observe on the input signal frequency f Cl and record the measured
11. By using equation, f C  (f Ch  f Cl ) / 2 , then calculate the captured range.
12. Let J1 be open circuit, J3 be short circuit and J2 be open circuit, which
means that C2 changes to C5, i.e. 100 nF changes to 10 nF, then repeat
step 3.
8－15
13. Adjust the variable resistor VR1, so that the free-running frequency (fo) of
the VCO O/P is 20 kHz. Let J1 be short circuit and at the input terminal,
input 0.25 V amplitude and 20 kHz square wave frequency, then repeat
step 6 to step 11.
Experiment 1-2: Voltage and frequency conversion of LM565

2. Let J2 be short circuit and J3 be open circuit, i.e. C2 = 100 nF. Let J1 be
open circuit and adjust the variable resistor VR1 so that the free-running
frequency (fo) of VCO O/P is 2 kHz.
3. Let J1 be open circuit, i.e. SW1 be open circuit.
4. At the demodulated FM input port (FM I/P), input 0.25 V amplitude and
2 kHz square wave frequency. Then measure the voltage of Audio O/P
and record the measured results in table 8-2.
5. Change the input signal frequencies to 0.5 kHz, 1 kHz, 1.5 kHz, 2 kHz,
2.5 kHz, 3 kHz, 3.5 kHz. Then measure the voltage of Audio O/P and
6. Sketch the characteristic diagram with voltage versus frequency in figure

8-8.
7. Let J3 be short circuit and J2 be open circuit, which means that C2

changes to C5, i.e. 100 nF changes to 10 nF.
8－16
8. Let J1 be open circuit and adjust the variable resistor VR1, so that the
free-running frequency (fo) of the VCO O/P is 20 kHz.
9. Let J1 be open circuit, i.e. SW1 be open circuit.
10. At the FM I/P, input 0.25 V amplitude and 20 kHz square wave
frequency. Then measure the voltage of Audio O/P and record the
11. Change the input signal frequencies to 16.5 kHz, 17.5 kHz, 18.5 kHz, 20
kHz, 21.5 kHz, 22.5 kHz, 23.5 kHz. Then measure the voltage of Audio
O/P and record the measured results in table 8-3.
12. Sketch the characteristic diagram with voltage versus frequency in figure
8-9.
Experiment 1-3: LM565 FM demodulator

ACT-17300-04 module to produce the demodulated FM signal as the
signal source. Let J1 be short circuit, i.e. the circuit is the FM modulator.
J3 be short circuit and J2 be open circuit, i.e. the selected capacitor is C4
= 10 nF. Adjust variable resistor VR1 so that the frequency at the
modulated FM output port (FM O/P) is 20 kHz square wave.

ACT-17300-04 module. Let J3 be short circuit, J1 and J2 be open circuit,
8－17
i.e. C5 = 10 nF. Adjust the variable resistor VR1, so that the free-running
frequency (fo) of the VCO O/P is 20 kHz.
3. Connect the output port (FM O/P) of the VCO LM566 to the input port
(FM I/P) of the PLL LM565.
4. At the audio input port (Audio I/P) of the VCO LM566, input 250 mV
amplitude and 1 kHz sine wave frequency. By using oscilloscope,
observe on the output signal waveforms of the demodulated FM signal
(Audio O/P) at PLL LM565. Then record the measured results in table
8-4.
Experiment 2: MC4046 FM demodulator

ACT-17300-04 module to produce the demodulated FM signal as the
signal source. Adjust variable resistor VR1 so that the frequency at the
modulated FM output port (FM O/P) is 20 kHz square wave.

ACT-17300-04 module. Adjust the free-running frequency (fo) of the
VCO output port (TP1) be 20 kHz.
8－18
3. Connect the output port (FM O/P) of the VCO MC4046 to the input port
(FM I/P) of the PLL MC4046.
4. At the audio input port (Audio I/P) of the VCO MC4046, input 250 mV
amplitude and 1 kHz sine wave frequency. By using oscilloscope,
observe on the output signal waveforms of the demodulated FM signal
(Audio O/P) at PLL MC4046. Then record the measured results in table
8-6.
8－19
Table 8-1 Measured results of the basic characteristics of LM565 PLL.
Free-running
Locked Range fL Captured Range fC
Frequency Range
Ｃ2 fo
foh fol fLh fLl fCh fCl
Hz Hz Hz Hz
100
2 kHz
nF
Hz Hz fL = Hz fC = Hz
Hz Hz Hz Hz
10 20
nF kHz
Hz Hz fL = Hz fC = Hz
8－20
Table 8-2 Measured results of the voltage and frequency conversion characteristics of
LM565 PLL. (Vm = 0.25 V, fo =2 kHz, C2 = 100 nF)
Input Signal
Frequencies 0.5 1.0 1.5 2.0 2.5 3.0 3.5
(kHz)
Output Voltages
(V)
Output
Voltage
(V)
Input Signal
Frequency
0.5 1.0 1.5 2.0 2.5 3.0 3.5 ( kHz )
Figure 8-8 Characteristics curve of voltage versus frequency.
8－21
Table 8-3 Measured results of the voltage and frequency conversion characteristics of
LM565 PLL. (Vm = 0.25 V, fo =20 kHz, C5 = 10 nF)
Input Signal
Frequencies 16.5 17.5 18.5 20 21.5 22.5 23.5
(kHz)
Output Voltages
(V)
Output
Voltage
(V)
Input Signal
Frequency
0.5 1.0 1.5 2.0 2.5 3.0 3.5 ( kHz )
Figure 8-9 Characteristic curve of voltage versus frequency.
8－22
Table 8-4 Measured results of the input and output signal waveforms of PLL frequency
demodulator. ( Vm  250 mV , f o  20 kHz )
Audio signal
FM I/P Audio O/P
frequencies
1 kHz
2 kHz
3 kHz
8－23
Table 8-5 Measured results of the input and output signal waveforms of PLL frequency
demodulator. ( Vm  500 mV , f o  20 kHz )
Audio Signal
FM I/P Audio O/P
Frequencies
1 kHz
2 kHz
3 kHz
8－24
Table 8-6 Measured results of the input and output signal waveforms of FM to AM
conversion frequency demodulator. ( Vm  250 mV , f o  20 kHz )
Audio Signal
1 kHz 2 kHz
Frequencies
FM I/P
TP2
LPF IN
Audio O/P
8－25
Table 8-7 Measured results of the input and output signal waveforms of FM to AM
conversion frequency demodulator. ( Vm  500 mV , f o  20 kHz )
Audio Signal
1 kHz 2 kHz
Frequencies
FM I/P
TP2
LPF IN
Audio O/P
8－26
1. From the measured results of the basic characteristics experiment of

LM565 PLL, when the input signal frequency moves away from the
frequency locked range, what is the oscillation frequency of the VCO?
2. For LM565 PLL, compare the locked range and the captured range.
3. In figure 8-4, what are the functions for capacitor C3? If let C3 change
from 0.1 F to 0.01 F, what are the changes of the pin 7 of LM565?
4. In the LM565 frequency demodulator experiment, if the output signal

passes through the first order low-pass filter, then is the output signal
flatter than the previous one? Try to design the low-pass filter.
5. How to use the PLL circuit and the logic circuit to comprise a doubler
frequency circuit?
8－27
8－28
Chapter 9
TDM Multiplexer
1. To understand the operation theory of time-division

multiplexing (TDM).
2. To design and implement the TDM multiplexer.
3. To measure and adjust the TDM multiplexer.
In the communication system, the simultaneous transmission of
several separate information channels over the same communications circuit
without interference is called as multiplexing. Multiplexing can be
accomplished by time division or frequency division. In this chapter we will
discuss the operation theory of time division multiplex.
9-1 The Operation Theory of Sampling
Analog signal is the continuous function of time, which means the
signal is varied from time. If the signal is separated into several slots of time,
then we called this method as sampling.
First, we consider a fundamental signal, X(t) with a frequency
9－2
Chapter 9 TDM Multiplexer
bandwidth (fM) and a constant sample rate (TS), then the expression of the
sampling signal, S(t) is

S(t)=  X ( t )  ( t  nTS ) (9-1)
n  
S(t) can be assumed as the fundamental signal X(t) multiple by a delta
function ( ( t  nTS ) ) as shown in figure 9-1.
X(t) S(t)
t t


n  
(t  nTS )
Figure 9-1 Instantaneous sampling diagram.
This type of sampling mode is called as instantaneous sampling or
ideal sampling. In equation (9-1), by using Fourier transform, we can obtain
the spectrum of the sampling S(f) as

S(f)= f S   X (f  nf S ) (9-2)
n  
9－3
1
Where f S  .
TS
As a result of the instantaneous sampling utilizes delta function,
practically, it is difficult to implement. Therefore, by considering a signal
X(t) with a frequency bandwidth (fM), we can sample the signal with a
certain period sampling function t  nTS  . Assume that the amplitude
of the sampling function is 1, the period is TS, the width of the slot is , then
by sampling the signal X(t) with the sampling function, we can obtain Y(t)
as follow
 t  nTS
Y(t)=  X ( t )  ( ) (9-3)
n   
X(t) Y(t)
t t

t  nTS

n  
(

)
Figure 9-2 Natural sampling diagram.
9－4
The diagram of natural sampling is shown in figure 9-2. In equation
(9-3), by using Fourier transform, we can obtain the spectrum of the ideal
sampling Y(f) as

Y(f)= f S     sin c( nf S  )  X (f  nf S ) (9-4)
n  
Generally, when the fundamental signal X(t) passes through the
instantaneous sampling, we will obtain the sampling function S(t) and its
spectrum S(f) is the multiple permutation of the spectrum of the
fundamental signal. If the sampling frequency (fS) is large enough which is
fS > 2fM, then the permutation of the spectrum will separate without
overlapping. Hence, by using a low-pass filter, we can recover the spectrum
of the original fundamental signal X(t) as shown in figure 9-3.
S(f) LPF
f
-f S -f M fM fS-fM fS
Figure 9-3 Output signal spectrum of sampling when fS > 2fM.
In figure 9-3, we can see that if S(f) passes through a low-pass filter
(LPF), the frequency band will smaller than fS-fM but greater than fM, then
we can recover the original signal from the signal after sampling. However,
9－5
if the frequency bandwidth of the fundamental signal is fM, then the
frequency bandwidth of the sampling frequency (fS) must be greater than
2fM, or else, after sampling the signal will overlap and unable to recover the
original signal, as shown in figure 9-4. Therefore, the minimum sampling
frequency fS = 2fM is called as nyquist sampling frequency.
S(f) LPF
f
-f S fS
Figure 9-4 Output signal spectrum of sampling when fS＜2fM.
From the above-mentioned discussion, we know that the sampling
value is transmitted with a gap Ts, and the sampling value can be assumed
as a series pulse with different amplitudes. In order to have the function of
multiplexing, the Ts must be increased until it is enough for the sampling
value of other signal. Let the numbers of the input signals are M, then the
gap between the pulses is TS M  1 M  f S , therefore, after multiplexing,
the number of pulses per second is
r = M  f S ≧2M  f M (9-5)
where r is also known as pulse rate or signal rate.
9－6
9-2 Time Division Multiplexing (TDM)
Time division multiplexing (TDM) means multiple signals can be
transmitted over the same transmission channel. Time division indicates the
signal is divided into several slots in time domain, then these slots will
transmit to the receiver by following a fixed time slot. It uses the technique
of sampling to divide the signal into several slots, therefore, these slots is
also called as sampling values. If the fixed time slot is large enough for
other sampling value of other signal to fill in, then this method can achieve
the function of multiplexing. As for the TDM system with several input
signals, we can refer to the basic structure as shown in figures 9-5 and 9-6.
Y(t)
m1(t)
m2(t)
Figure 9-5 TDM system with two signals m1(t) and m2(t).
9－7
m 1 (t) Synchronous LPF m 1 (t)
m 2 (t) LPF m 2 (t)

Communication
Channel
mN (t) LPF mN (t)
Figure 9-6 Circuit structure of TDM system.
9-3 Waveform Generator
As a result of TDM uses the same channel to transmit several groups
of signals, therefore, in this chapter, we utilize sinusoidal, square and
triangle waves as the several groups of signals to achieve the TDM
modulation. The following are the discussion of the sinusoidal, square and
triangle waveform generators.
9-3-1 Sinusoidal Waveform Generator
We can utilize the Wien bridge oscillator to implement the sinusoidal
waveform generator. Figure 9-7 is the circuit diagram of sinusoidal
waveform generator. Resistors R1, R3 and the operational amplifier comprise
a close loop non-inverted amplifier. Resistors R2, R4 and capacitors C1, C2
comprise a feedback network which the phase different between Vo and Vf
is 0. From figure 9-7, we know that
R3
A ( j)  1  (9-6)
R1
9－8
1
R2
jC1
1
R2 
Vf jC1
( j)  
Vo 1
R2
1 jC1
R4  
jC 2 1
R2 
jC1
R2 1 R2 R4 R2
(   )
C 2  2 C1 C 2 C 2

1 1 R R R
(R 2 R 4  2 )2  2 ( 2  4  2 )
 C1 C 2  C1 C 2 C 2
1 R2 1
(R 2 R 4  2 )
 C2  C1C 2
j (9-7)
1 1 R R R
(R 2 R 4  2 )2  2 ( 2  4  2 )
 C1C 2  C1 C 2 C2
R3
Vf R3 Vo
A 1
R1 R1
+12V
Vo
A
-12V Output C2 R4
Vf
C2 R4 R2 C1
R2 C1 ( j)
Feedback
Network
(a) Circuit diagram of oscillator. (b) Oscillator feedback structure.
Figure 9-7 Circuit diagram of Wien bridge oscillator.
9－9
According to Barkhausen principle, we know that A ( jo )( jo )
should be a real number and the phase must be 0o during oscillation. From
equation (9-6), A ( jo ) is a real number, and from equation (9-7), the
imaginary part of ( jo ) is at the second term. Obviously, we can assume
this term as zero, that means
1 R2 1
(R 2 R 4  2 )
o C 2 o C1C 2
0 (9-8)
1 1 R2 R4 R2
(R 2 R 4  2 )  2(
2
  )
o C1C 2 o C1 C 2 C 2
1
o2  (9-9)
R 2 R 4 C1C 2
If R 2  R 4  R and C1  C 2  C , then, equation (9-9), i.e. the oscillation
frequency of Wien Bridge can be rewritten as
1
o  (9-10a)
RC
1
fo  (9-10b)
2RC
In this case, we consider the oscillation condition of Wien Bridge
oscillator, then we get
A ( jo )( jo )  R e {A ( jo )( jo )}  1 (9-11a)
9－10
R2 1 R2 R4 R2
(   )
C 2 o2 C1 C 2 C 2
A 1 (9-11b)
1 1 R R R
(R 2 R 4  2 )2  2 ( 2  4  2 )
o C1C 2 o C1 C 2 C 2
Then substituting equation (9-10a), R 2  R 4  R and C1  C2  C
into equation (9-11b). At the same time, when oscillation occurs, the loop
gain should be at least 1. Therefore, the oscillation conditions of Wien
Bridge oscillator are as follow
R3
A  (1  )3 (9-12a)
R1
R3
2 (9-12b)
R1
From the above-mention, in order to let the Wien Bridge oscillator to
oscillate in a proper way, the following conditions must be achieved
1
1. f o 
2RC
R3
2. A  (1  )3
R1
Unfortunately, we can only know that the amplifier gain of A should
be more than 3 from above-mentioned analysis about the Wien Bridge
oscillator, but there is no information about the value of the voltage, V o .
Practically, when the gain achieves the oscillation condition, the circuit will
9－11
output a sinusoidal waveform and the oscillation frequency will maintain at
f o  1 2RC . In addition, the output voltage may become larger and larger,
and then generate a non-linear distortion in the output waveform of
oscillators.
In order to prevent the non-linear distortion, which we have mentioned
before, we can utilize the structure of diodes amplitude-limited Wien Bridge
oscillator as shown in figure 9-8. In figure 9-8, since R 3  VR1  R 5 ,
therefore, we can adjust the magnitude of VR1 to satisfy the condition for
oscillation and let the gain of the amplifier larger than 3, i.e., a sinusoidal
wave frequency ( f o ) is produced. Nevertheless, when the amplitude of Vo
is very large, the diodes D1 and D 2 will conduct ( D 2 conducts when the
positive half cycles is very large, D1 conducts when the negative half
cycles is very small). Since D1 or D 2 conducts, this situation is as well
as shunt the forward-conducted resistor of diode and the result is the same
as to short R 5 . Then, R 3 will become smaller and A will decrease,
therefore, this situation will limit the increment of Vo to prevent the
non-linear distortion.
9-3-2 Triangle and Square Waveform Generators
We can implement the triangle waveform generator by using the
integrator as shown in figure 9-9. Then as for the square waveform
9－12
generator, we can obtain the square wave by using the comparator to
compare the triangle wave.
Assume that the output of U1 (O/P1) is positive voltage, and the two
terminals between capacitor C1 is 0 V. This is because the voltage at U1+
port is larger than U1- port, therefore, the output port (O/P1) is always
maintained at positive voltage and the capacitor C1 is charged by O/P1
through resistor R2 and variable resistor VR1. When the charge of capacitor
C1 is larger than (R1/R1+R3)VCC, the output will start to change from
positive voltage to negative voltage. The reason is the voltage at U1+ port is
smaller than U1- port, thus U1 can be used as a square wave generator. At
this moment, the output O/P1 is negative voltage and the capacitor C1 is
started to discharge by O/P1 through resistor R2 and variable resistor VR1.
When the charge of capacitor C1 is smaller than (R1/R1+R3)VCC, the output
will start to change from negative voltage to positive voltage. Then this
circuit can be used to produce triangle wave and square wave as shown in
figure 9-10. The function of variable resistor VR1 is to adjust the operation
period of the triangle wave, i.e. to adjust the frequency of the triangle wave.
Then U2, R4 and VR1 comprise a tunable inverting amplifier. The output
amplitude of the triangle wave is very small, therefore, it needs amplifier to
amplify the signal.
9－13
R3
D1 1N4148
R 5 3k3
VR 1 D 2 1N4148
5k
+12V
uA741
R1 O/P
2k -12V
C2
100 pF R 4
R2 C1 1k2
1k2 100 pF
Figure 9-8 Circuit diagram of diodes amplitude-limited Wien Bridge oscillator.
R2
100
VR 1 +12V
100 k
O/P1 O/P2
C1
10 nF uA741 uA741
-12V VR 1
R1 R3
10 k 100 k R4 100 k
10 k
Square Wave Generator Triangle Wave Generator
Figure 9-9 Circuit diagram of triangle wave and square wave generators.
9－14
V O/P1
+Vcc
-Vcc
O/P2
Figure 9-10 Output relation diagram of O/P1 and O/P2.
9-3-3 TDM Circuit
As a result of TDM uses the time slots to transmit signal, therefore, we
need to produce a time generator circuit, which can generate a fixed timing
as the switching circuit. Figure 9-11 is the circuit diagram of the switching
circuit with fixed timing. In figure 9-11, we utilize timer (NE555) and
counter (CD4017) ICs to implement the astable multivibrator and a divided
3 circuit, respectively. The time sequence is shown in figure 9-12. Then
9－15
finally match up the circuit with the analog switch (CD4066), we can obtain
the TDM circuit as shown in figure 9-13. When Q0 is at “High” level (ON),
the triangle wave will occur at the output port. When Q1 is at “High” level
(ON), the square wave will occur at the output port. When Q2 is at “High”
level (ON), the sinusoidal wave will occur at the output port. When the
counter counts to Q4, the IC CD4017 will reset and start to recount from Q0.
With this method, we can transmit the three different signals by using one
channel. Finally, we add a buffer at the output port, which is used as
impedance matching.
In figure 9-11, the operation period of NE555 is
T  0.7(100k * 2 *10K *100nF) (9-13)
The operation time (T) of NE555 is the time of every time slot, therefore,
the operation period is same. Then with this reference, we can obtain the
original signal during demultiplexing.
9－16
R1
100 k 16
4 8
7 3 t1
2 t2
R2
+
555 3 13
Vcc 10 k Timer 4017 4 t3
2 Counter
6 15 7
Vc C1 1 5 8
100 nF
C2
10 nF
Figure 9-11 Circuit diagram of time generator.
t0
t1
t2
Clk
Figure 9-12 Time sequence of the time generator.
9－17
CD 4066
Triangle
Wave
t1
-
Square U1
Wave +
TDM
Output Signal
t2
Sinusoidal
Wave
t3
Figure 9-13 Circuit diagram of TDM multiplexer.
9－18

參實驗項目
Experiment 1: Waveform Generator
1. Refer to the sinusoidal, triangle and square waves generator in figure 9-8
and figure 9-9 or refer to figure ACS9-1 of ACT-17300-05 module.
2. By using oscilloscope, observe on the output signal waveform of triangle

wave output port (TP1). Adjust variable resistor VR3 so that the amplitude
of TP1 is maximum without distortion, then record the output signal
waveform and voltage in table 9-1.
3. By using oscilloscope, observe on the output signal waveform of square

wave output port (TP2). Adjust variable resistor VR1 so that the amplitude
of TP2 is maximum without distortion, then record the output signal

sinusoidal wave output port (TP3). Adjust variable resistor VR2 so that
the amplitude of TP3 is maximum without distortion, then record the
output signal waveform and voltage in table 9-1.
9－19
Experiment 2: TDM multiplexer
1. Refer to the time generator and analog switch in figure 9-11 and figure
9-12 or refer to figure ACS9-1 of ACT-17300-05 module.
2. Turn the variable resistor “Clock Adj.” left to the end, at this moment, the
counter of the clock is slow. By using the CH1 of the oscilloscope,
observe on the output signal waveform of triangle wave output port (TP4).
Then by using CH2 of the oscilloscope, observe on the output signal
waveform of the TDM output port (TDM O/P). Finally record the output
signal waveforms and voltages in table 9-2.
3. By using the CH1 of the oscilloscope, observe on the output signal

waveform of square wave output port (TP5). Then by using CH2 of the
oscilloscope, observe on the output signal waveform of the TDM output
port (TDM O/P). Finally record the output signal waveforms and voltages
in table 9-2.
4. By using the CH1 of the oscilloscope, observe on the output signal

waveform of sinusoidal wave output port (TP6). Then by using CH2 of
the oscilloscope, observe on the output signal waveform of the TDM
output port (TDM O/P). Finally record the output signal waveforms and
voltages in table 9-2.
9－20

Table 9-1 Measured results of waveform generator.
TP1
TP2
TP3
9－21
Table 9-2 Measured results of TDM multiplexer.
TP4
and
TDM O/P
TP5
and
TDM O/P
TP6
and
TDM O/P
9－22
1. Describe how the multiple signals transmit on the same transmission

channel.
2. Explain the method of producing the sinusoidal waveform.
3. Explain the method of producing the square waveform.
4. Explain the method of producing the triangle waveform.
9－23
9－24
Chapter 10
TDM Demultiplexer
1. To understand the operation theory of TDM demultiplexer.
2. To design and implement the TDM demultiplexer.
3. To measure and adjust the TDM demultiplexer.
In chapter 9, we utilized the theory of sampling and the segment of
time to divide the time of the transmission channel into several time slots.
There is a small gap between each time slots, which is known as guard time
and it is used to prevent the interference between the symbol and jitter of the
demultiplexer. Therefore, we can utilize the pulse at a certain period to
process different numbers of channels. On the other hand, according to the
synchronous signal at the transmitter, the receiver can also separate the
signals of different channels accurately. The concept of TDM can be applied
in data communication system, which is known as packet switching.
Therefore, for every time slot in packet switching, the transmitted data is not
a symbol but is an independent packet.
10－2
Chapter 10 TDM Demultiplexer
Figure 10-1 is the example of a simple TDM system. The four
channels use switch to change to different channels and the switch
represents the synchronous signal as shown in the time sequence in figure
10-2. When S1 and S2 rotated, the signal at the transmission path can be
transmitted repeatedly and the receiver can also utilize the synchronous
signal to separate the signal. Practically, the switch is comprised by
transistor, FET or IC. For example, in TDM multiplexer, the switch is
implemented by using the analog switch CD 4066.

S1 S1
S2 S2
S3 S3
S4 S4
TDM Multiplexer TDM Demultiplexer
Figure 10-1 TDM system diagram.
S1 S1
S2 S2
S3 S3
S4 S4
TDM Multiplexer TDM Demultiplexer
S1 S2 S3 S4 S1 S2 S3 S4
Synchronous Time Pulse
Figure 10-2 Transmission diagram of TDM system.
10－3
10-1 The Implementation of TDM Demultiplexer
In chapter 9, we utilize the timer (NE 555) and counter (CD 4017) to
generate the sampling signal and then by using the analog switch (CD 4066)
to complete the TDM multiplexer. When the counter counts to a certain
channel, that channel will be ON, therefore, the signal at the input port will
occur at the output port. Similarly, for the TDM demultiplexer, we also
utilize the timer (NE 555) and the counter (CD 4017) to implement the
sampling signal generator as shown in figure 10-2. The operation time of
NE 555 is
T  0.7(100k * 2 *10K *100nF) (10-1)
The output of CD 4017 is shown in figure 10-3. When the counter
counts to Q3, the CD 4017 will reset and start to count from Q0. Thus, this
circuit is just similar to the three signals in the TDM multiplexer. Therefore,
we just need to obtain the synchronous signals, then we can recover the
original signal.
Figure 10-4 is the circuit diagram of TDM demultiplexer. When TDM
signal inputs by matching with the synchronous signal generator, then we
can obtain the input sequences, which are the triangle, square and sinusoidal
waveforms.
10－4
R1
100 k 16
4 8
7 3 t1
2 t2
R2
+
10 k 555 3 13
Vcc
Timer 4017 4 t3
2 Counter
6
15 7
Vc C1 1 5 8
100 nF
C2
10 nF
Figure 10-3 Synchronous signal generator.
-
uA741
+ Triangle
Wave
t1
-
- uA741
TDM uA741 + Square
Signal +
Input Wave
t2
-
uA741
+ Sinusoidal
Wave
t3
Figure 10-4 Circuit diagram of TDM demultiplexer.
10－5
Experiment 1: TDM Demultiplexer
1. Refer to the circuits in figure 10-3 and figure 10-4 or refer to figure
ACS10-1 of ACT-17300-05 module.
2. Connect the output port (TDM O/P) of TDM multiplexer in figure

ACS9-1 to the input port (TDM I/P) of TDM demultiplexer in figure
ACS10-1.
3. By using oscilloscope, observe on the output signal waveform of the

amplifier (TP1) of TDM demultiplexer. Then record the output signal
4. Connect the triangle wave output port (TP4) of the TDM multiplexer to
the triangle wave input port (TP2) of the TDM demultiplexer. By using
CH1 of the oscilloscope, observe on the output signal waveforms of
triangle wave input port (TP2). Then by using CH2 of the oscilloscope,
observe on the output signal waveforms of triangle wave output port
(O/P1) of the TDM demultiplexer. Finally record the output signal
waveforms and voltage in table 10-2.
observe on the output signal waveforms of square wave output port
10－6

observe on the output signal waveforms of sinusoidal wave output port
7. Connect the square wave output port (TP5) of the TDM multiplexer to
the square wave input port (TP3) of the TDM demultiplexer. By using
square wave input port (TP3). Then by using CH2 of the oscilloscope,
observe on the output signal waveforms of triangle wave output port
observe on the output signal waveforms of square wave output port
10－7
observe on the output signal waveforms of sinusoidal wave output port
10. Connect the sinusoidal wave output port (TP6) of the TDM multiplexer
to the sinusoidal wave input port (TP4) of the TDM demultiplexer. By
using CH1 of the oscilloscope, observe on the output signal waveforms
of sinusoidal wave input port (TP4). Then by using CH2 of the
oscilloscope, observe on the output signal waveforms of triangle wave
output port (O/P1) of the TDM demultiplexer. Finally record the output
signal waveforms and voltage in table 10-8.
oscilloscope, observe on the output signal waveforms of square wave
oscilloscope, observe on the output signal waveforms of sinusoidal wave
10－8

Table 10-1 Measured results of the input of TDM demultiplexer.
Table 10-2 Measured results of the output signals of TDM demultiplexer.
TP2 and O/P1
10－9
TP2 and O/P2
TP2 and O/P3
10－10
TP3 and O/P1
TP3 and O/P2
10－11
TP3 and O/P3
TP4 and O/P1
10－12
TP4 and O/P2
TP4 and O/P3
10－13
1. Describe how the TDM demultiplexer separates the triangle wave,

square wave and sinusoidal wave.
2. Explain the functions of NE555 in the synchronous signal generator.

And also calculate the time in equation (10-1).
3. Explain the functions of CD4066 in figure 10-4.
10－14
Chapter 11
FDM Multiplexer
1. To understand the operation theory of frequency-division

multiplexing (FDM).
2. To design and implement the FDM multiplexer.
3. To measure and adjust the FDM multiplexer.
We have discussed the modulation system, which transmits multiple
signals over the same transmission channel, however, if the transmission
channel only consists of one modulated signal, then the usage of channel is
very low and the efficiency is also not good. Therefore, in order to comfort
with the economic benefit, the channel must be able to transmit multiple
signals, such as in the telephone system, the frequency range of the sound is
300 Hz to 3 kHz. In order to transmit this kind of signal via a single channel,
we must divide the signal into several slots to prevent the interference, then
we can obtain the original signal at the receiver. Generally, there are two
types of signal division, which are frequency division multiplexing (FDM)
and time division multiplexing (TDM).
11－2
Chapter 11 FDM Multiplexer
Audio Balanced
Signal 1 Modulator
Carrier
Signal
Audio Balanced
Linearity Adder
Signal 2 Modulator
FDM
O/P
Carrier
Signal
Audio Balanced
Signal 3 Modulator
Carrier
Signal
Figure 11-1 Block diagram of FDM multiplexer.
Figure 11-1 is the system block diagram of FDM. Like TDM, FDM is
used to transmit multiple signals over the same communications channel
simultaneously. However, unlike TDM, FDM does not use pulse modulation.
In figure 11-1, assume that all the input audio signals are low-pass pattern
and after each input signal, there will be a low-pass filter. The objective is to
remove all the unwanted signals except the audio signals. Then the audio
signals will be sent into the modulator so that the frequency range of the
11－3
signals will shift to different region. The conversion of the frequency is
controlled by the carrier signal, therefore, we utilize the simplest technique,
which is the AM modulation to implement the modulator. Then the
modulated signals will pass through the bandpass filter, which can limit the
signal bandwidth to prevent the interference between each signal. Finally, all
the signals will be added by the linearity adder. As compare to TDM, we
utilize sampling to implement the TDM system and AM modulation to
implement the FDM system.
11-1 Implementation of Audio Signal Generator
Figure 11-2 is the circuit diagram of adjustable audio signal generator.
We use ICL8038 to design the audio generator, which can produce sine
wave, triangle wave and square wave. The range of the output frequency
and output amplitude are 1 Hz to 200 kHz and 0 V to 2 V, respectively. In
this circuit, we only use sine wave with 2 V output amplitude and 300 Hz to
1.5 kHz output frequency. In figure 11-2, the VR1 is to adjust the output
frequency, which can change the time of charge and discharge. The faster
the time of charge and discharge (the smaller the value of resistor), the
higher the output frequency; nevertheless, the slower the time of charge and
discharge (the larger the value of resistor), the lower the output frequency.
VR2 is used to adjust the output amplitude where the output amplitude can
be varied from 0 V to 2 V.
11－4
C 1 10 nF
R3
100 k
+12 V
Frequency
VR 2 Adjustment
14 13 12 11 10 9 8
10 k Audio Signal
Vo VR 1
Generator (ICL8038) 10 k
Output 1 2 3 4 5 6 7
Amplitude R4
Adjustment 1k
R2 R1
Q1
22 k 22 k
3904
+12 V
Figure 11-2 Audio signal generator.
11-2 Implementation of Carrier Signal Generator
In this chapter, we utilize the Wien Bridge oscillator to implement the
carrier signal generator. Figure 11-3 is the circuit diagram of Wien Bridge
oscillator. We can see that a closed-loop non-inverting amplifier is
comprised by R1 , R 3 and OP amplifier. Moreover, R 2 , R 4 , C1 and
C 2 comprise a feedback network that the phase differences between Vo
and Vf is 0o . From figure 11-3, we know that
R3
A ( j)  1  (11-1)
R1
11－5
1
R2
jC1
1
R2 
Vf jC1
( j)  
Vo 1
R2
1 jC1
R4  
jC 2 R  1
2
jC1
R2 1 R2 R4 R2
(   )
C 2 2 C1 C 2 C 2

1 1 R R R
(R 2 R 4  2 )2  2 ( 2  4  2 )
 C1C 2  C1 C 2 C 2
1 R2 1
(R 2R 4  2 )
 C2  C1C 2
j (11-2)
1 1 R R R
(R 2R 4  2 )2  2 ( 2  4  2 )
 C1C 2  C1 C2 C 2
R3
Vf R3 Vo
A 1
R1 +12V R1
Vo
A
-12V
Output
C2 R4
Vf
C2 R4 R2 C1
R2 C1 ( j)
Feedback
Network
(a) Oscillator circuit diagram. (b) Oscillator feedback structure.
Figure 11-3 Circuit diagram of Wien Bridge oscillator.
11－6
From Barkhausen principle, we know that A( jo )( jo ) should be a
real number and the phase must be 0o during oscillation. From equation
(11-1), A( jo ) is a real number, and from equation (11-2), the imaginary
part of ( jo ) is at the second term. Obviously, we can assume this term
as zero, that means
1 R2 1
(R 2 R 4  2 )
o C 2 o C1C 2
0 (11-3)
1 1 R2 R4 R2
(R 2 R 4  2 )  2(
2
  )
o C1C 2 o C1 C 2 C 2
1
o2  (11-4)
R 2 R 4 C1C 2
If R 2  R 4  R and C1  C 2  C , then, equation (11-3), i.e. the oscillation
frequency of Wien Bridge can be rewritten as
1
o  (11-5a)
RC
1
fo  (11-5b)
2RC
Then we consider the oscillation condition of Wien Bridge oscillator
and we get
A ( jo )( jo )  R e {A ( jo )( jo )}  1 (11-6a)
11－7
R2 1 R2 R4 R2
(   )
C 2 o2 C1 C 2 C 2
A 1 (11-6b)
1 1 R R R
(R 2 R 4  2 )2  2 ( 2  4  2 )
o C1C 2 o C1 C 2 C 2
Then substituting equation (11-5a), R 2  R 4  R and C1  C2  C
into equation (11-5b). At the same time, when oscillation occurs, the loop
gain should be at least 1. Therefore, the oscillation conditions of Wien
Bridge oscillator are as follow
R3
A  (1  )3 (11-7a)
R1
R3
2 (11-7b)
R1
From the above-mention, in order to let the Wien Bridge oscillator to
oscillate in a proper way, the following conditions must be achieved
1
1. f o 
2RC
R3
2. A  (1  )3
R1
Unfortunately, we can only know that the amplifier gain of A should

be more than 3 from above-mentioned analysis about the Wien Bridge
oscillator, but there is no information about the value of the voltage V o .
Practically, when the gain achieves the oscillation condition, the circuit will
output a sinusoidal waveform and the oscillation frequency will maintain at
11－8
f o  1 2RC . In addition, the output voltage may become larger and larger,
and then generate a non-linear distortion in the output waveform of
oscillators.
R3
D1
R5
VR1 D2
+12V
A
R1 -12V O/P
C2 R4
R2 C1
Figure 11-4 Circuit diagram of diodes amplitude-limited Wien Bridge oscillator.
In order to prevent the non-linear distortion, which we have mentioned
before, we can utilize the structure of diodes amplitude-limited Wien Bridge
oscillator as shown in figure 11-4. In figure 11-4, since R 3  VR1  R 5 ,
therefore, we can adjust the magnitude of VR1 to satisfy the condition for
oscillation and let the gain of the amplifier larger than 3, i.e., a sinusoidal
wave frequency ( f o ) is produced. Nevertheless, when the amplitude of Vo
is very large, the diodes D1 and D2 will conduct ( D 2 conducts when the
positive half cycles is very large, D1 conducts when the negative half
11－9
cycles is very small). Since D1 or D 2 conducts, this situation is as well
as shunt the forward-conducted resistor of diode and the result is the same
as to short R 5 . Then, R 3 will become smaller and A will decrease,
therefore, this situation will limit the increment of Vo to prevent the
non-linear distortion.
11-3 Implementation of DSB-SC Modulator
DSB-SC modulation is a kind of AM modulation, therefore, we can
utilize the structure of AM modulator to implement the DSB-SC modulator.
Figure 11-5 is the frequency spectrum between the AM signal and DSB-SC
signal. Figure 11-5(a) is the frequency spectrum of AM signal. We can see
that the frequency spectrum consists of three kinds of signals, which are
f c  f m , f c and f c  f m . The output voltage of fc is higher than the other
two signals, therefore, the carrier signal does not contain any signal, and the
power is consumed in carrier during transmission of amplitude modulation
signal. Figure 11-5(b) is the frequency spectrum of DSB-SC signal. We can
see that the frequency spectrum consists of two kinds of signals, which are
f c  f m and f c  f m . These two kinds of signals consists of the transmission
signal, therefore, by using this type of modulation, the power will not
consume in the carrier. Besides, as a result of the audio signal is hidden in
the double sideband, so, the stronger the double sideband signal, the
transmission efficiency will be better.
11－10
Figure 11-6 is the block diagram of DSB-SC modulator. We utilize
balanced modulator MC1496 to design the DSB-SC modulated signal.
Figure 11-7 is the internal circuit diagram of MC1496, where D1, R1, R2, R3,
Q7 and Q8 comprise an electric current source, which can supply DC bias
current for Q5 and Q6. Q5 and Q6 comprise a differential combination to
drive the dual differential amplifiers constructed by Q1, Q2, Q3 and Q4. Pin 1
and 4 are the inputs of audio signal; Pin 8 and 10 are the inputs of carrier
signal. The resistor between pins 2 and 3 controls the gain of the balanced
modulator; the resistor of pin 5 determines the magnitude of bias current for
amplifier.
Figure 11-8 is the circuit diagram of AM modulator. We can see that
the carrier signal and audio signal belong to single ended input. The carrier
signal is inputted from pin 10 and the audio signal is inputted from pin 1.
Therefore R8 determine the gain of the whole circuit and R9 determine the
magnitude of bias current. If we adjust the variable resistor VR1 or change
the input amplitude of audio signal, then we can control the percentage
modulation of amplitude modulation, which means we can adjust the output
become the DSB-SC modulation. By adjusting variable resistor VR2, we can
control the magnitude of the output amplitude, which is also the gain.
11－11
x AM ( f )
A DC A c
0 .5 mA DC A c 0 . 5 mA DC A c
f (Hz)
(a) Frequency spectrum of AM.
x AM (f )
0.5mADCA c 0.5mA DC A c
f (Hz)
(b) Frequency spectrum of DSB-SC.
Figure 11-5 Different frequency spectrums of AM modulation.
Audio Balanced DSB-SC Modulation

Signal Modulator Output
Carrier Signal
Figure 11-6 Block diagram of DSB-SC modulation.
11－12
(12)

Output

Q1 Q2 Q3 Q4 (6)
Carrier (10)
Signal 
Input 
(8) Q5 Q6
(4)
Audio 
Signal
Input (2)
 Gain
(1) Q7 Adjustment
Terminal
Bias Q8 (3)
Adjustment
(5) D1
Terminal
R2 R3
R1 500
(14) 500
500
V
Figure 11-7 The internal circuit diagram of MC1496.
R7
1k 1k
+12
V
R3 C3 R8 1 k
0.1uF
R10 R11
3.9 k 3.9 k
C1 R4 2 3 DSB-SC
Carrier 51 8
0.1uF 6 Signal
Signal C4
10 Output
Input 0.1uF
MC1496
Audio C2
1 12
Signal
0.1uF 4 1
Input 5
R1 R2 R5 R6 4
10 k 10 k 300 1k
R9
50 k 6.8 k
VR1
5V
Figure 11-8 Circuit diagram of DSB-SC modulation by utilizing MC1496.
11－13
11-4 Linearity Adder
The circuit diagram of linearity adder is shown in figure 11-9. The
main objective of linearity adder is to add the three DSB-SC modulated
signals to become the FDM signal.
R1 R4
100 k 100 k
DSB - SC1
R2 +12 V
DSB - SC2 FDM
100 k uA741
O/P
DSB - SC3
R3 -12 V
100 k
Figure 11-9 Circuit diagram of linearity adder.
11－14

參實驗項目
Experiment 1: FDM signal generator
Experiment 1-1: Audio signal generator
1. Refer to the audio signal generator in figure 11-2 or refer to figure

2. By using oscilloscope, observe on the output signal waveform of audio

signal generator 1 (TP1). Adjust the variable resistors “Audio Frequency
Adjust 1” and “Audio Gain Adjust 1”, so that the output frequency is
500 Hz and the amplitude is 600 mV. Finally, record the measured

800 Hz and the amplitude is 600 mV. Finally, record the measured

Adjust 3” and “Audio Gain Adjust 3”, so that the output frequency is 1.2
kHz and the amplitude is 600 mV. Finally, record the measured results in
table 11-1.
11－15
Experiment 1-2: Carrier signal generator
1. Refer to the carrier signal generator in figure 11-4 or refer to figure

2. By using oscilloscope, observe on the output signal waveform of carrier

signal generator 1 (TP2). Adjust the variable resistor “Carrier Gain
Adjust 1”, so that the output amplitude is 600 mV. Finally, record the


11－16
Experiment 2: DSB-SC modulated signal generator
1. Refer to the DSB-SC modulated signal generator in figure 11-8 or refer

to figure ACS11-1 of ACT-17300-06 module.

balanced modulator 1 (TP5). Adjust the variable resistor “Modulator
Adjust 1”, so that the output signal is DSB-SC modulated signal. Finally,


11－17
Experiment 3: FDM multiplexer
1. Refer to the audio signal generator in figure 11-2, carrier signal

generator in figure 11-4, DSB-SC modulated signal generator in figure
11-8 and the linearity adder circuit in figure 11-9 or refer to figure
2. By using oscilloscope, observe on the output signal waveform of FDM

output port (FDM O/P), then record the measured results in table 11-4.
11－18

Table 11-1 Measured results of audio signal.
TP1
TP3
11－19
Table 11-1 Measured results of audio signal. (Continued)
TP7
Table 11-2 Measured results of carrier signal.
TP2
11－20
Table 11-2 Measured results of carrier signal. (Continued)
TP4
TP8
11－21
Table 11-3 Measured results of DSB-SC modulated signal.
TP5
TP6
11－22
Table 11-3 Measured results of DSB-SC modulated signal. (Continued)
TP9
Table 11-4 Measured results of FDM modulated signal.
FDM O/P
11－23
1. Explain the meaning of FDM multiplexing. And also explain the

advantages of FDM multiplexing.
2. Explain the method of producing the audio signal.
3. Explain the method of producing the carrier signal.
4. Explain the reasons of using DSB-SC modulation to implement the

FDM multiplexer.
11－24
Chapter 12
FDM Demultiplexer
1. To understand the operation theory of frequency-division

demultiplexing.
2. To design and implement the FDM demultiplexer.
3. To measure and adjust the FDM demultiplexer.
In previous chapter, we utilize the DSB-SC modulation to modulate
several audio signal and also use different carrier signals to modulate the
signals at different frequency ranges, then finally, we use the linearity adder
to add all the modulated signals to become the FDM signal.
There are two ways to implement the FDM demultiplexer. The first
way is shown in figure 12-1(a). Let the FDM signals pass through a
bandpass filter and a low-pass filter. The objective of bandpass filter is to
remove the signal, which its frequency is larger and lower than fo, then only
left a single DSB-SC modulated signal. After that this signal will pass
through a low-pass filter, then we can recover the modulated signal and
obtain the original audio signal. The second way to implement the FDM
12－2
Chapter 12 FDM Demultiplexer
demultiplexer is shown in figure 12-1(b). Figure 12-1(b) is the block
diagram of synchronous product detector. After the signal passed through
the synchronous product detector, we will add a low-pass filter to remove all
the unwanted signal and recover the original audio signal. In this chapter,
we will discuss the operation theory and the design of synchronous product
detector.
BPF LPF Audio 1
BPF LPF Audio 2

FDM
I/P
BPF LPF Audio 3
Figure 12-1(a) Block diagram of FDM demultiplexer.
FDM Audio
Multiplier
I/P Signal
Carrier Signal
Figure 12-1(b) Block diagram of synchronous product detector.
Figure 12-1 Block diagram of FDM demultiplexer.
12－3
12-1 The Implementation of Synchronous Product

Detector
Let xAM(t) be the modulated DSB-SC signal and xC(t) be the carrier
signal, then
x c ( t )  A c cos (2 f c t ) (12-2)
When these two signals input into two differential ports of balanced
modulator, then the balanced modulator output signal is as follow
x out (t )  kx c ( t )  x AM ( t )
k A DC A c2 k A DC A c2 (12-3)
  m cos (2f m t )
2 2
k A DC A c2
  1  m cos (2f m t)cos2 (2f c t)
2
Where k represents the gain of the balanced modulator, the first term is
the DC signal, second term is the audio signal and third term is the second
harmonic of amplitude modulated signal. If we can take out the second term
from xout (t), then we can obtain the demodulated DSB-SC signal or audio
signal.
12－4
Figure 12-2 is the circuit diagram of synchronous product detector.
The variable resistor VR1 controls the input magnitude of carrier signal;
variable resistor VR2 controls the input magnitude of amplitude modulated
signal; then the output signal of MC1496 is located at pin 12. C 7 , C 9
and R 9 comprise a low-pass filter which can remove the unwanted third
term of equation (12-3), i.e. second harmonic of amplitude modulated
signal. The DC signal, which is the first term of equation (12-3), can be
blocked by C10. Therefore the signal that we obtain at output port will be:
k A DC A c2
x out ( t )  m cos (2 f m t ) (12-4)
2
original amplitude modulated signal can be taken out via product detector.
R2 R4
1k 1k
+12 V
C1 R1 C4 R 51 k
100 nF 1k 100 nF C8
R7 R8 100 nF
C2 8 2 3 2k 2k
VR1 R3
10
Carrier 100 k 100 nF
1k 6 TP1
I/P MC1496
C3100 nF
FDM 1 Balanced +12V
I/P Modulator TP2 R9
12 + C10
1k Audio
C9 uA741
100 nF O/P
14
VR 2 10 nF
100 k +
4 5 C6 C7 -12V
2 u2F 100 nF
C5 R6 R11
100 nF R10
10 k
10 k +12 V 10 k
Figure 12-2 Circuit diagram of synchronous product detector.
12－5
12-2 The Implementation of Low-pass Filter
Figure 12-3 is the circuit diagram of second order active low-pass
filter. In figure 12-3, resistors, R1 , R 2 , R 3 , capacitor C1 and operational
amplifier U1 not only comprise a Miller integrator circuit, but also provide
the function of weighted summer. The objective is to multiply a weighted to
the input signal and output signal of operational amplifier, U 3 , respectively,
after that sum the input signal and output signal of U 3 . Resistor, R 4 ,
capacitor C 2 and operational amplifier U 2 comprise a Miller integrator
circuit. Resistors, R 5 , R 6 and operational amplifier U 3 comprise an unit
gain inverting amplifier. Since we utilize the network synthesize theory, this
circuit satisfies the conditions of Butterworth filter, i.e. there is no ripple
permitted in the passband and the frequency response is very flat.
R3
R2 15 k
15 k
C1 R 15 k
C2 6
Input R1
10 nF
(Vin ) R4 10 nF
7 k5 uA741 +12 V
R5
15 k uA741
U1 15 k uA741
U2
U3 -12 V Output
(Vout )
12－6

參實驗項目
Experiment 1: FDM Demultiplexer
1. To implement a FDM multiplexer as shown in figure 11-2 or refer to
figure ACS11-1 on ACT-17300-06 module to produce the modulated
FDM signal source.

500 Hz and the amplitude is 600 mV.

800 Hz and the amplitude is 600 mV.

1.2 kHz and the amplitude is 600 mV.
5. By using oscilloscope, observe on the output signal waveform of TP5,

TP6 and TP9. Then adjust variable resistors “Mod Adjust 1”, “Mod
Adjust 2” and “Mod Adjust 3” so that the output signal is the modulated
DSB-SC signal.
6. To implement a product detector as shown in figure 12-2 and a low-pass

filter as shown in figure 12-3 or refer to figure ACS12-1 on
12－7
7. Connect the modulated FDM signal (FDM O/P) in figure ACS11-1 to

the input terminal (FDM I/P) in figure ACS12-1. Connect the carrier
signal (TP2) in figure ACS11-1 to the input terminal 1 of the carrier
signal (Carrier I/P1) in figure ACS12-1. Connect the carrier signal (TP4)
in figure ACS11-1 to the input terminal 2 of the carrier signal (Carrier
I/P2) in figure ACS12-1. Connect the carrier signal (TP8) in figure
ACS11-1 to the input terminal 3 of the carrier signal (Carrier I/P3) in
figure ACS12-1.

audio signal 1 (Audio O/P1). Then adjust variable resistors “Carrier
Adjust 1” and “Gain Adjust 1”, so that the output amplitude is the
maximum without distortion. Finally, record the measured results in
table 12-1.

table 12-1.

table 12-1.
12－8

Table 12-1 Output signal waveforms of audio signal.
Audio O/P1
12－9
Table 12-1 Output signal waveforms of audio signal. (Continued)
Audio O/P2
12－10
Table 12-1 Output signal waveforms of audio signal. (Continued)
Audio O/P3
12－11
1. Describe the types of FDM demultiplexer. And also explain the type of
the FDM demultiplexer in this chapter.
2. Describe the demodulation mode in figure 12-2.
3. Describe the functions of low-pass filter in figure 12-3.
12－12
Chapter 13
Analog to Digital
Converter
1. To understand the operation theory of analog to digital

converter.
2. To understand the operation theory and characteristics of

ADC0804 and ADC0809.
3. To implement the analog to digital converter by using

ADC0804 and ADC0809.
In general, the continuous signal that we measure in voltage or current
status is called as analog signal. If via a device that can convert the analog
signal to digital signal, then we called this device as analog to digital
converter (ADC). ADC can reduce the effect of noise and by using the
technique of coding, ADC has the function of debugging. On the other hand,
digital signal can also be easily stored. Next we will discuss on the basic
theory of the analog to digital converter.
13－2
Chapter 13 Analog to Digital Converter
13-1 The Operation Theory of ADC
Figure 13-1 is the characteristic curve of an ideal 3-bit analog to
digital converter, and the analog input range is from 0 V to 5 V. We can
divide the input signal into 8 (23 = 8) ranges, at each range all the analog
values use the same binary code to represent, and this binary code is
corresponding with the mid-value. Therefore, during the processing of
converter, it consists of  1 / 2 least significant bit (LSB) quantization
uncertainty or quantization error, and also includes the previous converter
that has the analog error, then all of the errors comprise the error value of
ADC. One of the methods to reduce the quantization error is to increase the
number of bits of the converter. The more the numbers of bits, the more the
numbers of ranges and the data signal will be more detail. This is because
the  1 / 2 LSB becomes small, therefore, the quantization error will
reduce. Quantization value (Q) means when the digital output changes 1
LSB, the required input voltage value also changes, the expression is
FS
Q (13-1)
2 1
n
Where FS is the full scale, the value equals to [(2 n  1) / 2 n ] , 2 n is
defined as resolution, where n is the ADC digital output bit, so when the
larger the value of n, the higher the resolution. In general, the ADC technical
manual defines resolution in bits. For example, the resolution of ADC0804
is 8 bits.
13－3
The methods of conversion for analog to digital converter are various,
normally can be divided as A/D conversion methods are digital-ramp ADC,
successive approximation ADC, flash ADC and tracking ADC. In this
chapter, only the successive approximation ADC is discussed, therefore, we
will discuss on the operation theory of successive approximation ADC.
Digital Output
7/8 111
6/8 110
5/8 101
Ideal Steps
4/8 100
3/8 011 Normal

Quantization
Value
2/8 010
Q
1/8 001
0 000 Analog Input

0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 1
FS
Note: Full scale (FS) is the maximum value of the digital output correponding
to the mid-value of analog input, which is 7/8.
Figure 13-1 Ideal waveform of analog to digital converter.
Figure 13-2 is the block diagram of successive approximation ADC,
which is provided with 8-bit resolution. When we input the analog signal,
sample-and-hold, S&H circuit will capture the input signal Vin to avoid
13－4
any signal change during conversion period. At this moment, the control
logic will store all the bits and reset to" 0 ", follow by the most significant
bit, MSB D 7 is set to " 1 ". Thus, the output voltage of DAC is
Vref 1
V (D)  2 n 1  Q  2 n 1   Vref (13-2)
2n 2
+ Sample and Hold

Vin Circuit +
Comparator Control Logic clock
_
V(D)
DAC Register
Vref
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
Digital Output
Figure 13-2 Basic block diagram of successive approximation ADC.
This voltage is half of the reference voltage, Vref . If the input voltage
Vin is higher than V(D), then D 7 remains at " 1 ", otherwise alters to " 0 ".
Next, make second bit D6 as " 1 ", after passing through a DAC then obtain
an output voltage V(D), at this moment comparing the new V(D) and Vin ,
if Vin is higher than V(D), then D6 remains at " 1 " otherwise alters to " 0 ".
Similarly for the others until the comparison of D7 to D0 have been
completed, then we can obtain the complete D7 to D0 digital output.
13－5
13-2 ADC0804 Analog to Digital Converter
ADC0804 is a 20-pin DIP package with an 8-bit resolution single
channel IC. The analog input voltage range is from 0 V to 5 V with single 5
V power supply, 15 mW power consumption and 100 s conversion time.
As a result of this IC contains of 8-bit resolution, so it has 28  256
quantization steps, if the reference voltage is 5 V , each step will be
5 / 256  0.01953 V . 00000000 (00H) represents 0.00 V and 1111111 (FFH)
represents 4.9805 V. The unadjusted error of ADC0804 is  1 LSB, which
is 0.01953 V, which includes full-scale error, offset error and non-linearity
error.
Figure 13-3 shows the pins diagram of ADC0804. In figure 13-3, the D 0
to D7 of ADC0804 is the 8-bit output pins, when CS and RD are low, the
digital data will be sent to the output pins. If any pins of CS and RD are
high, then D0 to D7 are in floating condition.
WR is the write control signal, when CS and WR are Low,
ADC0804 will do the clear action, when WR backs to high, ADC will start
the conversion. CLK IN (Pin 4) is the clock input, the frequency range starts
from 100 kHz to 800 kHz. During the conversion period, INTR is at high
level and then after the conversion completed, INTR will alter to low. Pin 6
Vin () and pin 7 Vin () are differential analog signal inputs, ordinarily used
13－6
single input terminal and Vin () is connected to ground. ADC0804 has two
ground terminals, one is analog ground (A GND) and another one is digital
ground (D GND). Pin 9 ( Vref / 2 ) is 1/2 of the reference voltage, if pin 9 is
floating, then the 1/2 reference voltage equals to power supply voltage Vcc.
ADC0804 has a built-in Schmitt trigger as shown in figure 13-4. If we add a
resistor and capacitor at CLK R (pin 19) and CLK IN (pin 4), then we can
generate the ADC operating time, where the frequency is
1
f CLK  (Hz) (13-3)
1.1 RC
Therefore, we need not input an external clock signal to CLK IN
terminal. We can determine the clock signal by the external R and C via pin
4 and pin 19.
CS 1 20 Vcc
RD 2 19 CLK R
WR 3 18 D0 (LSB)
CLK IN 4 17 D1
INTR 5 16 D2
VIN (+) 6 15 D3
VIN ( ) 7 14 D4
A GND 8 13 D5
VREF /2 9 12 D6
D GND 10 11 D 7 (MSB)
Figure 13-3 Pins diagram of ADC0804.
13－7
Figure 13-5 is the circuit diagram of ADC0804 analog to digital
converter, the analog signal input range is controlled by VR2 and input
through the Vin ( ) terminal and at the same time, the Vin () is short
circuit. Vref / 2 is provided by R1, R2 and VR1. C1 and R3 is used to control
the clock of the circuit, CS and RD are short circuit, so that the IC is
enable, then let WR and INTR connect to SW1 in order to simulate the
control signal.
13-3 ADC0809 Analog to Digital Converter
ADC0809 is a 28-pin DIP package, which has 8-bit resolution and
8-channel multiplexer IC. It operates with 5 V single power supply, the
input analog voltage range is from 0 V to 5 V and the power consumption is
15 mW. The 8-channel multiplexer can directly access any of 8 single-ended
analog signals. With 8-bit resolution, the ADC0809 have 28 = 256
quantization steps. Therefore, for the 5 V voltage power supply condition,
each step is 5 V / 256 , so the quantization value (Q) is 0.01953 V. So
00000000 (00H) represents 0.00 V and 11111111 (FFH) represents
(255 / 256)  5  4.9805 V . The unadjusted error is  1 LSB, which is
same as 0.01953 V where it contains of full-scale error, offset error,
non-linearity error and multiplexer error. ADC0809 needs a group of clock
input signals to operate, the frequency range of the clock signal starts from
13－8
10 kHz to 1280 kHz. At 640 kHz clock frequency, the typical conversion
time is 100 s.
19
CLK R
4
CLK
CLK IN
ADC0804
Figure 13-4 Internal circuit diagram of ADC0804.
+5 V
R 3 10k C4
0.1 uF
C1 Vcc
1 20
150 pF 9-pin network resistors
CLK R
2 19
D0 150
3 18
D1 150
4 17
SW 1
D2 150
5 16
R1 D3 150
2k 6 15
C2 D4 150
7 14
VR1 0.1 uF 150
D5
500 8 13
VR 2 10k D6 150
9 12
R2 C3 D7 150
2k 10 11
0.1 uF
Figure 13-5 Circuit diagram of ADC0804 circuit.
13－9
Figure 13-6 is the pins diagram of ADC0809. In figure 13-6, the
ADC0809 pins 5, 4, 3, 2, 1, 28, 27 and 26 are the 8 input ports, which is IN7
to IN0. Pins 21, 20, 19, 18, 8, 15, 14 and 17 are the output ports, which are D7
to D0 and pin 10 is the clock input port. Pin 11 is the power supply Vcc input
port and pin 12 is the positive reference voltage Vref () input port. Normally,
pins 11 and 12 are connected together. Pin 13 is grounded and pin 16 is the
negative reference voltage Vref () input port that normally connects to
ground pin 13. The selections of channels are controlled by pins 25, 24 and 23
which are ADD A, ADD B and ADD C. If select pin 26 (IN0) as input port,
then connect 23, 24 and 25 to ground.
ADC0809 can be easily connected with microprocessor, where pin 6
(START), pin 7 (end of conversion, EOC), pin 9 (output enable, OE) and
pin 22 (address latch enable, ALE) are normally used to control the ADC
and the clock of data conversion of microprocessor. When ADC0809
conversion is finished, EOC can enable the central processing unit (CPU).
When CPU is ready to receive data, it will enable pin OE and read the data.
After that enables ALE and START, to let ADC0809 continue the next
conversion. If under the condition of using multi-channel inputs, pins 23
(ADD C), 24 (ADD B) and 25 (ADD A), ALE and START must be set
during the period of enable.
13－10
Figure 13-7 is the circuit diagram of ADC0809 analog to digital
converter, which EOC (pin 7) output signal is the START input signal, and
the ALE and CLK output signal are the clock signal. The input signal range
of analog input port IN0 is determined by VR1. The IN1 to IN7 input signal
ranges are determined by R1 to R7, which is a group of resistor networks.
The channel selection is controlled by SW1, SW2 and SW3. We use LED to
represent the digital output, therefore, LED “on” represents “1” and LED
“off” represents “0”.
IN3 1 28 IN2
IN4 2 27 IN1
IN5 3 26 IN0
IN6 4 25 ADD A
IN7 5 24 ADD B
START 6 23 ADD C
EOC 7 22 ALE
D3 8 21 D7
O/P ENABLE 9 20 D6
CLOCK 10 19 D5
Vcc 11 18 D4
Vref (+) 12 17 D0
GND 13 16 Vref ( )
D1 14 15 D2
Figure 13-6 Pins diagram of ADC0809.
13－11
+5 V
VR1 5k 9-pin network
resistor
11
C1 26 150
17
IN0 Vcc D0
0.1 F 27 150
R1 IN1 D1 14
1k 150
28
IN2 D2 15
R2 1 8
150
1k IN3 D3
2
150
IN4 D4 18
R3 150
1k 3 19
IN5 D5
4 20 150
R4 IN6 D6
1k 5 150
21
IN7 D7
R5 12 23  5V
1k Vref ( ) ADD C
SW3
16 24  5V
Vref () ADD B
R6 SW2
9 25  5V
1k OE ADD A
SW1
10 13
R7 CLK GND
1k 22 6
ALE START
7
EOC
Clock Input
Figure 13-7 Circuit diagram of ADC0809.
13－12
Experiment 1: ADC0804 analog to digital converter

ACT-17300-07 module. Let J1 be open circuit.
2. Use the digital voltage meter to measure the reference voltage input
port (TP1). Adjust VR1 so that the voltage of TP1 is 2.5 V. At this
moment, ADC0804 analog voltage input range is 0 V to 5 V.
3. By using oscilloscope, observe on the TP2 and record the measured

4. Adjust VR2 so that the input voltage of the analog signal input port
(TP3) is 0 V.
5. Let J1 be short circuit, i.e. to maintain the output digital signal. Observe
on the changes of LED, LED “on” represents “1”, LED “off” represents
“0”, finally record the measured results in table 13-1.
6. Let J1 be open circuit, i.e. the digital output signal will be varied from
the analog input signal.
7. Adjust VR2 so that the input voltage of TP3 is similar to the values in
table 13-1, then repeat step 5 and record the measured results in table
13-1..
13－13
Experiment 2: ADC0809 analog to digital converter

2. At the CLK input port (CLK I/P), input 120 kHz frequency and a TTL
signal with 5 V offset.
3. Let SW3, SW2 and SW1 switch to GND (push down the slide switch), at
this moment, the multiplexer selects to channel 0 and the analog signal
is inputted from the IN0 input.
4. Use the digital voltage meter to measure the TP1 of channel 0. Adjust
VR1 so that the input voltage of TP1 is similar to the values in table
13-2. Observe on the changes of LED, LED “on” represents “1”, LED
“off” represents “0”, then record the measured results in table 13-2.
5. Adjust VR1 so that the input voltage of TP1 is similar to the values in
table 13-2. Repeat step 4 and record the measured results in table 13-2.
6. Use the digital voltage meter to measure the TP2 of channel 1 until TP7
of channel 6, then record the measured results in table 13-3.
7. Refer to table 13-3, by using SW3, SW2 and SW1, select the different
input terminals as the analog input. Then observe on the changes of
LED and record the measured results in table 13-3.
13－14
Table 13-1 Measured results of ADC0804.
TP2
Output Signal
Waveforms
Digital Output
Analog Input
Ideal Values Experiment Values
Voltages (V)
Binary Digits Binary Digits
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
13－15
Table 13-2 Measured results of ADC0809 single channel input.
Digital Output
Analog Input
Ideal Values Experiment Values
Voltages ( V )
Binary Digits Binary Digits
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
13－16
Table 13-3 Measured results of ADC0809 multi-channel input.
Analog Input Digital Output

(Ideal Value) (Experiment Value)
SW3 SW2 SW1
Input
Voltage (V) Binary Digits
Terminal
GND GND + 5 V TP2
GND + 5 V GND TP3
GND + 5 V + 5 V TP4
+ 5 V GND GND TP5
+ 5 V GND + 5 V TP6
+ 5 V + 5V GND TP7
13－17
13-5: Problem Discussion
1. In figure 13-5, what are the purposes of R3 and C1?
2. In figure 13-7, what are purposes of SW1, SW2 and SW3?
3. In experiment 1, what are the unadjustable errors of ADC0804？
4. In experiment 2, what are the unadjustable errors of ADC0809？
13－18
Chapter 14
Digital to Analog
Converter
1. To understand the basic theory of digital to analog converter.
2. To understand the operation theory and characteristics of

DAC0800.
3. To generate the unipolar and bipolar analog voltage by using

DAC0800.
Digital to analog converter (DAC) is a device, which converts the
digital signal to analog signal. We normally store a digital signal in a media
or transmission line. Then a DAC changes the digital signal to an analog
signal in order to control data display or further analog signal processing.
For example, from a digital communication system, when a receiver
receives the digital modulation signal, then after via a demodulator and a
decoder, we can obtain the digital signal, and follow by using DAC to
convert this digital signal to the analog signal. Next we will discuss the
basic operation theory of DAC.
14－2
Chapter 14 Digital to Analog Converter
14-1 The Basic Theory of Digital to Analog Converter
Basically, DAC is a digital code that represents digital value converted
to analog voltage or current. Figure 14-1(a) is a general 4-bit DAC binary
codes, the digital input terminal D3, D2, D1 and D0 are manipulated by the
register in a digital system. The 4-bit code represents 24 = 16 groups of 2
binary value, as shown in figure 14-1(b). For every binary code input, DAC
will output a voltage (Vout), which is double or other order of the binary
value. According to this, analog output voltage Vout and the digital input
binary values are the equivalent. If the DAC output is current, Iout, the
theory is similarly.
Assume that the input is 10112, then after passed through the DAC, the
value is 1110. The calculation is as follow
X = 123 + 022 + 121 + 120 = 8 + 2 + 1 = 1110 (14-1)
Figure 14-2 is the basic block diagram of DAC. The reference voltage
(Vref) is used to provide the reference voltage during conversion. Then due
to the magnitude of the input binary code, the digital control switch will
output different binary codes to the resistors network. Normally, the DAC
analog output is represented by current, if we want to obtain the voltage
output, we need to connect an operational amplifier, which can convert the
current to voltage level.
14－3
D3
Digital D2 Analog Output
Inputs D1 DDAC
A DAC
C V out or I out
D0
(a)
D3 D2 D1 D0 Vout D3 D2 D1 D0 Vout
0 0 0 0 0 1 0 0 0 8
0 0 0 1 1 1 0 0 1 9
0 0 1 0 2 1 0 1 0 10
0 0 1 1 3 1 0 1 1 11
0 1 0 0 4 1 1 0 0 12
0 1 0 1 5 1 1 0 1 13
0 1 1 0 6 1 1 1 0 14
0 1 1 1 7 1 1 1 1 15
(b)
Figure 14-1 (a) 4-bit DAC binary codes; (b) Truth table.
Reference
Voltage
Vref
RF
MSB
.
Digital . Digital . Resistors Analog
Inputs . Control . OP
LSB Switch . Network I Voltage Output
out
Analog
Current Output
Figure 14-2 Basic block diagram of DAC.
The resistors network is the main structure of DAC circuit, the most
common circuits are the binary-weighted resistor converter, as shown in
figure 14-3(a) and R-2R ladder resistors network, as shown in figure 14-3(b).
14－4
But the disadvantage of the binary-weighted resistor converter is the resistor
value range is too large. Due to the high accuracy demand, this wide range
resistor value is difficult to implement, especially for the implementation of
integrated circuit (IC), which is a big problem. But for the R-2R ladder
resistors network, it just needs two resistor values, which are R and 2R
resistors. The resistor values are simple and just twice of the relation,
therefore, it is easy to implement in integration circuit (IC). This chapter
uses the digital to analog converter DAC0800 resistors network, which is
the R-2R ladder resistors network, therefore, we will discuss the theory of
R-2R ladder resistors network in next section.
RF
+12V
+5 V 1
D3
- VO
R uA741
0
+5 V 1
+
D2
12V
2R
0
+5 V 1
D1
4R
0
V0  VRF ( D  2 D1 4  D 2  8  D 3 )
8R 0
+5 V 1
D0
8R
0
(a) Binary-weighted resistor converter.
14－5
R9
1k R 11
1k
+12V
R1
+5 V 1
D3 2k TP1 R 10
- 1k
0
uA741 - Output
R2 TP5
+5 V 1 R3 1k
+ uA741
Vout
D2 2k +
TP2
12V
0 R4
+5 V 1 R5 1k
D1 2k
TP3
0 R6
R7 1k
+5 V 1
D0 2k
TP4
0 R8
2k
(b) R-2R ladder resistors network.
Figure 14-3 Circuit diagram of DAC with 4-bit resistor network.
Figure 14-3(b) is the circuit diagram of DAC with 4-bit R-2R ladder
resistors network. By using the theory of overlapping, then in figure 14-3(b),
first we consider D3 and let the rest of the diodes connect to ground. Also, by
using the concept of virtual ground, then we know that the current flows into
the negative terminal of the amplifier is 5 V 2 R , because we need not
calculate D2. As for the consideration of D1, as shown in figure 14-4, by using
the concept of virtual ground, we can obtain the current flows into the negative
terminal of the amplifier is 5 V 8 R . Similarly for D0, the current flows into
the negative terminal of the amplifier is 5 V 16 R .
14－6
R T  R  2 R // R
R R A R Amplifier
R 2R 2R 2R
2R//2R R=
Virtual V/2R 5R/3
2R//2R
Ground
(Can be
+5 V Neglected)
(a) R-2R network circuit. (b) Simplified R-2Rnetwork circuit.
Figure 14-4 Circuit diagram of 4-bit R-2R ladder resistors network.
Assume that D1 is 1 and the rest are 0, as shown in figure 14-4(a).
Then simplify the circuit as shown in figure 14-4 (b), we can obtain the
current flow through resistor RT as
5V R 15 V
I RT   
2R 5 16R
R
3R
and
2R 15V 2R 5 V
I IN (  )  I RT     (14-2)
R  2R 16R 3R 8R
By adding all the currents flow through the negative terminal of the
amplifier, then we can obtain Iout as
I OUT  I D3  I D2  I D1  I D0
1 5V 0 V 5V 5V
     
R 2 4 8 16 

5V
8  2  1  5 11 V (14-3 )
16R 16R
14－7
By using Ohm’s Law, we can obtain the output voltage Vout as
Vout  I out  R
5  11 55
 R  V
16R 16
Where D3, D2, D1 and D0 represent 1 or 0, respectively. If the switch
locates at +5 V, it represents the input is 1, on the other hand, it represents
the input is 0. Therefore, we just need to control D3, D2, D1 and D0
appropriately, then we can obtain the required output current Iout.
14-2 Input Weight
Input weight illustrates that from the DAC digital input, when only
one of the bits is 1 and the other bits are 0, the DAC output signal range is
called input weight. From Figure 14-1(a), if every time we let one of the bits
of D3, D2, D1 and D0 as high level, the other bits is zero level, then the power
of lowest bit D0 is 1 V, D1 is 2 V, D2 is 4 V, D3 is 8 V. For every bit, the input
weight starts from the lowest bit and then increases by following the weight.
So we can say that Vout is the sum of weight of the digital input. For
example, to find the Vout of digital input 0111, we can sum D2, D1 and D0
bits weight and the total value is 4  2  1  7 V .
14－8
14-3 Resolution and Step Size
The resolution of DAC illustrates that when the digital input terminal
changes a unit, it will produce a small change at the analog output terminal,
which is normally the LSB levels. Refer to figure 14-1(b), when the digital
input value changes a unit, Vout will change at least 1 V, so the resolution is
1 V.
Resolution is also called step size because Vout will change, when the
digital input step varies from one to another. Figure 14-5 shows a 4-bit
binary counter as DAC digital input signal, the counter has a clock input, so
it can output 16 types of statuses continuously in cycle. The output
waveform of DAC is every step with 1V change. When the counter
generates 1111, the DAC output is the maximum value, which is 15 V. We
call this situation as full-scale output. When the counter generates 0000, the
DAC output is 0 V. Resolution or step size is to indicate the difference
between two steps. For example, if the step size is 1 V then the difference
between the steps is 1 V.
Figure 14-5 shows 16 types digital inputs corresponding to the 16
levels of output steps waveform. From 0 V to 15 V (full-scale), there are
only 15 steps size. Generally, N bits of DAC will produce 2N different levels
and 2N-1 steps size.
14－9
D3
四位元 D2 DAC
4-bit
Resolution Vout
Counter D1
Clock
計數器 1V
D0
15 V Full-scale
10V
5V
4V
3V
2V
Resolution = Step Size = 1 V
0V
Time
Figure 14-5 Input of DAC output waveform by using the binary counter.
14-4 DAC 0800 Digital to Analog Converter
DAC 0800 is a cheap and commonly used 8-bit DAC, the internal
circuit consists of reference voltage power supply, R-2R ladder resistors
network and transistor switch. The voltage power supply range is between
 4.5 V to  18 V, under the  5 V condition, the power loss is
approximately 33 mW and the settling time is approximately 85 ns. Figure
14-6 is the pins diagram of DAC0800.
14－10
Figure 14-7 is the circuit diagram of DAC0800 single polarity voltage
output, which D 7 ~ D o are the 8-bit digital inputs. The positive reference
voltage is  5 V and passes through R1 to connect to Vref ( ) (pin 14).
The negative reference voltage is GND and passes through R2 to connect to
Vref () ( pin 15 ). The reference current I ref that passes through R1 can be
expressed as
Vref
I ref  (14-4)
R1
At the current output terminal ( pin 4 ), the output current I out is
Vref D7 D 6 D5 D 4 D3 D 2 D1 D
I out  (        0 ) (14-5)
R1 2 4 8 16 32 64 128 256
Threshold
Control VLC 1 16 Compensation
Iout 2 15 Vref ()
V 3 14 Vref ()
Iout 4 13 +V
D7 5 12 D0
D6 6 11 D1
D5 7 10 D2
D4 8 9 D3
Figure 14-6 Pins diagram of DAC 0800.
14－11
12V +12V
C1 C2 C3 R3
4. 7 k
0.1uF 0.01uF 0.1uF

I ref
+12V
3 16 13
Vref 14 I out
+5V
R1 DAC0800 4 -
4.7 k Output
DAC uA741
Vout
15 MSB LSB 2 +
5 6 7 8 9 10 11 12 1
R2 12V
4.7 k
D 7 D 6 D5 D 4 D 3 D 2 D1 D0
Digital Inputs
Figure 14-7 Circuit diagram of DAC0800 single polarity voltage output.
The objective to let I out connects to A 741 is to convert the current
output into the voltage output. In figure 14-7, the output voltage ( Vout ) of
A741 is
Vout  Iout R 3 (14-6)
Figure 14-8 is the circuit diagram of bipolar output voltage of
DAC0800, the main different of figure 14-7 unipolar output voltage is the
connection of the I out output terminal (pin 2) to A741 positive input
terminal ( Vin ), so the output voltage ( Vout ) of A741 is
Vout  ( I out  I out ) R 4 (14-7)
14－12
Where I out and Iout is the complementary output current, I out  I out is
the full-scale current, I FS , then
I out  I FS  I out (14-8)
Substituting equation (14-7) into equation (14-6), we get
Vout  2 I out R 4  I FS R 4 (14-9)
-12 V +12 V
R4
C1 C2 C3
4.7 k
Iref 0.1 uF 0.01 uF 0.1 uF

+12V
3 16 13
Vref 14 I out
+5V R1 DAC0800 4 - Output
4.7 k
DAC I out uA741
Vout
15 MSB LSB 2 +
5 6 7 8 9 10 11 12 1
R2
R3
4.7 k 4.7 k 12V
D 7 D 6 D5 D 4 D 3 D 2 D1 D0
Digital Inputs
Figure 14-8 Circuit diagram of bipolar output voltage of DAC0800.
I FS  I out  I out , where I out and Iout are in complementary relation,
so when I out equals I FS , I out is zero. When I out is zero, then Iout is
I FS . From the above mentioned and equation (14-9), we know that the
maximum value of Vout of the bipolar output voltage circuit is I FS R 4 and
the minimum value is the negative I FS R 4 . Besides DAC0800, there are
14－13
many types of DAC in the market, such as DAC0808 and etc. The theory
and usage are almost the same, if interested, you can refer to related books.
As we know the advantages of unipolar/bipolar DAC circuit, we
combine both of them into one circuit, as shown in figure 14-9, so that the
DAC0800 converter can be used at more applications.

12V +12V
C1 C2 R4
1F 0. 01.F C3
4.7 k
I ref 0.1F
+12V
3 16 13
Vref 14 I out
+5V
R1 DAC0800 4 J1 -
4.7 k Output
DAC uA741
Vout
2 J2 +
15 MSB LSB
5 6 7 8 9 10 11 12 1 J3
R2 I out
R 3 12V
4.7 k 4.7 k
D 7 D 6 D5 D 4 D 3 D 2 D1 D0
Digital Inputs
Figure 14-9 Circuit diagram of unipolar/bipolar output voltage of DAC0800.
14－14
Experiment 1: R-2R network DAC

1. Refer to the circuit diagram in figure 14-3(b) or figure ACS14-1 on
ACT-17300-07 module
2. Let SW1, SW2, SW3 and SW4 switch to 1 (“0” represents as GND, “1”
represents as “+5 V”).
3. By using voltage meter to measure TP1, TP2, TP3, TP4, TP5 of R-2R
network and output port of D/A converter (Vout). Then record the
4. According to the switching of SW1, SW2, SW3 and SW4 in table 14-1,
repeat step 3 and record the measured results in table 14-1.
14－15
Experiment 2: DAC0800 converter

Experiment 2-1: DAC0800 unipolar voltage output
ACT-17300-07 module. Let J1, J2 and J3 be short circuit.
2. Calculate the step size and record the calculation in table 14-2.
3. In table 14-2, the binary values are used as the digital inputs, which " 0 "
represents GND, " 1 " represents  5 V .
4. Using equation (14-5) and equation (14-6) to calculate the theoretical

values of the output current Iout and output voltage Vout (Rf = 4.7 k),
then record in calculation in table 14-2.
5. Let J1 be open circuit, then connect the digital current meter to J1 for
measuring the output current, I out . Finally record the measured results
in table 14-2.
6. Remove the current meter and let J1 be short circuit. Using digital
voltage meter to measure the output voltage (O/P) of A741. Then
7. According to the digital inputs in table 14-2, adjust the on/off of D7 to

D0. Repeat step 5 and step 6, then record the measured results in table
14-2.
14－16
Experiment 2-2: DAC0800 bipolar voltage output

ACT-17300-07 module. Let J1 and J2 be short circuit, J3 be open
circuit.
2. Calculate the step values and record the calculation in table 14-3.
3. In table 14-3, the binary values are used as the digital inputs, which " 0
" represents GND, " 1 " represents  5 V .
4. Using equation (14-5) to calculate I out and I FS , then substitute I out

and I FS into equation (14-9). Find the theoretical value of output
voltage, Vout , finally record the measured results in table 14-3. (note:
when Do to D7 is 1, I out  I FS )
5. Let J1 and J2 be short circuit, J3 be open circuit. Using digital voltage

meter to measure the output voltage, Vout , then record the measured
6. Let J1 and J3 be open circuit, J2 be short circuit. Connect the digital

current meter to J1, then measure the output current, I out . Finally record
7. Let J2 and J3 be open circuit, J1 be short circuit. Connect the digital

current meter on J2 to measure the output current, I out . Finally record
8. Calculate I out  I out and record the measured results in table 14-3.
9. According to the digital inputs in table 14-3, adjust the on/off of D7 to

D0. Repeat step 5 ~ 8, then record the measured results in table 14-3.
14－17

Table 14-1 Measured results of R-2R network DAC converter.
Step Value = V
Digital Inputs Outputs
SW1 SW2 SW3 SW4 TP1 TP2 TP3 TP4 TP5 O/P
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0
Voltage Unit: V
14－18
Table 14-2 Measured results of unipolar voltage output of DAC0800.
Step Value = V
Digital Inputs Analog Outputs
Vout I out
D7 D6 D5 D4 D3 D2 D1 D0 Theoretical Measured Theoretical Measured
Results Results Results Results
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
0 0 0 0 0 1 0 0
0 0 0 0 1 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 1 0 0 0 0 0 0
1 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
Voltage unit: V Current unit: mA
14－19
Table 14-3 Measured results of bipolar voltage output of DAC0800.
Step Value = V
Digital Inputs Analog Outputs

Theoretical Measured
Results Results
D 7 D6 D5 D 4 D3 D2 D 1 D0
Vout Vout I out Iout Iout  Iout
0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0
0 0 0 0 1 0 0 0
0 0 1 0 0 0 0 0
0 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0
1 0 0 0 0 0 1 0
1 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0
1 1 0 0 0 0 0 0
1 1 1 1 1 1 1 1
Voltage unit: V Current unit: mA
14－20
1. In experiment 2-2, if the digital input signal is 01101010, then what is

the output voltage?
2. Try to use the step value and the output voltage range to compare the
differences between the DAC0800 unipolar voltage output and bipolar
voltage output.
8. According to the measured results in table 14-3, what is the
complementary current output (i.e. the relationship of I out and Iout )?
14－21
14－22
Chapter 15
Frequency Converter
1. To understand the operation theory of the frequency multiplier

and frequency converter.
2. To understand the waveforms and frequency spectrums of the

frequency multiplier and frequency converter.
3. To design and implement the frequency multiplier and

frequency converter.
4. To measure and adjust the frequency multiplier and frequency

converter.
In previous chapters, we have discussed the design theories and
implementation of different analog modulators and demodulators. However,
the above-mentioned analog modulators and demodulators are belonging to
the baseband of the wireless transceiver. Therefore, in this chapter, we will
focus on the frequency conversion between the frequency of the baseband
signal and the frequency of the transceiver. On the other hand, we will also
show the phenomenon of the frequency converter by using the basic
equipments. In this chapter, we will discuss the design and implementation
of the frequency doublers and up/down converter.
15－2
Chapter 15 Frequency Converter
15-1 Frequency Multiplier
Figure 15-1 is the input and output signal waveforms of the frequency
multiplier. In figure 15-1, we assume that the audio signal be
A m cos(2f o t ) and the carrier signal be A c cos(2f o t ) . If we multiply the
audio signal by the carrier signal directly at frequency fo, then we get
X DF t   A m cos(2f o t )  A c cos(2f o t )
 A m A c [cos(2f o t )  cos(2f o t )]
 A m A c  cos 2f o  f o  t   cos 2f o  f o  t  

1
2
 A m A c  cos 22f o  t   1 
1
(15-1)
2
where
A m : The amplitude of audio signal.
A c : The amplitude of carrier signal.
f o : The frequency of audio signal and carrier signal.
In equation (15-1), we know that the first term A m A c cos22f o t  2
represents the output term of the double frequency signal; the second term
A m A c 2 represents the DC signal. On the other hand, from equation
(15-1), we can sketch out the output signal spectrums of the frequency
multiplier as shown in figure 15-2.
15－3
Am
Audio Signal
Frequency
Multiplier
Am
Frequency
Multiplied Signal
Carrier Signal
Figure 15-1 Input and output signal waveforms of the frequency multiplier.
X D F f 
1
2
AM A M
f (Hz)
0 fM  fM
Figure 15-2 Frequency spectrum of modulated AM signal and frequency

multiplied signal.
Input signal Multiplier Frequency

Multiplied Signal
Figure 15-3 Basic structure diagram of frequency multiplier.
15－4
From the above-mentioned discussion, we know that in order to design

the frequency multiplier, we need two similar signals input into the two
ports of the multiplier, therefore, the basic structure of the frequency
multiplier is shown in figure 15-3. We utilize the balanced modulator
MC1496 to design the multiplier. Figure 15-4 is the internal circuit diagram
of the balanced modulator MC1496, where D1, R1, R2, R3, Q7 and Q8
comprise an electric current source, which can supply DC bias current for
Q5 and Q6. Q5 and Q6 comprise a differential combination to drive the dual
differential amplifiers constructed by Q1, Q2, Q3 and Q4. Pin 1 and 4 are the
inputs of audio signal; Pin 8 and 10 are the inputs of carrier signal. The
resistor between pins 2 and 3 controls the gain of the balanced modulator;
the resistor of pin 5 determines the magnitude of bias current for amplifier.
Figure 15-5 is the circuit diagram of the frequency multiplier. We can
see that the carrier signal and audio signal belong to single ended input. The
carrier signal input from pin 10 and the audio signal input from pin 1.
Therefore R6 determines the gain of the whole circuit and R10 determines
the magnitude of bias current. If we adjust the variable resistor VR1 or
change the input amplitude of audio signal, then we can change the
symmetry of the output signal waveforms. By adjusting the external
resistors R6 and R7 at pin 2 and pin 3 of the balanced modulator, we can
change the magnitude of the output amplitude, which is the adjustment of
the gain of the balanced modulator.
15－5
(12)

Output

Q1 Q2 Q3 Q4 (6)
Carrier (10)
Signal 
Input 
(8) Q5 Q6
(4)
Audio 
Signal
Input (2)
 Gain
(1) Q7 Adjustment
Terminal
Bias Q8 (3)
Adjustment
(5) D1
Terminal
R2 R3
R1 500
(14) 500
500
V
Figure 15-4 Internal circuit diagram of balanced modulator.
R4
1k R8 1 k +12 V
+
R 6 100 C6 C7
+ 100 nF
C3 100 uF
100 uF J3
J2 R9
R7 1 k R1
3k9 1
TP1 3k9
R5 2 3 Doubler
100 8 6
TP5 C4
O/P1
10 MC1496
+ 100 nF
C2 TP2 Balanced
C1 J1 TP3
RF 100 uF Modulator TP6 Doubler
1 12
I/P 100 nF 4 C5 O/P2
TP4 14 5 TP7
R3 100 nF
R1 R2 R6
10 k 100 R 10
10 k 100
V 6k8
R1
100 k C3 +
100 uF -12 V
Figure 15-5 Circuit diagram of frequency multiplier.
15－6
15-2 Up/Down Frequency Converter
In previous discussion, we multiply the audio signal by the carrier
signal at the same frequency, then we can obtain the double frequency
signal output. However, if we assume the multiplication between two
different signals (i.e. let the audio signal be A S1 cos(2f S1t ) and the carrier
signal be A S2 cos(2f S2 t ) ), then the output signal X out ( t ) of the
multiplier will be
X OUT t   A S1 cos(2f S1t )  A S2 cos(2f S2 t )
 A S1A S2 m cos(2f S1t ) cos(2f S2 t ) (15-2)
 A S1A S2  cos2f S1  f S2  t   cos2f S1  f S2  t  

1
2
A S1 : The amplitude of audio signal.
A S 2 : The amplitude of carrier signal.
f S1 : The frequency of audio signal.
f S2 : The frequency of carrier signal.
In equation (15-2), we know that the first term
A S1A S2 cos2f S1  f S2 t  2 represents the sum of the frequency of audio
signal and carrier signal that is the up frequency signal; the second term
A S1A S2 cos2f S1  f S2 t  2 represents the difference of the frequency
between the audio signal and the carrier signal that is the down frequency
15－7
signal. On the other hand, from equation (15-2), we can sketch out the
output signal spectrums of the up/down frequency converter as shown in
figure 15-6.
Practically, in the application of communication, in order to design a
transmitter, we can assume the audio signal as the baseband modulated
signal and the carrier signal as the transmitted frequency. After the
multiplication of these two signals, we utilize a high-pass filter to obtain the
sum of the signal frequency, which is the up converter. The output signal
spectrum of the up frequency converter is shown in figure 15-7. On the
other hand, in order to design a receiver, we can assume the audio signal as
the RF signal received from the antenna and the carrier signal as the LO
signal of the receiver. After the multiplication of these two signals, we
utilize a low-pass filter to obtain the difference of the signal frequency,
which is the down converter. The output signal spectrum of the down
frequency converter is shown in figure 15-8.
X FC f 
1 A S1 A S2
2
f (Hz)
f S1  f S2 f S1  f S2
Figure 15-6 Output signal spectrums of up/down frequency converter.
15－8
X FC f 
1 A S1 A S2
2
f (Hz)
f S1  f S2 f S1  f S2
Figure 15-7 Output signal spectrums of up frequency converter.
X FC f 
1 A S1 A S2
2
f (Hz)
f S1  f S2 f S1  f S2
Figure 15-8 Output signal spectrums of down frequency converter.
From the above-mentioned discussion, we know that the up/down
frequency converter is the modification of the frequency multiplier and then
with the assistant of the high-pass filter or low-pass filter, we can obtain the
up converter signal and down converter signal, respectively. Figure 15-9 is
the structure diagram of the up/down frequency converter. The circuit
diagram of the up/down frequency converter is shown in figure 15-10. The
block in figure 15-10 is the circuit diagram of the frequency multiplier in
figure 15-5. Resistors R12, R14 and capacitors C9, C11 comprise the low-pass
filter in figure 15-9. The objective is the remove the high frequency signal
15－9
f s1  f s 2 , so that the frequency at the output port is the low frequency signal
f s1  f s 2 , i.e. the down converter. Resistors R13, R15 and capacitors C8, C10
comprise the high-pass filter in figure 15-9. The objective is the remove the
low frequency signal f s1  f s 2 , so that the frequency at the output port is the
high frequency signal f s1  f s 2 , i.e. the up converter.
High-pass
fs1  fs 2
Filter
Input Multiplier
Signal 1
Low-pass
Filter
fs1  fs 2
Input
Signal 2
Figure 15-9 Structure diagram of up/down frequency converter.
C9 C 11
R 12 1 nF 1 nF
S1 LO Doubler Down Con.
I/P I/P O/P1 1k5 O/P
R 14 1k5
S2 RF C8 C 10 Up Con.
Doubler
I/P I/P O/P2 O/P
1 nF 1 nF
R 13 R 15
1k5 1k5
Figure 15-10 Circuit diagram of up/down frequency converter.
15－10

參實驗項目
Experiment 1: Frequency multiplier
1. Refer to the circuit diagram of frequency multiplier in figure 15-5 or

refer to figure ACS15-1 of ACT-17300-08 module.
2. Let J1 be short circuit, i. e. to connect the pin 1 and pin 10 of the

balanced modulator. Let J2 be short circuit and J3 be open circuit, i.e. to
set the resistor between pin 2 and pin 3 be R7 = 1 k, which is the gain
controller.
3. At the RF input port (RF I/P), input 300 mV amplitude and 10 kHz sine
wave frequency.

frequency multiplier (Doubler O/P1 and Doubler O/P2). Adjust the
variable resistor VR1 so that the output signal waveform is symmetry
and the frequency is the two times of the input signal. Then record the

carrier signal input ports of the balanced modulator, which are pin 8
(TP1) and pin 10 (TP2), the audio signal input ports, which are pin 1
(TP3) and pin 4 (TP4). Finally, record the measured results in table 15-1.
6. By using oscilloscope, observe on the output signal waveforms of pin 6

(TP5) and pin 12 (TP6) of the balanced modulator. Then record the
15－11
7. By using oscilloscope, observe on the magnitude of the voltage of the

balanced modulator, which is pin 5 (TP7). Then record the measured
8. According to the input signals in table 15-1, repeat step 4 to step 7, then
9. Let J1 be short circuit, i. e. to connect the pin 1 and pin 10 of the

balanced modulator. Let J2 be open circuit and J3 be short circuit, i.e. to
set the resistor between pin 2 and pin 3 be R16 = 100 , which is the
gain controller.
10. According to the input signals in table 15-2, repeat step 3 to step 8, then
15－12
Experiment 2: Up/Down frequency converter
1. Refer to the circuit diagram of up/down frequency converter in figure

15-10 or refer to figure ACS15-1 of ACT-17300-08 module.
2. Let J1 be open circuit, i. e. to disconnect the pin 1 and pin 10 of the

balanced modulator, so that the LO signal and the RF signal can be
inputted into the balanced modulator separately. Let J2 be short circuit
and J3 be open circuit, i.e. to set the resistor between pin 2 and pin 3 be
R7 = 1 k, which is the gain controller.
3. At the LO signal input port (LO I/P), input 300 mV amplitude and 100
kHz sine wave frequency. At the RF signal input port (RF I/P), input
300 mV amplitude and 120 kHz sine wave frequency.
4. By using oscilloscope, observe on the output signal waveforms of up

converter output port (Up Con. O/P) and down converter output port
(Down Con. O/P). Adjust variable resistor VR1 so that the frequency of
Up Con. O/P is the sum of the LO signal and the RF signal, then the
frequency of Down Con. O/P is the difference between the LO signal
and the RF signal. Finally record the measured results in table 15-3.

carrier signal input ports of the balanced modulator, which are pin 8
(TP1) and pin 10 (TP2), the audio signal input ports, which are pin 1
(TP3) and pin 4 (TP4). Finally, record the measured results in table
15-3.
15－13
6. By using oscilloscope, observe on the output signal waveforms of pin 6

(TP5) and pin 12 (TP6) of the balanced modulator. Then record the
7. By using oscilloscope, observe on the magnitude of the voltage of the

balanced modulator, which is pin 5 (TP7). Then record the measured
8. At the LO signal input port (LO I/P), change the frequency of the LO
signal to 120 kHz. At the RF signal input port (RF I/P), change the
frequency of the RF signal to 100 kHz. Repeat step 4 to step 7 and
9. Let J1 be open circuit, i. e. to disconnect the pin 1 and pin 10 of the

balanced modulator, so that the LO signal and the RF signal can be
inputted into the balanced modulator separately. Let J2 be open circuit
and J3 be short circuit, i.e. to set the resistor between pin 2 and pin 3 be
R16 = 100 , which is the gain controller. Repeat step 3 to step 8 and
finally record the measured results in table 15-4.
15－14

Table 15-1 Measured results of frequency multiplier. (R7 = 1 k)
Output Signal Input Signal Frequencies

Ports 10 kHz 50 kHz
Doubler O/P1
Doubler O/P2
TP1
TP2
15－15
Table 15-1 Measured results of frequency multiplier. (Continued) (R7 = 1 k)

Ports 10 kHz 50 kHz
TP3
TP4
TP5
TP6
TP7
15－16
Table 15-2 Measured results of frequency multiplier. (R16 = 100 )

Ports 10 kHz 50 kHz
Doubler O/P1
Doubler O/P2
TP1
TP2
15－17
Table 15-2 Measured results of frequency multiplier. (Continued) (R16 = 100 )

Ports 10 kHz 50 kHz
TP3
TP4
TP5
TP6
TP7
15－18
Table 15-3 Measured results of frequency converter. (R7 = 1 k)
Output Input Signal Frequencies

Signal Ports f LO  100 kHz ; f RF  120 kHz f LO  120 kHz ; f RF  100 kHz
Up Con.
O/P
Down Con.
O/P
TP1
TP2
15－19
Table 15-3 Measured results of frequency converter. (Continued) (R7 = 1 k)

TP3
TP4
TP5
TP6
TP7
15－20
Table 15-4 Measured results of frequency converter. (R16 = 100 )

Up Con.
O/P
Down Con.
O/P
TP1
TP2
15－21
Table 15-4 Measured results of frequency converter. (Continued) (R16 = 100 )

TP3
TP4
TP5
TP6
TP7
15－22
1. Explain the operation theory of frequency multiplier and its circuit

block diagram.
2. In this experiment of frequency multiplier, explain the objectives of J1

to be short circuit.
3. Refer to the measured results of frequency multiplier, try to explain the

differences between the output signal of Doubler O/P1 and Doubler
O/P2.
4. Explain the operation theory of frequency converter and its circuit

block diagram.
5. In the application of communication, describe the design of the

frequency converter in order to design a transmitter.
6. In the application of communication, describe the design of the

frequency converter in order to design a receiver.
7. Try to sketch the frequency spectrums of frequency multiplier and

frequency converter, respectively.
15－23
15－24
Chapter 16
Signal Recovery
1. To understand the operation theory of the carrier signal

recovery circuit and the clock recovery circuit.
2. To design and implement the carrier signal recovery circuit

and clock recovery circuit.
3. To measure and adjust the carrier signal recovery circuit and

clock recovery circuit.
In previous chapters, we have discussed the demodulator by using
synchronous detection such as the product detector in AM demodulator,
which it required a synchronous carrier signal. Therefore, in this chapter, we
will focus on the design and implementation of carrier signal recovery
circuit.
In digital transmission system, we know that the Clock of the data
signal is not only being used in the transmitter. In the receiver, if we are
unable to obtain the clock signal, which is synchronous with the transmitter,
then the receiver is unable to read the initial bit of the data signal. This
situation will also cause the loss and error of the data signal during decoding.
16－2
Chapter 16 Signal Recovery
Therefore, in this chapter, we also focus on the design and implementation
of the clock recovery circuit.
Carrier Signal Freq. Waveform Carrier Recovery

Freq.
Input Amp. PLL Divider Shaping Output
Multiplier
(1/2) Circuit
(Carrier I/P) (Recovered O/P)
Figure 16-1 Completed structure diagram of carrier signal recovery circuit.
16-1 Carrier Signal Recovery Circuit

As we have mentioned before, the carrier signal recovery circuit is
used in the receiver. However, in the transceiver system, the carrier signal of
the transmitter is hidden in the transmitted signal, and generally, this signal
also includes the modulated signal. Therefore, in the carrier signal recovery
circuit, the objective of the first stage circuit is to remove the modulated
signal by using the frequency multiplier, and then generates a double
frequency carrier signal. After that amplify the signal by using the amplifier.
The second stage of the carrier signal recovery circuit is to lock the double
frequency carrier signal by using phase locked loop (PLL). As a result of the
doubler frequency is directly produced from the transmitted signal received

by the receiver, so, the carrier signal at the transmitter will be synchronized
with the doubler frequency carrier signal. And due to the first two stages of
the recovery circuit is the doubler frequency carrier signal of the transmitter,
therefore, in the third stage, we utilize the frequency divider to recover the
doubler frequency signal to the original frequency signal, which is similar to
16－3
carrier signal at the transmitter. This means that the output signal of the
frequency divider is synchronous and similar to the carrier signal of the
transmitter. Figure 16-1 is the completed structure diagram of the carrier
signal recovery circuit. In figure 16-1, there is an additional waveform

shaping circuit. The objective is to convert the digital output level (square
wave) to standard sinusoidal wave carrier signal, therefore, in this structure,
the waveform shaping circuit is a low-pass filter circuit.
In figure 16-1, for the block of the frequency multiplier, we can utilize
the frequency multiplier in chapter 15 to implement. As for the operation
theory and design of PLL, we have discussed in chapter 8. We use the

integrated circuit 74HC393 to implement the frequency divider. The
operation theory of the circuit is very simple, we will discuss it in next
section. As for the final stage, which is the waveform shaping circuit, we
know that it is a low-pass filter, therefore, we can utilize the concept of
low-pass filter in chapter 1 to implement the waveform shaping circuit.
From the above-mentioned, we notice that the circuits in this chapter

are similar to the circuits as mentioned in previous chapters. Therefore, we
can implement the carrier signal recovery circuit easily. Figure 16-2 is the
circuit diagram of the carrier signal recovery circuit. In figure 16-2, the
circuit of the frequency multiplier is shown in figure 15-5. Resistors R1, R2,
R3, capacitor C1 and A741 comprise the amplifier. As for the PLL part, it
is comprised by Resistors R4, R5, R6, variable resistor VR1, capacitors C2, C3,
16－4
C4 and 74HC4046. Among these components, resistor R5 and capacitor C2

comprise the loop filter in the PLL; variable resistor VR1 and capacitor C4
determine the free running frequency of the internal voltage controlled
oscillator of PLL. We utilize integrated circuit 74HC393 to implement the

frequency divider and finally, the waveform shaping circuit is comprised by
resistors R7, R8, R9, capacitor C5, C6 and A741, which is also the second
order low-pass filter.

R1 R3
1k 9k1
R9
+12 V C5 100 k
C3 +5 V +5 V 1 nF R8
C1 + 10 nF Recovered
10 k TP7 uA741
10 nF uA741 14 16 3 14 TP6
+
O/P
Carrier Freq. TP1 4 2 3
Multiplier TP2 TP4 74HC393 R7
I/P
R2 6 Divider C6
-12 V 2 C4 1 7 8 15 10 k 100 pF
1k5 R4 7 1 nF
74HC4046
4k7 PLL 12
TP3 9
VR1
R5 11 100 k
680
8 5 R6
C2
10 k
10 nF
Figure 16-2 Circuit diagram of carrier signal recovery circuit.
16-2 Clock Recovery Circuit
In digital transmission system, in order to let the receiver to read the
initial bit of the data signal and the required clock signal during decoding,
clock recovery circuit is needed. The objective of the clock recovery circuit
is to recover the clock signal of the data signal and with this clock signal,
we can understand the information of each data signal.
16－5
Figure 16-3 is the structure diagram of the clock recovery circuit. In
figure 16-3, the can see that the clock recovery circuit is quite simple. It
only needs a delay circuit, exclusion OR (XOR) gate and PLL. As for the
Manchester encoder, we just utilize this technique as the received data
signal, which can hide the clock signal of the data signal in the transmitted
signal. Then the receiver is able to recover the clock signal from the
received data signal.
Figure 16-4 is the sequence diagram of clock recovery circuit. In
figure 16-4, we notice that the received data signal (Coded O/P) will be
delayed and operate again with the original data signal by the exclusion OR
gate (XOR). Then the output signal is a pulse (XOR O/P), which the
frequency is similar to the original clock signal. The only different is the
time delay, which means these two signals are synchronized. However, since
the output of the operation of XOR is pulse signal, therefore, this signal is
unable to be a standard clock signal. So, we utilize the phase locked loop
(PLL) to produce the standard clock signal and the reference signal, which
is required by the PLL, is provided by XOR. Finally, the clock signal from
PLL is similar to the original clock signal.
Figure 16-5 is the circuit diagram of clock recovery circuit. In figure
16-5, the frequency divider (74HC393) and the exclusion OR gate (XOR)
comprise the Manchester encoder, which is used to produce the received
16－6
data signal. Resistor R1, capacitors C1, C2 comprise a delay circuit. The PLL
is comprised by resistors R2, R3, R4, R5, R6, variable resistor VR1, capacitors
C3, C4, C5, C6 and LM565. Among the components, resistor R5 and
capacitor C5 comprise the loop filter of the PLL; variable resistor VR1 and
capacitor C6 determine the output free running frequency of the internal
voltage controlled oscillator of the PLL.
Manchester Encoder Clock Recovery Circuit
CLK I/P A
2
B
XOR Recovered
D
XOR PLL CLK O/P
Delay C
Circuit
Figure 16-3 Structure diagram of the clock recovery circuit.
CLK I/P
t
1/2 O/P
1 0 1 0 1 0 1 0 1 0 1
(A)
t
Coded
O/P
(B)
t
Delay
O/P
(C)
t
XOR
O/P
(D)
t
Figure 16-4 Sequence diagram of clock recovery circuit.
16－7
C4
100 nF
R2 +5 V
R3
Clock 10 k 4k7
+5 V 3 16 Recpvered
4
TP1 R4 O/P
14 XOR:A TP4 4k7 5
Clock R 1 TP3
2 3 XOR:B 2
I/P 74HC393 74HC86 C3 C5 LM565
(1/2) C1 100 nF
1 7 8 15
1k C 2 74HC86 7
10 nF PLL
330 pF 220 nF 12 +5 V
6 9
R5 C6 VR 1
1 8
10 k 220 pF 50 k
-5 V R6
20 k
Figure 16-5 Circuit diagram of the clock recovery circuit.
16－8

參實驗項目
Experiment 1: Carrier signal recovery circuit
1. Refer to the circuit diagram of carrier signal recovery in figure 16-2 and
the frequency multiplier in figure 15-5 or refer to figure ACS 16-1 and
figure ACS15-1 of ACT-17300-08 module.
2. In figure ACS15-1, let J1 be short circuit, i. e. to connect the pin 1 and

pin 10 of the balanced modulator. Let J2 be short circuit and J3 be open
circuit, i.e. to set the resistor between pin 2 and pin 3 be R7 = 1 k.
3. At the RF input port (RF I/P), input 300 mV amplitude and 10 kHz sine
wave frequency.

frequency multiplier (Doubler O/P1). Adjust the variable resistor VR1
so that the output signal waveform is symmetry and the frequency is the
two times of the input signal. Then record the measured results in table
16-1.
5. Connect the output signal of the frequency multiplier (Doubler O/P1) in

figure ACS15-1 to the signal input port (Doubler Signal I/P) in figure
ACS16-1.

PLL (TP4). Adjust variable resistor VR1 so that the output frequency of
PLL can lock the input signal of the frequency multiplier. Finally,
16－9

amplifier (TP1), loop filter of the PLL, which are pin 2 (TP2) and pin 9
(TP3), input port (TP5) and output port (TP6) of frequency divider,
input port (TP7) and output port (Recovered O/P) of the waveform
shaping circuit. Finally, record the measured results in table 16-1.
8. According to the input signal in table 16-1, repeat step 4 to step 7 and
16－10
Experiment 2: Clock recovery circuit
1. Refer to the circuit diagram of clock recovery in figure 16-5 or refer to

figure ACS 16-2 of ACT-17300-08 module.
2. At the clock signal input port (Clock I/P), input 2.5 V amplitude, 2.5 V
offset (i.e. High is 5 V, Low is 0 V TTL signal) and 10 kHz square wave
frequency.

output port of the frequency divider (Data), the output port of the
exclusion OR (XOR) and the output port after encoding (TP1). Finally,

output port of the PLL (Recovered O/P). Adjust variable resistor VR1 so
that the output frequency of the PLL can lock the input clock signal.
Then record the measured results in table 16-2.
5. By using oscilloscope, observe on the output signal waveforms of test

point TP2, output port of the delay circuit (TP3) and output port of the
exclusion OR (TP4). Finally, record the measured results in table 16-2.
6. According to the input signal in table 16-2, repeat step 3 to step 5 and
16－11

Table 16-1 Measured results of the carrier signal recovery circuit. (R7 = 1 k)

Ports 10 kHz 20 kHz
Doubler O/P1
TP4
TP1
TP2
16－12
Table 16-1 Measured results of the carrier signal recovery circuit. (Continued) (R7 = 1 k)

Ports 10 kHz 20 kHz
TP3
TP5
TP6
TP7
Recovered
O/P
16－13
Table 16-2 Measured results of the clock recovery circuit.

Ports 10 kHz 20 kHz
Data
Clock
TP1
Recovered
O/P
16－14
Table 16-2 Measured results of the clock recovery circuit. (Continued)

Ports 10 kHz 20 kHz
TP2
TP3
TP4
16－15
1. Describe the applications of the carrier signal recovery and the clock
recovery in the application of communication.
2. Explain the operation theory of the carrier signal recovery circuit and
its circuit block diagram.
3. Refer to figure 16-2, explain the functions of resistor R5 and capacitor

C2, and also the variable resistor VR1 and capacitor C4.
4. Explain the operation theory of the clock recovery circuit and its circuit
block diagram.
5. Refer to figure 16-5, explain what are the components comprised the
delay circuit.
16－16

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Chapter 1

Second Order Filters

1-1: Curriculum Objectives

1. To understand the basic theory of filters.

2. To design and implement the second order low-pass filters.

3. To design and implement the second order high-pass filters.

4. To design and implement the second order bandpass filters.

5. To design and implement the second order band reject filters.

1-2: Curriculum Theory

frequency domain. Normally filters can be classified into three different

classifications: If discriminated by filtering range, then there are four types

low-pass, high-pass, bandpass and band-reject filters.

If discriminated by the frequency response of passband area, then

filter, as shown in figure 1-2. Butterworth filter is also known as maximally

flat filter since no ripple is permitted in its passband. However, ripple is

stopband and the attenuation of transition band is sharper than Butterworth

(a) Low-pass filter (b) High-pass filter

(c) Bandpass filter (d) Band-reject filter

Figure 1-1 Frequency responses of ideal filters.

(a) Butterworth filter (b) Chebyshev filter

Figure 1-2 Frequency responses of Butterworth and Chebyshev filters.

If discriminated by components, then there are two types, which are

years, active components such as operation amplifier (OP) are generally

active filter are as below:

1. After special circuit arrangement, the transfer function provides property

of inductor, therefore it can replace inductor components.

3. Active components have function of amplifying, hence active filter also

In the experiments, we will introduce the implementation of second

Normally the cut-off frequency of a filter is determined by the frequency

with an attenuation of 3 dB.

1-1 Second Order Low-pass Filter

The purpose of low-pass filter is to enable low frequency signal pass

integrator or Miler integrator circuit, its transfer function is:

low-pass filter, we need two Miller integrator circuits and an inverting

low-pass filter. It is comprised by two Miller integrator circuits, a unit gain

then the transfer function is

Figure 1-3 Miller integrated circuit.

Simplify the above equation, we get

Vout (S) Ko2

Equation (1-2) is the standard equation of the second order active

obtain the second order low-pass filter.

low-pass filter, which is based on the block diagram in figure 1-4. We

be more complicated. If we assume

Then the transfer function can be expressed as

Figure 1-5 Circuit diagram of second order active low-pass filter.

Compare equations (1-2) and (1-3), we obtain

weighted summer. The objective is to multiply an individual weight for

on input signal and the output signal of U1 : C . R4, C2 and U1 : B

comprise a Miler integrator circuit; R5, R6 and U1 : C comprise an

inverting amplifier. According to the theory of network composition, this

circuit satisfies the conditions of Butterworth, therefore the curve for

frequency response at passband area is very smooth with no ripple.

1-2 Second Order High-pass Filter

The frequency response of second orders high-pass filter is just the

reverse of second order low-pass filter. The objective is to enable high

1-6 is the block diagram of high-pass filter. It is constructed by two Miler

The above function is the standard function of high-pass filter. We can

the function from the block diagram.

Figure 1-6 Block diagram of second order high-pass filter.

Figure 1-7 Circuit diagram of second order high-pass filter.

integrator circuit are combined and replaced by U1 : A . The second adder

and inverting amplifier is replaced by U1 : B . Then we can save two

become more complicated. We assume