EEE 21 Problem Set #4

Due September 25, 2008, 5PM

Instructions: Write your name and section on each page of your answer sheet. Do not use the
back side of your answer sheets. Show your complete solution. Use the following colors for
your answer sheets:
DC Instructor Paper Color
Dean Michael B. Ancajas Yellow
Chris Vincent J. Densing Blue
Percival DC Magpantay Pink
Joy Alinda P. Reyes Green

1. Shown below is a circuit that is “intended” to implement an 8 state gray code (1 bit
transition per adjacent states) counter. Unfortunately, the circuit has a connection error
that makes its behavior different from what was intended. The outputs are taken as
CQ,BQ,AQ.

3 4

Q Q Q
T C T B T A
Q Q Q

CLK
6
2

a.) Derive the state transition table implemented by the circuit above
b.) Draw the state diagram implemented by the circuit above
c.) Determine the “correction” that must be made to the circuit schematic to realize the
original intended function (8 state gray code counter).

2. Derive the reduced state table of the given state machine described below using a
prime implicant table and by state partitioning:

NS, Z
PS x=0 x=1
A B,0 E,0
B C,0 B,0
C B,0 G,0
D B,0 D,0
E F,0 E,0
F C,0 B,0
G F,0 D,1
3. Given the state table below:
State X=0 X=1 State X=0 X=1
1 2,0 3,0 7 10,0 12,0
2 4,0 5,0 8 8,0 1,0
3 6,0 7,0 9 10,1 1,0
4 8,0 9,0 10 4,0 1,0
5 10,0 11,0 11 2,0 1,0
6 4,0 12,0 12 2,0 1,0

a. Minimize the number of states using inspection, partition and implication.

b. Draw the minimized state diagram.

4. Given the state table below:

a. Minimize the number of states using inspection, partition and implication.
b. Draw the minimized state diagram.

Present Input X (two bits)

State
0 1 2 3 0 1 2 3
1 6 2 1 1 0 0 0 0
2 6 3 1 1 0 0 0 0
3 6 9 4 1 0 0 1 0
4 5 6 7 8 1 0 1 0
5 5 9 7 1 1 0 1 0
6 6 6 1 1 0 0 0 0
7 5 10 7 1 1 0 1 0
8 6 2 1 8 0 0 0 0
9 9 9 1 1 0 0 0 0
10 6 11 1 1 0 0 0 0
11 6 9 4 1 0 0 1 0
Next State Output Z (one-bit)
5. Consider the state diagram below:
1/0

a 0/0 0/0 1/0 1/1

b c d e
0/0
1/0 1/0
0/0 0/0 0/0 1/1

0/0 0/0 0/0

f 1/0 g h j i
1/0 1/1
1/0
0/0

a) Reduce the number of the state diagram shown above using reduction by partition
method. Show the resulting state diagram.
b.) Implement the design using JK flip-flops and multiplexers (specify size) only

6. A finite state recognizer has one input (X) and one output (Z). The output is asserted
whenever the input sequence 010 has been observed, as long as the sequence 100 has
never been seen. A sample sequence is shown below:
X: 0010101001011010
Z: 0001010100000000
a.) Draw a minimized state diagram
b.) Draw the state transition table for JK flip-flops and indicate state assignment
c.) Determine the flip-flop excitation equations
d.) Draw the circuit

7. Design a counter that outputs the given sequence of numbers. Treat any unused
numbers (states) as don't cares. Make the circuit self-correcting by transitioning any
unused states to state '0'.
a.) 0,1,3,6,7. Use J-K Flip-flops
b.) 0,2,3,5,6. Use T Flip-flops
c.) 0,1,2,3,6,7. Use D Flip-flops
d.) 0,2,4,6. Use S-R Flip-flops

8. Draw a state diagram for a clocked synchronous state machine with two inputs, INIT
and X, and one Moore-type output Z. As long as INIT is asserted, Z is continuously 0.
Once INIT is negated, Z should remain 0 until X has been 0 for two successive ticks and
1 for two successive ticks, regardless of the order of occurence. Then Z should go to 1
and remain 1 until INIT is asserted again. Your state diagram should be neatly drawn and
planar(no crossed lines). (Hint: No more than 10 states are required)
9. Design a clock synchronous state machine that checks a serial data line for even
parity. The circuit should have two inputs, SYNC and DATA, in addition to CLOCK, and
one Moore-type output, ERROR, Devise a state/output table that does the job using just
four states, and include a description of each state's meaning in the table. Choose a 2-bit
assignment, write transition and excitation equations, and draw the logic diagram using D
flip-flops.