INTERNATIONAL JOURNAL OF RESEARCH IN TECHNOLOGY (IJRT)
2394-9007
Vol. V, No. I, February 2018
A Comparative Analysis of Leakage Power Reduction
Technique for Nanoscale Digital Circuit Design
Jaya Nigam, S. S. Gawande
Abstract— Sub-threshold leakage current becomes major
component of total power dissipation as scaling down the feature
size. This paper presents comparative analysis of different logic
circuits for reducing sub-threshold leakage current with
improved performance in dynamic logic circuits. In this paper
dual threshold voltage DOIND (INDEP) logic approach is
proposed with and without sleep switch for logic which reduces
the leakage current with minimum delay penalty. Comparative
evaluations with existing driver circuits are reported. The circuit
design issues of this family are discussed. Also, it is compared
with the conventional CMOS logic from the points of view of the
area, the average propagation delay, the average power
consumption, and the logic swing using a proper figure of merit.
Simulation results are derived by HSPICE tool with PTM bulk
CMOS process fabrication at 32nm technology node. Simulation
results shows that reduction in leakage current by DOIND, dual
Vth domino, dual Vth DOIND, sleep switch dual Vth domino and
sleep switch dual Vth DOIND approaches are 89.72%, 80.12%,
95.27%, 99.96% and 99.98% respectively.
Keywords: low power, Nanometer, INDEP, CMOS.
I. INTRODUCTION
In recent years reliability has emerged out to be a major
concern in integrated circuit design. Aggressive scaling trend
in the VLSI industry has led to various sources of transistor
parameter variations. At deep sub-nanometer scale main source
of transistor parameter variation are inter and intra{die process
variation, which is the outcome of limitation in the accuracy of
the fabrication process, leading to variation in important
parameters of a transistors such as threshold voltage, oxide
thickness, random do pant fluctuation etc. [1-2]. Variation in
these vital parameters of the transistor leads to unreliable
circuits which are prone to functional failure and hence results
in failure of system as a whole. Performance critical circuits in
a system are highly affected by device parameter variations.
Register File (RF) is one such circuit deployed a general
purpose processor operating at the computing speed of a
processor. High speed microprocessors are used in almost all
the smart devices being used today such as iPhone, android
based phones, and other smart phones.
Manuscript received on February, 2018.
Jaya Nigam, Research Scholar, Department of Electronics & Communication
Engineering, Bhabha Engineering Research Institute, Bhopal, M.P., India.
Prof. S. S. Gawande, Asst. Professor, Department of Electronics &
Communication Engineering, Bhabha Engineering Research Institute, Bhopal,
M.P., India.
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Register file is an integral part of such high speed processors
[3]. They are used almost in each clock cycle, as in order to
execute each instruction data should be read or written to the
register file. Moreover, register _le comes in the critical path
of a processor [2]. Therefore, any variation in timing of the RF
due to process variation may directly affect the operation of
microprocessor.
This paper is organised as follows in section II all the
reviewers have given their suggestion on leakage power and
we have seen as we scale down the technology sub-threshold
and gate oxide leakage current will dominant. In section III
there is a comparison of different parameters of power
consumption 32nm technology and in section IV conclusion is
provided.
II. RELATED WORK
There are several techniques to control leakage current at
transistor level design in domino logic circuits. Body biasing is
one of the techniques to reduce leakage current of circuit.
INDEP approach [4] is the technique which mitigates the
leakage current in nanoscale circuit. This technique has two
extra inserted transistors between pull up and pull down
networks which are input logic dependent. This technique is
used for static CMOS circuit and has sufficient delay penalty.
Sleepy keeper approach [5] uses two weak keeper transistors
which are connected parallel to the sleep transistors and gate of
both sleepy keepers is controlled by output voltage. This
technique reduces delay and area as compare to sleepy stack
approach [6-7] but has additional dynamic power dissipation.
Dual threshold voltage domino logic [5] has low threshold
voltage transistors and high threshold voltage transistors. Low
threshold voltage transistors are connected in critical path
which improve the performance and high threshold voltage
transistors are connected in non critical path to mitigate le
leakage current. This technique reduces leakage power
dissipation but has lower noise margin.
Significant efforts have been devoted to achieve efficient
leakage reduction at the circuit level. The transistor stacking
techniques reported in [8] reduces the leakage current of the
series connected transistors. In this approach the stacking
causes increase in the source voltage that reduces gate-to
source, drain-to-source and create body-bias. The dual-
threshold and multi-threshold approach of leakage reduction as
reported in [9], achieves the leakage reduction by adopted high
38
INTERNATIONAL JOURNAL OF RESEARCH IN TECHNOLOGY (IJRT) ISSN No. 2394-9007
Vol. V, No. I, February 2018 www.ijrtonline.org
threshold transistors for non-critical path whereas low
threshold transistor for the critical path to avoid increase in
delay. Some new techniques such as LECTOR [10], ONOFIC,
super cut off, etc have also shown as good approach to reduce
leakage current. The LECTOR approach utilizes two extra
transistors in series between pull-up and pull-down network
whereas ONOFIC approach utilizes parallel connected nMOS
and pMOS transistor between pull-up and pull-down network.
In the super cut-off approach as reported in [11], utilizes on
pMOS transistor to gate leakage current and biased in supper
cut-off condition. Although, the leakage reduced by supper cut-
off is very high but the variable bias requirement increases its
complexity.
Dual threshold voltage with sleep switch domino logic [6]
has same configuration as dual threshold voltage domino logic
except an extra high threshold voltage transistor is connected
between dynamic node and ground. This technique reduces
leakage current in sleep mode. Variable threshold voltage (b)
keeper [12] is another leakage reduction technique in domino Fig. 1: Leakage reduction techniques (a) INDEP Low Vth
logic circuits. In this technique threshold voltage of keeper (b) INDEP High Vth
transistor is dynamically modified by using body biasing to
reduce power and it also improves speed of domino logic
circuit. Noise immunity also improves as compare to standard
domino logic circuit but it required extra circuitry to generate
body bias voltage. Leakage biased domino circuit [13-16]
In this approach different input pattern at the inserted
transistors M1 and M2 provides different control to the leakage
current. In standby condition both the transistors are kept in
cut-off mode to reduce the leakage current whereas in normal
active mode both are kept in ON conditions. The simulation
results in the next section shows the efficacy of the proposed
approach over the existing leakage reduction techniques.

Fig. 2: Transient characteristics waveform of 2-input INDEP NAND gate

using HSPICE in CMOS technology

III. SIMULATION ENVIRONMENT

All the approaches of leakage reduction are first implemented
in Tanner 14.1 with similar sizing of the transistors. The 3-
input NAND gate is used as design for applying leakage
reduction techniques. From the schematic diagram, the netlist
is created and simulated with 32nm technology PTM files
using HSPICE simulator from Synopsys. The all possible
combination of the input patterns are applied and
corresponding leakage is evaluated and compared.
A novel DHS, DFS and DHFS leakage reduction
technique is proposed for low power application in digital
(a) circuits. Results show CMOS technology is used for ultra low
power applications, reduction to design a device which is
having lowest possible leakage. The experiment results shows
that saving of dynamic power in proposed DHFS circuit is
much lower than other circuits, the reduction is about 17.17%

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INTERNATIONAL JOURNAL OF RESEARCH IN TECHNOLOGY (IJRT) ISSN No. 2394-9007
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in NG, 25.68% in NGHS, 12.85% in NGFS, 25.75% in comparison is shown in Figure5.4 and Figure.5.5 with existing
NGHFS and 2.86% in LECTOR. The proposed technique can and proposed circuit. From the below table calculation of
be applied on high performance, low power applications, leakage power is shown in all input vector combination for
where leakage is major concern such as microprocessor, calculation of worst leakage condition with scaling the
memory units and other portable devices. Comparison of dimension of MOS transistor.
average power is shown in Figure.5.3. Leakage power
TABLE I: AVERAGE POWER CONSUMPTION AT 32NM TECHNOLOGY
Techniques Dynamic Power Delay (ps) PDP (aWS)
(µW)
Low Vth High Vth Low Vth High Vth Low Vth High Vth
NAND Gate 0.143 0.096 7.816 12.13 1.113 1.156
NAND Gate Header Sleep 0.159 0.109 11.57 18.18 1.834 1.971
NAND Gate Footer Sleep 0.136 0.095 10.38 17.07 1.400 1.613
NAND Gate Header Footer Sleep 0.158 0.113 14.42 23.82 2.273 2.680
LECTOR 0.124 0.092 10.36 26.88 1.275 2.468
INDEP Approach 0.137 0.083 17.88 42.14 2.440 3.471
TABLE II: LEAKAGE POWER AT 32NM 250C
Techniques Leakage Power (nW)
Low Vth High Vth
00 01 10 11 00 01 10 11
NAND Gate 9.464 73.29 73.79 63.72 2.483 19.30 2.488 19.26
NAND Gate Header Sleep 0.875 2.035 2.034 2.835 0.194 0.254 0.260 0.035
NAND Gate Footer Sleep 4.926 9.449 8.448 15.84 1.190 2.489 2.488 2.411
NAND Gate Header Footer Sleep 0.654 0.868 0.868 0.285 0.145 0.199 0.199 0.039
LECTOR 9.447 65.89 66.99 54.38 2.413 16.09 15.99 5.368
INDEP Approach 0.656 0.855 0.848 0.285 0.142 0.197 0.199 0.036
TABLE III: LEAKAGE POWER AT 32NM 1100C
Techniques Leakage Power( nW)
Low Vth High Vth
00 01 10 11 00 01 10 11
NAND Gate 46.33 60.13 52.43 57.65 10.39 12.98 12.59 12.98
NAND Gate Header Sleep 9.389 9.729 9.740 9.730 1.733 1.763 1.731 0.149
NAND Gate Footer Sleep 18.35 45.42 46.03 53.99 8.385 11.09 10.97 10.84
NAND Gate Header Footer Sleep 8.687 9.393 9.397 0.974 1.661 1.707 1.704 0.153
LECTOR 41.3 52.42 52.37 14.08 10.44 19.35 19.12 14.29
INDEP Approach 8.602 9.262 9.264 0.972 1.593 1.639 1.649 0.150

IV. CONCLUSION
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