ECE 102 – Digital Circuit Logic

DIGITAL CIRCUIT LOGIC

UNIT 15: REDUCTION OF STATE TABLES /
STATE ASSIGNMENT

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ECE 102 – Digital Circuit Logic

Learning Objectives
1. Define equivalent states, state several ways
of testing for state equivalence, and determine if
two states are equivalent.
2. Define equivalent sequential circuits and
determine if two circuits are equivalent.
3. Reduce a state table to a minimum number
of rows.
4. Specify a suitable set of state assignments for
a state table, eliminating those assignments
which are equivalent with respect to the cost of
realizing the circuit.
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ECE 102 – Digital Circuit Logic

Learning Objectives
5. State three guidelines which are useful in
making state assignments, and apply these to
making a good state assignment for a given state
table.
6. Given a state table and assignment, form the
transition table and derive flip-flop input
equations.
7. Make a one-hot state assignment for a
state graph and write the next-state and output
equations by inspection.

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ECE 102 – Digital Circuit Logic

Guidelines for Construction of State

Graphs
Example 1:

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ECE 102 – Digital Circuit Logic

Guidelines for Construction of State

Graphs
Example 1 (continued):

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ECE 102 – Digital Circuit Logic

Guidelines for Construction of State

Graphs
Example 1 (continued):

 See pages 469-472 for more examples.

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ECE 102 – Digital Circuit Logic

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ECE 102 – Digital Circuit Logic

Equivalent States
State Equivalence:
Two states are equivalent if there is no way of
telling them apart through observation of the
circuit inputs and outputs.

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ECE 102 – Digital Circuit Logic

Equivalent States

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ECE 102 – Digital Circuit Logic

Elimination of Redundant States

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ECE 102 – Digital Circuit Logic

Elimination of Redundant States

Eliminating Redundant States from Table 15-1:
Looking at the table, we see that there is no way of telling
states H and I apart. That is, if we start in state H, the next
state is A and the output is 0; similarly, if we start in state I,
the next state is A and the output is 0. We say that H is
equivalent to I(H≡I).
Similarly, rows K, M, N, and P have the same next state
and output as H, so K, M, N, and P can be replaced by H, and
these rows can be deleted.
Also, the next states and outputs are the same for rows J
and L, so J≡L. Thus, L can be replaced with J and eliminated
from the table. The result is shown in Table 15-2.
Having made these changes in the table, rows D and G are
identical and so are rows E and F. Therefore, D≡G, and E≡F,
so states F and G can be eliminated.
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ECE 102 – Digital Circuit Logic

Elimination of Redundant States

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ECE 102 – Digital Circuit Logic

Elimination of Redundant States

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ECE 102 – Digital Circuit Logic

Determination of State Equivalence

Using An Implication Table
Implication Table Method Procedure:
1. Construct a chart which contains a square for each
pair of states.
2. Compare each pair of rows in the state table. If the
outputs associated with states i and j are different,
place an X in square i-j to indicate that i≢j. If the
outputs are the same, place the implied pairs in
square i-j. (If the next states of i and j are m and n
for some input x, then m-n is an implied pair.) If the
outputs and next states are the same (or if i-j only
implies itself), place a check (Ë) in square i-j to
indicate that i≡j.
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ECE 102 – Digital Circuit Logic

Determination of State Equivalence

Using An Implication Table
Implication Table Procedure (continued):
3. Go through the table square-by-square. If
square i-j contains the implied pair m-n, and
square m-n contains an X, then i≢j, and an X
should be placed in square i-j.
4. If any X’s were added in step 3, repeat step 3
until no more X’s are added.
5. For each square i-j which does not contain an
X, i≡j.

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ECE 102 – Digital Circuit Logic

Determination of State Equivalence

Using An Implication Table
Enumerate all possible combinations of states taken two at a time
S0

S1 S1
Next States
Under all S2 S2
Input
S3 S3
Combinations
S4 S4

S5 S5

S6 S6

S0 S1 S2 S3 S4 S5 S6 S0 S1 S2 S3 S4 S5

Naive Data Structure: Implication Chart

Xij will be the same as Xji
Also, can eliminate the diagonal
ECE 102 – Digital Circuit Logic

Determination of State Equivalence

Using An Implication Table
Entry Xij — Row is Si, Column is Sj

Si is equivalent to Sj if outputs are the same and

next states are equivalent

Xij contains the next states of Si, Sj which must be equivalent if

Si and Sj are equivalent

If Si, Sj have different output behavior, then Xij is crossed out

Example: S0 S1-S3
S0 transitions to S1 on input 0, S2 on input 1; S2-S4
S1 transitions to S3 on input 0, S4 on input 1;
S1
So square X<0,1> contains entries S1-S3 (transition on zero)
S2-S4 (transition on one)
ECE 102 – Digital Circuit Logic

Determination of State Equivalence

Using An Implication Table

Output a 1 whenever the serial sequence 010 or 110 has been

observed at the inputs
State transition table:
Next State Output
Input Sequence Present State X=0 X =1 X =0 X=1
Reset S0 S1 S2 0 0
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0
ECE 102 – Digital Circuit Logic
Implication Chart Method

S1-S3 S2 and S4
S1 S2-S4 have different
S1-S5 S3-S5 I/O behavior
S2 S2-S6 S4-S6
S1-S0 S3-S0 S5-S0 This implies that
S3 S2-S0 S4-S0 S6-S0 S1 and S0 cannot
be combined
S4
S1-S0 S3-S0 S5-S0 S0-S0
S5 S2-S0 S4-S0 S6-S0 S0-S0
S0-S0
S6 S0-S0
S0 S1 S2 S3 S4 S5
Starting Implication Chart
ECE 102 – Digital Circuit Logic

Determination of State Equivalence

Using An Implication Table
Implication Table Procedure (continued):
3. Go through the table square-by-square. If
square i-j contains the implied pair m-n, and
square m-n contains an X, then i≢j, and an X
should be placed in square i-j.
4. If any X’s were added in step 3, repeat step 3
until no more X’s are added.
5. For each square i-j which does not contain an
X, i≡j.

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ECE 102 – Digital Circuit Logic

S1
S3-S5
S2 S4-S6
Results of First Marking Pass
S3
Second Pass Adds No New Information
S3 and S5 are equivalent S4
S4 and S6 are equivalent
This implies that S1 and S2 are too! S5 S0-S0
S0-S0
S0-S0
S6 S0-S0
S0 S1 S2 S3 S4 S5
Next State Output
Input Sequence Present State X =0 X =1 X =0 X =1
Reset S0 S1' S'1 0 0
Reduced State 0 or 1 S1' S3' S'4 0 0
Transition Table 00 or 10 S3' S0 S0 0 0
01 or 1 1 S4' S0 S0 1 0
ECE 102 – Digital Circuit Logic

Next State Output

Input Sequence Present State X=0 X =1 X =0 X=1
Reset S0 S1 S2 0 0
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0

Next State Output

Input Sequence Present State X =0 X =1 X =0 X =1
Reset S0 S1' S'1 0 0
Reduced State 0 or 1 S1' S3' S'4 0 0
Transition Table 00 or 10 S3' S0 S0 0 0
01 or 1 1 S4' S0 S0 1 0
ECE 102 – Digital Circuit Logic

Determination of State Equivalence

Using An Implication Table

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ECE 102 – Digital Circuit Logic

Determination of State Equivalence

Using An Implication Table

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ECE 102 – Digital Circuit Logic

Determination of State Equivalence

Using An Implication Table

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ECE 102 – Digital Circuit Logic

Equivalent Sequential Circuits

Equivalent Sequential Circuits Formal Definition:

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ECE 102 – Digital Circuit Logic

Equivalent Sequential Circuits

Equivalent State pairs:

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ECE 102 – Digital Circuit Logic

Reducing Incompletely Specified

State Tables
Incompletely Specified Examples:

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ECE 102 – Digital Circuit Logic

Reducing Incompletely Specified

State Tables

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ECE 102 – Digital Circuit Logic

Reducing Incompletely Specified

State Tables
Procedure to Reduce an Incompletely Specified
Table:
To reduce an incompletely specified table, a
minimum of the maximal compatibles are selected,
say C1, C2, . . . , Ck, so that
(1) each state of the table appears in at least one of
the Ci, and
(2) for each input combination x and each Ci, the next
states of the states in Ci are contained in some Cj. (It
may be that j=i.)

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ECE 102 – Digital Circuit Logic

Reducing Incompletely Specified

State Tables
Even Parity Detector for 0 Through 5:

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ECE 102 – Digital Circuit Logic

Derivation of Flip-Flop Input

Equations
Procedure to Derive Flip-Flop Input Equations:
1. Assign flip-flop state values to correspond to the
states in the reduced table.
2. Construct a transition table which gives the next
states of the flip-flops as a function of the present states
and inputs.
3. Derive the next-state maps from the transition table.
4. Find flip-flop input maps from the next-state maps
using the techniques developed in Unit 12 and find the
flip-flop input equations from the maps.
See pages 516-520 for applications of this procedure.

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ECE 102 – Digital Circuit Logic

Equivalent State Assignments

Equivalent State Assignments:
Now we must assign flip-flop states to correspond to
the states in the table.

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ECE 102 – Digital Circuit Logic

Equivalent State Assignments

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ECE 102 – Digital Circuit Logic

Equivalent State Assignments

J and K Input Equations:

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ECE 102 – Digital Circuit Logic

Equivalent State Assignments

Equivalent and Distinct State Assignments:
Two state assignments are equivalent if one
can be derived from the other by permuting and
complementing columns.
Two state assignments which are not equivalent
are said to be distinct.

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ECE 102 – Digital Circuit Logic

Equivalent State Assignments

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ECE 102 – Digital Circuit Logic

Guidelines for State Assignment

Guidelines:

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ECE 102 – Digital Circuit Logic

Guidelines for State Assignment

Derivation of State Assignment:

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ECE 102 – Digital Circuit Logic

Guidelines for State Assignment

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ECE 102 – Digital Circuit Logic

Guidelines for State Assignment

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ECE 102 – Digital Circuit Logic

Guidelines for State Assignment

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ECE 102 – Digital Circuit Logic

Guidelines for State Assignment

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ECE 102 – Digital Circuit Logic

Using a One-Hot State Assignment

One-Hot State Assignment:
The one-hot assignment uses one flip-flop for each state,
so a state machine with N states requires N flip-flops.
Exactly one of the flip-flops is set to one in each state.
For example, a system with four states (S0, S1, S2, and
S3) could use four flip-flops (Q0, Q1, Q2, and Q3) with the
following state assignment:
S0: Q0 Q1 Q2 Q3=1000, S1: 0100, S2: 0010, S3: 0001
The other 12 combinations are not used.
In general, when a one-hot state assignment is used,
each term in the next-state equation for each flip-flop
contains exactly one state variable, and the reduced
equation can be written by inspecting the state graph.
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ECE 102 – Digital Circuit Logic

Machine Learning

 What is Machine Learning?

 Use statistical techniques to give computer systems the ability

to "learn" with data, without being explicitly programmed.
ECE 102 – Digital Circuit Logic

Machine Learning

 What is Machine Learning?

 Apply a prediction function to a feature representation of the
image to get the desired output:

f( ) = “apple”
f( ) = “tomato”
f( ) = “cow”
ECE 102 – Digital Circuit Logic

Machine Learning

y = f(x)
output prediction Image
function feature
 Training: given a training set of labeled examples
{(x1,y1), …, (xN,yN)}, estimate the prediction
function f by minimizing the prediction error on the
training set
 Testing: apply f to a never before seen test
example x and output the predicted value y = f(x)

Slide credit: L. Lazebnik

ECE 102 – Digital Circuit Logic

Machine Learning

Training
Labels
Training
Images
Image Learned
Training
Features model

Testing
Image Learned
Prediction
Features model
Test Image Slide credit: D. Hoiem and L. Lazebnik