EE 668: System Design

Madhav P. Desai
January 18, 2011

1 Overview
It is well known that every eighteen months or so, VLSI system capacity doubles
and gate delays decrease by a factor of 0.7X. The system designer faces the
challenge of using this complexity and delivering efficient, reliable systems in a
cost-effective manner.
We will study the two dominant and necessary processes in system design:
decomposition and assembly. Decomposition is the process by which a complex
entity is broken up into simpler entities. Assembly is the process by which a
complex entity is constructed out of simpler entities. The challenge for the
system designer is to make appropriate choices while decomposing the system
so that the assembled entity will meet the specifications.
The primary goal of the course is to provide a clear understanding of the
concepts that support these processes, so that the student has the conceptual
tools necessary to make the appropriate choices in designing systems. Specifi-
cally, we will cover the following topics (numbers in brackets denote the hours
devoted to each topic)
1. interconnect issues (12)
(a) signal interconnect models: lumped, distributed, transmission-line
(b) delay and crosstalk
(c) power and clock distribution
2. decomposition of a system into data and control paths (8)
(a) Mealy/Moore state machines
(b) register-transfer-level descriptions
(c) implementation using a single clock positive-edge-triggered paradigm
3. decomposition of the control path (6)
(a) additive decomposition, state machine re-use

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 (b) multiplicative decomposition, control synchronization, control dead-
locks
4. parallelism and system decomposition (8)
(a) pipelines: control-flow and data-flow pipelines.
(b) communication between sub-systems
(c) queueing models of systems and performance modeling
(d) resource contention and deadlocks
5. memory sub-systems (6)
(a) memory architecture
(b) shared memory data hazards and consistency, mutual exclusion
6. Test and verification: formal and simulation based methods for system
testing and verification (4)

2 Tools and infra-structure that will be needed

during the course
The following tools are currently installed in the VLSI laboratory in the EE
department, and will be used for assignments and projects during this course.
1. NGSPICE, NGNUTMEG (circuit simulator and result viewer).
2. CAPEM capacitance extractor.
3. GHDL or Mentor Graphics Modelsim.
4. Xilinx ISE (FPGA synthesis tool set).
5. IMAGE simulation accelerator (FPGA based cosimulation environment).
6. Synopsys DC or Mentor Graphics Leonardo Spectrum (may be used).
7. Cadence SoC Encounter (may be used).

3 Pre-requisites
An introduction to basic electrical circuits, analog and digital circuits is a must.
An introduction to VLSI design is desirable. All students will be required to use
VHDL in their assignments, so a basic familiarity with this language is essential.

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4 Reading material
The following texts are likely to be useful.
1. W. J. Dally, J. W. Poulton, Digital Systems Engineering, Cambridge Uni-
versity Press, 1998 (broad treatment of electrical aspects of digital system
design).
2. S. H. Hall, G. W. Hall, J. A. McCall, High-Speed Digital System Design,
John Wiley and Sons, 2000 (practical hand-book of interconnect-theory
and design practice).
3. J. M. Rabaey, Digital Integrated Circuits, A Design Perspective Prentice-
Hall India, New Delhi, 1997 (a useful general reference for digital VLSI
design).
4. H. G. Cragon, Memory Systems and Pipelined Processors, Narosa, 1996
(comprehensive text on memory sub-systems).
Additional reading material will be assigned during the course.