Effective System Design

with ARM System IP

Mentor Technical Forum 2009

Serge Poublan
Product Marketing Manager
ARM

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 Higher level of integration

WiFi Platform OS Graphic 13 days standby

Bluetooth MP3

Camera Flash 9

128 MB DDR H.264

Skype

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Processors are evolving, e.g. MP
 World-class market-proven technology ARMv7 Cortex
x1-4

 20+ processors for every application

Cortex-A9

Cortex-A8
 200+ silicon partners ARMv6 ARM11 MPCore
x1-4

 500+ licenses ARM1176JZ(F)-S

 15Bu shipped
ARM1156T2(F)-S
ARM1136J(F)-S

ARMv5 Cortex-R4F
ARM1026EJ-S
Cortex-R4
ARM968E-S
ARM926EJ-S
ARM966E-S
ARM946E-S

ARM7EJ-S SC200

ARMv4 ARM920T Cortex-M3

SC300
ARM922T
Cortex-M1
ARM7TDMI(S) SC100
Cortex-M0

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 ARM Mali GPU - Scalable Performance to over 1G Pixel/s

Mali™-400 MP
Console 3D
Gaming
Next
Generation
Navigation HD 3D
Visual complexity

Gaming
Mali™-200
Mobile 2D/3D
Gaming Presentations
Flash Flash 10
Lite
HD Video
Post
Mali™-55 TV HD UI Processing
3D
Navigation
Web Video
Browsing Java Post
Gaming Processing

Screen resolution

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Higher Mobile Device Resolution
Requirements of next generation Mobile
platform
- Increasing bandwidth requirements simply to
refresh the display
- Ignoring Fill rate, Input Vertex Data
and Texture bandwidth
1080p60
1080p30 1920x1080
1920x1080

WXGA
1280x800
WSVGA
1024x600
Display Refresh Bandwidth MB/s

WVGA 1080p60, 1920x1080, 60fps 475

800x480
1080p30, 1920x1080, 30fps 237
720p, 1280x720, 30fps 105
VGA
640x480 WVGA, 800x480, 30fps 44
QVGA
320x240 VGA, 640x480, 30fps 35

2007 2008 2009 2010 2011 2012 2013

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Example SoC Mobile Platform
Media
CPU
L2 Media
CPU Engine
Cache Engine Graphic
Graphic Video DMA LCD
Video DMA LCD
Engine Engine Engine Ctrl
Engine Engine Engine Ctrl
L2CC
L2CC
Bandwidth
64 or 128 requirement
Latency requirement

AMBA
Interconnect

Dynamic Static Interrupt

Dynamic Static Interrupt
Memory
SDRAM Memory Controller
Memory Memory Controller
Controller
Ctrl Ctrl
Controller Ctrl

NAND
LPDDR2 UART0 SPI
Flash UART1 WDT Timer0 Timer1 RTC GPIO

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Example SoC Mobile Platform
Media
CPU
L2 Media
CPU Engine
Cache Engine Graphic
Graphic Video DMA LCD
Video DMA LCD
Engine Engine Engine Ctrl
Engine Engine Engine Ctrl
L2CC
L2CC

64 or 128

AMBA
Interconnect

Dynamic Static Interrupt

Dynamic Static Interrupt
Memory
SDRAM Memory Controller
Memory Memory Controller
Controller
Ctrl Ctrl
Controller Ctrl

NAND
LPDDR2
Flash “Digital Highway”

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ARM Design Flow for Digital Highway
 Design Your Intelligent Digital Highway

 Configure and connect your RTL

AMBA Designer
 Verification & performance exploration in simulation
AVIP
 Improve your software
CoreSight
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AMBA Ecosystem :
 The on-chip infrastructure is critical to system performance
 Increased focus on processor memory performance
 Different types of processors have different requirements
 ARM has grown the AMBA architecture eco-system to help
accelerate SoC design:
 70+ Connected Community partners
have AMBA compatible products
 10+ AMBA specification downloads a day

“… the de facto standard is of course the ARM bus architecture, AMBA.”

Ron Wilson, EETimes
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Design to Minimise Latency
 Each path must be designed to minimise the inherent pipeline
latency
Round trip memory latency
Processor sub-system
AXI Interconnect
Dynamic Mem Ctrl
DDR2 PHY
DDR2 SDRAM
Address DDR2 Data FIFO
De-skew and bus
format and SDRAM and interface
arbitration CAS latency capture

 Next generation AXI Interconnect halves the interconnect latency

 Masters which issue multiple AXI requests effectively hide latency
 PrimeCell Cache Controllers
Trade an increase in minimum latency for dramatically reduced average latency

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Design to Maximise Throughput
 Effective on-chip Quality of Service depends on the co-
operation of the interconnect and memory controller

 Support for multiple outstanding requests

 The best use of memory pages by scanning
the list of requests
 Controlling the order of queued transactions to
 Meet maximum latency targets
 Ensure throughput-dependent
processors are well serviced
 Provide low latency paths

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ARM Level2 Cache Controllers
Media
CPU Media
CPU Engine
Engine Graphic
Graphic Video DMA LCD
Video DMA LCD
L2 Engine Engine Engine Ctrl
L2 Engine Engine Engine Ctrl
Cache
Cache

64 or 128

AMBA
Interconnect

Dynamic Static Interrupt

Dynamic Static Interrupt
Memory
SDRAM Memory Controller
Memory Memory Controller
Controller
Ctrl Ctrl
Controller Ctrl

NAND
LPDDR2
Flash “Digital Highway”

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 L2CC Increases Processor Performance
Benchmark : MPEG4 decode
512K L2 +104%
256K L2
System : ARM PrimeXsys Platform for
+102%
ARM1136J-S
128K L2
+74%
CPU : 400MHz ARM1136J-S 16K I & D caches
No L2
Memory : 100MHz 32 bit SDRAM
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 L2 cache : L210 128K unified L2 cache
MPEG4 Decode on ARM1136EJ-S
Relative performance

Web Page Render Time as a function of L2 Cache Size

Benchmark: Linux + Mozilla (5 html
512 pages from I-Bench looped 4 times)
L2 Cache Size (KB)

CPU: Cortex-A8 (speed, L1 cache), L2

256 part of Cortex-A8

128
Results may vary for system
First Time configuration and web content
0 Subsequent

0.0 1.0 2.0 3.0 4.0

Speed Up Compared to 0K L2

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L2CC Increases System Performance
 Reduced System Power Consumption
 External memory access ~10x more energy than on-chip
 External memory accesses reduced with L2 cache
 Enables use of lower-power and lower-cost memory
sub-system
 E.g. 16-bit instead of 32-bit external interface
 Or LPDDR instead of DDR2

 Reduced On-Chip traffic & contention

 Only cache misses propagated to the interconnect
 Improve overall system performances
 Provide more bandwidth to others SoC components

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ARM AMBA Interconnect
Media
CortexA8
A8 Media
Cortex Engine
Engine Graphic
Graphic Video DMA LCD
Video DMA LCD
Engine Engine Engine Ctrl
Engine Engine Engine Ctrl
L2CC
L2CC

64 or
128

NIC-301

Dynamic Static Interrupt

Dynamic Static Interrupt
Memory
SDRAM Memory
Memory Memory Controller
Controller Ctrl Controller
Ctrl
Controller Ctrl

NAND
LPDDR2
Flash “Digital Highway”

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AMBA Interconnect (NIC-301)
 Low latency communication for ARM CPUs

 High bandwidth for ARM Graphics and Video

 Supporting:
 AXI, AHB & APB
 Data widths from 32- to 128-bit
 Supporting both synchronous & GALS implementations
 Quality of service

 Configurable through AMBA Designer

 For minimum area & maximum frequency

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Optimise your Interconnect Topology
Real-time masters Real-time masters

Cortex A9

Freq F

Fx2.5
Cortex A9

Fx2.5
RAM SMC DMC

Low bandwidth peripherals

RAM SMC DMC

 High connectivity & increasing Fx2.5
numbers of IP cores does not scale
with a single interconnect

Low bandwidth peripherals

 Use properties of the traffic to influence

the topology

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Topology Optimisation with ARM Interconnect

Cortex Neon
Cortex Neon
Graphic Video DMA LCD
Graphic Video DMA LCD
Engine Engine Engine Ctrl
Engine Engine Engine Ctrl
L2CC
L2CC

64 or
128

NIC-301
400MHz
NIC-301
Low Latency
200MHz
Interconnect

Dynamic Static Interrupt

Dynamic Static Interrupt
Memory
SDRAM Memory Controller
Memory Memory Controller
Controller
Ctrl Ctrl
Controller Ctrl

NAND
LPDDR2
Flash

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ARM Memory Controllers
Cortex Neon
Cortex Neon
Graphic Video DMA LCD
Graphic Video DMA LCD
Engine Engine Engine Ctrl
Engine Engine Engine Ctrl
L2CC
L2CC

64 or
128

Low Latency
Interconnect

Interrupt
SMC-35x Interrupt
DMC-34x
SDRA
DMC-34x SMC-35x Controller
Controller
M Ctrl

NAND
LPDDR2
Flash

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ARM Memory Controllers
 Synthesizable, Configurable soft cores
 Wide range of memory types, silicon processes & target
applications
 AXI Dynamic Memory Controllers for SDR, DDR, LPDDR,
DDR2 and LPDDR2 (DMC-34x)
 Over 20 licensees to date
 AXI Static Memory Controllers for NOR Flash, NAND
Flash and SRAM (SMC-35x)
 Over 40 licensees to date
 AHB Memory Controllers for Dynamic and Static Memories
(PL24x)
 Over 60 licensees to date

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ARM Design Flow for Digital Highway
 Design Your Intelligent Digital Highway

 Configure and connect your RTL

AMBA Designer
 Verification & performance exploration in simulation
AVIP
 Improve your software
CoreSight
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What is AMBA Designer?
 Topolology

 Configure

 Cross-configure

 Stitch & Check

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What is AMBA Designer?
Interface checking on:

 Topolology •Signal widths

•Signal direction
•Interface properties
•Valid response
types
•Interleave depth

 Configure
•…

 Cross-configure

 Stitch & Check

(Export as individual signals)

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ARM Design Flow for Digital Highway
 Design Your Intelligent Digital Highway

 Configure and connect your RTL

AMBA Designer
 Verification & performance exploration in simulation
AVIP
 Improve your software
CoreSight
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AVIP Features for RTL Simulation
 Functional IEEE 1800 SystemVerilog Testbench
Verification
 For Verification Directed
Prof.
Vectors
Data AXI Master
AXI Slave
Interface
AXI Master
Interface AXI Slave
Engineers, AVIP is a
set of System Verilog User VIP User
UUT
Prof.
Data
(Block or Sub-system) AXI Monitor
modules that enable
faster and higher AXI Slave
Interface
AXI Master
Interface
User IP
AXI Master
quality verification of
AXI based IP.

 Performance
Exploration
 For SoC architects, HW
and Verification
Engineers. AXI based
SoC performance can
be explored and verified.

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AVIP Features for RTL Simulation
 Protocol IEEE 1800 SystemVerilog Testbench

Checkers
AXI Slave AXI Master

 OVL and SVA AXI Master Interface Interface AXI Slave

assertion libraries
provided for AXI
User VIP User
UUT
(Block or Sub-system) AXI Monitor

protocol checking. AXI Slave AXI Master

User IP
Interface Interface
AXI Master

 AXI Protocol
Coverage
 Channel level,
transaction level and
sequence level pre-
defined coverage points
for AXI protocol
coverage.

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AMBA Designer + AVIP: RTL Design Flow
 To optimise interconnect and memory Configuration
Configuration
architecture ARM recommends the Integration
Integration
following flow:
Simulation
 Configuration Simulation

 Set the correct parameters and check Analysis

Analysis
the components
 Integration
 Assemble the sub-system and statically
check the design
 Simulation
 Run test scenarios to check usage
modes
 Analysis
 Check results and loop back

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Fabric Design Tools: What is AVIP?
IEEE 1800 SystemVerilog Testbench

AXI Slave AXI Master

Interface Interface
AXI Master AXI Slave

User VIP User UUT AXI Monitor

(Block or Sub-system)

AXI Slave AXI Master

User IP
Interface Interface
AXI Master

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Fabric Design Tools: What is AVIP?
 It enables System Exploration at RTL level
 TTT = Time to tweak = 20s
 TTS = Time to simulate = 5 mins

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System Exploration Methods
SoC, static
Spreadsheet
Analysis

Block-level, Internal bus, RTL simulation

RTL simulation, AVIP, User VIP

Industry standards VIP

SoC, Real Stimulus, external I/F

Acceleration/Emulation
VIP, Logic Tiles, SW

Real-time Behavior

Silicon/Applications

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Iteration time vs Realism
LOW Mathematical LOW
Spreadsheet formula, not
mins/hrs
Static analysis dynamic

Statistical or

Realistic behaviour
mins/hrs AVIP recorded traffic
Internal bus simulation
profiles
Cycle time

Adding S/W,
SoC + s/w
days/wks external I/F with
Emulation/proto
realistic scenarios

Observe
Silicon + Appl actual
mths/yrs
CoreSight™ behaviour
HIGH HIGH

AVIP: the iteration time of a spreadsheet with the accuracy approaching RTL simulation

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ARM Design Flow for Digital Highway
 Design Your Intelligent Digital Highway

 Configure and connect your RTL

AMBA Designer
 Verification & performance exploration in simulation
AVIP
 Improve your software
CoreSight
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Improve the Performance of Your SoC
 Analyzing real silicon performance enables you to
confidently improve the next design
 If you want to find out how a car really performs, drive it
 CoreSight Design Kit & Performance Profiling
 Provide accurate, real-time ‘telemetry’ from your system
 Essential tools for delivering system performance improvements
 Your SoC may be optimized, but is the software?
 ARM Profiler analyzes system performance, enabling optimization via
Profile Driven Compilation

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CoreSight Debug & Trace
 The Debug & Trace Architecture for the Digital World
 Open Standard available on www.arm.com
 Optimise software productivity
on your multi-core SoC
 SW Debug
 SW Performance
Optimisation
 SoC Performance
optimisation
 Visibility and trace of the
whole SoC
 ARM trace and performance sources (ETM, PTM, Interconnect)
 Leverage CoreSight architecture for YOUR IP

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ARM Digital Highway
 ARM Digital Highway technology
delivers to YOU

 Key Soft IP and Physical IP elements

 The de-facto communication standard

 Tools to analyze and optimize your system

design before committing to silicon AVIP
 Solution to debug and optimise once your
silicon has been manufactured

 Faster time to revenue through reducing design effort and

ensuring quality of results

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