Vlsi Lab Manual

LAB MANUAL
ON
ES / VLSI LAB
IV B.TECH I SEMESTER ECE
(JNTUA-R13)
Verified and Compiled by:
Dr. V. THRIMURTHULU, M.E, Ph.D., MISTE, MIETE

Professor, Dept. of ECE
Mr. S. VAMSEE KRISHNA, M.Tech., (Ph.D) Mr. K. PURNA CHANDRA RAO,M.Tech

Associate Professor, Dept. of ECE Assistant Professor, Dept. of ECE
DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING
CHADALAWADA RAMANAMMA ENGINEERING COLLEGE

CHADALAWADA NAGAR, RENIGUNTA ROAD, TIRUPATI (A.P) – 517506
VLSI & EMBEDDED SYSTEMS LABORATORY
LIST OF EXPERIMENTS
VLSI LAB
Target Device Specifications, Simulation, Synthesis, Generating RTL Schematic, Technology Map,
Synthesis report & Design Summary of
1. Realization of Logic Gates.

2. 3- to - 8Decoder- 74138.
3. 8 x 1 Multiplexer-74151 and 2 x 4 De-multiplexer-74155.
4. 4-Bit Comparator-7485.
5. D Flip-Flop-7474.
6. Decade counter-7490.
7. Shift registers-7495.
8. ALU Design.
EMBEDDED SYSTEMS LAB
1. Configuring MSP-EXP430G2 Launch pad digital I/O pins.

2. Configuring the MSP-EXP430G2 Launch pad for Low Power Mode (LPM3).
3. Learning and understanding GPIO based Interrupt programming.
4. Learning and understanding how to configure the PWM and ADC modules.
5. Understanding the ULP Advisor capabilities.
6. Understanding and Configuring 2 MSP430F5529 Launch pads.
7. A basic Wi-Fi application.
8. Understanding Energy Trace Technology analysis tool.
# Open Xilinx Project Navigator.
# Create new project.
# Specify device properties.

# Add new source to the project.
# Select source type [VHDL or Verilog].

# Specify input and output port names.
# New source summary window will appear as shown below.

# Enter program code in the HDL editor window.
# Save the program and synthesize the process.
# The design summary window after synthesis appears as shown below.

# Create another new source.
# Select source type as Test bench wave form.

# Associate the test bench to the source.
# Test bench wave form summary window will appear as shown below.
# Assign clock and timing details.
# Give the input waveforms for the source.

# Save the input waveforms and perform behavioral simulation.
# The simulated output waveforms window will be as shown below.
# Dumping process:
# Assign pin numbers to input and output ports.

# Select JTAG clock in the startup options of process properties by
right clicking on ‘Generate programming file.
# Select configure device using Boundary scan in the impact window.

# Generate ‘programming file generation report’.
# Select the generated bit file.
# Xilinx boundary scan window will appear as shown below.

# Select the program by right clicking on Xilinx component.
# The programming properties window will appear as shown below.

# After successful dumping the program succeeded window will appear as shown
below.
EXP.NO: 1(A)
DESIGN AND IMPLEMENTATION OF
DATE: 01/07/2011 HALF ADDER USING VHDL & VERILOG
AIM: To write a VHDL & Verilog code for half adder and to generate synthesis report,
RTL schematic and to implement design using FPGA.
SOFTWARE REQIURED:
 Xilinx ISE 9.1i
HARDWARE REQUIRED:
 SPARTAN – 3E XC3S500E KIT
PROCEDURE:
1. Open Xilinx ISE 9.1i.

2. Create a new source file in a new project with suitable name.
3. Create the file in VHDL/Verilog module.
4. Select the appropriate input and output ports according to the
requirements.
5. Type the program and save it.
6. Select Synthesize XST, check for syntax errors and generate report and RTL
schematic.
7. In the process window, go to ‘user constraints’ and select ‘assign package
pins’ and after that double click on ‘implement design’.
8. Select properties by right clicking on ‘generate programming file’. Select
‘JTAG’ clock in startup options.
9. Select boundary scan in ‘impact window’ after double clicking on ‘configure
device’.
10. In ‘generate programming file’ double clicking on ‘programming file

generation report. Bit file will be generated.
11. Xilinx boundary scan window will appear when the bit file is selected. Right
click on Xilinx component and select program.
12. Programming properties will appear and finally program will be succeeded.
13. Thus the program can be dumped into FPGA kit and finally output can be
seen on the kit.
PROGRAM (IN VHDL):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity halfadder is
Port (a: in STD_LOGIC;
b: in STD_LOGIC;
sum: out STD_LOGIC;
carry: out STD_LOGIC);
end halfadder;
architecture Behavioral of halfadder is
begin
sum<= a xor b;
carry<= a and b;
end Behavioral;
PROGRAM (IN Verilog):
module halfadderveri (a, b, sum, carry);

input a;
input b;
output sum;
output carry;
xor (sum,a,b);
and (carry,a,b);
endmodule
BLOCK DIAGRAM:
TRUTH TABLE:
Inputs Outputs
a b sum carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
DEVICE UTILIZATION SUMMARY:
Number of Slices : 1 out of 4656 0%

Number of 4 input LUTs : 2 out of 9312 0%
Number of I/Os : 4
Number of bonded IOBs : 4 out of 232 1%
RTL SCHEMATIC:
TECHNOLOGY SCHEMATIC:
SIMULATED OUTPUT WAVEFORMS:

RESULT: Thus the VHDL/Verilog code for half adder is verified, synthesis report is
generated and the design is implemented using FPGA.
EXP.NO: 1(B) DESIGN AND IMPLEMENTATION OF

HALF SUBTRACTOR USING VHDL &
DATE: 01/07/2011 VERILOG
AIM: To write a VHDL/Verilog code for half subtractor and to generate synthesis
report, RTL schematic and to implement design using FPGA.
SOFTWARE REQIURED:
 Xilinx ISE 9.1i
HARDWARE REQUIRED:
PROCEDURE:

requirements.
schematic.
device’.
seen on the kit.
PROGRAM (IN VHDL):

library IEEE;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity halfsubtractor is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
diff : out STD_LOGIC;
borr : out STD_LOGIC);
end halfsubtractor;
architecture Behavioral of halfsubtractor is
begin
diff <= a xor b;
borr <= (not a) and b;
end Behavioral;
module halfsubtractorveri(a, b, x1, diff, borrow);

input a;
input b;
inout x1;
output diff;
output borrow;
xor (diff,a,b);
not(x1,a);
and(borrow,x1,b);
endmodule
BLOCK DIAGRAM:
TRUTH TABLE:
Inputs Outputs
a b diff borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Number of I/Os : 4
RTL SCHEMATIC:

RESULT: Thus the VHDL/Verilog code for half subtractor is verified, synthesis report
is generated and the design is implemented using FPGA.
EXP.NO: 2(A)
DATE: 08/07/2011 FULL ADDER USING VHDL & VERILOG
AIM: To write a VHDL/Verilog code for full adder and to generate synthesis report,
SOFTWARE REQIURED:
 Xilinx ISE 9.1i
HARDWARE REQUIRED:
PROCEDURE:

requirements.
schematic.
device’.
seen on the kit.
PROGRAM (IN VHDL):
library IEEE;
--library UNISIM;
entity fulladder is
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end fulladder;
architecture Behavioral of fulladder is
begin
sum <= a xor b xor c;
carry <= (a and b) or (a and c) or (b and c);
end Behavioral;
module fulladder(a, b, c, x1, x2, x3, sum, carry);
input a;
input b;
input c;
inout x1;
inout x2;
inout x3;
output sum;
output carry;
xor(sum,a,b,c);
and(x1,a,b);
and(x2,b,c);
and(x3,a,c);
or(carry,x1,x2,x3);
endmodule
BLOCK DIAGRAM:
TRUTH TABLE:
Inputs Outputs
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Number of I/Os : 5
RTL SCHEMATIC:

RESULT: Thus the VHDL/Verilog code for full adder is verified, synthesis report is

FULL SUBTRACTOR USING VHDL &
DATE: 08/07/2011 VERILOG
AIM: To write a VHDL/Verilog code for full subtractor and to generate synthesis
report, RTL schematic and implement design using FPGA.
SOFTWARE REQIURED:
 Xilinx ISE 9.1i
HARDWARE REQUIRED:
PROCEDURE:

requirements.
schematic.
device’.

seen on the kit.
PROGRAM (IN VHDL):
library IEEE;
--library UNISIM;
entity fullsubtractor is
b : in STD_LOGIC;
borrin : in STD_LOGIC;
borrout : out STD_LOGIC;
diff : out STD_LOGIC);
end fullsubtractor;
architecture Behavioral of fullsubtractor is
begin
diff <= a xor b xor borrin;
borrout <= ((not a) and (borrin or b)) or (b and borrin);
end Behavioral;
module fullsubtract(a, b, c, x1, x2, x3, x4, diff, borrow);

input a;
input b;
input c;
inout x1;
inout x2;
inout x3;
inout x4;
output diff;
output borrow;
xor(diff,a,b,c);
not(x1,a);
and(x2,x1,b);
and(x3,b,c);
and(x4,x1,c);
or(borrow,x2,x3,x4);
endmodule
BLOCK DIAGRAM:
TRUTH TABLE:
INPUTS OUTPUTS
A B Borrin Diff Borrout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Number of I/Os : 5
RTL SCHEMATIC:

RESULT: Thus the VHDL/Verilog code for Full subtractor is verified, synthesis report
EXP.NO: 3(A)
DATE: 15/07/2011 ENCODER USING VHDL & VERILOG
AIM: To write a VHDL/Verilog code for 4:2 encoder and to generate synthesis report,
SOFTWARE REQIURED:
 Xilinx ISE 9.1i
HARDWARE REQUIRED:
PROCEDURE:

requirements.
schematic.
device’.

seen on the kit.
PROGRAM (IN VHDL):
library IEEE;
--library UNISIM;
entity encode is
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
x : out STD_LOGIC;
y : out STD_LOGIC);
end encode;
architecture Behavioral of encode is
begin
x <= c or d;
y <= d or b;
end Behavioral;
PROGRAM (IN VERILOG):
module encoderveri(I, Y);

input [3:0] I;
output [1:0] Y;
reg Y;
always @(I)
begin
case(I)
4'b1000:Y=2'b00;
4'b0100:Y=2'b01;
4'b0010:Y=2'b10;
4'b0001:Y=2'b11;
endcase
end
endmodule
BLOCK DIAGRAM:
TRUTH TABLE:
Inputs Outputs
A B C D X Y
1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1

Number of I/Os : 6
RTL SCHEMATIC:
RESULT: Thus the VHDL/Verilog code for 4:2 encoder is verified, synthesis report is
EXP.NO: 3(B)
DATE: 15/07/2011 DECODER USING VHDL & VERILOG
AIM: To write a VHDL/Verilog code for 2:4 decoder and to generate synthesis report,
SOFTWARE REQIURED:
 Xilinx ISE 9.1i
HARDWARE REQUIRED:
PROCEDURE:

requirements.
schematic.
device’.

seen on the kit.
PROGRAM (IN VHDL):
library IEEE;
--library UNISIM;
entity decoder is
b : in STD_LOGIC;
e : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0));
end decoder;
architecture Behavioral of decoder is
begin
process(a,b,e)
begin
if(e='1')then
if(a='0' and b='0')then
y<="1000";
elsif(a='1' and b='0')then
y<="0100";
y<="0010";
y<="0001";
end if;
else
y<="0000";
end if;
end process;
end Behavioral;
module decoderveri(I, Y);

input [1:0] I;
output [3:0] Y;
reg Y;
always @(I)
begin
case(I)
2'b00:Y=4'b1000;
2'b01:Y=4'b0100;
2'b10:Y=4'b0010;
2'b11:Y=4'b0001;
endcase
end
endmodule
BLOCK DIAGRAM:
TRUTH TABLE:
Inputs Outputs
A B Y1 Y2 Y3 Y4
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

Number of Slice Flip Flops : 4 out of 9312 0%
Number of IOs :7
IOB Flip Flops :4
Number of GCLKs : 1 out of 24 4%
RTL SCHEMATIC:

RESULT: Thus the VHDL/Verilog code for 2:4 decoder is verified, synthesis report is
EXP.NO: 4(A)
DATE: 22/07/2011 MULTIPLEXER USING VHDL & VERILOG
AIM: To write a VHDL/Verilog code for 2:1 multiplexer and to generate synthesis
SOFTWARE REQIURED:
 Xilinx ISE 9.1i
HARDWARE REQUIRED:
PROCEDURE:

requirements.
6. Select Synthesize XST, check for syntax errors and generate report and
RTL schematic.
device’.
seen on the kit.
PROGRAM (IN VHDL):
library IEEE;

--library UNISIM;
entity multiplexer is
b : in STD_LOGIC;
s : in STD_LOGIC;
y : out STD_LOGIC);
end multiplexer;
architecture Behavioral of multiplexer is
begin
process(a,b,s)
begin
if(s='0')then
y<=a;
else
y<=b;
end if;
end process;
end Behavioral;
module multiplexer(a, b, s, y);

input a;
input b;
input s;
output y;
reg y;
always @ (s)
begin
case (s)
1'b0:y=a;
1'b1:y=b;
endcase
end
endmodule
BLOCK DIAGRAM:
TRUTH TABLE:
Inputs Output
A B S Y
0 0 0 0
0 1 1 1
1 0 0 1
1 1 1 1

Number of IOs :4
RTL SCHEMATIC:
RESULT: Thus the VHDL/Verilog code for 2:1 multiplexer is verified, synthesis report

DEMULTIPLEXER USING VHDL &
DATE: 22/07/2011
VERILOG
AIM: To write a VHDL/Verilog code for 1:2 demultiplexer and to generate synthesis
SOFTWARE REQIURED:
 Xilinx ISE 9.1i
HARDWARE REQUIRED:
PROCEDURE:

requirements.
RTL schematic.
device’.
seen on the kit.
PROGRAM (IN VHDL):
library IEEE;

--library UNISIM;
entity demux is
s : in STD_LOGIC;
y1 : out STD_LOGIC;
y2 : out STD_LOGIC);
end demux;
architecture Behavioral of demux is
begin
y1<=(a and (not s));
y2<= (a and s);
end Behavioral;
module demultiplexer(a, sel, y);

input a;
input sel;
output [1:0] y;
reg y;
always @ (sel)
begin
case(sel)
1'b0:y=2'b01;
1'b1:y=2'b10;
endcase
end
endmodule
BLOCK DIAGRAM:
TRUTH TABLE:
Inputs Outputs
A S Y1 Y2
0 0 1 0
0 1 0 1

Number of IOs :4
RTL SCHEMATIC:

RESULT: Thus the VHDL/Verilog code for 1:2 demultiplexer is verified, synthesis
report is generated and the design is implemented using FPGA.
EXP.NO: 5(A)
DATE: 29/07/2011 D – FLIP FLOP USING VHDL & VERILOG
AIM: To write a VHDL/Verilog code for D-flip flop and to generate synthesis report,
SOFTWARE REQIURED:
 Xilinx ISE 9.1i
HARDWARE REQUIRED:
PROCEDURE:

requirements.
RTL schematic.
device’.
seen on the kit.
PROGRAM (IN VHDL):
library IEEE;

--library UNISIM;
entity dflipflop is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
q : inout STD_LOGIC:='0';
qbar : inout STD_LOGIC:='1');
end dflipflop;
architecture Behavioral of dflipflop is
begin
process(d,clk,q,qbar)
begin
if(clk='1' and clk'event)then
if d='1' then
q<='1';
qbar<='0';
else
q<='0';
qbar<='1';
end if;
else
q<=q;
qbar<=qbar;
end if;
end process;
end Behavioral;
module dflipflop(d, rst, clk, q);

input d;
input rst;
input clk;
output q;
reg q;
always @ (posedge(clk) or posedge(rst))
if(rst==1'b1)
q=1'b0;
else
q=d;
endmodule
BLOCK DIAGRAM:
TRUTH TABLE:
Inputs Outputs
State
clk D Q
0 X Q0 No change
1 0 0 RESET
1 1 1 SET

Number of IOs :4
IOB Flip Flops :2
RTL SCHEMATIC:
RESULT: Thus the VHDL/Verilog code for D-flipflop is verified, synthesis report is
EXP.NO: 5(B)
DATE: 29/07/2011 RS – FLIP FLOP USING VHDL & VERILOG
AIM: To write a VHDL/Verilog code for RS-flip flop and to generate synthesis report,
SOFTWARE REQIURED:
 Xilinx ISE 9.1i
HARDWARE REQUIRED:
PROCEDURE:

requirements.
RTL schematic.
device’.

seen on the kit.
PROGRAM (IN VHDL):
library IEEE;
--library UNISIM;
entity rsflipflop is
Port ( s : in STD_LOGIC;
r : in STD_LOGIC;
clk : in STD_LOGIC;
q : inout STD_LOGIC:='0';
qbar : inout STD_LOGIC:='1');
end rsflipflop;
architecture Behavioral of rsflipflop is
begin
process(r,s,clk,q,qbar)
begin
if(r='0' and s='0')then
q<=q;
qbar<=qbar;
elsif(r='0' and s='1')then
q<='1';
qbar<='0';
q<='0';
qbar<='1';
q<='X';
qbar<='X';
end if;
end if;
end process;
end Behavioral;
module rsflipflop(s, r, clk, rst, q, qbar);

input s;
input r;
input clk;
input rst;
output q;
output qbar;
reg q,qbar;
always @ (posedge(clk) or posedge(rst))
if(rst==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
else
if(s==1'b0 && r==1'b0)
begin
q=q;
qbar=qbar;
end
else if(s==1'b0 &&r==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
else if(s==1'b1 && r==1'b0)
begin
q=1'b1;
qbar=1'b0;
end
else
begin
q=1'b0;
qbar=1'b1;
end
endmodule
BLOCK DIAGRAM:
TRUTH TABLE:
Inputs Outputs
DEVICE State UTILIZATION
SUMMARY: R S Q Q’
0 0 NC NC No change Number of Slices

: 2 out of 4656 0%
0 1 1 0 RESET Number of Slice Flip
Flops : 2 out of 9312
1 0 0 1 SET
0%
1 1 − − FORBIDDEN Number of 4 input
LUTs : 3 out of 9312 0%
Number of IOs :5
IOB Flip Flops :2
RTL SCHEMATIC:
RESULT: Thus the VHDL/Verilog code for RS-flipflop is verified, synthesis report is
EXP.NO: 6(A)
DATE: 05/08/2011 UP COUNTER USING VHDL & VERILOG
AIM: To write a VHDL/Verilog code for up counter and to generate synthesis report,
SOFTWARE REQIURED:
 Xilinx ISE 9.1i
HARDWARE REQUIRED:
PROCEDURE:

requirements.
RTL schematic.
device’.

seen on the kit.
PROGRAM (IN VHDL):
library IEEE;

--library UNISIM;
entity upcounter is
Port ( clk : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0):="0000");
end upcounter;
architecture Behavioral of upcounter is
begin
process(clk,q)
begin
if(clk='1'and clk'event)then
if(q="1111")then
q<="0000";
else
q<= q+1;
end if;
end if;
end process;
end Behavioral;

module up_counter(c, clr, q, tmp);
input c;
input clr;
output [3:0] q;
output [3:0] tmp;
reg[3:0]tmp;
always @ (posedge (c) or posedge (clr))
begin
if(clr)
tmp=4'b0000;
else
tmp=tmp+1'b1;
end
assign q=tmp;
endmodule Flip flop outputs

Clock
pulse Q3 Q2 Q1 Q0
0 0 0 0 0
BLOCK DIAGRAM:
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
TRUTH TABLE:
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

Number of IOs :5
RTL SCHEMATIC:

RESULT: Thus the VHDL/Verilog code for up counter is verified, synthesis report is

DOWN COUNTER USING VHDL &
DATE: 05/08/2011
VERILOG
AIM: To write a VHDL/Verilog code for down counter and to generate synthesis
SOFTWARE REQIURED:
 Xilinx ISE 9.1i
HARDWARE REQUIRED:
PROCEDURE:

requirements.
RTL schematic.
device’.

11. Xilinx boundary scan window will appear when the bit file is selected.
Right click on Xilinx component and select program.
seen on the kit.
PROGRAM (IN VHDL):
library IEEE;

--library UNISIM;
entity douncounter is
Port ( clk : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0):="1111");
end douncounter;
architecture Behavioral of douncounter is
begin
process(clk,q)
begin
if(q="0000")then
q<="1111";
else
q<=q-1;
end if;
end if;
end process;
end Behavioral;
module downcounter(c, s, q, tmp);

input c;
input s;
output [3:0] q;
output [3:0] tmp;
reg [3:0] tmp;
always @ (posedge c)
begin
if(s)
tmp=4'b1111;
else
tmp=tmp-1'b1;
end
assign q=tmp;
endmodule
BLOCK DIAGRAM:
TRUTH TABLE:
Flip flop outputs

Clock
pulse Q3 Q2 Q1 Q0
0 0 0 0 0
1 1 1 1 1
2 1 1 1 0
3 1 1 0 1
4 1 1 0 0
5 1 0 1 1
6 1 0 1 0
7 1 0 0 1
8 1 0 0 0
9 0 1 1 1
10 0 1 1 0
11 0 1 0 1
12 0 1 0 0
13 0 0 1 1
14 0 0 1 0
15 0 0 0 1

Number of IOs :5
RTL SCHEMATIC:

RESULT: Thus the VHDL/Verilog code for down counter is verified, synthesis report
EXP.NO: 7(A) DESIGN AND IMPLEMENTATION OF

SERIAL IN SERIAL OUT SHIFT
DATE: 19/08/2011 REGISTER USING VHDL & VERILOG
AIM: To write a VHDL/Verilog code for serial in serial out shift register and to
generate synthesis report, RTL schematic and to implement design using FPGA.
SOFTWARE REQIURED:
 Xilinx ISE 9.1i
HARDWARE REQUIRED:
PROCEDURE:
requirements.
RTL schematic.
device’.

seen on the kit.
PROGRAM (IN VHDL):
library IEEE;

--library UNISIM;
entity sisoregister is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q4 : out STD_LOGIC);
end sisoregister;
architecture Behavioral of sisoregister is
signal q1,q2,q3:std_logic;
component dff
port(d,clk,reset:std_logic;
q:out std_logic);
end component;
begin
y1:dff port map (d,clk,reset,q1);
y2:dff port map (q1,clk,reset,q2);
end Behavioral;
library IEEE;
entity dff is
port(d:in std_logic;
clk:in std_logic;
reset:in std_logic;
q:out std_logic);
end dff;
architecture behavioral of dff is

begin
process(d,clk,reset)
begin
if(reset='1')then
q<='0';
elsif(clk='1' and clk'event)then
q<=d;
end if;
end process;
end behavioral;
module siso(clk, rst, a, b, c, d, e);

input clk;
input rst;
output a;
output b;
output c;
output d;
input e;
reg a,b,c,d;
always @ (posedge (clk) or posedge (rst))
if(rst)
begin
a<=0;
b<=0;
c<=0;
d<=0;
end
else
begin
a<=b;
b<=c;
c<=d;
d<=e;
end
endmodule
BLOCK DIAGRAM:

Number of IOs :4
RTL SCHEMATIC:
RESULT: Thus the VHDL/Verilog code for serial in serial out shift register is verified,
synthesis report is generated and the design is implemented using FPGA.

PARALLEL IN PARALLEL OUT SHIFT
DATE: 19/08/2011 REGISTER USING VHDL & VERILOG
AIM: To write a VHDL/Verilog code for parallel in parallel out shift register and to
generate synthesis report, RTL schematic and to implement design using FPGA.
SOFTWARE REQIURED:
 Xilinx ISE 9.1i
HARDWARE REQUIRED:
PROCEDURE:

requirements.
RTL schematic.
device’.

seen on the kit.
PROGRAM (IN VHDL):
library IEEE;

--library UNISIM;
entity piporegister is
Port ( d : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end piporegister;
architecture Behavioral of piporegister is

component dff
port (d,clk,rst:in std_logic;
q:out std_logic);
end component;
begin
y1: dff port map (d(0),clk,rst,q(0));
end behavioral;
library IEEE;
entity dff is
port (d:in std_logic;
clk:in std_logic;
rst:in std_logic;
q:out std_logic);
end dff;
architecture behavioral of dff is
begin
process(d,clk,rst)
begin
if(rst='1')then
q<='0';
elsif(clk='1' and clk'event)then
q<=d;
end if;
end process;
end Behavioral;
module pipo(din, dout, clk, rst);

input [3:0] din;
output [3:0] dout;
input clk;
input rst;
wire clk,rst;
wire [3:0]din;
reg[3:0]dout;
always @ (posedge (clk) or negedge (rst))
begin
if(!rst)
begin
dout<=4'b0;
end
else
begin
dout<=din;
end
end
endmodule
BLOCK DIAGRAM:
DEVICE UTILIZATION SUMMARTY:

Number of IOs : 10
IOB Flip Flops :4
RTL SCHEMATIC:

RESULT: Thus the VHDL/Verilog code for parallel in parallel out shift register is
verified, synthesis report is generated and the design is implemented using FPGA.

Vlsi Lab Manual

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LAB MANUAL

Verified and Compiled by:

Dr. V. THRIMURTHULU, M.E, Ph.D., MISTE, MIETE

Mr. S. VAMSEE KRISHNA, M.Tech., (Ph.D) Mr. K. PURNA CHANDRA RAO,M.Tech

DEPARTMENT OF ELECTRONICS & COMMUNICATION

CHADALAWADA RAMANAMMA ENGINEERING COLLEGE

1. Realization of Logic Gates.

EMBEDDED SYSTEMS LAB

1. Configuring MSP-EXP430G2 Launch pad digital I/O pins.

# Create new project.

# Specify device properties.

# Select source type [VHDL or Verilog].

# New source summary window will appear as shown below.

# Save the program and synthesize the process.

# The design summary window after synthesis appears as shown below.

# Select source type as Test bench wave form.

# Give the input waveforms for the source.

# The simulated output waveforms window will be as shown below.

# Assign pin numbers to input and output ports.

# Select configure device using Boundary scan in the impact window.

# Select the generated bit file.

# Xilinx boundary scan window will appear as shown below.

# The programming properties window will appear as shown below.

 Xilinx ISE 9.1i

 SPARTAN – 3E XC3S500E KIT

1. Open Xilinx ISE 9.1i.

10. In ‘generate programming file’ double clicking on ‘programming file

PROGRAM (IN VHDL):

PROGRAM (IN Verilog):

module halfadderveri (a, b, sum, carry);

DEVICE UTILIZATION SUMMARY:

Number of Slices : 1 out of 4656 0%

SIMULATED OUTPUT WAVEFORMS:

EXP.NO: 1(B) DESIGN AND IMPLEMENTATION OF

 Xilinx ISE 9.1i

 SPARTAN – 3E XC3S500E KIT

1. Open Xilinx ISE 9.1i.

PROGRAM (IN VHDL):

PROGRAM (IN Verilog):

module halfsubtractorveri(a, b, x1, diff, borrow);

DEVICE UTILIZATION SUMMARY:

Number of Slices : 1 out of 4656 0%

SIMULATED OUTPUT WAVEFORMS:

 Xilinx ISE 9.1i

 SPARTAN – 3E XC3S500E KIT

1. Open Xilinx ISE 9.1i.

PROGRAM (IN VHDL):

PROGRAM (IN Verilog):

module fulladder(a, b, c, x1, x2, x3, sum, carry);

DEVICE UTILIZATION SUMMARY:

Number of Slices : 1 out of 4656 0%

SIMULATED OUTPUT WAVEFORMS:

EXP.NO: 2(B) DESIGN AND IMPLEMENTATION OF

 Xilinx ISE 9.1i

 SPARTAN – 3E XC3S500E KIT

1. Open Xilinx ISE 9.1i.

10. In ‘generate programming file’ double clicking on ‘programming file

PROGRAM (IN VHDL):

PROGRAM (IN Verilog):

module fullsubtract(a, b, c, x1, x2, x3, x4, diff, borrow);

A B Borrin Diff Borrout

DEVICE UTILIZATION SUMMARY:

Number of Slices : 1 out of 4656 0%

SIMULATED OUTPUT WAVEFORMS: