This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2499784, IEEE
Transactions on Power Electronics

Decoding and Synthesizing Transformerless PWM Converters

Abstract—PWM converters have been widely applied for power processing and they are typically the stems of other
types of converters, such as quasi-resonant, Z-source and switched-inductor hybrid converters. Development of
PWM converters has been spanning over a century, starting from the buck converter. The well-known PWM con-
verters include buck, boost, buck-boost, Ćuk, SEPIC, Zeta, Z-source, quasi-Z source, etc. Many attempts have been
proposed to develop these converters based mostly on canonical cell concepts and by introducing extra LC filters to
the cells. This paper presents an enhancement to the layer and graft schemes by introducing the ideas of dc volt-
age/current offsetting, capacitor/inductor component splitting, diode grafting and inverse operation of PWM con-
verters. The PWM converters, which can be operated in CCM or DCM, therefore can be synthesized systematically
according to decoded transfer gains. Decoding and synthesizing PWM converters uniquely bridges transfer gains to
converter topologies, and provides readers a comprehensive understanding of PWM-converter evolution from the
original converter, the buck converter. Additionally, in this paper, the Ćuk, SEPIC, and Zeta converters all with the
same transfer gain of D/(1-D) are proved to be equivalent to the buck-boost converter with an extra LC filter. For
further illustrating the proposed approaches, various types of Z-source converters,
switched-capacitor/switched-inductor hybrid converters and a single-stage interleaved converter are reviewed, and
new PWM converters are developed.

Keywords—PWM converter, Z-source converter, layer scheme, graft scheme, and switched-capacitor/switched-inductor
hybrid converter.
I. Introduction
PWM converters and their derived have woven the power electronics field over almost the entire 20 th century for their
straightforward operational principle, analysis, design and control. In the 21st century, they still play the key role in power
processing due to the advance in switching and magnetic devices, and the state-of-the-art fabrication skills. Development of
PWM converters is always an on-going hot topic. Researchers’ contributions have driven the power electronics further into
the leading character in electrical engineering field.
Power transfer between inductors and capacitors is in resonant manner and theoretically has no loss. Its input-to-output
transfer gain can be effectively controlled with pulse-width modulation (PWM) when the switching frequency is much
higher than the resonant frequency of the inductor-capacitor network. The buck converter is the most well-known and the
earliest developed converter applying this concept. Based on the buck converter and its related cells, many researchers have
devoted themselves to investigating topological properties, synthesis methods and basic characteristics of the PWM
converters and their derived [1]-[33]. In the earlier research [1], [2], [4]-[7], the efforts went to finding the topological
relationship among the six PWM converters, including buck, boost, buck-boost, Ćuk, SEPIC and Zeta, and analyzing their
static and dynamic properties. By inserting dc transformers into buck and boost converters [3], many isolated PWM
converters have been developed, such as flyback, forward, push-pull, half-bridge, full-bridge, TRW, IBM, Weinberg, Clarke,
etc. Introducing resonant cells into the non-isolated and isolated PWM converters has yielded many sets of quasi-resonant
and multi-resonant converters [8], [9]. The tree theory has been adopted to interpret the PWM converter topology to find the
relationship among the converters and then to develop new PWM converters [9], [11], [19]. In general, the aforementioned
synthesis approaches were based primarily on arranging component connection, instead of the manipulation of transfer
gains and converters. Thus, their developments of new PWM converters are at component or cell level, but not at converter
level. Based on the buck converter and the duality principle [1], two unified approaches, layer and graft schemes [13], [14],
were proposed to develop PWM converters according to transfer gains and at converter level, which have laid out a firm
foundation for decoding and synthesizing PWM converters. Other similar approaches to deriving buck-boost and Ćuk
converters based on transfer gains and at converter level can be found in [20], [21].
Recently, new PWM converters and inverters were developed, such as voltage-fed Z-source, current-fed Z-source and
quasi-Z-source converters [27]-[30], [32], [33], and they were successfully adopted for various applications [34]-[41].
Moreover, the author [26], [31] introduced canonical switching cells for generating and analyzing more PWM converters. In
[42], switched-capacitor and switched-inductor were deliberately introduced to the six PWM converters to generate hybrid
dc/dc converters which can achieve higher step-down or step-up conversion. Their derivation or generation concepts were
still based on cell level and by introducing extra LC filter to the fundamental converters. Some of the so-called new
converters were derived by changing the dc-offset voltages of capacitors and/or the dc-offset currents of inductors. From
power conversion point of view, the converters even with different dc-offset values on components are just equivalent since
their transfer gains are identical.
This paper presents an enhancement to the layer and graft schemes by introducing the ideas of dc voltage/current
offsetting, capacitor/inductor component splitting, diode grafting and inverse operation of PWM converters. The PWM
converters, which can be operated in continuous conduction mode (CCM) or discontinuous conduction mode (DCM),
therefore can be synthesized systematically according to decoded transfer gains. Given the original converter, buck
converter, and its input-to-output voltage transfer gain, we expect that all of the rest of transformerless PWM converters can
be derived systematically. By inserting dc transformers into the converters, the isolated PWM converters can be readily
1

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Transactions on Power Electronics

evolved or derived as well [3]. Conventionally, the converters were developed first and their transfer gains were derived
based on volt-second balance principle. Unlike the conventional approaches, the proposed is that the codes or transfer gains
are factorized or decoded first and certain converters derived from the buck converter are used to synthesize the factorized
codes. This approach uniquely bridges transfer gains to converter topologies, and provides readers a comprehensive
understanding of PWM-converter evolution from the original converter. Additionally, in this paper, the Ćuk, SEPIC, and
Zeta converters all with the same transfer gain of D/(1-D) are proved to be equivalent to the buck-boost converter with an
extra LC filter. For further illustrating the proposed approaches, various types of Z-source converters, switched-capacitor or
switched-inductor hybrid converters, and a single-stage interleaved converter are reviewed, and new PWM converters are
developed.
In section II, some fundamentals used in decoding and synthesizing PWM converters are introduced. Section III pre-
sents the principle of decoding and synthesizing PWM converters. Section IV presents the evolution and derivation of sev-
eral well-known transformerless PWM converters with the proposed approaches, and section V presents synthesized new
PWM converters by combining layer and graft schemes and by taking feedback from various ports. Summary, discussion
and future study of the proposed approaches are addressed in section VI.
II. Some Fundamentals
Layer and graft schemes have laid out a firm foundation for decoding and synthesizing PWM converters. This section
presents some fundamentals to enhance these two schemes, which can further develop more variety of PWM converters.
The fundamentals include dc voltage/current offsetting, capacitor/inductor component splitting, diode grafting and deriva-
tion of three fundamental PWM converters in CCM, DCM and inverse operations.
Power transfer between energy storage elements, capacitor and inductor, has three types of configurations, as shown in
Fig. 1. The two types shown in Fig. 1(a) and 1(b) will result in electrical energy loss up to half the initially stored energy
when turning on switch S1 and under the condition of capacitance C1 = C2 or inductance L1 = L2. To conserve the total elec-
trical energy during power transfer, the only configuration is shown in Fig. 1(c) where the power transfer is from capacitor
to inductor or vice versa and it is conducted in resonant manner. A practical example applying this configuration is shown in
Fig. 2, in which Fig. 2(a) shows a current output and Fig. 2(b) shows a voltage one. With the free-wheeling diode D1, the
converter shown in Fig. 2(b) can be operated with PWM to tune its input-to-output transfer gain. After decoding and synthe-
sizing the PWM converters, we will recognize that this converter, buck converter, is considered the original converter for
realizing the codes or transfer gains.
S1 S1 S1

C1 C2 L1 L2 C1 L1

(a)lossy (b)lossy (c)lossless

Fig. 1. Three types of configurations of power transfer between capacitor and inductor.

S1 Io S1 L1

Vi C1 Vi C1 C2 Vo
D1 L1 D1

(a) (b)
Fig. 2. A practical example applying the configuration shown in Fig. 1(c): (a)with current output, and (b)with voltage out-
put.
In synthesizing PWM converters based on the decoded transfer gains, dc voltage/current offsetting, capacitor/inductor
component splitting and diode grafting concepts are used frequently. They are explained as follows:
A. DC Voltage/Current Offsetting
A voltage source is buffered with a capacitor and when it is in series with another capacitor, the two capacitors can be
equivalent to a single one, as illustrated in Fig. 3. The only difference is that the capacitor is with a dc-offset voltage VS, and
it can be shown that this dc-offset voltage does not affect the input-to-output voltage transfer gain. Similarly, Fig. 4 shows a
current source in parallel with an inductor and they are equivalent to a single inductor with a dc-offset current. Two typical
examples applying the dc-offset concept are illustrated in Figs. 5 and 6. It has been shown that the converter in Fig. 5(a) is
equivalent to that in Fig. 5(c) in the aspects of transfer gain and operational principle, and they should be considered the
same converter topology but with different component configurations. Similarly, the converter in Fig. 6(a) is also equivalent
to that in Fig. 6(c), and they are identical topology.
Note that capacitors with different dc-offset voltages just change their own bias voltages, but do not change node volt-
ages in converters. In general, volt-second balance principle is applied on the inductors of converters to derive input-output
voltage transfer gain, and it is based on node voltages or the voltage difference between nodes. Thus, capacitors with differ-
ent dc-offset voltages do not affect the transfer gain.
C1 C1
C'1
VS CS

Fig. 3. A voltage source in series with a capacitor is equivalent to a single capacitor with a dc-offset voltage.

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IS L1 IS LS L1 L'1

Fig. 4. A current source in parallel with an inductor is equivalent to a single inductor with a dc-offset current.
L1 L1 L1
C1
Vi C1 Vi Vi C'1
Vi

(a) (b) (c)

Fig. 5. Illustration of capacitor C1 with different dc-offset voltages in a quasi-resonant buck converter.
L'1
L1 Ii L1
Ii C1 X Y C1 Ii C1
Ii

(a) (b) (c)

Fig. 6. Illustration of inductor L1 with different dc-offset currents in a quasi-resonant boost converter.

B. Capacitor/Inductor Component Splitting

If the voltage difference between nodes can be kept identical and the capacitor voltage complies with ampere-second
balance, a capacitor can be split into two capacitors, as shown in Fig. 7(a), in which VXZ = VYZ = VC and VXY = 0 in both net-
works. Similarly, an inductor can be split into two inductors, as shown in Fig. 7(b), when their total branch currents are
identical (i.e., il1 + il2 = il). In addition, since in a valid converter topology, inductors must be operated with volt-second bal-
ance in the steady state, their average voltages across the inductors over a switching cycle will be zero, VXY = 0, in both
networks shown in Fig. 7(b). This component splitting concept will be verified in later synthesis of PWM converters ac-
cording to the decoded transfer gains.

X Y VC VC
X Y
C11 C12 A. VXY = 0
VXZ C1 VC VYZ B. VXZ = VYZ = VC
VXZ VYZ

Z Z

(a)

A. il1 + il2= il.

L11 L12 B. In a valid converter topology, inductors L11 and L12 must be operated with
X Y X Y
volt-second balance in the steady state. Thus, their average voltage over a
il1 il2 switching cycle will be zero, and VXY = 0.
Z1 L1 il Z 2 Z1 Z2
(b)
Fig. 7. (a) A capacitor is split into two capacitors with identical node voltages, and
Z
Z (b) an inductor is split into two inductors with identical total branch current and
node voltages.
C. Diode Grafting
In [14], grafted switches were proposed to integrate power converters. Similarly, the diodes in the converters operated
in unison and sharing at least a common node can be also grafted to simplify the converter configuration. If two diodes are
in series or in parallel, they can be simply replaced with a single one. However, if they share only a common node, common
N-N or P-P as shown in Fig. 8, they can be grafted depending on their node voltages. Fig. 8(a) shows two diodes with a
common N-N node, and they can be grafted into a single one D12. While, it might require two blocking diodes, DB1 and DB2,
to block the voltage difference between Vx and Vy, as shown in Fig. 8(b). If (i) Vx > Vy, diode DB1 is always in forward bias
and it can be shorted. On the contrary, if (ii) Vx < Vy, diode DB2 can be shorted. If (iii) Vx = Vy, both DB1 and DB2 can be
shorted and there is only D12 left, as shown in Fig. 8(b). Similarly, two diodes share a common P-P node, as shown in Fig.
8(c) can be grafted into the configurations shown in Fig. 8(d).
(ii) VX<VY
DB1 DB2 DB1
VX VY V VY
X

VX VY D12 D12
VZ VZ
D1 N D2 (i) VX>VY (iii) VX=VY
DB2
VX VY VX VY
VZ
D12 D12

VZ VZ
(a) common N-N (b)

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(ii) VX<VY
VZ VZ
D12 D12
VZ DB1 DB2 DB2
VX VY VX VY
P
(i) VX>VY (iii) VX=VY
D1 D2
VZ VZ
D12 D12
VX VY DB1
VX VY VX VY
(c) common P-P (d)
Fig. 8. Diodes sharing a common node can be grafted into different configurations.
D. Three Fundamental PWM Converters
(A) CCM Operation
Given a buck converter and its CCM transfer gain, as shown in Fig. 9(a), the other two fundamental PWM converters,
boost and buck-boost converters, can be decoded and evolved from the buck converter. Taking the output from capacitor C1
of the buck converter yields VO/Vi = D, but taking it from C2 will yield VO′/Vi = 1-D, where D is the duty ratio of active
switch S1. A forward transfer gain D with a positive unity feedback VO to Vi yields VO/Vi = D/(1-D), as shown in Fig. 9(b).
Its corresponding converter synthesis is shown in Fig. 9(c), which can be redrawn to the form shown in Fig. 9(d) as a
buck-boost converter. Again, if taking the output from C2 of the buck-boost converter, we can have V'O/Vi = 1+D/(1-D) =
1/(1-D), which is the transfer gain of a boost converter. Applying the dc-offset concept to C1 and redrawing the circuit con-
figuration will yield the boost converter shown in Fig. 9(e), where C12 = C1//C2. Note that since voltages Vi, VO and V'O form
a loop in the buck-boost converter, one of the voltage is a dependent variable and one of the capacitors C1, C2 and input ca-
pacitor is no longer needed.
(B) DCM Operation
For the buck converter shown in Fig. 2(b) and operated in DCM, the input-to-output transfer gain can be derived as
Vo/Vi = d1/(d1 + d2), where d1 is the duty ratio of switch S1 and d2 is that of the free-wheeling diode. If d1 + d2 = 1, the buck
converter is in CCM operation and Vo/Vi = d1 = D. Thus, CCM operation is just a special case of DCM. Similarly, the
transfer gain of the buck-boost converter in DCM operation can be derived as Vo/Vi = d1/d2 by substituting the transfer gain
D shown in Fig. 9(b) with the gain, d1/(d1 + d2), of the buck converter in DCM. The transfer gain of the boost converter,
therefore, can be derived as Vo/Vi = 1 + d1/d2 = (d1 + d2)/d2. Based on the transfer gains of the fundamental converters in
DCM operation, the rest of the converters discussed in the following can be also derived correspondingly. They come out
the same topologies with those operated in CCM. Thus, the converter manipulation with the layer scheme can be extended
to the converters operated in both DCM and CCM. In the rest of the sections, for simplicity, the discussion of decoding and
synthesizing transformerless PWM converters will be based on CCM operation only.
V 'o
V'O 1  D
Vi
C2 Vi VO
Σ D
S1

Vi C1 VO
1

(a) buck: V0/Vi = D (b) V0/Vi = D /1-D

V'O
Buck Converter V 'O D 1
 1 
C2 Vi 1 D 1 D

Vi Vi+VO VO
Vi C1 VO V D
O

Vi 1 D

(c) (d) buck-boost: V0/Vi = D /1-D

Vi C12 V'O

(e) boost: V'0/Vi = 1 /1-D

Fig. 9. Decoding, synthesizing and evolution of buck-boost and boost converters from the buck converter.
From the above discussion, we observed that the fundamental PWM code is D, and the derived codes include (1-D),
1/(1-D), and D/(1-D). These codes can be adopted in decoding transfer gains. By exchanging the roles of the active and the
passive switches in the converters shown in Fig. 9, the following codes, 1/D, (1-D) and (1-D)/D, can be obtained from D,
1/(1-D), and D/(1-D), respectively. Again, these codes will be used in decoding transfer gains. Illustrations of decoding the
transfer gains of PWM converters will be presented in later sections.
With dc-offset and component splitting schemes, the switch operation in PWM converters are not affected. With the
layer scheme, the output voltage or current is fed back to the input which does not change the PWM operation. With the
4

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Transactions on Power Electronics

graft scheme, the active switches or the diodes are operated in unison and they can be integrated into a grafted switch or a
grafted diode if they share at least a common node. The grafted switches or the grafted diodes are still operated in PWM
manner. Therefore, synthesizing the decoded transfer gains with the above discussed schemes can always yield PWM con-
verters. In the following sections, these schemes will be used for decoding and synthesizing PWM converters.
III. Principle of Decoding and Synthesizing
When conducting power conversion, usually, we have a desired input-to-output transfer gain in mind first and search
for a converter topology to realize the transfer gain. However, the transfer gain might not be always in a form which can be
synthesized readily or straightforwardly. Thus, it needs to decode the transfer gain into several codes which can be synthe-
sized by the existing PWM converters. The proposed decoding processes are summarized as follows:
1) Using a long division to detach the unity gain from the given transfer gain. For instance, a transfer gain f(D) is
V 1 D D V' , (1)
f ( D)  o   1  1  o  1  f ( D)
1  2D 1  2D
r
Vi Vi
where fr(D) = V’o/Vi = D/(1-2D).
2) Conducting a cross multiplication of V’o/Vi = fr(D) to find a relationship among Vi, V’o and D, which is denoted as
equation (4).
V 'o D (2)
 f ( D) 
1  2D
r
Vi
Or,
V 'o (1  D)  (Vi  V 'o ) D (3)
That is,
D (4)
V 'o  (Vi  V 'o )
1 D
3) Using a transfer block diagram to illustrate equation (4) and adding up with the unity gain if it exists (in this example,
it is denoted in dashed line). The overall transfer block diagram can be represented in either Fig. 10(a) or (b).
4) Synthesizing the transfer block diagram with the original converter and its derived. The synthesis approaches include
layer scheme, graft scheme, dc offsetting, component splitting, etc. It should be noted that even though the same
transfer gain can be represented in different transfer block diagrams, some of them could not be synthesized with
single-switch PWM converters due to no common nodes between active switches. For instance, Fig. 10(a) can be
synthesized with a single-switch PWM converter (as illustrated in Fig. 16), while the one shown in Fig. 10(b) cannot
be done. In general, starting from a simple representation, like Fig. 10(a), has more chance to yield the form which can
be synthesized with a single-switch PWM converter.
In the following sections, the decoding processes and synthesis approaches will be illustrated with the well-known and
new PWM converters.
1 1
c
c

Vi V'O VO Vi V''O V'O VO

D 1
Σ 1-D
Σ Σ 1-D
D Σ
V'O
1 D

(a) (b)
Fig. 10. Two transfer block diagrams to represent the transfer gain of Vo/Vi = (1-D)/(1-2D).
IV. Illustration of Decoding and Synthesizing PWM Converters
This section presents illustration of decoding and synthesizing PWM converters, including two sub-sections. Based on
the fundamentals presented in section II, the conventional PWM converters, Ćuk, SEPIC and Zeta converters can be de-
duced to the buck-boost converter with an extra LC filter. This confirms that identical transfer gain should yield identical
converter topology, but might be with different component configurations. This is presented in sub-section A. Several fur-
ther illustration examples, including current-fed Z-source converter, voltage-fed Z-source converter,
switched-capacitor/switched-inductor hybrid converters, and a single-stage interleaved converter are presented in
sub-section B.
A. Deduction from Ćuk, SEPIC and Zeta to Buck-Boost Converter
In addition to the buck, boost and buck-boost converters, there are three well-known PWM converters, Ćuk, SEPIC
and Zeta. They are all with the same number and same type of components and with the same input-to-output voltage trans-
fer gain, VO/Vi = D/(1-D), which is identical to that of the buck-boost converter. Thus, they can be considered as the same
topology but with different component configurations. In the following, deduction from the Ćuk, SEPIC and Zeta to the
buck-boost converter with an extra LC filter is presented, and this will confirm the argument.
(A) From Ćuk to Buck-Boost
Fig. 11(a) shows a Ćuk converter and Fig. 11(b) shows the configuration by relocating inductors L1 and L2 to the return
path. Changing the dc-offset voltage of capacitor C1 by re-wiring from Vi+ to Vi- yields the one shown in Fig. 11(c). Again,
changing the dc-offset voltage of C1 by re-wiring from VO- to VO+ will yield the one shown in Fig. 11(d), and with a proper
arrangement, a buck-boost converter with an extra L2C1 filter is shown in Fig. 11(e). Since L1, C1 and L2 form a loop, the
average voltage of C1 in the steady state must be zero and L1 is equivalently in parallel with L2. Therefore, from topological
point of view, the one shown in Fig. 11(e) is just a buck-boost converter.

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L1 L2
C1 C1

C2 VO Vi C2 VO
L1 L2

(a) Ćuk (b)

C1 Vi C2 VO
Vi C2 VO
L1 X L2
Y
L1 L2
Y C1
X

(c) (d)

L2
Vi VO
L1 C2
C1

(e) buck-boost with an extra LC filter

Fig. 11. Deduction from Ćuk to buck-boost converter.
(B) From SEPIC to Buck-Boost
A SEPIC converter is shown in Fig. 12(a). When relocating inductor L1 to the return path and changing the dc-offset of
capacitor C1 by re-wiring from Vi+ to Vi-, we can obtain an equivalent converter as shown in Fig. 12(b). Then, redrawing the
converter will become the form shown in Fig. 12(c). Again, one more step to redraw the converter will come out the one
shown in Fig. 12(d). Finally, relocating the diode from the return path to the forward yields a buck-boost converter with an
extra L2C1 filter, as shown in Fig. 12(e). As described in the previous sub-section, C1 and L2 play the role of a filter and L1 is
equivalently in parallel with L2. Thus, this configuration is just a buck-boost converter.
L1
C1 C1
Vi L2 C2 VO Vi L2 C2 VO

L1

(a) SEPI (b)

L2
C2
C1 C2 Vi L1 L2 VO
Vi L1 VO
C1

(c) (d)
LC filter

C2
Vi L1 L2 VO
C1

(e) buck-boost with an extra LC filter

Fig. 12. Deduction from SEPIC to buck-boost converter
(C) From Zeta to Buck-Boost
Fig. 13(a) shows a Zeta converter and Fig. 13(b) shows the configuration by relocating inductor L2 from the forward
path to the return. Changing the dc-offset of capacitor C1 by re-wiring from VO+ to VO- yields the one shown in Fig. 13(c).
Then, redrawing the configuration becomes the one shown in Fig. 13(d). Finally, relocating the diode from the return path to
the forward will yield a buck-boost converter with an extra L2C1 filter, as shown in Fig. 13(e). Similarly, this configuration
is equivalent to a buck-boost converter.

L2 C1
C1
VO Vi L1 C2 VO
Vi L1 C2
L2

(a) Zeta (b)

C1 C1
C2
Vi L1 C2 VO Vi L1 L2 VO

L2

(c) (d)

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L2
Vi VO
L1 C2
C1

(e) buck-boost with an extra LC filter

Fig. 13. Deduction from Zeta to buck-boost converter.
(D) Discussion
From the previous deduction, it reveals that Ćuk, SEPIC and Zeta converters are all equivalent but its buffer capacitor
C1 with different dc-offset voltages. This can be simply confirmed with the evolution of Zeta converter from SEPIC. Fig.
14(a) shows a SEPIC converter, and when relocating L1 and the diode, we obtain a configuration shown in Fig. 14(b).
Changing the dc-offset of capacitor C1 by re-wiring from Vi+ to Vi- yields the one shown in Fig. 14(c). Again, changing the
dc-offset of C1 by re-wiring from VO+ to VO- yields the one shown in Fig. 14(d). Finally, relocating C1 from return path to the
forward yields the Zeta converter, as shown in Fig. 14(e). Similarly, the evolution of Ćuk converter from SEPIC can be also
conducted by changing the dc-offset of capacitor C1 and relocating the diode.

L1 C1
C1
L2 C2 VO
L2 C2 VO Vi
Vi
L1

(a) SEPIC (b)

L2

Vi C1 L2 VO L1 VO
C2 Vi C2
C1
L1

(c) (d)
L2
C1
Vi L1 C2 VO

(e) Zeta
Fig. 14. Evolution of Zeta converter from SEPIC.
B. Further Illustration Examples
In the literature, voltage-fed and current-fed Z-source converters [27]-[33] have been widely applied for dc-dc voltage
conversion, of which their transfer gains are VO/Vi = (1-D)/(1-2D) and (2D-1)/(1-D), respectively. The quasi Z-source con-
verter is another example with the transfer gain of D/(1-2D). Switched-capacitor/switched-inductor hybrid dc/dc converters
[42] were developed recently which have higher step-up or step-down ratios than their conventional counterparts. Moreover,
converters in interleaving operation and grafted with an inverter were proposed for power factor correction (PFC) and elec-
tronic ballast application [43]. In the following, their transfer gains will be decoded and synthesized from the fundamental
converters.
(A) Voltage-Fed Z-Source Converter
A transfer block diagram to decode VO/Vi = (1-D)/(1-2D) is shown in Fig. 15, which consists of a D/(1-D), a positive
unity feedback and an input feedforward. The transfer block enclosed in the dashed-line block can be realized by either
SEPIC or Zeta with a positive unity feedback. The one with SEPIC is illustrated in Fig. 16. Fig. 16(a) shows the SEPIC
converter with the feedback, which can yield V'O/Vi = D/(1-2D). Note that when the duty ratio D is greater than 0.5, the
output voltage will be negative, and the switch and the diode have to be replaced with bi-directional switches.
Taking the output from (Vi +V'O) will yield VO/Vi = (1-D)/(1-2D), which is illustrated in Fig. 16(b). Redrawing the con-
figuration and combining C2 and Cf yields the one shown in Fig. 16(c), in which C'2 = C2//Cf. Changing the dc offset of C'2
by re-wiring from Vi- to Vi+ yields the one shown in Fig. 16(d), and redrawing the configuration will have the form shown in
Fig. 16(e). By splitting inductor L1 into L11 and L12, we can obtain the voltage-fed Z-source converter, as shown in Fig. 16(f).
In fact, the one shown in Fig. 16(d) is good enough to function identically to the Z-source converter, and capacitor C'2 an CO
are in parallel, which can be combined into a single capacitor. It has been shown that the transfer block diagram shown in
Fig. 15 can be also synthesized with a Zeta converter.
1
Vi
Vi V'O VO
D
Σ 1-D
Σ
VO 1 D
1 
Vi 1 2D

Fig. 15. A transfer gain block diagram to decode Vo/Vi = (1-D)/(1-2D)

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V0=Vi+V'O
L1 C1
C0
L1 C1 L2
Vi+V'O L2 V'O
C2
Vi
Vi Cf C2 V'O
Cf

(a) (b)
L1
Vi C1 C2' L1
C0 VO
Vi C1
C0 VO
L2
C2'
L2

(c) (d)

L1 L11 L12
C2'
Vi C0 V0 C2'
C1 Vi C0 V0
C1
L2
L2

(e) (f)
Fig. 16. Synthesizing the transfer gain block shown in Fig. 15 with the SEPIC converter.
(B) Current-Fed Z-Source Converter
Fig. 17(a) shows a Zeta converter by taking its output from (V'O-Vi ) which yields the transfer gain of VO/Vi = (2D-1)/(1-D). Re-
drawing the configuration with the input-output on the left-right location and changing the dc offset of capacitor C2 from V’O to Vi
yield the one shown in Fig. 17(b). Relocating inductor L2 from the return path to the forward and changing the dc offset of C1 by
re-wiring from VO+ to VO- will yield the one shown in Fig. 17(c). Splitting inductor L1 into L11 and L12, and moving L11 from the return
path to the forward yields the current-fed Z-source converter shown in Fig. 17(d). In fact, the one shown in Fig. 17(b) functions iden-
tically to the current-fed Z-source converter, and capacitor C2 can be merged into the input source. As described previously, SEPIC
converter can be evolved from Zeta converter; thus, the current-fed Z-source converter can be also derived from SEPIC converter.
VO
2D 1
C0 VO V 'O Vi  L2
1 D
C1 L2 VO
Vi C1
D
Vi L1 C2 V'O  Vi L1
1 D C2

(a) Zeta (b)

L2 L11 L2

VO C2
C1 Vi VO
Vi C1 C0
C2
L1
L12

(c) (d)
Fig. 17. Synthesizing the transfer gain block of VO/Vi = (2D-1)/(1-D) with a Zeta converter
(C) Quasi Z-Source Converter
The transfer gain block of D/(1-D) with a positive unity feedback can yield VO/Vi = D/(1-2D), as illustrated in Fig. 18.
A SEPIC converter to synthesize the transfer gain is illustrated in Fig. 19(a). Rearranging the components will yield the one
shown in Fig. 19(b), and pulling the active switch to the output terminal yields the configuration shown in Fig. 19(c).
Changing the dc-offset voltage of capacitor C2 yields the quasi Z-source converter shown in Fig. 19(d), but the voltage
across C2 must be changed to Vi+VO, instead of the original VO. Both configurations shown in Fig. 19(c) and 19(d) come out
the same transfer gain and component stress imposed on the switching devices, and it can be proved that they are with the
same dynamics. Similarly, since Zeta and SEPIC are equivalent converter with different dc-offset capacitor voltages, the
transfer gain block shown in Fig. 18 can be also synthesized with a Zeta converter.
Vi D VO
Σ 1-D
V0 D

1 Vi 1  2 D

Fig. 18. A transfer gain block of D/(1-D) with a positive unity feedback yielding VO/Vi = D/(1-2D)
L1 C1

L1
S1 L2 C2 VO
Vi L2
C1
Vi VO
C2

(a) (b)

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L2 C1 C1
L2
L1
VO L1

C2 Vi C2 VO+Vi
Vi

(c) (d)
Fig. 19. Synthesizing the transfer gain block of VO/Vi = D/(1-2D) with a SEPIC converter
(D) Switched-Capacitor/Switched-Inductor Hybrid Converters
The transfer block of D with a negative (1-D)/D feedback can yield Vo/Vi = D/(2-D), as illustrated in Fig. 20. A buck
converter with an inverse buck-boost converter to synthesize the transfer gain block shown in Fig. 20 is illustrated in Fig.
21(a). Rearranging switch S2 to the feedback path yields the one shown in Fig. 21(b). Since switches S1 and S2 have a com-
mon node D-S, they can be grafted into a single one S12 with two diodes DF1 and DF2, as shown in Fig. 21(c). It can be
proved that the currents flow through S1 and S2 are identical, and diodes DF1 and DF2 are no longer needed, which can be
simplified to the one shown in Fig. 21(d). Finally, rearranging the component connection can yield the hybrid dc-dc PWM
step-down converter, as shown in Fig. 21(e), and it was presented in Fig. 7 of [42]. Similarly, one can use the transfer block
of D/(1-D) with a negative 1/D feedback to yield Vo/Vi = D/(2-D), as shown in Fig. 22. A buck-boost converter with an in-
verse buck converter to synthesize the transfer gain block shown in Fig. 22 is illustrated in Fig. 23(a). By following the
same procedure of grafting switches, as shown in Fig. 23(b), we can yield the same hybrid converter shown in Fig. 23(c).
Another example of synthesizing D/2(1-D) is illustrated by Figs. 24-26. Fig. 24 shows the transfer gain block decoded
by D/(1-D) and (1-D)/D. Fig. 25 shows that with SEPIC and inverse Ćuk converters step by step, mainly counting on graft
and layer schemes. Fig. 25(h) and Fig. 26(i) show the same converter configurations which were presented in Fig. 20 and
Fig. 18 of [42], respectively.
From the above decoding, deduction, synthesizing and evolution, we observe that each of the derived converters can be
decoded and synthesized with graft, layer, dc offsetting and component splitting schemes. The same concepts can be applied
further to obtain other transformerless PWM converters.
Vi Vo
Σ D
Vo D
1 D

Vi 2D
D

Fig. 20. A transfer gain block of D with a negative (1-D)/D feedback yielding Vo/Vi = D/(2-D)
L1 D2 D S2 S

1 D
D1 Vo L2 C2 Vo
C1 D

S
S1
D

(a)

L1 D2 L1
D2
D1 L2 D1 Vo C1
DF1 L2
S1 S C2
S C2
D S12 DF2
S D
S2 D
I1 = I2 ➔ DF1 and DF2 can be saved (open)
(b) (c)
L1 D2
L1
D1 D2
D1 C1
Vo
L2 C1 Vo

L2

(d) (e)
Fig. 21. Synthesizing the transfer gain block of Vo/Vi = D/(2-D) with buck plus inverse buck-boost converters.
Vo
D
Vi Σ 1 D
Vo D

1 Vi 2  D
D

Fig. 22. A transfer gain block of D/(1-D) with a negative 1/D feedback yielding Vo/Vi = D/(2-D).

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S1 S2
D S D S
L2
1
L1 C1 Vo C2 D Vo

(a)
T D1 L2 X
Y T Z
L1

C1 D2 D1 D2
DF1 L1 Vo
C2 Vi C1 Vo
S12
Z L2
DF2
X Y

(b) (c)
Fig. 23. Synthesizing the transfer gain block of Vo/Vi = D/(2-D) with buck-boost plus inverse buck converters.
Vo
Vi D
Σ 1 D

1 D
D
Fig. 24. A transfer gain block of D/(1-D) with a negative (1-D)/D feedback yielding Vo/Vi = D/2(1-D)
L2
S1 S2
D S D S
L2 Vi
L1 Co Vo L3
S
Vi L1 Co Vo L3 S1
D

S
S2
D

(a) (b)
L2 L2
D2

Vi Vi
L1 L1 D1 Co
D1 Co Vo L3 Vo

DF1

S12
DF2 L3

D2
I1 = I2 ➔ DF1 and DF2 can be saved

(c) (d)
U T X U T X
L2 L2
L1
Vi Vi
L1 D1 Co Vo D1 Co Vo
L31
L3
Y L32 Y
Z
Z

D2 D2

(e) (f)
U T X
L2

Vi L2
L1
D1 Co Vo
D1 D2
L1 Vo
Lꞌ 2 Co
Vi VO D
Z Y 
Vi 2(1  D)
D2

(g) (h)
Fig. 25. Synthesizing the transfer gain block of Vo/Vi = D/2(1-D) with Zeta plus inverse buck-boost converters.
D S
L2 L3
D
S
Vi S1 I 1 S2 VX
L1 Vo
S D
I2

1 1 D
Let LS = L1 = L2 = L3, and we have I1 = I2 VX  Vi  VO
2 D
(a)

10

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S12
D S

L3

LS L2
C1 C3
Vi L1 C2 Vo
CX

(b)
S12
D S

LS L2
C1 C3
Vi
L1 C2 Vo

L31
L32 CX

(c)
T X Z

LS31 L2
D1

Vi S12 L1 Vo
D2

Y
C3

(d)
C1 D1
T X

L1 L2
S12
C2
Z
D2 Y

(e)
C1 D1

L1 L2
S12
C2

D2

(f)
C1

L1 L2
S12
C2

(g)
C12

C
L1 L2 +
S12 C0 V0
- L

C
LC is just a filter of L2

L2 L L2 '

(h)
D1

L1 L2 +
S12 Co Vo V
D
- O 
Vi 2(1  D)

D2

11

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(i)
Fig. 26. Synthesizing the transfer gain block of Vo/Vi = D/2(1-D) with SEPIC plus inverse Ćuk converters.
(E) Single-Stage Interleaved Boost Converters Grafted with Half-Bridge Inverter
In the previous illustrations, only are grafted-switch technique and layer scheme adopted. Fig. 27 illustrates the syn-
thesis of a single-stage interleaved boost converter grafted with a half-bridge inverter using both grafted-switch and graft-
ed-diode techniques. In Fig. 27(a), two boost converters are interleaved and connected to a half-bridge inverter. Their
switches S1~S4 share common nodes D-D and S-S, and they can be operated in unison, respectively. Thus, they can be
grafted into S13 and S24 with blocking diodes, respectively. The voltages across switches S1~S4 are all equal to Vdc when the
boost converters operate in CCM. However, when they operate in DCM for achieving PFC, the voltages across S1 and S2 are
Vi1 and Vi2, respectively, which are lower than Vdc. Thus, only are DB3 and DB4 can be shorted (saved), yielding the circuit
shown in Fig. 27(c). Diodes DB1 and D1 share a common N-N and diodes DB2 and D2 share a common P-P, and they can be
grafted according to the conditions presented in Fig. 8. The circuit will become the one shown in Fig. 27(d). It can be recog-
nized that diodes D1 and D2 are anti-paralleled with S24 and S13, respectively, and they can be realized with their body diodes,
as shown in Fig. 27(e). This is the topology presented in [43] for PFC and electronic ballast application.
S13 Vdc
Vi1
Z
DB1 D1 DB3
Vi1 S1 Vdc S3
Z
D1

DB2 D2

D2 DB4
Vi2 S2 S4 Vi2 S24

(a) (b)

Vi1 S13 Vi1 S13

DB1 DB1
Z Z
D1 D1

D2 D2

DB2 DB2
Vi2 Vi2 S24
S24

(c) (d)

DB1
Vi1 S13 D2

Vi2 S24 D1
DB2

(e)
Fig. 27. Single-stage interleaved boost converters grafted with a half-bridge inverter.
V. Decoding and Synthesizing New PWM Converters
In the previous section, all of the illustrations are based on the existing converters. This section presents two illustration
examples of decoding and synthesizing new ones. Fig. 28(a) shows the transfer gain blocks of 1/(1-D)*D/(1-D) and Fig.
28(b) shows the synthesis of the transfer gain block with boost and buck-boost converters in cascade. With the graft scheme,
the two active switches, S1 and S2, can be integrated into a single one when they are operated in unison and share a common
node. From Fig. 28(b), we can see that switches S1 and S2 share an S-S common node and they can be replaced with a T-type
graft switch, as shown in Fig. 28(c). Since the voltages across S1 and S2 are VC1 and VC1+VO, respectively, when both
switches are turned off and VC1+VO > VC1, diode DB2 can be shorted. The final circuit to achieve D/(1-D)2 is shown in Fig.
28(d), in which there is only one active switch S12 but with three diodes. If taking VC1 feedback to the input, we can obtain
the converter shown in Fig. 28(e) to achieve the transfer gain, V’o/Vi = -1/(1-D).
Vi 1 D VO
1-D 1-D V0

D
Vi (1  D) 2

(a)
L1 D1 D2
L1 D1
D D2
DB1 C1 VC1
Vi S1 C1 L2 C2 VO
Vi VO
C2
S
DB2 L2
S12
S D

(b) (c)
12

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L1 L1 D1 D2
D1 D2

DB1 C1 VꞌC1
DB1 C1 VC1
Vi VOꞌ
Vi VO L2
C2
L2 S12
S12

(d) Vo/Vi = D/(1-D)2 (e) V'o/Vi = -1/(1-D)

Fig. 28. Decoding and evolution of the boost+buck-boost grafted PWM converter from boost and buck-boost converters in
cascade.
Another illustration example is shown in Fig. 29, which yields a new buck derived PWM converter. From the switch
operation of the buck converter shown in Fig. 29(a), the voltage across diode D1 is pulsating and it is filtered with an L1C1
filter to obtain smooth output voltage Vo1, which is the conventional output voltage Vo1 = DVi. Similarly, the voltage across
switch S1 is also pulsating and it can filtered with another set of L2C2 filter to obtain smooth output voltage Vo2 = (1-D)Vi, as
shown in Fig. 29(b). Relocating components S1, L2 and C2 to the return path yields the circuit shown in Fig. 29(c). Feeding
Vo2 back to Vi can achieve the transfer gain of V’02/Vi = (1-D)/D, as shown in Fig. 29(d). After redrawing the component
connection, we can obtain the one shown in Fig. 29(e). Finally, moving components S1, L2 and C2 back to the forward path
results in the converter shown in Fig. 29(f).
The same concepts and procedures can be applied to other existing PWM converters to yield new PWM converter to-
pologies.
Vo2
L2
C2
S1 L1
S1 L1

Vi D1 C1 Vo1 Vi D1 C1 Vo1

(a) (b)
L1

Vi D1 C1 Vo1
=DVi
S1
C2 L2

Vo2
=(1-D)Vi
(c)
L1

Vi D1 C1 Vꞌo1

S1
Vꞌo2
C2 L2 Vi Σ 1-D

V 'o 2 1  D
Vꞌo2  1
Vi D
(d)

L1 L 2 C2

Vi D1 C1 S1 L1
Vꞌo1 Vꞌo2
Vꞌo2
S1 Vi D1 C1 Vꞌo1
C 2 L2

(e) (f)
Fig. 29. Buck derived PWM converter with V'o2/Vi = (1-D)/D
VI. Summary, Discussion and Future Study
A. Summary
The procedure of decoding and synthesizing transformerless PWM converters can be summarized as follows:
1 Starting from the original converter, buck converter, and obtaining its transfer gain can derive the buck-boost and boost
PWM converters, and their transfer gains D/(1-D) and 1/(1-D) with the layer scheme [13].
2 Through input and output voltage combination of the derived PWM converters, and applying the layer scheme again can
derive more PWM converters. If the output voltage will change from positive to negative when varying the duty ratio (D)
from 0 to 1, the active and passive switches need to be replaced with bi-directional types of switches.
3 With the concepts of dc offsetting, component splitting, diode grafting and inverse operation of PWM converters, many
well-known and new PWM converters with special forms can be obtained.
4 To derive the PWM converters with a single active switch and possible multiple diodes, the graft scheme [14] can be
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adopted.
5 A dc transformer can be inserted into a non-isolated PWM converter to derive an isolated version [3].
B. Discussion
Unlike the conventional graft and layer approaches, the proposed decoding and synthesizing method uses only the
voltage source concept. Thus, a voltage source in series with an inductor is not processed as a current source, but just a
voltage source in series with a filter inductor. This idea can also resolve the non-one-to-one correspondence problem of the
duality between voltage source and current source, as illustrated in Fig. 30. In Fig. 30, the buck converter is fed with a volt-
age source which is realized with a capacitor, and the boost converter is fed by a so-called current source which is realized
with a capacitor in series with an inductor. It is quite confusing that why a current source is not realized with an inductor
only. In fact, buck and boost are not dual converters because their components are not in one-to-one correspondence.
L1 L1

Vi C1 VO Vi C1 VO

voltage source current source

(a) (b)
Fig. 30. Illustration of non-one-to-one correspondence of the duality between voltage source and current source.
The proposed approach can only deal with the converters of which their power transfer is conducted between inductors
and capacitors, but no capacitor multipliers, because the power transfer in the capacitor multipliers cannot be modulated
with PWM. The power transfer between pure capacitors or pure inductors is lossy, while that between inductor and capaci-
tor is in resonant manner and is lossless. The power transfer in resonant manner can reduce current and voltage slew rates,
which in turn can reduce EMI levels.
As presented in section IV, the buffer capacitor C1 in Ćuk, SEPIC and Zeta converters is with different dc-offset volt-
ages, but they do not affect the input-to-output voltage transfer gain, D/(1-D), and the voltage and current stresses imposed
on the switches. The three converters are equivalent to the buck-boost converter with an extra LC filter. For a practical ap-
plication, we can just add an LC filter to the input or the output of the buck-boost converter depending on the desired filter-
ing purpose.
In the decoding and synthesizing PWM converters, there is no need to adopt component splitting concept except that
we want to configure the converters into special forms. For component splitting, we have to insure that the voltages between
nodes and the total branch currents are identical before and after splitting. Thus, the transfer gains can be kept without
change.
There are some converters with multi-phase interleaving. If they are constructed from the PWM converters, typically
the same decoding and synthesizing approach still applies. However, if they are integrated with capacitor lift or capacitor
multiplier, the proposed approach does not apply.
In applications, we need to select a proper converter topology for converting input to output, and we might have certain
concern, such as a high step-up or high step-down conversion, over a specific duty-ratio range. Fig. 31 shows the plots of
various types of transfer gains which can serve as a guideline in selecting converters. For other considerations of converter
selection, users may find out from literature or explore themselves.

(a) (b)

(c) (d)
Fig. 31. Plots of four types of transfer gains: (a) step down, (b) step up, (c) step up and down, and (d) ± step up and down.
C. Future Study
(A) In decoding a transfer gain into codes and transfer blocks, there might be more than one transfer block diagram which
can yield the same transfer gain. How to systematically select an effective transfer block diagram which can be synthe-
sized by existing PWM converters needs further study.
(B) The proposed decoding and synthesizing approaches are based on transfer-gain concept. However, the gain does not
correspond to a converter topology uniquely. In future, we have to develop an expression for each converter and define
operators for manipulating the expressions to yield converter directly. For instance, as shown in Fig. 32, the buck and
boost converters are first expressed in certain forms, and then through an operator, one can obtain the expression of the
14

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buck-boost converter. Finally, from the expression, the buck-boost converter topology can be uniquely obtained.

[Buck] ? [Boost] = [Buck-Boost]

Buck-Boost
Fig. 32. Conceptual expression and operation of buck and boost converters to yield buck-boost converter uniquely.
VII. Conclusions
This paper has presented the approaches to decoding and synthesizing transformerless PWM converters, which can be
operated in either DCM or CCM. From the decoded transfer gains, synthesis, deduction and evolution of PWM converters
can be conducted systematically. Given the original converter, the buck converter, and its transfer gain, all of the other
PWM converters can be derived. The Ćuk, SEPIC and Zeta converters have been proved to be equivalent to the buck-boost
converter with an extra LC filter. Additionally, there is no need to adopt current-source concept to explain the derivation of
PWM converter, on which the well recognized duality property between the buck and boost converters has been identified
to be infeasible. Moreover, the well applied voltage-fed Z-source, current-fed Z-source and quasi Z-source converters, and
the switched-capacitor/switched-inductor hybrid converters have been decoded and synthesized from the fundamental PWM
converters, such as buck-boost, Ćuk, Zeta and SEPIC. All of the above narrations have been illustrated by transfer gain
block diagrams and converter configurations step by step. At the end of this paper, two possible future study topics are
pinpointed, including how to systematically select an effective transfer block diagram and how to express converters in the
forms which can be manipulated to derive new converters uniquely.
References
[1] S. Ćuk, “General Topological Properties of Switching Structures,” Proceedings of the IEEE PESC, pp. 109-130, 1979.
[2] R. W. Erickson, “Synthesis of Switched-Mode Converters,” Proceedings of the IEEE PESC, pp. 9-22, 1983.
[3] R. P. Severns and G. E. Bloom, Modern DC-to-DC Switch Mode Power Converter Circuits, Van Nonstrand Reinhold
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Tsai-Fu Wu(S’88–M’91–SM’98) received the B.S. degree in electronic engineering

from National Chiao-Tung University, Hsinchu, Taiwan, in 1983, the M.S. degree in
electrical and computer engineering from Ohio University, Athens, in 1988, and the
Ph.D. degree in electrical engineering and computer science from the University of Il-
linois, Chicago, in 1992.
From 1985 to 1986, he was a System Engineer at SAMPO, Inc., Taiwan, where he
was involved in developing and designing graphic terminals. From 1988 to 1992, he
was a Teaching and Research Assistant in the Department of Electrical Engineering and
Computer Science, University of Illinois, Chicago. From 1993 to 2012, he was with the Department of
Electrical Engineering, National Chung Cheng University, Chia-Yi, Taiwan. He is currently a Professor
in the Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan. Dr. Wu
has served as an Associate Editor for IEEE Transactions on Power Electronics since 2000. He served as
Guest Editor-in Chief for IEEE Trans. on Power Electronics in DC Distribution Systems from 2012 to
2013. His current research interests include development and modeling of power converters, design of
solar-array supplied inverters for grid connection, design and development of D-Σ digital controlled
single-phase and three-phase inverters with grid connection, rectification, APF, STATCOM and UPS
functions.
Dr. Wu has been involved in power electronics education since 1993 and has published more than
200 referred technical papers and 5 books (in Chinese), focusing more on development of power con-
verters, controls for various power electronics applications and key power modules for harmonized
ac/dc microgrid. He also owns 24 patents. Dr. Wu received six Best Paper Awards from the Taipei
Power Electronics Association in 2007–2013. In 2006 and 2014, he was awarded as an outstanding re-
searcher by the Ministry of Science and Technology, Taiwan.

16

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