I

Introduction
ors~ ~ ~
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Although continuing cost and performance improve-

ments of the new bipolar and MOS RAM devices are
providing strong incentives for their greatly expanded
use in mainframe memory and other storage applica-
tions, these components have not yet reached the degree
of reliability required for large memory systems. For-
tunately, however, memory system organization is com-
patible with a wide variety of low-cost fault detection
I

and correction techniques6'10'1' that go a long way toward

SpecmialFeature.
Semiconducr
Memory Reliability
with Error Detecting
and Correcting Codes
Len Levine
Xerox Corporation
Ware Meyers
Consultant
n

compensating for otherwise error-prone systems.

The theory and methods of implementation of error
detection and correction (EDAC) are well developed.,-
The use of EDAC with semiconductor memory enables
the designer to retain the device advantages of low
cost, high density, low power, and high speed, while
still achieving acceptable levels of memory system reli-
ability. Surprisingly enough, however, the impact of
EDAC on memory cost, speed, size, power, and relia-
bility has not received much attention in the literature.
It is our purpose, therefore, to develop the relation-
ships between these factors for design decision purposes,
focusing particular attention on the improvement in hard-
ware reliability and its relationship to system maintenance
policy.
Memory organization for error correction
The type of error coding most suitable for main memory
is based on Hamming's single-error correcting code;
accordingly, we will concentrate on memory organiza-
tion using only Hamming code. (BCH* multiple-error
correcting codes are fairly complex and therefore not
generally used in semiconductor memories.)
Single-error correction and double-error detection are
basically achieved by adding redundancy to the data
field. As shown in Figure 1, a field of k parity bits
is generated over k subsets of the m data bits, and both
data bits and parity bits are stored. The total number
of bits stored, n, equals m, + k.
*BCH denotes Bose, Chaudhuri,, and Hocquenghem, the three
men credited with the discovery of multiple-error correcting
codes.
October 1976
Figure 1. Error correction and detection block diagram.
Upon recovery from memory, another field of k parity
bits is generated over the same subsets of the m retrieved
data bits. The k regenerated parity bits are compared to
the k recovered parity bits. The result of the comparison
is k syndrome bits.
If the two fields of parity bits agree, no detectable
error has occurred in storing and reading out. The syn-
drome bits are all zero. If the two fields differ, an
error has occurred and the configuration of the syn-
drome field identifies the particular bit in error. The
error-correction logic then inverts this bit, so that m
data bits returned to the computer are correct. The k-bit
syndrome field is also made available to the computer
in order to identify and store the location of devices
containing bit errors so they may be removed during the
scheduled maintenance period.
The physical organization of the memory components
is important in obtaining the benefit of EDAC. The RAMs
are arranged so that one RAM is assigned to only one
bit of a word in memory. This arrangement ensures that a
single RAM failure does not cause a failure of two or more
bits. Similarly, the organization of the storage modules
can be arranged so that each module is associated with
only one bit of the data word and, therefore, a module
failure produces only a single correctable error.
43
Redundancy ratio
As shown in Table 1, the ratio of parity or error-
code bits k to data bits m required for single-error
correction and double-error detection decreases as word
length increases. The information contained in the table
is based upon the error correction and detection scheme
devised by R. W. Hamming.4 Since the scheme is covered
in standard texts,' no further explanation will be given
here.
In general, k error-code bits provide error correction
and detection over a range of data bits, up to a maximum
given by the formula contained in Table 1. Because the
error-code bits (bits added to achieve redundancy) must
increase in increments of one bit and since each added
bit provides error correction and detection for a range of
data bits, the redundancy ratio and coding efficiency are
discontinuous functions at each change in k.
Table 1. Error code bits required to provide single-error correction and
double-error detection (minimum Hamming code distance: 4)
ERROR-CODE BITS k 5 6 7
DATA BITS (MAX) m = 2k-1 k- 1 4 -10 11-25 26-56
TOTAL BITS n = m + k 9-15 17-31 33-63
REDUNDANCY RATIO R = n/m 2.25-1.5 1.55-1.24 1.27-1.13
CODING EFFICIENCY CE = mrk 0.8-2.0 1.8-4.2 3.7-8.0
Cost and power requirements
The percentage of redundancy required, however, de-
creases rapidly as word length (m) increases. (For common
word lengths, the ratios are shown in Table 2.) Similarly,
coding efficiency increases rapidly.
The redundancy ratio is a fairly good measure of the
cost increase resulting from the addition of error detec-
tion and correction to a memory system. This ratio
exactly represents the relative cost of the additional
storage required to store the error-code bits, but it
does not include the cost of the parity generators,
comparator, decoder, and error-correction logic. However,
the quantity of these elements is fixed for any number
of words. For -a small-size memory, EDAC logic represents
a larger percentage of the total cost. For a large-size
memory, EDAC logic recedes to a smaller percentage
of the total cost. To illustrate this point the cost of
the EDAC logic was less than 5% of the cost of a 64K X
32-bit MOS memory and only 1% of the cost of a
256K X 32-bit memory.
The increase in memory subsystem power is approxi-
mately proportional to the amount of additional storage
plus a slight increase in the logic power for the EDAC
circuits.
Need for error correction
The criterion for determining whether to add error
correction and detection to a memory system is the mean
time between failure (MTBF) required for the applica-
tion. The failure rate of the bipolar and MOS RAM de-
vices may be assumed to be a constant, termed X.
44
The MTBF is then given by
MTBF = 1/dX
where d is the total number of devices in the memory sub-
system. This formula assumes that the infant mortality
period is over and that the memory system (without
error correction) has failed when one device has failed
(i.e., when at least one storage bit has malfunctioned).
Small memories do not usually require error correction;
byte or word parity is generally regarded as sufficient.
As an example a 4K X 16-bit memory using a 1K RAM
with a device failure rate of 0.1% per 1000 hours would
have an MTBF of 15,600 hours. However, a 256K X 64-
bit memory using the same device would have an MTBF
of 64 hours. At this memory size, error correction looks
quite attractive.
Table 2. Redundancy and coding efficiency
for common word lengths.
8 WORD LENGTH m 16 24 32 48 64
57-119 REDUNDANCY
65-127 RATIO (m + k)lm 1.375 1.25 1.22 1.15 1.13
1.14-1.07 CODING EFFI-
7.1-14.9 CIENCY mrk 2.67 4.0 4.57 6.86 8.0
Figures 2 and 3 are provided as a convenient means
of rapidly determining the MTBF for a wide range of
memory sizes. In Figure 2 memory size in number of
words stored is related to the number of RAM devices
required, with word length as the parameter. Specifically,
the figure is based on the equation, d = nw/b, where
d represents the number of devices, n the word length,
w the number of words, and b the number of bits per
device.
Figure 3 is a log/log plot relating the number of de-
vices to the mean time between failures, with device
failure rate as the parameter. This nomograph is based
on the MTBF equation. For example, for a 16K X 16-bit
memory, Figure 2 indicates that 256 1K devices would be
employed. From Figure 3 read off the MTBF of 3900
hours. Similarly, a 256K X 32-bit memory has an MTBF
of 120 hours, using the same device reliability. It should
be noted that Figure 3 is based solely on the RAM de-
vices and does not include other components making up
the total memory. In effect, this nomograph reveals rela-
tive MTBF's for various size memories over a range of
device failure rates.
The dominant cause of memory failure is the chip
failure rate; therefore, Figures 2 and 3 provide a simple
and fairly accurate estimate of performance.
Effect on access time
The impact of EDAC on time delay for most applica-
tions is minimal. The addition of EDAC logic typically
increases the memory-access time from about 15 to 40
nanoseconds depending on whether TTL, Schottky, or
MECL technology is used.
COMPUTER
 256K

224K

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CU
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256 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 11,000 12,000 13,000 14,000
NUMBER OF 1 K x 1 MOS RAM DEVICES
I I I I 1 1. .I 1 1 I1
250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500
*K= 1024 NUMBER OF 4K x 1 MOS RAM DEVICES

Figure 2. Relation of memory size to number of devices.

t
x
0 103
1-

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C-

5r0
w
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U-
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m 102
z

IV-10
r. I1
120 1000 3900 104
MTBF HOURS

Figure 3. Relation of memory size in devices to mean time between failures.

October 1976 45
Reliability improvement
The implementation of EDAC codes is known to im-
prove the data integrity of the memory subsystem;
however, a quantification of this improvement is neces-
sary to gauge the benefit.
MTBF is useful for systems without EDAC as a cri-
terion for establishing the need for error detection and
correction. However, MTBF is not helpful in providing
much insight into the improvement in reliability of an
EDAC memory system. The relationship between the
MTBF for a system without redundancy and one with
redundancy is complex. In a redundant system the MTBF
is a function of the renewal time-the interval between
scheduled service periods in which defective devices are
replaced.'2
Memory devices are subject to a number of failure modes
which could result in the loss of a single bit or row or
column of bits or all the bits in a device. Bit failure
may be intermittent (soft) or continuous (hard). Inter-
mittent errors, which are usually of short duration and
low frequency, are a source of great frustration when
one is trying to debug or operate a system. With an
EDAC system, intermittent errors are almost always
entirely invisible and for this reason make EDAC even
more desirable. Intermittent errors will not be considered
in the analysis of system reliability with EDAC since
their influence on reliability is minor.
Device failure will be considered a failure of all
bits in the device, in order to determine a worst-case, con-
servative bound for measuring the benefits of EDAC.
Actually device faults are often single bit, or single row
or column, and the reliability with EDAC is usually
greater than the lower bound. Initially only storage de-
vices will be considered since their effect is dominant.
The contribution of other memory subsystem components
will be addressed later.
A page of memory is defined as the number of memory
words formed by a minimum set of memory chips. This
number of words will vary with the number of data bits
in the memory device. For example, if a memory is con-
structed from 1024 bit devices, then a 32-bit data word
would have 32 1K RAMs and the memory page would be
1024 words of 32 bits in length.
The expression for a single-bit error in the original
page, developed in detail in the appendix, is
Ple = mR(m - 1)( - R))
where R e- XI and X is the chip failure rate.
Similarly, the-expression for a double-bit error in the page
with k added bits for single-error correction (SEC) is
(m + k)(m + k - 1)R(m+k-2)(l -R )2
2e 2 period of resumed operation, the reliability improvement
The reliability improvement ratio is defined as the ratio of
the probability of single-bit error without SEC to the
probability of a double error with SEC:
Ri = Ple -P2e
Substituting, simplifying, and regrouping to separate the
terms involving word length from those involving time
and failure rate gives the following expression:
Ri- 2m 1 errors from the system. The devices which store the k
(m k)(m k-i)
+ + R(k-1)(1-R)
46
For example, given
m = 32databits,
k= 7 error-code bits,
X = 0.1%/1000 hours = 10-6 failures/hour,
t = 1000 hours,
then
R = eXt = e(°0-001) = 0.9990005,
1-R = 0.0009995,
2m (2 X 32)
(m + k)(m + k - 1) = (32 + 7)(32 + 7 - 1)
= 0.0432
Ri = 0.9940 X-0.0432
0.0009995-=4.7
=
In this example, the addition of SEC has made the
system 43 times more reliable at the 1000-hour operating
point for the failure rate given.
Figure 4 is a log/log plot of reliability improvement
Ri versus operating time t in hours, with the failure
rate X , number of data bits m, and number of error-code
bits k, as parameters. Tables 3 and 4 list the calculations
at failure rate, 10-6 per hour, supporting Figure 4.
In the case of the foregoing example, at the end of the
first 1000 hours (about 1.4 months of continuous opera-
tion), there is 43 times less chance of system failure,
as compared to a similar memory without error correction.
During the next 9000 hours (roughly a year of con-
tinuous operation), the reliability improvement ratio de-
clines from 43 to 3.5. By this time the chance of
system failure is approaching that of the memory without
error correction.
From Figure 4 we can draw four observations. First,
reliability improvement decreases as word size increases
This result was not intuitively obvious. Second, the
increase in coding efficiency which results from the in-
crease in word length comes at the expense of reliability
improvement. Coding efficiency is traded for reliability
improvement. Third, as might be expected, reliability
improvement diminishes with higher component failure
rates (increasing X ). And fourth, reliability improvement
is not constant for a specified memory design, but de-
creases with increasing operating time. After each
scheduled maintenance, of course, when all failed com-
ponents have been replaced, operation time may be
thought of as starting over again. During the early
ratio is again at the higher figure.
System service policy
The accumulation of single-bit errors within the mem-
ory increases the probability of a double error occurring
at some word location in memory. Therefore, the largest
improvement in the reliability of an EDAC system is
gained in the early periods of operation when there are few
single-bit errors. EDAC is most effective when a scheduled
service policy repetitively purges all the devices with bit
error-code bits must also be replaced or else the benefits of
SEC will be lost.
COMPUTER
 a:
-
z
w
w
0
a:
a-

w
a:

Figure 4. Reliability improvement OPERATING TIME tin HOURS

Ri vs operating time with
X , m and k parameters.
Table 3. Reliability improvement calculation.

ERROR 2m
DATA CODE TOTAL WORD (m + k) (m + k - 1)
BITSm BITSk m + k = n

Table 4. Reliability improvement 8 5 13 0.1026

over three operating periods 16 6 22 0.0693
for various word lengths.
32 7 39 0.0432
Note: a = 2m 64 8 72 0.0250
(m + k) (m + k- 1)

t x R 1-R Rk-1 1IRk-1 k a Ri m

10,050 10-6 0.99 0.01 v0.9606 1.041 5 10.681 8
0.1026
103 10-6 0.999 0.001 0.996 1.004 5 102.71 -8
0.1026
102 10-6 0.9999 0.0001 0.9996 1.0004 5 1026.0 8
0.1026
10,050 10-6 0.99 0.01 0.951 1.052 6 7.29 16
0.0693
103 10-6 0.999 0.001 0.995 1.005 6 69.65 16
0.0693
102 10-6 0.9999 0.0001 0.9995 1.0005 6 693.0 16
0.0693
10,050 10-6 0.99 0.01 0.9415 1.062 7 4.59 32
0.0433
103 10-6 0.999, 0.001 0.994 1.006 7 43.46 32
0.0433
102 10-6 0.9999 0.0001 0.9994 1.0006 7 432.0 32
0.0433
10,050 10-6 0.99 0.01 0.9321 1.07 8 2.675 64
0.025
103 0.999 0.001 0.993 1.007 8 25.18 64
0.025
102 10-6 0.9999 0.0001 0.9993 1.0007 8 0.025 250.2 64

October 1976 47
 cc 0.01-

0.0001
10 100 1,000 10,000

Note: A 10-6 failures/hour

2 4 6 8 100 2 4 6 8 1000 2 4 6 8

OPERATING TIME IN HOURS

Figure 5. Probabilities of error for 32-bit, 1 K memory page Notes: 1. Only memory device failures are considered here.
2. A = 10O6failures/hour.

Figure 5 demonstrates that the advantage of single-

error correction declines as operation time increases; Figure 6. Probabilities of error for 32-bit, 64K word memory
that is, the P2e line approaches the Pie line. Figure 5
is based on a 32-bit 1K word page of memory.
Figure 6 may be used to select the system service
interval; it is a plot of the probability of a single-bit
error Ple and the probability of a double-bit error P2e for Table 5. Reliability failure analysis for a 64K 32-bit EDAC memory.
a 64K-word memory with 32 bits of data and single-
error correction. This plot represents the worst-case lower
reliability bound which is obtained when a device failure FAILURE/ X/XT X 100
is considered to mean all bits are bad. X 106 HRS (%)
If the system is serviced after every 500 hours of MEMORY STORAGE DEVICES 2443 91.92
operation (a period corresponding to the MTBF of the MEMORY SUPPORT LOGIC (AND 210 7.9
system without SEC), the probability of a double-bit MISCELLANEOUS COMPONENTS)
error at the 500-hour point is 0.02, or a 2% chance of
failure exists. The probability of a double-bit error at EDAC LOGIC (AND MISCEL- 4.0 0.08
LAN EOUS COM PON ENTS)
1000 hours is 0.056 or 5.6%. A graphical interpretation of
the MTBF improvement for the SEC memory can be
made by comparing (from Figure 6) the points where the Note: XT = 2657
probability of an error is 0.5. One point occurs at 4500 hours
of operation for the memory with SEC and the other point
at 350 hours for the memory without SEC.
Appendix-Binomial Reliability
Reliability of the total memory subsystem A special type of binomial reliability model arises when
m components operate in parallel, but i out of the m
Thus far we have confined our discussion to the storage components need to be functional for the system to
device and its failure rate. We will now examine the operate. This is referred to as a binomial system,
reliability of the memory storage and its support logic. since its reliability expression takes the form of the
A failure analysis summary is given in Table 5 for a 64K- general binomial distribution.12
word 32-bit memory system with EDAC. This system is The binomial system can be used to represent the
implemented with a 1K MOS RAM and Schottky TTL memory system when a word or a page of memory
logic. The failure rates were obtained from MIL-HDBK- depends on m devices operating in parallel. When only a
217B.9 single word of memory is of interest, the device is con-
The example shown in Table 5 demonstrates that the sidered to be only a single bit from the RAM. When
RAM storage device contributes 92% of the system a page of memory is of interest, the device is then con-
failure' rate. Therefore the use of Figure 3 to determine sidered to be the entire RAM. The following binomial
system MTBF and the use of Figure 4 to determine the equations are useful for either a single word or single
reliability improvement result in excellent approxima- increment of memory when the appropriate substitution
tions even though these figures omit the effect of support is made forX:
logic.
Other sources of memory failures must be considered XRAM YXb
in the development of the total memory subsystem re-
liability model. Among these are the control logic, power where X RAM is the RAM failurte rate, X b the bit failure
supply, cooling system, memory controller, back panel, rate, Ya constant relating the bit failure rate to the device
and various interfaces to the central processor. The list failure, and Y is strongly dependent upon the device
can be continued to include any functional module which organization and technology.
causes the memory subsystem to fail. All of these other The probability of a single device operating successfully7
sources of failure can be included in the total memory is given by
subsystem reliability model by the application of the
reliability product rule given in the appendix. M R e-Xt
48 COMPUTER
The probability of a single device failing is given by
Q = (1 -R) = 1-e-x .
The probabilities of success and failure for all combina-
tions of m devices8 is given by

(R+Q)m = Rm+mR(m-l)Q + m(m-1)Rm-2Q2

+ m(m - 1)(m - 2)R(m-3)Q3 NOW
3!
+ m(m 1)(m -2)(m - 3)R(M-4)Q4 11111 AVAILABLE _11
~~~~~4!
-
+
from the IEEE Computer Society
+ ... + Qm = 1.

This expression results from the binomial expansion of Database Management Systems
(R + Q)m.. The first term, POe = Rm, is the probability
of all devices operating successfully. The second term,
= mR(m-l) Q, is the probability of only one defective
INFORMATION TECHNOLOGY SERIES,
Ple
device. The third term, P2e = m(m - 1) R(m-2) Q2)/2! is VOLUME 1
the probability of only two defective devices, and so on.
The last term, Pme = Q m, is the probability of all m de- The Information Technology Series brings together
vices failing.8 in specialized volumes the most valuable papers from
From this expansion the probability of a single-bit
error in the memory increment of m bits is given by past NCC's. Under the direction of series editor Jack
Sherman of Lockheed/Sunnyvale, the large number
= mR (m-1) (1- R)
Pi of papers and wide variety of topics covered in the
conference proceedings will be conveniently grouped
The probability of a double-bit error in the error- and readily available.
coded increment of m + k bits is given by
This first volume, just published by AFIPS Press,
p (m + k)(m + k - l)R(m+K-2)(1 - R)2 contains 16 papers on database management systems.
2e 2 Editor Ben Shneiderman of the University of Mary-
land provides excellent introductions to the areas
Consider the probability of more than one error in the covered: management and utilization perspectives,
increment of memory: implementation and design of database management
systems, query languages, security, integrity, privacy
P>le =1-POe -Ple and concurrency, and specification, simulation and
= 1 - Rm - mR(ml1)(1 - R), translation of database systems.
where R(t = e-t. The reliability function for a single
increment is: Price: Non-members, $15.00; members, $11.25.
R= )=1-P,e=Rm +mR(m-1)(1-R)
- - - - - - - - - - -- - - - - -- -
= Rm(1 - m) + mR(m-)
= cmk(1 -m) + me-(m-1) (increment reliability). Please send the
INFORMATION TECHNOLOGY SERIES,
VOLUME 1
The reliability function for a larger memory matrix of C Non-member, $15.00
N increments is El Member, $11.25
[RN(t)I = [(1 - m)e-m + me-(m-1)k1N
W
El My total payment of $ . .
is enclosed *
where Nis an integer 2 1. El Add $2.00 billing charge and invoice me
Assuming the reliability implications of EDAC are
limited to the page level of memory organization, the IEEE or IEEE Computer Society member no.
total memory subsystem reliability R. is obtained from
the reliability product rule'2 and is given by
L Addcress
Rs(t) = [RI(t)]N n R#(t), -it. State
j=l
Country. Zip
*Caiifornia residents add 6% sales tax
where L is the number of series components which
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October 1976
 The subsystem MTBF5 is References
00 L 1. William W. Peterson and E. J. Weldon, Jr., Error-
MTBF = p;[R1(t)IN fR/t) Correcting Codes, MIT Press, Cambridge, Massachusetts,
1972.
o j~=1
2. Shu Lin, An Introduction to Error Correcting Codes,
Prentice Hall, Englewood Cliffs, New Jersey, 1970.
fo [(1-m)e-mt + me-(m-1)X] n RR(t). 3. Elwyn R. Berlekamp, Algebraic Coding Theory, McGraw
J.=1 Hill, New York, 1968.
Since the MTBF expression is formidable, we will look 4. R. W. Hamming, "Error Detecting and Error Correcting
for an easier means of measuring improvement in Codes," Bell System Technical Journal, 26, Vol. 26, No. 2
(April 1950), pp. 147-160.
reliability. A graphical means of interpreting the MTBF
is given in Figure 6. 5. Frederick J. Hill and Gerald R. Peterson, Introduction
Curves similar to Figure 6 can be generated for any to Switching Theory and Logical Design, John Wiley and
size memory from the curves plotted in Figure 5 by Sons, Inc., New York, 1968.
means of the following method (since the probability of 6. Jack Goldberg, Karl N. Levitt, and John Wensley,
more than two errors is small, we omit them): From "An Organization for a Highly Survivable Memory,"
Figure 5 determine the probability of a double error IEEE-TC, Vol. C-23, No. 7 (July 1974), pp. 693-705.
P2e for a number of time intervals T and construct 7. J. M. Wiesen, "Mathematics of Reliability," Proc., 6th
a table for PI9e. Two or three points are all that is National Symposium on Reliability and Quality Control,
necessary for a log/log graph. The table below for Figure 6 January 1960.
is based on a 32-bit 64K word memory.
8. Bertram L. Amstadter, Reliability Mathematics Funda-
mentals; Practices; Procedures, McGraw Hill, New York,
1971.
T P2e N (1 -P2e) [PP2e N-= 1 -( - P2e) 9. Military Standardization Handbook, Reliability Prediction
of Electronic Equipment, MIL-HDBK-217B, 20 September
1974.
1020 0.001 64 0.038046 0.061954 10. W. C. Carter, D. C. Jessep, and A. Wadia, "Error-Free
4020 0.01 64 0.525582 0.474418 Decoding for Failure-Tolerant Memories," Proc. IEEE
Computer Group Conference, June 1970.
11. W. C. Carter, K. A. Duke, and D. C. Jessep, Jr., "Lookaside
Techniques for Minimum Circuit Memory Translaters,"
IEEE-TC, Vol. C-22, No. 3 (March 1973).
( 0
12. Randall C. Cork, "Reliability with Error-Detecting and
Correcting Codes in Semiconductor Memories," Ph.D.
dissertation, Arizona State University, 1975.

Len Levine is currently a manager in power

supply design at Xerox. Earlier he served as
program manager of the Sigma Nine Com-
puter MOS memory development project.
The author of several papers and holder of
one patent on memory architecture, he has
15 years of experience in analog and digital
systems design. Levine received his BSEE in
June 1961 from the City College of the Uni-
versity of New York.
Ware Myers is a free-lance writer specializing
in computer subject matter. From 1965 until
Xerox withdrew from the computer business
in 1975, he was a member of the Systems
Development Group, Computer Systems
Division, in El Segundo, where he worked
on the development of analog instruments,
I color display stations, a microprogrammed
Proceedings of the 2nd International Conference on controller, and several MOS memories. His
SOFWARE ENMNERNG
(700 pages)
October 13-15, 1976
IiS d; principal contribution to these developments
was the preparation of design specifications, technical descrip-
tions, operating instructions, and reference manuals.
Topics covered in this proceedings include software require- From 1956 to 1965 he was with Consolidated Electro-
ments and specifications, program synthesis, operating dynamics Corp., and its subsidiary, Consolidated Systems
systems, education, performance evaluation, networks, Corp. He has also worked as an instructor and lecturer in en-
design and development, programming languages, modeling, gineering at UCLA.
testing, tools, and case studies. Myers received his BS from Case Institute of Technology
Non-members-$20 Members-$15 in 1935 and his MS from USC in 1951. He is a member of
Tau Beta Pi, ASEE, and the Computer Society.
Use multipurpose order form, p. 75 COM PUTER
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