8051

Microcontrollers
Architecture
 Learning Objectives
 Study Architecture of 8051 Microcontroller
 Understand 8051 Registers
 Learn Pin Diagram and function of each pin
 Study Reset Circuit
 Understand On-Chip ROM Address Range,
RAM Allocation, Memory Bank and SFRs
 Learn concept of Program and Data Memory
 Study I/O Ports and their functions
 Study Stack

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The 8051 Microcontroller
 The 8051 is the first microcontroller of the MCS-51 family
introduced by Intel Corporation at the end of the 1970’s.

 The 8051 family characteristics:

 4K Bytes ROM
 128 Bytes RAM
 two timer/counters (16 bit)
 A serial port
 4 general purpose parallel input/output port
 Interrupt controller
 The 8051 can address 64K of external data memory and 64K of
External program memory.

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Inside 8051 Microcontroller

External interrupts
On-chip Timer/Counter

Interrupt ROM for

On-chip Timer 1 Counter
Control program
RAM Inputs
code Timer 0

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxD RxD
Address/D
ata
4
8051 Registers

A DPTR DPH DPL

B
PC PC (Program counter)
R0
R1
16 bit Registers
R2
R3 A-Accumulator and B register perform arithmetic
operation
R4
R0-R7 are 8 general purpose registers.
R5
DPTR Data Pointer register - Points to data to be
R6 executed.
R7 PC Program counter – Points to next instruction to
be executed

8 bit Registers SP Stack Pointer register-Used for Push and Pop.

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PSW(Flag) Register
CY AC F0 RS1 RS0 OV -- P

CY PSW.7 Carry flag

AC PSW.6 Auxiliary carry flag
-- PSW.5 Available to the user for general purpose
RS1 PSW.4 Register Bank selector bit 1
RS0 PSW.3 Register Bank selector bit 0
OV PSW.2 Overflow flag
-- PSW.1 User define bit
P PSW.0 Parity flag Set/Reset odd/even parity

RS1 RS0 Register Bank Address

0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH
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8051 Pin Diagram

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Pin Description
 Vcc pin 40 Vcc = +5V provides supply voltage to the chip.
 GND pin 20 = ground
 XTAL1 and XTAL2 pins 19,18 Provides external clock.
 Way 1：using a quartz crystal oscillator
 Way 2：using a TTL oscillator
 RST pin 9 Power on reset (input pin, active high)
 Upon applying a high pulse to RST, the microcontroller will reset
and all values in registers will be lost. By applying logical zero to
this pin, the program starts execution from the beginning.
 Way 1 Power-on reset circuit
 Way 2 Power-on reset with key de-bounce

 Reset pulse must be high at least 2 machine cycles.

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Pin Description (cont …)
 /PSEN pin 29  Program Store Enable (output pin, active low)
 Connected to the OE pin of the ROM.
 If external ROM is used for storing program then it has a logic-0 value every time the
microcontroller reads a byte from memory.
 ALE pin 30  Address latch Enable (output pin, active high)
 8051 port 0 provides both address and data.
 The ALE signal is used for de-multiplexing the address and data bus.
 /EA  pin 31 External Access (Active low)
 The /EA pin is connected to GND to indicate the code is stored in external memory.
 By applying logic zero to this pin, port P0 and port P2 are used for data and address
transmission to external memory.
 It means if program is written into internal ROM of the microcontroller, will not be executed,
 the program written to external ROM will be used instead.

 /PSEN and ALE are used for external ROM.

 For 8051, /EA pin is connected to Vcc.
 By applying logic one to the EA pin, the microcontroller will use both memories, first internal and afterwards external,
up to end of address space.

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Crystal Connection
 Using a quartz crystal  Using a TTL oscillator
oscillator typically of
 XTAL2 is unconnected
11.0592MHz
 We can observe the frequency
on the XTAL2 pin.

C2
XTAL2 N XTAL2
30pF C

C1 EXTERNAL
XTAL1 OSCILLATOR XTAL1
30pF SIGNAL

GND GND

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RESET Value of Registers & Ckt

Power on Power on Reset

Reset with Debounce
31
On-Chip ROM/RAM Address Range
 8051 4K Internal ROM
 Address range 0000H to 0FFFH
 8052 8K Internal ROM
 Address range 0000H to 1FFFH

 RAM 128 bytes Address range 00H to 7FH

 Bank 0 – 00H to 07H, Bank 1 – 08H to 0FH
 Bank 2 – 10H to 17H, Bank 3 – 18H to 1FH
 Bit addressable area – 20H to 2FH 128 bits
 General purpose RAM – 30H to 7FH (80 locations)

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8051 RAM Allocation
1F

Bank 3
18
17

Bank 2
10
0F

Stack/
08
Bank 1
07 R7
06 R6
05 R5
04 R4
03 R3 Bank 0
02 R2
01 R1
00 R0

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15
Bit Addressable Memory
2F 7F 78
20h – 2Fh (16 locations X
2E
8-bits = 128 bits)
2D
2C
2B
Bit addressing:
2A mov C, 1Ah
29 or
28 mov C, 23h.2
27
26
25
24
23
1A
22
21 10

20 0F 08

07 06 05 04 03 02 01 00

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SFR (Special function register)
 Four I/O (Input/Output) ports
 P0, P1, P2, P3
 Timer Registers
 TH0 TL0 16-bit timer register for timer 0 to hold count
 TH1 TL1 16-bit timer register for timer 1 to hold count
 TMOD – Timer mode control register
 TCON – Timer control register
 Serial Communication Registers
 SCON Serial Control register -controls the baud rate of the serial port
 SBUF Serial Buffer register
 PCON – Power Control register
 Interrupt Register
 IE – Interrupt enable control
 IP - Interrupt Priority control

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SFRs

16
Program Memory (ROM)

18
External ROM Connection
PSEN OE
ALE G 74LS373 OC
P0.0 D A0
P0.7 A7

D0
D7
EA

P2.0 A8
P2.7 A15

8051 ROM
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Data Memory

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4 I/O Ports
 Ports P0,P1,P2,P3 Each has 8 pins and are Bidirectional

 Initially configured as output

 To configure as an input port
 MOV A, #0FFH To configure port 1 as input port
 MOV P1,A
 Port 0  I/O Port and Can be configured as AD0 – AD7
 Port 1  I/O Port
 Port 2  I/O Port and Can be configured as A8-A15
 Port 3  I/O Port and alternate functions

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Port 3: I/O, No Pull-up Resistors

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Port Bit latches & I/O buffers

(a) Port 0, (b) Port 1, (c) Port 2, (d) Port 3

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Port 0 Configuration
Port 0: I/O, Open Drain

Vcc
10 K

P0.0

Port
8051 P0.1
P0.2
89C5 P0.3
1 P0.4 0
P0.5
P0.6
P0.7

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Hardware Structureof I/O Pin

Read latch Vcc

TB2
Load(L1)

Internal CPU D Q P1.X

bus P1.X pin

Write to latch Clk Q M1

TB1
Read pin

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 Each pin of I/O ports
 Internally connected to CPU bus
 A D latch store the value of this pin
 Write to latch＝1：write data into the D latch
 2 Tri-state buffer：
 TB1: controlled by “Read pin”
 Read pin＝1：really read the data present at the pin
 TB2: controlled by “Read latch”
 Read latch＝1：read value from internal latch
 A transistor M1 gate

 Gate=0: open
 Gate=1: close

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Writing“1” to Output Pin P1.X

Read latch Vcc

TB2
Load(L1) 2. output pin is
1. write a 1 to the pin Vcc
D Q 1 P1.X
Internal CPU
bus P1.X pin

Clk 0 output 1
Write to latch Q M1

TB1
Read pin

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Writing“0” to Output Pin P1.X

Read latch Vcc

TB2
Load(L1) 2.
2. output pin is
1. write a 0 to the pin ground
D Q 0 P1.X
Internal CPU
bus P1. X pin

Clk 1 output 0
Write to latch Q M1

TB1
Read pin

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Reading “High” at Input Pin
Read latch Vcc 2. MOVA,P1
TB2 external
ext pin=High
1. write a 1 to the pin MOV Load(L1)
P1,#0FFH
1 1
Internal CPU bus D Q P1.X pin
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1

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Reading “Low” at Input Pin

Read latch Vcc 2. MOVA,P1

TB2
1. write a 1 to the pin Load(L1) ext
external pin=Low
MOV P1,#0FFH
1 0
Internal CPU bus D Q P1.X pin
P1.X

0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1

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Block Diagram
8051 Block Diagram
A (Accumulator)
B
PSW (Program Status Word)
SP (Stack Pointer)
PC (Program Counter)
DPTR (Data Pointer)

Used in assembler
instructions

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34
35
Pin Diagram with Alternate Function

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 8051 37 P0.2(AD2)
P0.3(AD3)
P1.4 5 36
P1.5 6 (8031) 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RX 10 31 EA/VPP
D)P 11 30 ALE/PROG
3.0 12 29 PSEN
(INT1)P3.3
(TX 13 28 P2.7(A15)
(T0)P3.4
D)P 14 27 P2.6(A14)
(T1)P3.5
3.1 15 26 P2.5(A13)
(WR)P3.6
(I 16 25 P2.4(A12)
NT0)
(RD)P3.7 17 24 P2.3(A11)
P3.2
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

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