PD - 94501

AUTOMOTIVE MOSFET
IRLR2908
IRLU2908
HEXFET® Power MOSFET
Features
l Advanced Process Technology D
l Ultra Low On-Resistance VDSS = 80V
l Dynamic dv/dt Rating
l 175°C Operating Temperature RDS(on) = 28mΩ
l Fast Switching G
l Repetitive Avalanche Allowed up to Tjmax
ID = 30A
S
Description
Specifically designed for Automotive applications, this HEXFET ® Power MOSFET
utilizes the latest processing techniques to achieve extremely low on-resistance per silicon
area. Additional features of this HEXFET power MOSFET are a 175°C junction operating
temperature, low RθJC, fast switching speed and improved repetitive avalanche rating.
These features combine to make this design an extremely efficient and reliable device for
use in Automotive applications and a wide variety of other applications.\

The D-Pak is designed for surface mounting using vapor phase, infrared, or wave
soldering techniques. The straight lead version (IRFU series) is for through-hole mounting D-Pak I-Pak
applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount IRLR2908 IRLU2908
applications.
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 39 A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (See Fig. 9) 28
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited) 30
IDM Pulsed Drain Current c 150
PD @TC = 25°C Maximum Power Dissipation 120 W
Linear Derating Factor 0.77 W/°C
VGS Gate-to-Source Voltage ± 16 V
EAS Single Pulse Avalanche Energy (Thermally Limited) d 180 mJ
EAS (tested) Single Pulse Avalanche Energy Tested Value i 250
IAR Avalanche Current c See Fig.12a,12b,15,16 A
EAR Repetitive Avalanche Energyh mJ
dv/dt Peak Diode Recovery dv/dt e 2.3 V/ns
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.3 °C/W
RθJA Junction-to-Ambient (PCB Mount) j ––– 40
RθJA Junction-to-Ambient ––– 110
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IRLR2908/IRLU2908
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 80 ––– ––– V VGS = 0V, ID = 250µA
∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.085 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 22.5 28 mΩ VGS = 10V, ID = 23A f
––– 25 30 VGS = 4.5V, ID = 20A f
VGS(th) Gate Threshold Voltage 1.0 ––– 2.5 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 35 ––– ––– S VDS = 25V, ID = 23A
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 80V, VGS = 0V
––– ––– 250 VDS = 80V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA VGS = 16V
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -16V
Qg Total Gate Charge ––– 22 33 nC ID = 23A
Qgs Gate-to-Source Charge ––– 6.0 9.1 VDS = 64V
Qgd Gate-to-Drain ("Miller") Charge ––– 11 17 VGS = 4.5V
td(on) Turn-On Delay Time ––– 12 ––– ns VDD = 40V
tr Rise Time ––– 95 ––– ID = 23A
td(off) Turn-Off Delay Time ––– 36 ––– RG = 8.3Ω
tf Fall Time ––– 55 ––– VGS = 4.5V f
LD Internal Drain Inductance ––– 4.5 ––– nH Between lead, D

6mm (0.25in.)
G
LS Internal Source Inductance ––– 7.5 ––– from package
S
and center of die contact
Ciss Input Capacitance ––– 1890 ––– pF VGS = 0V
Coss Output Capacitance ––– 260 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 35 ––– ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 1920 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 170 ––– VGS = 0V, VDS = 64V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 310 ––– VGS = 0V, VDS = 0V to 64V

Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 39 MOSFET symbol D

(Body Diode) A showing the

ISM Pulsed Source Current ––– ––– 150 integral reverse G

(Body Diode) c p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 23A, VGS = 0V f
trr Reverse Recovery Time ––– 75 110 ns TJ = 25°C, IF = 23A, VDD = 25V
Qrr Reverse Recovery Charge ––– 210 310 nC di/dt = 100A/µs f
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes  through ˆ are on page 11

HEXFET® is a registered trademark of International Rectifier.
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 IRLR2908/IRLU2908

1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
4.5V 4.5V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

100 4.0V 4.0V

3.5V 100 3.5V
3.0V 3.0V
2.7V 2.7V
BOTTOM 2.5V BOTTOM 2.5V
10

2.5V 10 2.5V

1
0.1

20µs PULSE WIDTH 20µs PULSE WIDTH

Tj = 25°C Tj = 175°C
0.01 0.1
0.01 0.1 1 10 100 0.01 0.1 1 10 100

VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000
60

TJ = 25°C
ID, Drain-to-Source Current (Α)

G FS , Forward Transconductance (S)

50

100
40
T J = 175°C
T J = 175°C
30
T J = 25°C
10
20

VDS = 25V
10
20µs PULSE WIDTH VDS = 10V
1 20µs PULSE WIDTH
2 3 4 5 0
0 10 20 30 40 50 60
VGS , Gate-to-Source Voltage (V)
ID, Drain-to-Source Current (A)

Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance

vs. Drain Current
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 IRLR2908/IRLU2908

100000 5.0
VGS = 0V, f = 1 MHZ
ID= 23A
Ciss = C gs + Cgd, C ds SHORTED VDS= 64V
Crss = Cgd

VGS , Gate-to-Source Voltage (V)

VDS= 40V
Coss = Cds + Cgd
4.0
10000 VDS= 16V
C, Capacitance(pF)

Ciss 3.0

1000
Coss 2.0

100
Crss 1.0

10 0.0
1 10 100 0 5 10 15 20 25
VDS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Fig 6. Typical Gate Charge vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000.00 1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)

100.00 100
T J = 175°C

100µsec
10.00 10

1msec

T J = 25°C
1.00 1
Tc = 25°C 10msec
Tj = 175°C
VGS = 0V Single Pulse
0.10 0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1 10 100 1000
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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 IRLR2908/IRLU2908

40 3.0
ID = 38A

RDS(on) , Drain-to-Source On Resistance

35 VGS = 4.5V
2.5
30
ID, Drain Current (A)

2.0
25

(Normalized)
20 1.5

15
1.0
10
0.5
5

0 0.0
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
T C , Case Temperature (°C) T J , Junction Temperature (°C)

Fig 9. Maximum Drain Current vs. Fig 10. Normalized On-Resistance

Case Temperature vs. Temperature

10
Thermal Response ( Z thJC )

1
D = 0.50
0.20
0.10
0.1
0.05
0.02 P DM
0.01
t1
0.01
SINGLE PULSE t2
( THERMAL RESPONSE ) Notes:
1. Duty factor D = t1/ t 2
2. Peak T J = P DM x Z thJC +T C
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1 1

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRLR2908/IRLU2908

400
15V
ID

EAS , Single Pulse Avalanche Energy (mJ)

TOP 9.3A
L DRIVER 16A
VDS 300 BOTTOM 23A

RG D.U.T +
V
- DD
IAS A 200
20V
VGS
tp 0.01Ω

Fig 12a. Unclamped Inductive Test Circuit 100

V(BR)DSS
tp

0
25 50 75 100 125 150 175
Starting T J , Junction Temperature (°C)

I AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
vs. Drain Current
QG

10 V
QGS QGD 2.5
VGS(th) Gate threshold Voltage (V)

VG
2.0

Charge
Fig 13a. Basic Gate Charge Waveform 1.5
Current Regulator ID = 250µA
Same Type as D.U.T.

50KΩ 1.0
12V .2µF
.3µF

+
V
D.U.T. - DS
0.5
VGS -75 -50 -25 0 25 50 75 100 125 150 175 200
3mA T J , Temperature ( °C )

IG ID
Current Sampling Resistors

Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage vs. Temperature
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 IRLR2908/IRLU2908

1000
Duty Cycle = Single Pulse

100 Allowed avalanche Current vs

Avalanche Current (A)

avalanche pulsewidth, tav

0.01
assuming ∆ Tj = 25°C due to
avalanche losses
10 0.05
0.10

0.1
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)

Fig 15. Typical Avalanche Current vs.Pulsewidth

200 Notes on Repetitive Avalanche Curves , Figures 15, 16:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 10% Duty Cycle 1. Avalanche failures assumption:
ID = 23A Purely a thermal phenomenon and failure occurs at a
EAR , Avalanche Energy (mJ)

150 temperature far in excess of T jmax. This is validated for

every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
100
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
50 voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
0 tav = Average time in avalanche.
25 50 75 100 125 150 175 D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
Starting T J , Junction Temperature (°C)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Fig 16. Maximum Avalanche Energy Iav = 2DT/ [1.3·BV·Zth]
vs. Temperature EAS (AR) = PD (ave)·tav
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IRLR2908/IRLU2908

Driver Gate Drive

D.U.T Period D=
P.W.
Period
+ P.W.

ƒ
*
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance
D.U.T. ISD Waveform
Current Transformer
+
‚ Reverse

-
„ +
Recovery
Current
Body Diode Forward
Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

RD
VDS

VGS
D.U.T.
RG
+
-VDD

10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

Fig 18a. Switching Time Test Circuit

VDS
90%

10%
VGS
td(on) tr t d(off) tf

Fig 18b. Switching Time Waveforms

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 IRLR2908/IRLU2908
TO-252AA (D-Pak) Package Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
6.73 (.265) 2.19 (.086)
6.35 (.250) 1.14 (.045)
0.89 (.035)
-A-
5.46 (.215) 1.27 (.050) 0.58 (.023)
5.21 (.205) 0.88 (.035) 0.46 (.018)

6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235) 10.42 (.410)
1.02 (.040) 9.40 (.370) LEAD ASSIGNMENTS
1.64 (.025) 1 2 3
1 - GATE
0.51 (.020) 2 - DRAIN
-B- MIN. 3 - SOURCE
1.52 (.060) 4 - DRAIN
1.15 (.045)
0.89 (.035)
3X
0.64 (.025) 0.58 (.023)
1.14 (.045) 0.46 (.018)
2X 0.25 (.010) M A M B
0.76 (.030)

2.28 (.090) NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
4.57 (.180) 2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).

TO-252AA (D-Pak) Part Marking Information

Notes : T his part marking information applies to devices produced before 02/26/2001
EXAMPLE: THIS IS AN IRF R120
WITH ASSEMBLY
LOT CODE 9U1P INTERNATIONAL DATE CODE
RECTIFIER IRFU120
YEAR = 0
LOGO 016
WEEK = 16
9U 1P

AS SEMBLY
LOT CODE

Notes: T his part marking information applies to devices produced after 02/26/2001

EXAMPLE: T HIS IS AN IRFR120

PART NUMBER
WIT H AS S EMBLY INT ERNAT IONAL
LOT CODE 1234 RECT IFIER IRFU120 DAT E CODE
AS S EMBLED ON WW 16, 1999 LOGO 916A YEAR 9 = 1999
IN THE ASS EMBLY LINE "A" 12 34 WEEK 16
LINE A
AS S EMBLY
LOT CODE

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IRLR2908/IRLU2908
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265) 2.38 (.094)
6.35 (.250) 2.19 (.086)
-A-
1.27 (.050) 0.58 (.023)
5.46 (.215)
0.88 (.035) 0.46 (.018)
5.21 (.205)
LEAD ASSIGNMENTS
4 1 - GATE
6.45 (.245) 2 - DRAIN
5.68 (.224) 3 - SOURCE
1.52 (.060) 6.22 (.245) 4 - DRAIN
1.15 (.045) 5.97 (.235)

1 2 3

-B- NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2.28 (.090) 9.65 (.380) 2 CONTROLLING DIMENSION : INCH.
1.91 (.075) 8.89 (.350) 3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).

1.14 (.045) 1.14 (.045)

3X 0.89 (.035)
0.76 (.030) 3X 0.89 (.035)
0.64 (.025)

2.28 (.090) 0.25 (.010) M A M B 0.58 (.023)

0.46 (.018)
2X

I-Pak (TO-251AA) Part Marking Information

Notes : T his part marking information applies to devices produced before 02/26/2001

EXAMPLE: T HIS IS AN IRFR120

INTERNATIONAL DATE CODE
WITH AS S EMBLY
RECT IFIER IRFU120
LOT CODE 9U1P YEAR = 0
LOGO 016
WEEK = 16
9U 1P

AS SEMBLY
LOT CODE

Notes: T his part marking information applies to devices produced after 02/26/2001

EXAMPLE: T HIS IS AN IRFR120 PART NUMBER

INT ERNATIONAL
WITH AS SEMBLY
RECT IFIER IRFU120 DAT E CODE
LOT CODE 5678
LOGO 919A YEAR 9 = 1999
AS S EMBLED ON WW 19, 1999
56 78 WEEK 19
IN T HE ASS EMBLY LINE "A"
LINE A
ASS EMBLY
LOT CODE

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 IRLR2908/IRLU2908
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) 8.1 ( .318 )

FEED DIRECTION FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
 Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11).
‚ Limited by TJmax, starting TJ = 25°C, L = 0.71mH, RG = 25Ω, IAS = 23A, VGS =10V. Part not recommended for use above
this value.
ƒ ISD ≤ 23A, di/dt ≤ 400A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
„ Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
… Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS .
† Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.
‡ This value determined from sample failure population. 100% tested to this value in production.
ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer
to application note #AN-994.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 02/03
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