2016 IEEE First International Conference on Control, Measurement and Instrumentation (CMI)

Implementation of a PID control PWM Module on

Altera DE0 Kit Using FPGA
Ruchi V. Jain M. V. Aware A. S. Junghare
Junior Research Fellow Professor Associate Professor
Department of Electrical Engineering Department of Electrical Engineering Department of Electrical Engineering
VNIT Nagpur, India VNIT Nagpur, India VNIT Nagpur, India
ruchi8397@gmail.com mvaware@eee.vnit.ac.in asjunghare@eee.vnit.ac.in

Abstract--The main aim of this paper is to design PID control The overall structure of the system is shown in Fig. 1.
PWM module using field programmable gate array (FPGA) Digital PID controller block and digital PWM block are
technology. FPGA based realization offers high speed, complex implemented on FPGA. This scheme can work for any plant
functionality, consume less power, and provides parallel like DC motor and DC-DC converter.
processing. In this paper, we have implemented PID control PWM
module on programmable logic design software Quartus II and
verified on DE0 Nano Board (Cyclone IV FPGA family of
company Altera). Signal Tap II analyzer and RTL viewer are
used for analyzing and debugging the design. For Proper timing
constraint and clock arrangement, Time Quest analyzer is used.
The simulation and hardware results shows that implementation
with FPGA has some advantages such as flexible design, high
reliability and high speed.

Keywords--Digital PID Controller; Digital PWM module; Quartus

II; DE0 Nano Kit. Figure 1. Block diagram of closed loop system

I. INTRODUCTION III. DIGITAL PID CONTROLLER

Proportional Integral Derivative (PID) based scheme is A conventional PID controller is shown in Fig. 2. The value
widely preferred in industries because of their simple structure of , are require to tune for controlling the plant.
and ease of realization. PID controller along with PWM module The conventional PID controller equation is given in (1).
is used for speed control of DC motor and current - voltage
control of DC –DC converter [1]. ( )= ( )+ ( )+ ( ) (1)
For digital implementation microcontrollers are used, but Equation 1 is described in digital form in (2).
FPGA has flexibility, increasingly better power efficiency and
decreasing prices. FPGA’s are flexible; you can add/subtract ( ) = ( − 1) + 0 ∗ ( ) + 1 ∗ ( − 1) + 2
functionality as required. Analog controllers work on low ∗ ( − 2) (2)
frequency and occupy more space. For analog controller design, Where coefficients 0 , 1 , 2 are given in (3), (4), and (5)
while changing controller parameters, we have to implement the ∗
whole circuit again. In FPGA, there is no fixed hardware 0 = + + (3)
structure, so it is defined by user [2] [3]. 2
∗ 2
In this paper, the PID control PWM module is designed on 1 = − − (4)
2
Altera Quartus II software. Various tools such as RTL viewer,
Time Quest analyzer and Signal Tap II analyzer are used for 2 = (5)
verification of the design and timing analysis. The appropriate Here, T is a sampling period.
design is downloaded on DE0 Nano Kit for hardware
verification. For the realization of PID difference equation on FPGA, it
must be stored all the error samples (0), (1), … ( − 1),
The paper is organized in the following way. Section 2 ( − 2). PID output at each clock cycle depends on present
describes the complete close loop structure of the system. input sample ( ), previous samples ( − 1), ( − 2) and
Section 3 deals with digital PID controller. Section 4 describes previous output sample ( − 1). Hence it is a recursive type
digital PWM module. In section 5, design is implemented on of structure. At each clock cycle, ( ), ( − 1), ( − 2)
Quartus II software which is loaded in DE0 kit for hardware
and ( − 1) are updated. Implement equation (2) on FPGA
verification. The paper ends with conclusion in section 6.
using registers, multipliers and adders as shown in Fig. 3. In
II. STRUCTURE OF CLOSED LOOP CONTROL this algorithm, all values are binary [3] [4]. In stage 2,
SYSTEM subtractor block is used to generate error signal for PID
controller.

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 2016 IEEE First International Conference on Control, Measurement and Instrumentation (CMI)
Figure 2. Conventional PID controller
The control signal can be saturated into a minimum (0) or
maximum value (4000). Since the output is restricted to 12 bits
only, hence the range of output should be 0 to 4000. We have
used bit conversion block which has implemented anti-windup
algorithm to avoid the condition of saturation and overflow.
IV. PWM MODULE
The PWM principle is widely used in power electronics
applications and motion control [5]. The PWM signal is
generated by comparing reference voltage with sawtooth wave
of constant amplitude and frequency. For digital
implementation of PWM, we have used register, counter and
comparator. The 12 bit counter is used to generate the sawtooth
signal. Counter counts from 0 (00000000000)2 to maximum
value 4000 (11110100000)2, when counter arrives to max
value, it returns to 0. The duty cycle is in the range of 0 ≤ D ≤
4000/4096=97.65%. At each clock cycle comparator compares
the output of register, A with counter output. If A>B,
comparator gives logic ‘1’, for A<B it gives logic ‘0’. Here,
pulses of 50 KHz are generated. The PWM output frequency
depends on maximum count value and counter operating
frequency. The block diagram of PWM module is shown in
Fig. 4.
= (6)
( + 1)
Figure 3. Architecture of a digital PID module
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Figure 4. Digital PWM module
200
= = 49.9875
(4000 + 1)
≈ 50
V. SIMULATION AND HARDWARE
IMPLEMENTATION
A. DE0 Nano Board (Altera Cyclone IV EP4CE22F17C6N
FPGA)
The DE0-Nano board is a compact-sized FPGA
development board. [6]. It consists of 2 pushbuttons, 8 users
LED and 4 dip-switches. It includes 8 channel 12 bit ADC, 3
axis accelerometer device and three expansion headers. The
DE0 Nano board is shown in Fig. 5.
B. Analog Input Interface
To connect with real world, the DE0-Nano contains an
ADC128S022 analog to digital converter. It converts analog
input signal into 12 bit digital signal. It consists of 8 analog
input channels. The conversion rate is from 50ksps to 200ksps.
The ADC reads the input signal from real world and converts it
into a 12 bit digital output. The analog input voltage range is
from 0 to 3.3V [7]. The ADC interfacing with FPGA and 2x13
GPIO header is shown in Fig. 6.
 2016 IEEE First International Conference on Control, Measurement and Instrumentation (CMI)
Figure 5. DE0 Nano kit
Figure 6. ADC Converter Interfacing
C. Digital Clock Manager
The DE0-Nano board includes a 50 MHz oscillator. The
oscillator is connected directly to a dedicated clock input pin of
the Cyclone IV E FPGA. The 50MHz clock input can be used
as a source clock to drive the phase lock loops (PLL) circuit. In
our design, we have used three frequency divider block as
shown in Fig. 7. ADC samples data at the rate of 0.8 MHz to
3.3 MHz. ADC requires 16 clock cycles to give 12 bit output
data. Accordingly, frequency of counter, comparator and PID
controller is calculated in Table I.
= (7)
16
Figure 7. Clock Arrangement Module
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TABLE I. CLOCK ARRANGEMENT OF DIFFERENT BLOCKS
Frequency divider Ratio Duty Cycle O/P Frequency
Frequency divider1 2/125 50% 0.8 MHz
Frequency divider 2 1/1000 50% 50 KHz
Frequency divider 3 4/1 50% 200 MHz
An effective way of determining the correctness of a logic
circuit is to simulate its behaviour. We have developed VHDL
code for PID and PWM module on Quartus II. Megawizard
Plug-in Manager tool can be used to enter schematic design on
Quartus II. The entered schematic diagram is processed by
several Quartus II tools such as Time Quest analyzer, Signal
Tap analyzer to analyze the file, synthesize the circuit and
generate an implementation of it for the target device DE0.
Time Quest analyzer analyzes timing paths in the design,
calculates propagation delay along each path and checks for
violations in timing constraints [8]. Signal Tap Analyzer
captures signal data and stored in the device memory [9]. It
does not require any external probes and equipment to analyze
the design and capture the state of internal I/O ports. After the
initial synthesis, a register transfer level (RTL) view of a
designed circuit, generated. It can be seen by using the RTL
Viewer. RTL schematic view of designed circuit is shown in
Fig. 8. Fig. 9 shows simulation results of PID controller
module on Simulation Waveform Editor. Here we have taken
0 = 1 = 2 = 1.These tools are controlled by the
application program called the Compiler. The compilation
report is shown below in compilation report. After compilation,
the design has been entered into DE0 board for hardware
verification. We have taken different error signals and check
PID module for = 2, = 3, = 1 on DSO as shown in
Fig. 10. Sampling time T is 0.00002 sec. We can vary the
tuning parameters according to plant.
Compilation Report
Quartus II 32-bit Version 13.0.
Revision Name – PID PWM Module
Top-level Entity Name – PID PWM Module
Family - Cyclone IV E
Device - EP4CE22F17C6
Timing Models- Final
Total logic elements - 1,030 / 22,320 (5 %)
Total combinational functions - 766 / 22,320 (3 %)
Dedicated logic registers - 766 / 22,320 (3 %)
Total registers - 766
Total pins - 25 / 154 (16 %)
Total virtual pins - 0
Total memory bits - 26,682 / 608,256 (4 %)
Embedded Multiplier 9-bit elements - 0 / 132 (0 %)
TOTAL PLL - 1/4 (25%)
2016 IEEE First International Conference on Control, Measurement and Instrumentation (CMI)

Figure 8. RTL Schematic View of PID-PWM Module

Figure 9. PID Controller Output on Simulation Waveform Editor

Figure 10. PID Control signals for (1) Sinusoidal signal (2) Ramp signal (3) Square signal. (4) Generated PWM Signal

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 2016 IEEE First International Conference on Control, Measurement and Instrumentation (CMI)

[3] Joao Lima, Ricardo Menotti, Joao M. P. Cardoso, and Eduardo Marques,
VI. CONCLUSION “A methodology to design FPGA based PID controllers,” 2006 IEEE
The design and implementation of the digital based PID International Conference on Systems, Man, and Cybernetics October 8-
control PWM module on FPGA is presented in this paper. We 11, 2006, Taipei, Taiwan.
[4] Sirin AKKAYA, Onur Akbati, and Haluk Görgün, “Multiple closed loop
have designed generalized digital PID-PWM module.
system control with digital PID controller using FPGA,” 2014 IEEE
According to plant, we can change the parameters
International Conference on Control, Decision and Information
{ , , , } to achieve the desired output. Application of
Technologies.
FPGA structure is very suitable for high speed processes. [5] Jakirhusen I. Tamboli, Prof Jagtap, “Pulse width modulation
Though it is high speed processor, we can set the proper implementation using FPGA and CPLD ICs,” International Journal of
sampling rate and control the speed of operation. This approach Scientific & Engineering Research vol 3, Issue 8, August-2012.
of design is practically tested and found feasible. [6] DE0 Nano User Manual. Available: http://www.terasic.com
[7] DE0 Nano ADC Altera University Program. Available:
ACKNOWLEDGMENT http://www.altera.com
This paper is supported by BRNS Project No [BRNS- [8] Time Quest Timing Analyzer Quick Start Tutorial. Available:
(No.2012/36/69/BRNS)]. http://www.altera.com
[9] Signal Tap II Analyzer Quick Start Tutorial. Available:
REFERENCES http://www.altera.com
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