1320 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO.

5, MAY 2012

Simulation of Fabricated 20-nm Schottky Barrier

MOSFETs on SOI: Impact of Barrier Lowering
J. L. Padilla, L. Knoll, F. Gámiz, Senior Member, IEEE, Q. T. Zhao, Member, IEEE,
A. Godoy, Member, IEEE, and S. Mantl, Member, IEEE

Abstract—In this paper, we develop a procedure to include in

device simulators the barrier lowering (BL) effects that appear
in the drain and source contacts of Schottky barrier MOSFETs
(SB-MOSFETs). We have checked it reproducing experimen-
tal results of 20-nm gate-length SB-MOSFETs with NiSi and
epitaxial NiSi2 S/D contacts. We make use of the Wentzel–
Kramers–Brillouin (WKB) approximation to get the tunneling
probabilities through the lowered barriers along with an appropri-
ate calibration of the effective masses which compensates to a large
extent the lack of accuracy of the WKB model when diverting
from the “wide barrier” assumption. A vertical discretization of
the channel is also included to allow the barrier height depen-
dence on the depth inside the channel. We show that corrected Fig. 1. Schematic cross section (not to scale) of the NiSi/epitaxial NiSi2
simulations including this effect describe in a very accurate way SB-MOSFETs simulated in this work along with their dimensions.
the behavior of these devices. We also check that the striking
experimental observation of tunneling current reduction at very
short gate lengths is also obtained, in contrast to the scaling ical channel lengths taking advantage of the abruptness of
behavior of conventional MOSFETs. We successfully explain this metal–semiconductor junctions. These contacts should there-
fact invoking the modification of the potential inside the channel, fore increase the performance in short-channel devices. How-
i.e., the overlapping of source and drain potential profiles leads to ever, it has been recently found [1] that the overlapping of
an increase of its total value even though BL mechanisms tend to source and drain potential profiles increases the potential inside
decrease it in the vicinity of the contacts.
the channel thus limiting the carrier injection from the source
Index Terms—Barrier lowering, metallic source/drain (S/D), and degrading the I–V characteristics. Simulated results pre-
nanotechnology, Schottky barriers, semiconductor device model- sented in this paper also show this trend.
ing, Wentzel–Kramers–Brillouin (WKB) method.
In conventional SB-MOSFETs, the metal–semiconductor
junction is formed by depositing a silicide instead of a metal
I. I NTRODUCTION
since the former is easier to form with a silicon-compatible

D URING THE LAST years, a renewed interest has

been observed in Schottky barrier (SB) MOSFETs
(SB-MOSFETs). These devices differ from conventional
MOSFETs because they introduce metallic contacts in both
source and drain in place of conventional doped semiconduc-
tor regions creating rectifying metal–semiconductor junctions
or SBs. The main benefits expected from these devices are
the reduction of source/drain resistance, an increased immu-
nity to process variation due to the elimination of dopants
in the contacts, or the possibility to define very short phys-
Manuscript received October 21, 2011; revised December 20, 2011 and
January 13, 2012; accepted February 2, 2012. Date of publication March 9,
2012; date of current version April 25, 2012. This work was supported in
part by the Junta de Andalucía under Research Project TIC2010-6902 and
in part by the Spanish Government under Research Projects FIS2008-05805
and TEC2008-06758-C02-01. The review of this paper was arranged by Editor
Y. Momiyama.
J. L. Padilla, F. Gámiz, and A. Godoy are with the Departamento de
Electrónica y Tecnología de los Computadores, Universidad de Granada, 18071
Granada, Spain (e-mail: jluispt@ugr.es).
L. Knoll, Q. T. Zhao, and S. Mantl are with the Peter Grünberg Institute
9 (PGI 9-IT), Forschungszentrum Jülich, 52425 Jülich, Germany.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2012.2187657
process. Some common silicides used for this purpose are PtSi,
NiSi, Ni1−x Ptx Si, epitaxial NiSi2 , and rare earth silicides such
as ErSi, ErSi2 , or DySi2−x . Large barrier heights (BHs) of some
silicides produce lower OFF-state thermal leakage but limit the
drive current and subthreshold swing [2], [3]. A convenient
choice would include a silicide presenting low inversion-mode
BH as a key issue for a good ON-state while trying to minimize
the OFF-state current through a thin-body region or a high-
body doping. For n-channel SB-MOSFETs, rare earth silicides
have the lowest electron BH among the known silicides [4]
but also tend to be very sensitive to interface state density
[5]–[10] and present large inhomogeneities at the rare earth
silicide/Si contacts causing larger values of Ioff . For p-channel
SB-MOSFETs, however, platinum silicide is preferred because
of its very low BH for holes [11].
In this paper, we have studied the behavior and performance
of SB-MOSFETs on SOI with NiSi and epitaxial NiSi2 S/D
by comparing experimental results and simulated data. These
silicides have BH for electrons of φbn = 0.65 eV and φbn =
0.37 eV, respectively, which leads to an ambipolar switching
behavior, which is greater in the case of NiSi.
The devices studied in this work were fabricated at
Forschungszentrum Jülich [12] and are shown in Fig. 1. More

0018-9383/$31.00 © 2012 IEEE

PADILLA et al.: SIMULATION OF FABRICATED 20-nm SCHOTTKY BARRIER MOSFETs ON SOI
Fig. 2. Modification of the height and shape of SB for electrons flow due to
image force and DL.
details of the fabrication process are given hereinafter. We
perform simulations that reproduce the main aspects of gate
length scaling investigating the importance of technological
parameters such as the underlap that appears between the
silicide and the gate (increasing the parasitic resistance) or the
barrier lowering (BL) processes that affect the BH producing
higher currents for increasing gate voltages.
In Section II, we summarize the main mechanisms con-
cerning BL in SB. In Section III, we present an intermediate
approach that allows to keep using the Wentzel–Kramers–
Brillouin (WKB) approximation (and, therefore, existing de-
vice simulators). In Section IV, fabrication details of the studied
devices are given. Section V is devoted to the discussion
and comparison between experimental and simulated results.
Finally, in Section VI, the main conclusions are drawn.
II. BARRIER L OWERING IN S CHOTTKY C ONTACTS
There exist two contributions appearing in Schottky contacts
that alter the shape and height of the barrier, as shown for
the case of electrons in Fig. 2. The first is a dynamic effect
consequence of the presence of charge carriers in the vicinity
of a metallic surface. It is called image force lowering (IFL)
because the classical treatment to account for it implies the
presence of an image potential acting upon the carriers. The
expression describing this mechanism is given by [13]
 and slightly modified in [23]. We use Silvaco ATLAS with field
qFx (y)
Δφb,ifl = (1)
4πs
where Fx (y) is the electric field perpendicular to the interface
and the y-direction goes down vertically from the top of the
channel.
The second one is called dipole lowering (DL). Originally,
this effect was explained in terms of interfacial states be-
tween the semiconductor and the metal due to an oxide layer
appearing between them [14]–[16]. However, this effect also
appears in atomically clean and abrupt interfaces indicating
that DL has another contribution coming from the quantum-
mechanical solution to the equilibrium charge distribution of
an ideal metal–semiconductor junction, which shows a cer-
tain penetration—the so-called Heine tails—of electronic wave
functions from the metal into the forbidden gap of the semicon-
ductor [17], [18]. The result is the formation of metal-induced
gap states [19], [20] and the appearance of a dipole layer at the
interface which consequently makes the BH decrease.
1321
An initial approach [21] suggested that DL could be directly
proportional to the interface electric field as
Δφb,dl = αFx (y). (2)
However, more recently [22], this empirically based depen-
dence has been thought to be described by
Δφb,dl = α [Fx (y)]γ (3)
where α and γ have to be fitted empirically.
An alternative formulation [23] based on the formalism of
Heine tails accounts for DL as
 
βQs λ −xm
Δφb,dl = exp (4)
 λ
where xm is the position of maximum potential, β is the
fraction of ionized dopants on the silicon side of the junction
that contribute to the effect, λ is the Heine tail length, and Qs
is the areal charge density on the silicon side. In this model,
realistic values for λ and β are fitted from experimental data.
Both image force and DL have an electric field dependence;
however, the electric field at the interface depends on the shape
of the SB which is, in turn, controlled by the gate and influenced
by short-channel effects due to the previously commented
overlap between source and drain potential profiles. Thus, a
self-consistent solution to the potential at and near the contacts
is required. Furthermore, as the barrier modulation affects its
thickness, the tunneling probability used when field emission
begins to appear would be also modified, and that would force
this consistency to account for it too. Unfortunately, as ex-
plained in [23], such a self-consistent BL calculation including
field emission is not currently implemented in TCAD software
(for example, [22] and [24]).
Recent simulations [18] using Sentaurus device simulator
implement BL mechanisms using the model presented in [17]
emission current described by the universal Schottky tunneling
(UST) approach presented in [25] and [26] where the tunnel-
ing probability is calculated using the WKB approximation
which assumes a triangular potential profile. The use of this
approximation has been commonly accepted [25], [27], [28]. In
our case, BL estimations applied to both thermionic and field
emissions are externally calculated (a detailed discussion for
this can be found in [23]) to the ATLAS simulator.
It is worth noting that, for high gate biases, the “wide barrier”
assumption, inherent in the WKB approximation, begins to be
less precise [29]. As a possible solution, it has been proposed
[30] that the accuracy of the WKB model could be extended if
BL were excluded or, if BL were included, at the expense of
excluding thermal current. However, these solutions are hardly
justifiable from a physical point of view. Instead of that, an
alternative Airy-transfer-matrix (ATM) formalism [30], [31]
was shown to be more precise. This formalism has a higher
complexity and is not currently implemented in commercial
simulators.
1322
Fig. 3. Conduction band profile for the NiSi device. Vgs = 1.0 V and
Vds = 0.3 V.
III. S IMULATION P ROCEDURE
We propose a tradeoff that allows to keep the widely used
WKB model correcting its deviations through an adequate
fitting of the carrier effective tunneling masses, used in the
estimation of the tunneling probabilities, along with a vertical
discretization of the channel. This vertical discretization makes
it possible to account for the BH dependence on the depth
inside the channel, which may be of considerable importance in
relative terms particularly for small barrier values. In Fig. 3, we
show an example of the conduction band profile that enlightens
this dependence in the NiSi SB-MOSFET.
As mentioned in the introduction, BL is estimated externally
to the Silvaco ATLAS simulator through an iterative procedure
that recalculates for each iteration the BH using the electric field
value extracted from the previous step. This process is repeated
until variations from one iteration to the next (in terms of Δφ)
are not significant.
The channel is vertically divided in several layers parallel to
the semiconductor/insulator interface, and the electric field is
extracted for each one of them very close to the contacts. The
role of the mesh here is crucial. Next to the contacts, it has to
be extremely fined because, otherwise, small fluctuations in the
slope of the potential may occur from one iteration to the next,
making the resultant value of the electric field not to converge
in the iterative procedure indicated earlier. A tradeoff has to be
assumed between the refining of the mesh, which determines
the minimum distance of the contacts at which the electric field
can be extracted assuring convergence (in our case, typically of
order 1 nm), and the computational cost in time that it implies.
Preliminary simulations for our devices including both IFL
and DL seemed to suggest that the contribution of the latter to
the total BL was considerably lower than that due to the first.
An explanation to this may be found in the abruptness of the
metal–semiconductor junctions that eliminates the contribution
of interfacial states to the DL effect. For this reason, in what
follows, DL will be assumed to be included through the fitting
of the tunneling effective masses, thus eliminating two fitting
parameters, without losing too much accuracy.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 5, MAY 2012
Fig. 4. (a) Drain currents for Vd = 0.1, 0.3, and 0.5 V in the device with
epitaxial NiSi2 . Solid lines represent simulated characteristics including BL,
and symbols stand for experimental data. (b) Profiles of the source/drain SBs
at 0.5 nm from the channel interface corresponding to (left, Vg = 1.4 V, Vd =
0.1 V) electrons and (right, Vg = −1.0 V, Vd = 0.1 V) holes (dashed lines)
without BL and (solid lines) with our BL estimation.
IV. D EVICE FABRICATION
The 20-nm gate-length SB-MOSFET fabrication process is
reported in [1]. The transistor consists of 15-nm SOI channel,
a 5-nm-thick HfO2 gate dielectric layer, and a TiN gate. The
source/drain contacts were formed with 10-nm-thick NiSi or
epitaxial NiSi2 layers as we have recently reported [12]. The
fast diffusion of Ni induces a large encroachment of NiSi after
annealing which causes serious variability of the devices when
the silicide layer is thick. The ultrathin silicide formation using
very thin Ni layer avoids this problem. A small misalignment
is caused due to the shadowing effect of the gate during Ni
deposition, resulting in a small gap of 5 nm between the channel
and the silicide, as schematically shown in Fig. 1, which
will be considered in our simulations. The measured BH for
electrons is 0.65 eV for NiSi and 0.37 eV for epitaxial NiSi2 on
n-Si(100) [32].
V. S IMULATED C HARACTERISTICS AND
E XPERIMENTAL DATA
In Fig. 4(a), we show the transfer characteristics of the
epitaxial NiSi2 S/D SB-MOSFETs with Lg = 20 nm. We see
that the n-channel current is higher than the p-channel one
which agrees with the BHs for electrons reported in Sections I
and IV. Solid lines stand for the simulated currents with tunnel-
ing masses of mh = 0.46 and me = 0.8 which are higher than
those reported, for example, in [18], [23], and [30]. Fig. 4(b)
shows how our BL procedure modifies the source/drain barriers
PADILLA et al.: SIMULATION OF FABRICATED 20-nm SCHOTTKY BARRIER MOSFETs ON SOI
Fig. 5. Simulated transfer characteristics with BL of the epitaxial NiSi2
SB-MOSFET for Vd = 0.1, 0.5 V including (dashed lines) only thermionic
emission and (solid lines) both thermionic and field emissions. Inset shows the
relative importance of tunneling current over the total current.
for electrons and holes. Note that, as the BL treatment is exter-
nal to the simulator, this estimation is not fully self-consistent,
leading to a consideration of the barriers as abrupt changes
in potential which was already mentioned in [23]. Therefore,
the resulting potential profiles after BL slightly divert from
the theoretical more rounded ones. This issue, along with the
current overestimation arising from the WKB approximation,
may help to understand the higher values for effective tunneling
masses used in our simulations.
In the right branch of Fig. 4(a), that of electrons, we have
marked the gate voltage values corresponding to flatband con-
dition in the source edge and at the bottom of the channel
(where flatbands first occur when increasing the gate bias) for
different values of Vd . These points represent the limit where
tunneling begins to appear when we increase Vg . Note how the
simulations (including BL) fit very well the region dominated
by tunnel current but show certain deviation from experimental
results in the case of pure thermionic emission for electrons. If
we now focus on the left side, hole current has tunneling and
thermionic contribution in the entire range of Vg , and thus, we
do not observe significant deviations in the simulated currents.
In order to quantify the relative importance of both
thermionic and field emission contributions when BL is in-
cluded, and to show explicitly where tunneling begins to appear
in the n-branch, we present in Fig. 5 a comparison between pre-
vious characteristics corresponding to epitaxial NiSi2 for Vd =
0.1 and 0.5 V including thermionic and field emissions (solid
lines shown in Fig. 4) and those including only thermionic
emission (dashed lines). The inset shows the relative impor-
tance of tunneling current over the total current. In light of
these curves, importance of field emission becomes apparent
for increasing values of |Vg |, particularly for the p-branch.
Differences of up to five orders of magnitude can be observed
for Vg = −1.5 V and Vd = 0.5 V.
Let us now focus on the role that discretization plays. If
the channel were not vertically discretized, the same low-
ered value for the SB would be present in the whole metal–
semiconductor surfaces. In Fig. 6, we display simulations for
NiSi2 SB-MOSFET at Vds = 0.5 V without discretization and
1323
Fig. 6. Comparison between simulated transfer characteristics of the epitaxial
NiSi2 SB-MOSFET for Vd = 0.5 V (solid line) with discretization and (dashed
and dashed-dotted lines) without it. Triangles stand for experimental data.
Fig. 7. Simulated electron BH dependence on Vgs for several depths go-
ing down the metal–semiconductor junction at the source in the NiSi2
SB-MOSFET. Recall that, for this device, zero-bias BH was φbn = 0.37 eV.
Note how flatband condition is first reached at the bottom of the contact.
compare them to the discretized curve (solid line) and ex-
perimental data (triangle markers). In the n-channel with no
discretization, if we use the value of the electric field in the
uppermost part of the junctions to calculate BL, the resultant
curve (dashed-dotted line) presents an unphysical kink around
Vgs = 0.4 V. The appearance of this kink relies on the fact that,
at the source, flatband condition first arises (Vgs ≈ 0.3 V) at
the bottom of the channel (see how in Fig. 7 for the NiSi2
SB-MOSFET, the deeper we go down the contact, the sooner
the BH for electrons coincides with the zero-bias height for
increasing gate voltages). However, in this case, BL does not
begin until flatband is reached at the top (Vgs ≈ 0.45 V) be-
cause that is the point where we are extracting the electric field.
Therefore, as no BL is being considered for Vgs = 0.3–0.45 V,
current is clearly underestimated in this range. Contrary to this
underestimation, as the gate voltage gets higher, the electric
field at the top of the junction increases faster (see in Fig. 7
that, for high gate voltages, BL is greater at the top), thus
producing an overestimation of the current. On the other hand,
if we choose the value of the electric field at the bottom of the
junctions, no kink appears (because BL is incorporated since it
1324
Fig. 8. Drain currents corresponding to the NiSi SB-MOSFET for Vd = 0.1,
0.3, and 1.5 V. Symbols stand for experimental data. Solid lines represent
simulated results.
first occurs at the bottom), but underestimated current results
for increasing gate voltages (dashed line). In the p-channel, as
tunneling is present in its whole branch, no unphysical kinks are
observed. Note that, in the case of holes, the discretized curve
lies very close to the undiscretized one using the value of the
electric field at the top of the contacts.
Simulations and experimental data for the NiSi SB-MOSFET
with Lg = 20 nm can be seen in Fig. 8. Tunneling effective
masses were taken as mh = 0.8 and me = 0.4. For Vd = 0.1 V,
there is a small region in the p-branch of purely thermionic
emission that gets narrower for increasing drain voltage. When
Vd = 1.5 V, this region has disappeared, and tunneling is
present in the whole range of Vg . Unlike what happened in
the epitaxial NiSi2 device, there is no significant deviation
between simulated curves and experimental results in those
regions where tunnel current is absent.
It is worth noting that, for both the NiSi and epitaxial NiSi2
SB-MOSFETs, the simulated characteristics including tunnel
current using the WKB approximation with BL and the fitted
tunneling effective masses remain very close to experimental
data even for high |Vgs | contrary to what was shown in [30]
where simulations using the WKB model and including BL dif-
fered up to one order of magnitude from experimental results.
This strengthens the usefulness of our proposed mechanism that
allows considerable accuracy with only two fitting parameters.
In Fig. 9, we show the comparison between the simulated
characteristics (including thermionic and field emissions) ob-
tained using internal ATLAS estimation for BL (dashed-dotted
lines) which only applies BL to thermionic emission and those
including our external BL calculation procedure (solid lines)
that account for it for both contributions. Misleading results
arising from the first curves clearly show a systematic under-
estimation of the total current in the range where tunneling
is present. If one attempts to modify the effective tunneling
masses trying to compensate that lack of current when using
internal ATLAS BL, it can be seen in Fig. 10, for NiSi, that there
are no values of mh and me neither producing a good fit to the
experimental data nor reproducing the shape of experimental
curves.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 5, MAY 2012
Fig. 9. Simulated characteristics including (dashed-dotted lines) internal
Silvaco ATLAS BL calculation (only applied to thermionic emission) and (solid
lines) our external BL estimation for epitaxial NiSi2 and NiSi SB-MOSFETs.
Both curves clearly differ when field emission contributes to the total current.
Fig. 10. Transfer characteristics for different effective tunneling masses using
internal ATLAS estimation of BL (only implemented for thermionic emission)
for NiSi SB-MOSFET. Diamonds stand for experimental data.
Another interesting point is the apparent reduction of tunnel
current obtained for increasing values of |Vgs | when the channel
length is reduced from 50 to 20 nm, contrary to what one
would expect considering the scaling behavior. This experi-
mental discovery [1] is also revealed in our simulations and
is consistent, for example, with the predictions made in [33],
where it was suggested that, for single-gate SB-MOSFETs,
the downsizing of the devices, starting at Lg ≈ 20 nm, would
make the influence of Schottky contacts become significant
across the entire length of the channel, making the conduction
band much stiffer to bending by the gate voltage. In Fig. 11,
we show this current reduction for Lg = 20 nm in the NiSi
SB-MOSFET as a result of the overlapping between source
and drain barriers and the subsequent increase of the total
potential inside the channel. The inset in Fig. 11 schematically
shows this effect in the range of positive Vg . This observed
difference between characteristics is higher for NiSi in the case
of electrons because, in the n-channel, branch tunneling occurs
for both source and drain in the whole range of voltages. Fig. 12
shows the simulated conduction band profiles for Lg = 20 nm
PADILLA et al.: SIMULATION OF FABRICATED 20-nm SCHOTTKY BARRIER MOSFETs ON SOI
Fig. 11. For increasing values of |Vgs |, we get higher current for (diamonds)
Lg = 50 nm than for (squares) Lg = 20 nm in the NiSi SB-MOSFET. This
behavior is reproduced in (solid lines) our simulations. Simulated characteris-
tics (dashed-dotted lines) using internal ATLAS estimation of BL do not follow
this pattern conclusively.
Fig. 12. Conduction band profiles for the NiSi SB-MOSFET with (dashed
line) Lg = 50 nm and (solid line) Lg = 20 nm after BL. A certain overlap
of source and drain barriers produces an increase of the potential inside the
channel as depicted in the inset.
(solid line) and Lg = 50 nm (dashed line) at Vg = 0.7 V and
Vd = 0.3 V. In the p-channel branch, however, tunneling begins
to appear in both interfaces at Vg ≈ −0.5 V, while for Vg >
−0.5 V, only thermionic emission occurs at the source. This
causes this overlapping to be less dramatic for holes as shown
in Fig. 13 for Vg = −1.0 V, thus moderating to some extent the
aforementioned overlapping.
Finally, due to short-channel effects (DIBL), it would be
reasonable to expect an increase of Id with Vds without appre-
ciable saturation. This behavior is indeed observed in Fig. 14 for
the three curves corresponding to Lg = 20 nm. Observe that,
however, the curve with Lg = 50 nm seems to show certain
saturation for Vg > 1.2 V. Simulations changing the underlap
between the gate and the silicide for Lg = 20 nm have been
performed showing, for increasing values of it, an apparent
degradation of performance manifested in a reduction of drain
current, thus indicating the impact that this underlap has on
parasitic resistance.
1325
Fig. 13. Valence band profiles for the NiSi SB-MOSFET with (dashed line)
Lg = 50 nm and (solid line) Lg = 20 nm after BL. As SB for holes in NiSi is
lower than that for electrons, the potential inside the channel is less affected by
the overlap as shown in the inset.
Fig. 14. Simulated output characteristics of NiSi SB-MOSFET. Dashed and
dashed-dotted lines correspond to Lg = 20 nm with underlaps of 4 and 6 nm,
respectively. Solid lines correspond to 5-nm underlap; the topmost one stands
for Lg = 50 nm. Diamonds represent experimental data for Lg = 20-nm with
underlap of 5-nm.
VI. C ONCLUSION
Inclusion of BL in SB-MOSFET simulations has been widely
discussed in the literature but not completely implemented yet
in TCAD simulators. In most cases, the tunneling probabilities
of carriers are described using the WKB approximation that
turns out to lose accuracy for narrow SB. To circumvent this
obstacle, some authors introduce an alternative ATM approach
or directly exclude BL trying to compensate the overestimation
of the WKB model. We propose an intermediate solution that
allows us to use Silvaco ATLAS simulator through an external
iterative procedure to calculate BL in which we include a
vertical discretization of the channel along with an appropriate
fitting of carrier tunneling masses. Comparisons between simu-
lated characteristics and experimental data from short-channel
epitaxial NiSi2 /NiSi SB-MOSFETs are shown. Simulations
also reproduce some interesting issues arising from these
20-nm-channel devices such as the lack of saturation of output
characteristics produced by the appearance of short-channel
effects (DIBL), the increase of parasitic resistance due to the
underlap between the gate and the silicides, and the total current
1326
reduction with respect to the Lg = 50 nm device due to the
overlap of the SB potential profiles.
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José Luis Padilla was born in Jaén, Andalucía,
southern Spain. He received the B.Sc. degree (with
honors) in physics from the University of Granada,
Granada, Spain, in 2003 and the M.A.S. degree in
theoretical physics from the University of Granada,
Spain, in 2005. He has been working toward the
Ph.D. degree in the Departamento de Electrónica
y Tecnología de los Computadores, University of
Granada, since 2008.
For several years, he worked on theoretical models
of neutrino masses and extra dimensions and coau-
thored papers in these subjects. He has been a Visiting Researcher with the
University of California Riverside UCR (2005 and 2007); the Max-Planck-
Institut für Physik, Munich, Germany (2006); and the Peter Grünberg Institut
(PGI-9 IT), Forschungszentrum Jülich, Jülich, Germany (2011). He is currently
investigating on nanoelectronics with special interest in theoretical modeling
and simulation of semiconductor devices and quantum effects.
Lars Knoll received the Diploma in physics from
RWTH Aachen University, Aachen, Germany, in
2010. He is currently working toward the Ph.D.
degree at the Peter Grünberg Institute 9 (PGI-9 IT),
Forschungszentrum Jülich, Jülich, Germany. During
his Diploma thesis, he studied nickel silicides regard-
ing their applicability in electronic devices.
He is currently working on processing and char-
acterization of short-channel field-effect transistors
with silicided source and drain contacts.
Francisco Gámiz (M’94–SM’02) received the B.S.
degree in physics and the Ph.D. degree from the
University of Granada, Granada, Spain, in 1991 and
1994, respectively.
In 1999, he was a Visiting Researcher with IBM
T. J. Watson Research Center, Yorktown Heights,
NY. Since April 2005, he has been a Professor of
electronics with the University of Granada. Since
1991, he has been working on the characterization
of scattering mechanisms and their influence on the
transport properties of charge carriers in semicon-
ductor heterostructures. He has studied electron mobility in silicon inversion
layers by the Monte Carlo method. He has coauthored more than 300 refereed
papers in major journals and conference proceedings. His current research
interests include the effects of many carriers on electron mobility and the
theoretical interpretation of the influence of high longitudinal electric fields on
the electrical properties of metal–oxide–semiconductor transistors. His other
interests are related to SiGe and SiC, silicon-on-insulator and germanium-on-
insulator devices, quantum transport, and single-transistor dynamic random-
access-memory cells. He is a coholder of four patents related to multibody
memory technology.
Dr. Gamiz is the Coordinator of the European Network on Silicon-on-
Insulator Technology, Devices, and Systems.
PADILLA et al.: SIMULATION OF FABRICATED 20-nm SCHOTTKY BARRIER MOSFETs ON SOI
Qing-Tai Zhao (M’11) received the Ph.D. degree in
solid-state physics from Peking University, Beijing,
China, in 1993.
From 1994 to 1997, he was a Research Staff with
the Institute of Microelectronics, Peking University,
first as a Lecturer and then as an Associate Professor,
where he worked on SOI materials and devices. In
May 1997, he was awarded as a Humboldt Research
Fellow and started his research at the Peter Grünberg
Institute 9 (PGI-9 IT), Forschungszentrum Jülich,
Jülich, Germany, where he is currently a Research
Scientist and the Leader of Si-based Device Group. His primary research
focuses on Si/SiGe-based devices and technology, thin silicide and Schottky
barrier engineering, nanowire devices, and tunnel FETs. He is the author or
coauthor of more than 140 scientific papers and is the holder of seven patents.
Andrés Godoy (M’08) received the B.S. and Ph.D.
degrees in physics from the University of Granada,
Granada, Spain, in 1993 and 1997, respectively.
He was a Visiting Researcher with the Beckman
Institute, University of Illinois, Urbana. He is
currently a Professor of electronics with the Departa-
mento de Electrónica y Tecnología de los Computa-
dores, University of Granada. His current research
interests include Monte Carlo simulation of semicon-
ductor devices, noise modeling, and nanoelectronics.
1327
Siegfried Mantl (M’04) received the Ph.D. de-
gree from the University of Innsbruck, Innsbruck,
Austria, in 1976.
In 1981/1982, he spent a sabbatical year with
the Materials Science Division, Argonne National
Laboratory. Since 1971, he has been with the Peter
Grünberg Institute 9 (PGI-9 IT), Forschungszentrum
Jülich, Jülich, Germany. He is the Head of the Ion
Beam Technique Division, PGI-9-IT, and a Professor
of physics with RWTH Aachen University, Aachen,
Germany. His research interests focus on the inves-
tigation of Si- and Ge-based nanoelectronic devices as well as on ion beam
techniques and various thin film growth methods. Specifically, nanowires and
strained heterostructures for novel transistors, such as short-channel FETs and
Schottky barrier and tunnel MOSFETs, are under investigation. He has authored
or coauthored more than 260 journal articles, book chapters, and review articles
and is the holder of over 20 patents.