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Objective
The objective of this laboratory session is to design and characterise a two-stage CMOS op-
erational amplifier. The caracterisation is to be carried out using both hand-calculations and
computer simulations. For the hand-calculations, you should use the parameters for the TSMC
0.18 µm CMOS process published at the course web-site. The hand-calculations should not be
carried out in the laboratory session!
Op-amp design
The opamp to be designed is shown in the figure below. You should create a cell that contanins
the schematic, and use suitable test-benches (as outlined in lab 2) for the different simulations
that you are going to carry out. Note, that on the figure, the gate of M6 is connected to the gates of
M7 and M8 — the bulk-terminal on M7 is not drawn; this is standard notation for current-mirrors
with multiple outputs.
VDD
M2
M1 M3
RC
(a) (b)
Figure 1: CMOS op-amp (a), transistor dimensions (b)
Transistor dimesions: The dimensions of most of the transistors are given in the figure; choose
the dimensions for the other transistors in the op-amp.
Parametric values: You will need to find CC and RC using simulations; to this end, it is very
useful to enter their values as paramters in the schematic. Choose rc Ohms as the Resistance
of RC , and cc F as the Capacitance of CC .
TL/lab3/July 28, 2015
School of Electrical Engineering
ELEC4602/lab3 p. 1/4 and Telecommunication
Building a generic testbench
Depending on the type of simulation you want to do, your test bench is going to look different.
The easiest way to handle that is to build a test bench in which you can “add” or “remove”
connections by entering extreme values of components (e.g. a resistor of 1 fΩ is effectivily
a short-circuit, while a resistor of 1 TΩ is effectivily an open-circuit). Build the generic test
bench for your op-amp shown in the figure below. v2 should be of type vpulse for transisent
simulations; the other voltage sources can be of vdc type.
VDD
Component Value
20uA VDD 1.8 V
CL 10 pF
1.8V IB IB 20 µA
vIP vO
V1 Cin 1 TF / 1 fF
vIM
v2 R in CL Rin 1 TΩ / 1 fΩ
Lfb 1 TH / 1 fH
Cin L fb R fb Rfb 1 TΩ / 1 fΩ
v3
(b)
Figure 2: Generic simulation test bench for op-amp
ELEC4602/lab3 p. 2/4
you can get a very good idea of the range the offset voltage (or some other parameter of interest)
will lie within.
To find the offset voltage range, first ensure that you are using the stat section of the tsmc018.scs
model library as described in lab 2, and have your DC simulation of the amplifier transfer func-
tion (i.e. the one you just found the DC gain on) set up — you will need an sweep band around the
common-mode voltage of about ±100 mV. Then, in the in the Analog Design Environment menu,
choose Tools-Monte Carlo ...; now, in the popped up Analog Statistical Analysis window
choose 30 for Number of Runs, choose Process & Mismatch for Analysis Variation, and
tick the box for Save Data Between Runs to Allow Family Plots. Finally, in the menu
choose Simulation-Run; it will take a little while for this simulation to run. Plotting vO will
now get you 30 transfer functions, each with a different offset.
Remember to enter an AC Magnitude of 1 for v2 ; you can now run an AC simulation; to find
the unity-gain frequency plot the magnitude of output voltage (vO ) in dB and find the frequency
where this has reduced to 0 dB. To find the phase margin, plot the phase of the output voltage,
and read tis value at the unity-gain frequency.
Parametric sweep: To find a good value for RC , choose in the simulation window menu
Tools-Parametric Analysis... and in the pop-up window enter rc as the Variable Name,
enter a Range Type of From/To, enter 1e3 in the From field, and 1e6 in the To field; under
Step Control choose Decade and enter 2 in the Steps/Decade field. Now select Analysis-
Start in the parametric window menu; this should start a series of AC simulations with different
values for RC . Choose a value for RC that give a smooth 20 dB/dec roll-off, and a good phase
margin. What is your unity-gain bandwith and your phase margin?
Slew-rate
To find the amplifiers slew-rate, prepare your test-bench to do transisent simulations on a unity-
gain configured amplifier; choose the following component values:
ELEC4602/lab3 p. 3/4
For v2 , enter rise and fall-times of 1 ns, 50 % duty cycle, a repetition period of 2 µs, and a voltage
swing between 0.8 V and 1.3 V. Now carry out a transient simulation, and note down the slew
rate (i.e., the highest dvO /dt) for both for rising and falling edges. Why are they different?
Report
A short report in .pdf format on the laboratory exercise must be prepared and uploaded on the
course Moodle site no later than the due date. This need to include:
• Your DC simulation.
– On which you read the DC gain (compare this with simple hand calculations).
– On which you read unity-gain frequency and phase margin (compare the unity-gain
frequency with simple hand calculations).
– On which you read the common-mode range (compare this with simple hand calcu-
lations)
– On which you read the slew rates (compare this with simple hand calculations)
ELEC4602/lab3 p. 4/4