IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO.

12, DECEMBER 2010 3433

Drifting-Dipole Noise (DDN) Model of MOSFETs

for Microwave Circuit Design
Giang D. Nguyen, Student Member, IEEE, and Milton Feng, Fellow, IEEE

Abstract—Physic-based formulations for the high-frequency

noise characteristics of nanometer MOSFETs working at satura-
tion are developed. In the derivation, field-dependent mobility, as
well as carrier heating effect in the gradual channel approxima-
tion region, is taken into account. In addition, diffusion noise due
to velocity saturation carriers in the high electric field region is
calculated using Statz’s drifting dipole theory. Excellent agree-
ment between the proposed model and experimental noise data
for 120-nm MOSFET technology was obtained over device sizes,
biases, and frequencies up to 26 GHz. The analytical noise model
can be incorporated into any compact model to enable first-pass
silicon design of microwave circuit.
Index Terms—Carrier heating, drifting dipoles, high-field diffu-
sion noise, nanometer MOSFET, velocity saturation.

Fig. 1. Purely thermal noise formulation, such as the one in BSIM3 model, op-
I. INTRODUCTION timistically predicts the minimum noise figure NF of a 120-nm nMOSFET
measured at the University of Illinois at Urbana-Champaign.

A GGRESSIVE scaling technology beyond 100 nm has

been greatly improving the microwave performance
of MOSFETs with cutoff frequency above 460 GHz and
minimum noise figure less than 1 dB in the 10-GHz
range [1]. Such advances bring several challenges in modeling
the physics of the devices used in silicon microwave integrated
circuit designs.
Currently, the high-frequency noise mechanisms in nanoscale
MOSFETs are still not clearly understood. As shown in Fig. 1,
the BSIM3 model optimistically predicts the minimum noise
figure of a 120-nm MOSFET. This discrepancy is due
to the fact that the purely thermal noise model in BSIM3 does
not include the effects of velocity-saturated carriers in deep sub-
micrometer MOSFETs. To resolve the problem, Scholten et al.
[2] proposed that noise in short-channel MOSFETs was thermal
noise mainly originated from the low-field source region, and
the increase in drain noise following drain voltage in sat-
uration mode came directly from the channel length modula-
tion (CLM) effect. However, the model prediction on 100-nm
MOSFET technology started to show deviation from experi-
mental results [3] and no further explanation has been made. Re-
cent report by Navid et al. [4] employed a ballistic-based model
and hydrodynamic simulator to explain the excess thermal noise
in the nanoscale MOSFET was due to partial suppression of shot
Manuscript received February 15, 2010; revised August 09, 2010; accepted
August 27, 2010. Date of publication October 07, 2010; date of current ver-
sion December 10, 2010. This work was supported by the Semiconductor Re-
search Corporation (SRC) under Grant SRC-2007-VJ-1603. This paper is an
expanded paper from the Asia–Pacific Microwave Conference, Singapore, De-
cember 7–10, 2009.
The authors are with the Department of Electrical and Computer Engineering,
University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA (e-mail:
gnguyen3@illinois.edu; mfeng@illinois.edu).
Digital Object Identifier 10.1109/TMTT.2010.2081530
0018-9480/$26.00 © 2010 IEEE
noise. Nevertheless, the results of the hypothesis was inconsis-
tent with the experimental noise data previously reported [5],
[6] for scaled devices. In general, recent published results on a
conventional bulk MOSFET also shared similar conclusion with
the work of Danneville et al. [7] in III–V field-effect transistors
(FETs), namely, the noise sources in the device channel mostly
originated from the source side.
Considering a device with 100-nm gate length under
source–drain bias voltage of 1 V, the average field across the
channel far exceeds the saturation field in silicon. In this case,
the high-field drain region of the device occupies a large portion
of the channel, which should strongly affect the device charac-
teristic including its noise behavior. Furthermore, according to
Shockley et al. [8], the general noise sources in semiconductor
devices are described by
(1)
where is the volume density of the noise current at ,
is the field dependent diffusion constant of the carriers, is the
carrier density, and is the bandwidth. Although velocity-
saturated carriers may not directly respond to any fluctuation
of high electric field, the direction of their random velocity can
still hold a spherical distribution around its original position. If
we assume uniform carrier density in the cross-sectional area
of the device, then (1) obviously describes a displacement noise
current produced by random motion of carriers
in the high-field saturation region within the distance .
In this paper, we present a new analytical high-frequency
noise formulation for nanometer MOSFETs working in satu-
ration, which completely advances previous results reported by
Park and Park [9]. A channel thermal noise model of the source
3434 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 12, DECEMBER 2010

where is the low-field mobility, is the surface

scattering factor, is the lateral mo-
bility reduction factor, and are empirical parameters, and
is the threshold voltage.
In Region II, the GCA fails because the vertical field no
longer dominates the lateral field. As a result, the potential
distribution in the space-charge region becomes 2-D and is
the solution of Poisson’s equation

(4)

Equation (4) assumes carrier accumulation is negligible due to

Fig. 2. Two-section MOSFET channel. Region I: ohmic property. Region II: high applied voltage at the drain side, and is the average
saturation velocity with drifting dipole noise mechanism. doping density in the substrate. A particular solution of (4) is
also the potential solution in Region I to guarantee the continuity
of potential at the boundary between the two regions, and is
side based on field-dependent mobility nonlinear relation be- given by the parabolic relation everywhere in the carrier stream
tween the electric field and drain current , as well as the car- [16]
rier heating effect is derived. To analyze the high-field noise in
the drain region, we directly apply Statz’s drifting-dipole noise (5a)
(DDN) theory [10] that has been widely used and validated for
the microwave noise models of GaAs MESFETs and HEMTs.
In addition, based on the two-section channel noise model, we
also develop the induced gate noise model, which is very impor- (5b)
tant at high frequency. Our proposed DDN model has been ex-
tensively verified and has shown excellent agreement with mea-
sured noise data of 120-nm MOSFETs. The capability of the (5c)
DDN model to scale with bias and device size makes it useful for
microwave circuit development, which has already been demon- (5d)
strated in the design of a 24-GHz low-noise amplifier for indus-
trial, scientific, and medical (ISM) applications [11]. where is the surface potential, is the quasi-Fermi poten-
tial at the critical point [12], is the separation of the Fermi
II. CHANNEL NOISE MODELING potential from the middle of the bandgap, is the flatband
voltage, is the coefficient accounting for the body effect on
A. MOSFET Channel Under High Lateral Field Effect the threshold voltage, is the depletion depth at the critical
point, is the length of Region I, is the gate capacitance
Fig. 2 shows a typical cross section of a nanometer MOSFET
per unit area, is the Boltzmann constant, is the ambient
structure. Within the effective channel length , we assume
temperature, and . In addition to the particular
a piece-wise approximation of carrier drift velocity [12]
solution, we have to add the homogeneous or Laplace solution
to satisfy the boundary conditions
(2) (6a)
(6b)
where is the carrier saturation velocity, is the ef- (6c)
fective mobility, is the lateral quasi-Fermi electric field, and
is the critical or saturation field. When the In (6b), we assume most of the carriers in Region II concen-
maximum lateral electric field in the channel exceeds the value trate within the depletion depth of . Following Grebene’s
of at the critical point, the channel of the MOSFET is di- approach [17] and approximating the solution to the lowest
vided into two regions: Region I of low-field ohmic property and space harmonic, we obtain
Region II of high-field saturation velocity. The critical point is
going to shift to the source side if the drain voltage continues to (7)
increase.
In Region I, we employ the gradual channel approximation From (5) and (7), the source–drain potential can be eval-
(GCA) and consider the effective mobility as a function uated at and , as seen by
of both gate voltage and drain voltage [13]–[15]

(3)
(8)
NGUYEN AND FENG: DDN MODEL OF MOSFETs FOR MICROWAVE CIRCUIT DESIGN 3435

where is the built-in potential of the drain-to-substrate junc- where is the voltage drop across the resistance of the
tion, is accounted for surface potential at strong inversion in infinitesimal segment in Region I.
(5b), and is given by In Appendix A, we give the derivation of the noise fluctuation
at the drain terminal as a consequence of the thermal
(9) noise generated in Region I. The result is

Since , (8) is clearly an implicit equation of (15)

the unknown , which can be solved numerically.
For the sake of simplicity, in this work we have consid- Substituting (13) and (15) into (14), we obtain the mean
ered the average effect in modeling the carrier transport in a square value of the drain noise voltage caused by the
nanometer MOSFET, though under high applied -field some infinitesimal voltage fluctuation in Region I
other nonequilibrium phenomena can happen, e.g., velocity
overshoot [18], [19]. Nonetheless, recent reports [20], [21] have
confirmed that carrier velocity at the source side still depends
strongly on the mobility , and average carrier velocity at
room temperature is not yet in the overshoot regime even for (16)
sub-100-nm devices, thus justifying our approximation.

B. Low-Field Enhanced Channel Noise at the Drain Terminal At the drain terminal, the total contribution of all noise
Generated by Fluctuation in Region I sources along the channel in Region I is therefore a straight
integration of (16) between the limits of and .
In this section, we evaluate the open-circuit noise voltage at The final result is
the drain due to voltage fluctuation of an infinitesimal seg-
ment within the channel of Region I. First of all, under the ap-
plied -field, carriers in the region gain energy and their effec-
tive temperature may increase above the ambient temperature
according to the relation [22]

(10)
(17)
where the hot electron temperature coefficient is an empir-
ical parameter. When the device is under strong inversion, the The drain noise model in (17) represents the “enhancement”
current is dominated by drift current. Using piece-wise ap- of thermal noise contributed by carriers in Region I through the
proximation of the carrier velocity as described by (2), the I–V “hot carrier” effect and the hyperbolic factor , which accounts
relation in Region I of the channel can be derived, as seen by for the noise-induced CLM.
[12]
C. High-Field Channel Noise at the Drain Terminal Generated
(11) by Drifting Dipoles in Region II
Under strong applied -field at the drain side, Region II is
clearly in a nonequilibrium condition. As stated earlier by (1),
At the end of Region I, where and , we obtain there should be a displacement noise current associated
with carriers drifting at due to their own rapid random mo-
(12) tion. At any position within the spatial interval , the noise
current consists of short impulses, uncorrelated from one
Since the current in the channel is continuous, from (11) and instant of time to the next. Comparing (1) to the shot noise ex-
(12) we can calculate the ratio and re-express (10) as a pression, at rate , the sequence of current
function of the quasi-Fermi potential impulses is clearly generated at the rate

(13) (18)

Although carriers in the channel become “hot” as the applied
field increases, the average velocity of the carriers is still smaller
than their thermal velocity. Hence, the equilibrium condition
still holds, and the voltage fluctuation can be modeled by
thermal noise with mean square value
(14)
In addition, each of the current impulses displaces a charge
across the interval , thus resulting in an electric dipole layer
of charge density at and at . Since
the carriers in the saturation velocity region do not respond to
the applied -field, the resulting dipole layers are unable to re-
cover and drift unchanged to the drain terminal. In this section,
we directly apply Statz’s analytical treatment of high-field noise
[10] to calculate the perturbation effect of the dipole potential
3436 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 12, DECEMBER 2010

difference on a MOSFET drain terminal under open-circuit con- Next, let the random process be the sum of all indepen-
ditions. As shown in Appendix B, the dipole potential difference dent events occurring at different time , then its spectral den-
at position can be approximated by sity is calculated using Carson’s rule as seen by

(24)

where the generation rate is defined by (18).

(19)
At the drain terminal, the noise voltage due to the generation
of dipole layers at position has the mean square value
where the sign applies for and the sign applies obtained from (18), (23), and (24)
for . Since the particular potential is consistent
across the device channel length, only has an impact
on the Laplace potential .
For , to maintain the boundary condition (6a), poten-
tials due to charges at the drain will be induced along the channel
to cancel the effect of . At the critical point, the in- (25)
duced potential is seen by
In (25), the carrier stream is assumed to flow through the cross
section .
(20) Finally, we calculate the total noise voltage produced by all
the dipole layers generated across Region II by integrating (25)
From (20), the potential induced on the drain terminal as a result over . The result is
of the formation of dipole-layer potential difference is, there-
fore,

(21)

The dipole generated at position and time , will

then drift at a steady speed of . The induced potential (26)
at the drain in (21) now becomes time dependent, as seen by
In (26), we assume the channel current in the high-field re-
gion is expressed by

(27)
(22) where is considered the effective junction depth at which
most of the carriers are collected by the drain terminal.
where .
Since the noise contributions of Regions I and II are uncorre-
For , the dipole layers directly affect the drain voltage.
lated, the total open-circuit noise voltage at the drain is given by
However, their potential contribution get canceled by the corre-
sponding image dipole layers mirrored at plane .
Equation (22) represents one of the many dipole layers ran-
domly generated at the plane at different times . We (28)
obtain the spectral density of each of these potential differences
by applying Fourier transform Under short-circuit conditions, the voltage fluctuations are
transformed into the drain noise currents, as seen by

(29)

where is the output conductance of the device

(23) and is given by (8).

has a very wide spectrum, which exponentially decays to- III. INDUCED GATE NOISE MODELING
ward infinity. However, the operating frequency of a nanometer
MOSFET is much smaller than the inverse of the carrier transit A. Gate Noise Current Induced by Fluctuations in Region I
time through Region II, THz. In (23), we only In low-field Region I, any noise voltage caused by in-
evaluate in the limit of . finitesimal ohmic segments will produce fluctuation charges on
NGUYEN AND FENG: DDN MODEL OF MOSFETs FOR MICROWAVE CIRCUIT DESIGN 3437

the gate through the oxide capacitor of the device, as ex-

pressed by (37)

(30) (38)

Then, from (16), (29), and (35), the mean square value of the
In (30), we use as a new lateral axis, and is the begin- fluctuation charge on the gate due to an infinitesimal noise
ning of Region I. Under short-circuit condition at the drain, the voltage in Region I can be expressed by
noise voltage also creates a fluctuation in the channel
current, as described by (29). In high-field Region II, the appear-
ance of the fluctuation current requires additional charges
to the channel current and, hence, induced charges on the gate
with opposite sign, as seen by

(31)
(39)
where is the transit time through Region II. The total induced
Integrating (39) over from to , we obtain the
fluctuation charge on the gate is, therefore,
total charge fluctuation on the gate

(32)

To calculate the induced gate charge in (32), we have to (40)

determine the distribution of the noise voltage as a function
of the position along the channel. In Appendix C, we show where is given in Appendix D. To simplify the integral
that calculation, we have assumed second-order approximation such
that
(41)
(33a) Since the charge fluctuations are time dependent, there will be
an induced gate noise current flowing into the gate and its mean
square value is given by
(33b) (42)
We have modified Statz’s formulation in the derivation of (33)
to account for the nonlinear relation between the carrier velocity
and the applied field, which is more appropriate for nanometer B. Gate Noise Current Induced by Drifting Dipoles in
MOSFETs, as described by (2). Region II
Inserting (33) into (32) and using the following relation [12]: Since the accumulation charges in the channel of Region II
are negligible, the dipole potential difference does
(34) not directly induce fluctuation charges. However, under short-
circuited drain condition, it will cause the noise current
to carry out the integral from to , we obtain to flow through the device channel. Since the noise mechanisms
in the two regions are independent, there is no potential jump
in this condition, and in (32) should be equal to zero.
From (35), we then obtain
(35) (43)
where , , and are defined as where is given by

(36) (44)
3438 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 12, DECEMBER 2010

The induced gate noise current will be calculated directly from

the channel noise current, as seen by

(45)

Inserting (26) into (45) and using (29), we then obtain its spec-
tral density

Fig. 3. Equivalent MOSFET small signal model for calculation of intrinsic

drain noise S and induced gate noise S after standard “Open” and “Short”
de-embedding.

Substituting (26) into (50) and employing (29), we then obtain

(46)

Finally, the total induced gate noise current is simply the

summation of and . (51)

IV. CORRELATION COEFFICIENT OF DRAIN NOISE AND Finally, using (49) and (51), the correlation coefficient de-
INDUCED GATE NOISE CURRENTS IN MOSFETs fined by (47) can be calculated. Its value is purely imaginary
due to the fact that the gate noise and drain noise currents are
The drain noise and the induced gate noise have some coupling through the gate–oxide capacitor.
correlation since parts of them generated from the same noise
sources in the channel. Due to the independence of noise mech-
anisms in Regions I and II, the pair of noise currents V. EXPERIMENTAL RESULTS AND DISCUSSION
and are uncorrelated. Hence, the correlation of In this section, we verify the proposed DDN model with
and can be defined as [10] experimental data of the 120-nm MOSFET technology. An
ATN automated noise-figure measurement system is employed
(47) to carry out the high-frequency on-wafer measurements in the
range of 2–26 GHz at different biasing conditions. Collected
data, including noise parameters and
In Region I, the cross-correlation of noise sources is ex-
-parameters, are then de-embedded using “Open” and “Short”
pressed by
techniques to remove the effects of the probing pads and in-
terconnections [23], [24]. For nanometer MOSFETs that have
(48) small-signal models described in Fig. 3, the noise contributions
from extrinsic components such as drain/source terminal re-
sistances , gate electrode resistance , and bulk
Inserting (35) into (48), then using (16) and (29) to carry out the impedance become very important. Hence, to
integration, we obtain extract the noise sources accurately, we further de-embed the
measured data from extrinsic to intrinsic level using Engberg’s
approach [25]. Finally, we obtain the intrinsic drain noise
and induced gate noise based on the well-known correlation
matrix method [24].
The devices-under-test (DUTs) are n-channel MOSFETs that
(49) have the dimensions of m nm. The effective
channel length, oxide thickness, effective junction depth, and
where is given in Appendix D. In (49), we have also em- threshold voltage of the DUTs are determined to be
ployed the approximation given by (41) to simplify the integral nm, nm, nm, and V,
calculation. respectively. As mobile carriers in the DUTs are electrons, sat-
Similarly, in Region II, we can evaluate the cross-correlation uration velocity of 8 10 cm/s and low-field mobility
using (43). The result is of 360 cm Vs were used to achieve best fitting results in the
– characteristic. The selection of saturation velocity is
in agreement with published results in [26]. For noise simula-
(50)
tion, we have set the high-field diffusion coefficient and the hot
NGUYEN AND FENG: DDN MODEL OF MOSFETs FOR MICROWAVE CIRCUIT DESIGN
Fig. 4. Measured versus DDN modeled drain noise S and induced gate noise
S of an nMOSFET in the frequency range of 2–26 GHz.
Fig. 5. Measured versus DDN modeled drain noise S of an nMOSFET as a
function of drain voltage V for a fixed gate voltage V .
electron temperature parameter to cm s and , Fig. 7 illustrates the measured versus modeled correlation co-
respectively. These values are within the range of the data re-
ported in [27] and [28].
It is shown in Fig. 4 that the measured noise sources of the
DUT, and , are in excellent agreement with their modeled
results at V and V over the frequency
range of 2–26 GHz. Next, we investigate the dependences of
these noise sources on lateral electric field in the device channel.
The achieved results, including the total noise as well as re-
gional noise contributions, are illustrated in Figs. 5 and 6 at
GHz, the middle point of the measured frequency range. As
the drain voltage increases for a fixed gate voltage , the
thermal noise in Region I starts to decrease while the high-field
noise in Region II continues to increase to keep the total mea-
sured noise sources unchanged or even increase slightly at cer-
tain biasing conditions. Furthermore, at high , we observe an
interesting feature that the DDN contributed by Region II actu-
ally becomes dominant over the thermal noise originated from
Region I. This fact confirms the noise contribution by the ve-
locity saturation region plays a very important role in studying
microwave noise behavior of nanometer MOSFETs.
3439
Fig. 6. Measured versus DDN modeled induced gate noise S of an
nMOSFET as a function of drain voltage V for a fixed gate voltage V .
Fig. 7. Measured versus DDN modeled correlation coefficient C of an
nMOSFET as a function of gate voltage V for a fixed drain voltage V .
efficient between drain noise and induced gate noise .
Also plotted in Fig. 7 are the regional correlation coefficients
and of noise sources in Region I and Region II. Note that to
keep the DUTs within normal operating condition as specified
by the process, no measured values of at high beyond
1.2 V are taken in our experiments. The coefficient of the
low-field region has a similar shape to the ones of long-channel
MOSFETs [29]. Meanwhile, the coefficient of the high-field
region contributes to form a more general pattern of the total cor-
relation . As increases, increases to reach its peak, and
then gradually reduces at high bias conditions. In addition, we
observe that noise sources in Region II are more correlated than
the ones originated from Region I. The data shown in Fig. 8 is
consistent with the results presented in [30] and [31].
For microwave circuit design purpose, we have incorporated
the DDN model with two noise sources— and —into the
large-signal model BSIM3 using a sub-circuit technique [32].
The approach can be applied for any other compact model. As
shown in Figs. 8 and 9, the DDN model well predicts the mea-
sured minimum noise figure of a 120-nm nMOSFET in
3440 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 12, DECEMBER 2010
Fig. 8. Measured versus DDN modeled minimum noise figure NF
nMOSFET as a function of frequency in the range of 2–26 GHz.
Fig. 9. Measured versus DDN modeled minimum noise figure NF
nMOS with different gatewidths at different biasing conditions.
Fig. 10. Measured versus DDN modeled equivalent noise resistance R
nMOSFET as a function of frequency in the range of 2–26 GHz.
the frequency range of 2–26 GHz, as well as at different bias cur-
rent levels. In addition, the impact of induced gate noise mod-
eling can be observed in Fig. 8 at very high frequency. Finally,
the DDN modeled results of other noise parameters such as the
equivalent noise resistance and optimum source reflection
Fig. 11. Measured versus DDN modeled optimum source reflection coefficient
of an 0 of an nMOSFET as a function of frequency in the range of 2–26 GHz.
Fig. 12. (a) Charge sheet on top of a ground plane. (b) Drifting dipole formed
in high-field Region II.
coefficient are also reported in Figs. 10 and 11, respec-
tively.
VI. CONCLUSION
of an
A high-field noise model for nanometer MOSFETs that
predicts both drain noise and induced gate noise at microwave
frequency has been developed based on Statz’s drifting dipole
theory. The proposed DDN model accurately predicts high-fre-
quency noise data of devices in 120-nm CMOS technology
under various biasing conditions. We find that the high-field
noise generated by the velocity saturation region cannot be
neglected, but is very crucial in determining the high-frequency
noise behavior of nanometer MOSFETs. The analytical formu-
lations of the proposed DDN model make it easy to incorporate
into compact models to assist microwave circuit design.
APPENDIX A
In this appendix, we derive the open-circuit noise voltage at
the drain terminal due to thermal noise generated by
an infinitesimal section in Region I. Since the drain fluctuation
current is zero under the assumed open-circuit drain conditions,
of an taking the differentiation of in (11) and neglecting second-
order terms, we then obtain
(A.1)
or
(A.2)
NGUYEN AND FENG: DDN MODEL OF MOSFETs FOR MICROWAVE CIRCUIT DESIGN 3441

Integrating (A.2) over the length of Region I, the noise voltage depletion width , and hence, the potential of
at the critical point due to is thus seen by the charge sheet now becomes

(A.3)

Since the drain current is kept constant, the critical voltage

also does not change its value. Therefore, the noise fluctu- (B.5)
ation at the critical point can only vary the length of both
Region I and Region II such that Next, the dipole potential difference can be calculated by dif-
ferentiating of (B.5), as seen by
(A.4)

This kind of noise induced CLM eventually results in the

drain voltage fluctuation, which can be obtained by differenti-
ating (8)

(A.5) (B.6)

where is a hyperbolic function shown by If we approximate the results to the lowest order term, and
consider the potential difference distribution for both cases
and , we finally obtain (19).
(A.6)
APPENDIX C
Under short-circuit drain condition, the appearance of any
The function is always larger than 1, thus thermal noise gen- noise voltage in Region I results in a drain current fluc-
erated by Region I is enhanced at the drain terminal. As ex- tuation . Applying the – relation given in (13), we can
pected, when . Substituting (A.3) into (A.5), write
we obtain (15).

APPENDIX B (C.1)

The potential distribution due to a charge dipole is calculated

in this section. As described in Fig. 12(a), a charge sheet of
density spreading from to and put where the function is defined by
on top of a ground plane at has a potential expressed in
general space-harmonic form by (C.2)

Taking the perturbation of , one obtains

(B.1) (C.3)
The potential satisfies the following boundary condi-
tions: Substituting (C.3) into (C.1) and neglecting high-order terms
lead to the following differential equation:
(B.2)
(B.3) (C.4)

The first condition is satisfied by choosing the functions rep- The solution of (C.4) is (33), which satisfies the conditions
resenting , while the second condition can be solved for at , and at .
using Fourier expansion, as seen by The coefficient in (33) is employed to account for the fact
that if , then it is not necessary that
at the end of Region I. At , from (33), the potential
(B.4) discontinuity is given by

For the MOSFET case shown in Fig. 12(b), we have assumed

(C.5)
the mobile carriers drifting through Region II confine within the
3442 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 12, DECEMBER 2010

The coefficient can then be determined by substituting (15) ACKNOWLEDGMENT

into (C.5) and considering
circuit conditions, as seen by
under short-
The authors would like to thank Dr. K. C. Wang, United Mi-
croelectronics Corporation (UMC), Hsinchu, Taiwan, for pro-
gram support. The authors are also appreciative of many valu-
(C.6) able discussions and feedbacks from Dr Y. J. Chuang, Skyworks
Inc., Woburn, MA.

REFERENCES
APPENDIX D [1] V. Dimitrov, J. B. Heng, K. Timp, O. Dimauro, R. Chan, M. Hafez,
From the integration of (39), we derive the quantity in J. Feng, T. Sorsch, W. Mansfield, J. Miner, A. Kornbit, F. Klemens, J.
Bower, R. Cirelli, E. J. Ferry, A. Taylor, M. Feng, and G. Timp, “Small-
(40). The result is signal performance and modeling of sub-50 nm nMOSFETs with f
above 460-GHz,” Solid State Electron., vol. 52, pp. 899–908, Jun. 2008.
[2] A. J. Scholten, L. F. Tiemeijer, R. van Langevelde, R. J. Havens, A. T.
A. Zegeres-van Duijnhoven, and V. C. Venezia, “Noise modeling for
RF CMOS circuit simulation,” IEEE Trans. Electron Devices, vol. 50,
no. 3, pp. 618–632, Mar. 2003.
(D.1) [3] A. J. Scholten, R. van Langevelde, L. F. Tiemeijer, and D. Klasssen,
“Compact modeling of noise in CMOS,” in Proc. IEEE Custom Integr.
where the coefficients are given by Circuits Conf., San Jose, CA, 2006, pp. 711–716.
[4] R. Navid, C. Jungemann, T. H. Lee, and R. W. Dutton, “High-fre-
quency noise in nanoscale metal oxide semiconductor field effect tran-
sistors,” J. Appl. Phys., vol. 101, 2007, Art. ID 124501.
[5] K. Han, H. Shin, and K. Lee, “Analytical drain thermal noise current
model valid for deep submicron MOSFETs,” IEEE Trans. Electron De-
vices, vol. 51, no. 2, pp. 261–269, Feb. 2004.
[6] A. J. Scholten, L. F. Tiemeijer, R. van Langevelde, R. J. Havens, A. T.
A. Zegers-van Duijnhoven, R. de Kort, and D. B. M. Klaassen, “Com-
pact modeling of noise for RF CMOS circuit design,” Proc. Inst. Elect.
Eng.—Circuits Devices Syst., vol. 151, no. 2, pp. 167–174, Apr. 2004.
[7] F. Danneville, H. Happy, G. Dambrine, J. Belquin, and A. Cappy,
“Microscopic noise modeling and macroscopic noise models: How
good a connection?,” IEEE Trans. Electron Devices, vol. 41, no. 5, pp.
779–786, May 1994.
[8] W. Shockley, J. A. Copeland, and R. P. James, “The impedance
field method of noise calculations in active semiconductor devices,”
in Quantum Theory of Atoms, Molecules, Solid State, P. Lowdin,
Ed. New York: Academic, 1966.
[9] C. H. Park and Y. J. Park, “Modeling of thermal noise in short-channel
MOSFETs at saturation,” Solid State Electron., vol. 44, pp. 2053–2057,
Nov. 2000.
[10] H. Statz, H. A. Haus, and R. A. Pucel, “Noise characteristics of gallium
arsenide field-effect transistors,” IEEE Trans. Electron Devices, vol.
ED-21, pp. 549–562, Sep. 1974.
[11] G. D. Nguyen, Y. Chiu, and M. Feng, “24-GHz low noise amplifier
using coplanar waveguide series feedback in 130 nm-CMOS,” in IEEE
From the integration of (48), we derive the quantity in Asia–Pacific Microw. Conf., Singapore, Dec. 2009, pp. 1148–1151.
[12] K. Takeuchi and M. Fukuma, “Effects of the velocity saturated region
(49). The result is on MOSFET characteristics,” IEEE Trans. Electron Devices, vol. 21,
no. 9, pp. 1623–1627, Sep. 1994.
[13] W. Firky, G. Ghibaudo, S. Cristoloveanu, and M. Dutoit, “Method for
extracting deep submicrometre MOSFET parameters,” Electron. Lett.,
(D.2) vol. 31, no. 9, pp. 762–764, Apr. 1995.
[14] M. El-Bana and M. A. Nokali, “A simple analytical model for hot-
where the coefficients are given by carrier MOSFET’s,” IEEE Trans. Electron Devices, vol. 36, no. 5, pp.
979–986, May 1989.
[15] Y. Tsividis, Operation and Modeling of the MOS Transistor. Oxford,
U.K.: Oxford Univ. Press, 2004.
[16] Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices. Cam-
bridge, U.K.: Cambridge Univ. Press, 2002.
[17] A. B. Grebene and S. K. Ghandhi, “General theory for pinched op-
eration of the junction-gate FET,” Solid State Electron., vol. 12, pp.
573–589, Jul. 1969.
[18] J. Ruch, “Electron dynamics in short channel field-effect transistors,”
IEEE Trans. Electron Devices, vol. ED-19, no. 5, pp. 652–654, May
1972.
[19] A. Sai-Halasz, M. F. Wonderman, D. P. Kern, S. Rishton, and E.
Gamin, “High transconductance and velocity overshoot in nMOS
devices at 0.1-m gate-length level,” IEEE Electron Device Lett., vol.
9, no. 9, pp. 464–466, Sep. 1988.
[20] H. Hu, “Experimental study of electron velocity overshoot in silicon in-
version layers,” Ph.D. dissertation, Dept. Phys., MIT, Cambridge, MA,
1994.
NGUYEN AND FENG: DDN MODEL OF MOSFETs FOR MICROWAVE CIRCUIT DESIGN
[21] A. Lochtefeld, I. J. Djomehri, G. Samudra, and D. A. Antoniadis, “New
insights into carrier transport in n-MOSFETs,” IBM J. Res. Develop.,
vol. 46, pp. 347–357, 2002.
[22] W. Baechtold, “Noise temperature in silicon in the hot electron region,”
IEEE Trans. Electron Devices, vol. 18, no. 12, pp. 1186–1187, Dec.
1971.
[23] J. P. K. Aufinger and J. Boeck, “A straightforward noise de-embedding
method and its application to high-speed silicon bipolar transistors,” in
Proc. ESSDERC, Sep. 1996, pp. 957–960.
[24] H. Hillbrand and P. H. Russer, “An efficient method for computer aid-
ednoise analysis of linear amplifier networks,” IEEE Trans. Circuits
Syst., vol. CAS-23, no. 4, pp. 235–238, Apr. 1976.
[25] J. Engberg, “Simultaneous input power match and noise optimization
using feedback,” in Eur. Microw. Conf. Dig., 1974, pp. 385–389.
[26] Y. Taur, C. H. Hsu, B. Wu, R. Kiehl, B. Davari, and G. Shahidi, “Satu-
ration transconductance of deep-submicron-channel MOSFETs,” Solid
State Electron., vol. 36, no. 8, pp. 1085–1087, Aug. 1993.
[27] C. Canali, C. Jacoboni, G. Ottaviani, and Alberigi-Quaranta, “High
field diffusion of electrons in silicon,” Appl. Phys. Lett., vol. 27, pp.
278–280, Sep. 1975.
[28] D. Gasquet, “Experimental and theoretical studies of transport param-
eters in semiconductors,” Ph.D. dissertation, Dept. Phys. Sci., Univ.
Montpellier II, Montpellier, France, 1984.
[29] C. Jungemann, B. Neinhus, C. D. Nguyen, B. Meinerzhagen, R. W.
Dutton, A. J. Scholten, and L. F. Tiemeijer, “Hydrodynamic modeling
of RF noise in CMOS devices,” in IEDM Tech. Dig., Dec. 2003, pp.
871–874.
[30] G. Knoblinger, “RF noise of deep-submicron MOSFETs: extraction
and modeling,” in Proc. ESSDERC, Sep. 2000, pp. 331–334.
[31] T. C. Lim, R. Valentin, G. Dambrine, and F. Danneville, “MOSFETs
RF noise optimization via channel engineering,” IEEE Electron Device
Lett., vol. 29, no. 1, pp. 118–121, Jan. 2008.
[32] W. Liu, MOSFET Models for SPICE Simulation Including BSIM3v3
and BSIM4. New York: Wiley, 2001.
Giang D. Nguyen (S’05) received the B.S degree
from the University of Technology, Ho Chi Minh
City, Vietnam, in 2000, and the M.S degree from
Bradley University, Peoria, IL, in 2005, both in
electrical engineering, and is currently working
toward the Ph.D. degree in electrical engineering at
the University of Illinois at Urbana-Champaign.
His research focuses on characterization and mod-
eling of MOSFET devices. He is also involved in RF
and mixed-signal integrated circuit design including
low-noise amplifiers and power amplifiers for high-
speed communications.
Mr. Nguyen was a recipient of the Vietnam Education Foundation Fellowship.
3443
Milton Feng (SM’82–F’92) received the Ph.D. de-
gree in electrical engineering from the University of
Illinois at Urbana-Champaign, in 1979.
From 1979 to 1983, he was Section Head of the
Material and Device Group, Torrance Research
Center, Hughes Aircraft Company, Torrance, CA.
From 1984 to 1991, he was with Ford Microelec-
tronics Inc., Colorado Springs, CO. He managed the
Advanced Digital Integrated Circuit Development
Program. He was then the Director of advanced
development, fabrication, and manufacturing tech-
nology on both digital and microwave/millimeter-wave programs. Since 1991,
he has been a Professor of electrical and computer engineering and a member
of the faculty of the Center for Compound Semiconductor Microelectronics,
University of Illinois at Urbana-Champaign. He was named the first Nick
Holonyak Jr. Professor of Electrical and Computer Engineering in 2000,
and the first Nick Holonyak Jr. Endowed Chair of Electrical and Computer
Engineering in 2005. He is the cofounder of Xindium, Champaign, IL, and a
board member of Supertex, Sunnyvale, CA (NASDAQ). In 2004, he co-dis-
covered the first transistor laser. In 2007, he (along with his students) made
the fastest heterojunction bipolar transistors (HBTs) with cutoff frequency,

ft 845 GHz. He has authored or coauthored over 190 journal papers and 150
conference papers. He holds 17 patents in the areas of high-speed microelec-
tronics, opto-electronics, and integrated circuits (ICs). His research interests
include III–V material and heterostructure field-effect transistors (HFETs),
opto-electronic devices, RF microelectromechanical systems (RFMEMS)
devices, HBTs, optical and microwave ICs, as well as RF CMOS technology.
Dr. Feng has been a Fellow of the Optical Society of America (OSA) since
2003. He was the recipient of the prestigious 1997 IEEE David Sarnoff Award
and the 2000 Outstanding Research Award of the Dr. Pan Wen Yuan Foundation
for outstanding contribution of noise reduction in microelectronics.