Chapter 4

The Stack, Subroutines, Interrupts and Resets

In many computers, memory is divided into three distinct areas:
- program area
- data area
- stack

The stack is an area of memory used for the temporary storage of information. Subroutines and
interrupts make use of the stack.

The stack pointer (SP) is a register within the µP that contains the address of the next location
available for the stack.

The µP’s internal logic causes the SP to decrement automatically when data is stored in the stack and
to automatically increment when it is removed. Therefore, the SP must initially be set to the
highest address in the stack area (called the top of the stack).

e.g., if the stack is to occupy locations $0200 to $02FF then use LDS #$02FF instruction as
initialization before using the stack.

SP instructions are:
- DES SP - 1 → SP
- INS SP + 1 → SP
- LDS M:M + 1 → SP (in immediate, direct, extended and indexed modes)
- STS SP → M:M + 1 (in direct, extended and indexed modes)
- TXS IX - 1 → SP
- TSX SP + 1 → IX
- TYS IY - 1 → SP
- TSY SP + 1 → IY

PUSH and PULL Instructions

The push (PSH) and pull (PUL) instructions store and load data to and from the stack.

PSHA (or B or X or Y) instruction writes the contents of the specified register in the stack at the SP
location (at the location whose address is contained in SP) and then decrements the SP once (for
PSHA and PSHB) or twice (for PSHX and PSHY) because the original stack location is no longer
vacant but contains the pushed data.

PULA (or B or X or Y) instruction first increments the SP once to point to the last item that has been
inserted into the stack and then transfers the contents of the stack appropriately to the specified
register.

Note that once the contents of a stack location have been pulled, the location is considered vacant,
although the data is still there. It will be overwritten by the next PUSH or other use of the stack. Also
note that the stack acts as a Last-In-First-Out (LIFO) structure. A pull instruction retrieves the
information that was last pushed onto the stack.

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 Stack structure and stack operations

Subroutines

When the same function is required more than once in a program, it is frequently written as a
subroutine, that is, a subprogram that can be used any number of times by the main program. This
capability is provided by the following three instructions;

o JSR (jump to subroutine)

o BSR (branch to subroutine)
o RTS (return from subroutine)

The following figure illustrates the use of the same subroutine by two different parts of the main
program. The subroutine located at $0200 can be entered from either location $0011 or $00CC by
placing a JSR (opcode = $BD) instruction at these addresses.

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JSR $0200 has the machine code “BD 02 00” in the extended addressing mode. After the subroutine
is completed (i.e., when a return from subroutine RTS instruction is executed), the program resumes
from the instruction following the location where it called the subroutine. The example shows that in
the first jump (a), the program returns back to $0014 when it executes the RTS and in the second
jump (b), the program returns back to $00CF following the execution of the RTS. Because the
subroutine must return to one of several locations, depending on which one caused it to be entered,
the original contents of the PC must be preserved so that the subroutine knows where to return.

IX + K

Note that JSR instruction has both indexed and extended modes. With the complete exucution of JSR,
the address of the next instruction to be executed (the one following the JSR) is stored automatically
in the stack and the PC is changed appropriately according to the addressing mode used for JSR i.e.,
the PC is changed to have the address of the first instruction in the subroutine.

BSR (branch to subroutine has only the relative addresing mode and the subroutine start address is
calculated by the CPU by using the offset value provided in the prpgram memory after the opcode of
the BSR.

Each subroutine must have RTS (return from subroutine) as the last insatruction of the subroutine.
With the execution of the RTS, the CPU restores the PC from the stack automatically and therefore
the program returns back to the instruction where it has left before the jump or branch to the
subroutine has occurred. The following example is for the extended case in the above figure:

...
39 = RTS [n +3] H
[n +3] L

Action of the RTS instruction

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Nested subroutines: Since PC saving and recovery is automatic by the use of stack, it is possible to
execute nested subroutines as follows.

Note that the stack state in the figure corrsponds to the time at which the processor executes
instructions within the second subroutine. Also note that if the stack is used for register savings in a
subroutine, the recovery should be done in the reverse order and in a balanced fashion, otherwise the
return address cannot be recovered properly into the PC.

Example: If a subroutine uses accumulators A and B and the CCR, how can the main program
preserve the contents of these registers?

The first four instruction of the subroutine may be

Opcode Mnemonic

36 PSHA
37 PSHB
07 TPA
36 PSHA

which puts A, B and CCR on the stack as follows:

Contents of the stack after entering the

subroutine and executing the first four
instructions

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Before returning to the main program, these registers should be restored in the subroutine in the
reverse order before the RTS as follows:

Opcode Mnemonic

32 PULA
06 TAP
33 PULB
32 PULA
39 RTS

Example: Solve example 9 (square from a lookup table) as a subroutine and use it in a main program
to calculate the square of two numbers stored in locations $41 and $42. Pass the input and the
output parameters using accumulator A only. Store the result in $43 and $44.

label mnemonic comment

SQR LDX #SQTAB load the base address of the table
TSTA check the input number
BEQ FOUND if it is zero, stop searching and goto FOUND
CONT INX otherwise; point to the next table entry
DECA decrement A
BNE CONT and repeat for a number of times
FOUND LDAA $00,X get the corresponding table entry
RTS return from subroutine

MAIN LDAA $41 get the input data

JSR SQR
STAA $43 store the first result
LDAA $42
JSR SQR
STAA $44 store the second result
END BRA END

Example: Write an M68HC11 program, which performs the following task:

• There is a data array which starts in the memory location $0500. The length of the array is given
in the memory location $0040.

• Some of the elements of the given array will be placed to another area in the memory starting at
location $0900. Each element of the original array will be checked whether it is a 2-digit valid
BCD number or not and will be placed in the new array by reversing its bit order if it is valid, i.e,
if the content of the memory location $0500, for example, is a valid 2-digit BCD number
X7X6X5X4X3X2X1X0 then X0X1X2X3X4X5X6X7 will be stored to the memory location $0900. If
the number is not a valid 2-digit BCD number, then it will not be stored. At the end, the memory
location $0041 will hold the total number of bytes in the new array.

• Write the BCD checking part of your code as a subroutine.

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Solution: (write comments for the program as an exercise)

MAIN
LDS #$STACKBASE
LDX #$0500
LDAB $40
STAB BYTECOUNT
LDY #$0900
CONT
LDAA $00,X
JSR CHKBCD
BNE CONT2
VALID
LDAB #$08
STAB BITCOUNT
CONTSHIFT
LSLA
ROR $00,Y
DECB
BNE CONTSHIFT
INY
CONT2
INX
DEC BYTECOUNT
BNE CONT
END
BRA END

CHKBCD
TAB
DAA
CBA
RTS

Interrupts and Resets

An interrupt is an hardware (sometimes software) initiated subroutine call or jump that interrupts the
currently executing program. Depending on the type of the interrupt and the logic state of the I bit in
the condition code register, the CPU may suspend its normal operation and service the interrupt.

The software used in response to the interrupt signal is called an interrupt service subroutine. After
the interrupt service subroutine is executed, the CPU returns to the original program segment and
resumes execution as if no interrupt has occurred. This requires the CPU’s registers to be saved when
CPU services an interrupt and to be returned unaltered when the service subroutine is finished. An
interrupt service subroutine ends with an RTI instruction (not an RTS) that automatically restores the
CPU registers.

Interrupt vectors

All resets and interrupts use vectors indicating the start address of reset or interrupt subroutines.
68HC11 uses a vector table to store these vectors.

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The vector addresses are fixed and they are at a permanent part of the chip - usually at the ROM area.
Hence, one has to tell the factory what to put in those areas before the mass production of the chip. In
order to be able to change the start address of any interrupt subroutine, something called a
pesudovector is used in the development boards. For example in Motorola EVBU Development
Boards, pesudovectors are reserved in the RAM area.

For each interrupt, the corresponding interrupt vector contains an address in the base page (memory
locations between $00 and $FF). The three-byte memory area starting from this RAM location is then
the pseudovector for the corresponding interrupt. Hence the user places the actual service subroutine
anywhere in the memory map and then writes a three byte jump instruction in the corresponding
pseudovector, which effectively means that the associated subroutine is executed in the case of the
corresponding interrupt.

The IRQ vector (locations $FFF2 and $FFF3) of the chip on the EVBU development board contains
$00EE. If the three byte RAM locations starting at $00EE is made to contain a “JMP Address”
instruction (machine code $7E AdressH AddressL) then in the event of an IRQ interrupt, the program
executes the code starting at location Address as illustrated below.

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When the signal at pin IRQ goes low, the CPU responds by putting the vector contents (i.e., $00EE)
to the PC, CPU then executes the instruction at $00EE, in this case JMP $C15A. Therefore, the actual
service subroutine starts at $C15A.

Interrupt masks and enables

An interrupt signal may or may not be recognized under programmer’s control by mostly setting the
interrupt mask bit (I bit) in the CPU’s CCR. If I = 1, CPU does not recognize interrupt signals =>
Interrupts are masked. I bit can be set by using the SEI instruction and cleared by using the CEI
instruction.

Stacking the registers

When an interrupt request occurs CPU pushes all CPU register values to stack in the order: PC, IY,
IX, ACCA, ACCBA, CCR (pushing low byte first for 16-bit registers). When RTI is executed the data
is pulled from the stack and the registers are restored.

For RESET: No stacking of the registers.

All interrupt service subroutines should end with an RTI instruction.

Hardware interrupts and resets

RESET: Executed whenever the chip is powered up and whenever the external RESET pin is
activated. Highest priority.

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Other processor resets: Computer Operating Properly (COP) failure reset, COP clock monitor fail
reset.

Nonmaskable interrupt (XIRQ): is used to handle the highest priority interrupts. When you power up
or RESET 68HC11, XIRQ is masked, i.e. X bit in CCR is set. To clear X, TAP (Transfer from ACCA
to CCR) instruction should be used.

Interrupt Request (IRQ): is maskable by setting bit I in the CCR.

IRQ 68HC11

XIRQ

IRQ versus XIRQ

1. CPU can ignore the IRQ input if the I flag is 1; it can ignore XIRQ if the X flag is 1. However
I flag can be set and cleared any time by software. X flag can be cleared only once and then it
remains at 0.
2. IRQ can be programmed as a level-sensitive or edge-sensitive input via the IRQE bit in the
OPTION (at $1039) register. XIRQ is always level sensitive.
3. XIRQ input has higher priority over IRQ input. When they are activated simultaneously
(while X=I=0), CPU will respond to XIRQ first.

Example of XIRQ interrupt

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Software and CPU control interrupts

Software interrupt (SWI): SWI instruction forces the CPU to respond the same way as it does to an
externally generated interrupt. It is useful in debugging the programs. Not maskable by I or X bits in
CCR.

Wait for Interrupt (WAI): When the WAI instruction is executed, 68HC11 reduces its power while
waiting to be woken up. All registers are stacked and only an unmasked interrupt wakes up the
controller.

STOP: When the STOP instruction is executed, if S bit in CCR is set, STOP performs like a NOP. If S
bit is reset, all internal clocks halt, thus halting the execution. To wake up the controller, RESET,
XIRQ or IRQ (when I=0) must be used.

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Steps that 68HC11 follows to service the IRQ.

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