92 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 10, NO.
1, MARCH 2010
A Novel Nanoscale 4H-SiC-on-Insulator MOSFET
Using Step Doping Channel
Ali A. Orouji, Member, IEEE, and Hossein Elahipanah
Abstract—In this paper, we present the unique features ex-
hibited by a novel step doping channel technique in nanoscale
silicon carbide metal–oxide–semiconductor field-effect transis-
tors (SDC-MOSFETs) for reaching a suitable threshold volt-
age upon device scaling and reliability improvement. The device
demonstrates large enhancements in performance areas such as
output resistance, hot-electron reliability, and threshold voltage
upon channel-length or drain-voltage variation. Also, we describe
an optimization technique in SDC-MOSFET for improving the
threshold-voltage characterization. It was also found that the
device performance is very much dependent upon the SDC region
parameters. Results show that the most difficult problem of using
silicon carbide in VLSI circuits could be solved and that the
proposed silicon carbide MOSFETs can work very well in the
nanoscale regime.
Index Terms—Channel engineering, hot carrier, metal–oxide–
semiconductor field-effect transistor (MOSFET), silicon carbide
(SiC), step doping, threshold voltage.
I. I NTRODUCTION
N OWADAYS, two main paths are explored to continue im-
proving the performances of metal–oxide–semiconductor
field-effect transistors (MOSFETs): new structures and new
materials [1]. As scaling continues, it becomes harder to
fabricate devices without compromising performance due to
undesirable effects such as threshold voltage roll-off, drain-
induced barrier lowering (DIBL), and degraded subthreshold
swing [2]–[9]. A number of structures have been proposed to
these problems [6], [7], [10]–[12]. On the other hand, with
new fabrication technologies, silicon carbide (SiC) semicon-
ductors can be promising candidates to achieve sub-100-nm
high-performance MOSFETs due to their unique electrical and
physical properties. SiC is better than silicon in terms of many
characteristics such as leakage current, breakdown voltage,
power dissipation, high temperature working, gate capacitance,
and DIBL [2]–[4].
One of the key design parameters in CMOS technology
is threshold voltage [5]–[9]. Therefore, one of the problems
affecting SiC MOSFETs is the control of threshold voltage that
is hardly dependent on the band gap of the channel material.
Silicon carbide devices have a higher threshold voltage than the
silicon ones. However, to the best of our knowledge, a confident
Manuscript received March 16, 2009; revised July 8, 2009. First published
November 3, 2009; current version published March 5, 2010.
The authors are with the Department of Electrical Engineering,
Semnan University, Semnan, Iran 35196-45399 (e-mail: aliaorouji@ieee.org;
hosseinelahipanah@yahoo.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TDMR.2009.2035511
1530-4388/$26.00 © 2010 IEEE
solution for this problem of SiC-on-insulator devices has not yet
been reported in the literature.
On the other hand, hot-electron reliability is a severe problem
in conventional deep-submicrometer MOSFETs in which high
substrate doping, which is used to prevent the punchthrough
effect, leads to large electric fields and enhanced impact ioniza-
tion [13]–[15]. The electrons generated via the impact ioniza-
tion process tend to be injected into the gate oxide (leading to a
threshold-voltage shift and the degradation of channel mobility)
or are injected into the drain. The generated holes are swept into
the substrate, thus giving rise to substrate leakage current and
enhanced impact ionization due to the forward biasing of the
source/substrate junction [5]–[8], [13]–[15].
Therefore, in this paper, a novel step doping channel (SDC)
has been proposed for channel engineering in high-performance
SiC MOSFETs (SDC-MOSFETs). The proposed device has
a special SDC region on the source side of the channel. In
this paper, we first describe the optimization technique that is
developed for SDC-MOSFET threshold-voltage (VT ) charac-
terization, based on 2-D device simulations and VT mapping
on the length and doping of the SDC region simultaneously. It
showed that the novel device structure exhibits more suitable
threshold voltage upon device scaling, higher output resistance,
and higher operation frequency. Also, using a 2-D Silvaco
ATLAS simulator (energy balance model and 2-D Monte Carlo
particle-based simulations) [16], we examine the hot-electron
reliability of SDC-MOSFETs [17], [18]. Both the 2-D Silvaco
ATLAS and the 2-D Monte Carlo particle-based simulator show
that the built-in electric fields at the source side of the channel,
due to the presence of the SDC region, lead to enhanced
current-drive capabilities of SDC-MOSFETs when compared
to conventional SiC MOSFETs (C-MOSFETs).
II. D EVICE S TRUCTURE AND S IMULATION
The 4H-SiC-on-insulator SDC-MOSFET structure is shown
in Fig. 1. The lengths of the channel and source/drain re-
gions are 90 and 20 nm, respectively. Also, the depth of the
source/drain junction has been chosen to be 15 nm for the de-
vice. The typical value of the channel doping density is 5×
1018 cm−3 . The doping values in the source/drain and substrate
regions are kept at 5×1019 cm−3 and 5×1016 cm−3 , respective-
ly. The typical values of the length and doping density of the
SDC region are chosen to be 20 nm and 1.5×1019 cm−3 , re-
spectively. All the device parameters of the SDC-MOSFET are
equivalent to those of the C-MOSFET, unless otherwise stated.
Simulations were performed with the ATLAS 2-D device
simulator, in which a drift/diffusion and a 2-D Monte Carlo
OROUJI AND ELAHIPANAH: NOVEL NANOSCALE 4H-SiC-ON-INSULATOR MOSFET USING STEP DOPING CHANNEL
Fig. 1. Cross-sectional view of a silicon carbide SDC-MOSFET structure.
Fig. 2. Variation of threshold voltage by the length and doping density of the
SDC region in the SDC-MOSFET.
particle-based model were used. Also, it is imperative to use
accurate SiC property models [16], [19]–[21] in order to
achieve realistic results. It is worth noting that the 2-D simulator
is calibrated to experimental data in the micrometer regime
[22]–[24]. Therefore, a good agreement between experimental
data and 2-D simulation results is achieved.
III. R ESULTS AND D ISCUSSION
As already discussed in the Introduction, the SDC-MOSFET
has an asymmetric channel doping profile that influences the
device performance. Therefore, threshold voltage is a function
of not only the doping density of the SDC region but also
the length of the SDC region. To understand the relationship
between the SDC parameters and threshold voltage, we have
simulated a large number of SDC-MOSFETs with different
values of the doping density and length of the SDC region.
Then, the extracted threshold voltages are mapped on a plane
of the SDC region (the length and doping density of the SDC
region on the horizontal and vertical axes, respectively). A
sample plot for a 90-nm-gate-length SDC-MOSFET is shown
in Fig. 2. From these plots, it is possible to find the length
and doping density of the SDC region for the desired threshold
voltage. As can be seen from the figure, we can find a suitable
threshold voltage upon device scaling, with the help of choosing
the appropriate doping density and length of the SDC region.
93
Fig. 3. Normalized drift velocity along the channel for different SDC-
MOSFETs with respect to the C-MOSFET for VG = 1.1 V and VD = 0.9 V.
Fig. 4. Normalized carrier energy along the channel for different SDC-
MOSFETs with respect to the C-MOSFET for VG = 1.1 V and VD = 0.9 V.
As the MOSFET channel lengths have penetrated into the
deep-submicrometer regime, many undesirable effects, causing
deviations from the ideal performance of the transistor, have
become more apparent [5]–[7]. One of these effects is hot-
electron degradation [13]–[15]. In short-channel MOSFETs,
the electric fields are extremely large, which results in a higher
percentage of hot carriers in the inversion channel that can be
trapped in the oxide [2], [7], [13]. Drastic changes in threshold
voltage and transconductance result from this oxide charging
[21]. Oxide charging is accumulative over time, and hence, the
effect limits the lifetime of the device. These unwanted effects
are expected to be less pronounced in SiC due to the large band-
gap and the very short energy relaxation time constant (it is
approximately ten times shorter than that in silicon) [2]–[4].
A 2-D Monte Carlo particle-based simulator has been used
to examine the enhancement in the current-drive capabilities
of SDC-MOSFETs with respect to C-MOSFETs. The Monte
Carlo model, which is used in the transport portion of the
simulator, is based on the usual band structure [17], [18].
In simulations, impact ionization and interface traps suggest
that source-to-drain tunneling might take place in the device
structure, thus leading to enhanced OFF-state leakage currents
[5]–[7]. The presence of a built-in electric field near the source
end of the channel can significantly accelerate those electrons
94 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 10, NO. 1, MARCH 2010

TABLE I
SDC R EGION PARAMETERS AT A F IXED T HRESHOLD VOLTAGE OF VT = 0.6 V AND L = 90 nm

that make it over the potential barrier [8]–[11]. Similar electric-

field conditions exist in bipolar junction transistors with lightly
doped regions and graded-channel MOSFETs [10]–[12], [21].
The normalized electron drift velocity and the electron energy
along the channel of the SDC-MOSFET with respect to the
C-MOSFET are shown in Figs. 3 and 4, respectively. Note that
both drift velocity and electron energy are low in the front
end of the SDC region. Because of the built-in field in the
SDC-MOSFET, once electrons surmount the potential barrier
at the source end of the channel, their energy and velocity
increase rapidly. Low electric fields at the middle and the drain
end of the channel lead to a reduction in both drift velocity
and electron energy. Hence, substrate leakage currents due to
impact ionization will reduce. The drift velocity is relatively
low near the source end of the channel, which, as will be shown
Fig. 5. Transfer characteristics of the SDC-MOSFET for VD = 0.3 V.
later, leads to at least 50% smaller drain current when compared
to the drain current of the SDC device. On the other hand, the
electron energy at the drain end of the channel is larger in the
C-MOSFET than that in the SDC-MOSFET. This gives rise to
hot-carrier degradation in C-MOSFETs and can be reduced by
the introduction of lightly doped regions. Simulations show that
electrons have a lower energy distribution in SDC-MOSFETs
as compared to that in C-MOSFETs, which can be explained
by the higher density of states at low energies [13], [21].
In Table I, we list five different combinations of SDC
parameters in the same threshold voltages that lead to the
best device performances. One should note that the device
performances are not identical in the five combinations of SDC
parameters, even though the threshold voltage is the same.
As can be seen from Table I, the drain current of the SDC-
MOSFET will reduce if the SDC parameters change from high
Fig. 6. ID –VD characteristics of the SDC-MOSFET compared with that of
doping densities and small lengths to low doping densities and the C-MOSFET under VG = 1.6-V and L = 90-nm conditions.
large lengths. These are important features of the SDC region.
Therefore, if we need a high-current SDC-MOSFET and the Fig. 7 shows the substrate currents of the C-MOSFET and
device reliability is less important, high doping and small length the SDC-MOSFET. In spite of the insulator layer that could
are best. For high reliability, low doping and large length have reduce the leakage currents, the substrate current is a good
to be used. Therefore, by using an appropriate SDC region, the indicator of hot-carrier degradation [13]–[15]. It is a common
threshold voltage of SiC devices can easily be reduced, and the practice to measure substrate and gate currents for MOSFETs
current drive and reliability of the device are controlled. to characterize hot-carrier degradation [14], [15], [21]. The
The transfer and output characteristics of the SDC-MOSFET substrate currents of the SDC-MOSFET are significantly lower
and the C-MOSFET are shown in Figs. 5 and 6, respectively. than those of the C-MOSFET, as shown in Fig. 7. Substrate
As can be seen from the figure, the threshold voltage of the current is also dependent on the parameters of the SDC region.
C-MOSFET is about VT = 1.1 V at 1-μA/μm drain current, Substrate current will increase if the SDC parameters change
and for the SDC device, depending on the length and doping of from low doping densities and large lengths to high doping
the SDC region, threshold voltage could be varied from VT = densities and small lengths.
0.5 to 1 V. Our simulations suggest that the SDC-MOSFET
IV. C ONCLUSION
being investigated exhibits a significantly higher drain cur-
rent when compared with the C-MOSFET performance. For We have proposed an optimization technique for reduc-
example, for a gate voltage VG = 1.0 V, the current of the ing threshold voltage in SiC MOSFETs with SDC. Using
SDC-MOSFET is at least 50% larger than the drain current of threshold-voltage plots for different SDC parameters, we have
the C-MOSFET. determined the SDC parameters that set the threshold voltage
OROUJI AND ELAHIPANAH: NOVEL NANOSCALE 4H-SiC-ON-INSULATOR MOSFET USING STEP DOPING CHANNEL
Fig. 7. Substrate current versus gate voltage for the SDC-MOSFET and the
C-MOSFET.
at the targeted value for the best device performance. We found
that, if the system requirements include high-current drive or
low-power operation, one needs to use the SDC region with
high doping density and small length. On the other hand, if
we require long device lifetime, for example, in high-power
and high-voltage circuits, then large length and low doping
density for the SDC region need to be used. Both 2-D Monte
Carlo particle-based simulations and Silvaco ATLAS simula-
tions suggest performance enhancement of SDC devices with
respect to C-MOSFETs. An increase in drain current at the
highest drain voltage has been found for the SDC device
when compared to the C-MOSFET device. Also, the substrate
current of the SDC-MOSFET is much lower than that of the
C-MOSFET, which presented lower hot-carrier degradation
in the proposed MOSFET. In addition to the good properties
of SiC MOSFETs, the proposed technique has given us
the opportunity to reduce threshold voltage and hot-electron
degradation by using silicon carbide in CMOS low-power
integrated circuits.
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Ali A. Orouji (M’05) was born in Neyshabour, Iran,
in 1966. He received the B.S. and M.S. degrees
in electronic engineering from Iran University of
Science and Technology, Tehran, Iran, in 1989 and
1992, respectively, and the Ph.D. degree from the
Indian Institute of Technology, Delhi, India, in 2006.
Since 1992, he has been with the Department of
Electrical Engineering, Semnan University, Semnan,
Iran, as a Faculty Member. His research interests
are in modeling of SOI MOSFETs, novel device
structures, and analog integrated-circuit design.
Hossein Elahipanah was born in Semnan, Iran,
in 1982. He received the B.S. degree in biomed-
ical engineering from the University of Isfahan,
Isfahan, Iran, in 2005. He is currently working to-
ward the M.S. degree in the Department of Electrical
Engineering, Semnan University, Semnan.
His research interests include novel nanoscale
CMOS structures, IV- and III–V-based power struc-
tures, and SOI device modeling.