IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO.
10, OCTOBER 2010
Physics, Technology, and Modeling of
Complementary Asymmetric MOSFETs
Constantin Bulucea, Fellow, IEEE, Sandeep R. Bahl, Senior Member, IEEE, William D. French,
Jeng-Jiun Yang, Member, IEEE, Pascale Francis, Tikno Harjono, Vijay Krishnamurthy,
Jon Tao, and Courtney Parker, Member, IEEE
Abstract—The physics, technology, and modeling of comple-
mentary asymmetric MOSFETs are reviewed and illustrated with
statistically representative silicon data from a recent manufactur-
ing implementation, in which the transistors for the secondary
power supply voltage are offered in asymmetric and symmet-
ric constructions. The in-depth analysis of the device physics of
asymmetric transistors provides new insights into their physical
operation and into the operation of transistors using halo im-
plants in general. The variability, matching, and noise implica-
tions of using halo implants are also analyzed, concluding that
both asymmetric and symmetric devices need to be offered for
uncompromised circuit design. The challenges associated with the
compact modeling the asymmetric transistors are also reviewed
and illustrated. The preferred manufacturing implementation
uses retrograde wells with no dopant fillers at the surface, while
avoiding the drain-to-source punch-through by source-side-only
halo implants. In addition to the known switching speed and
maximum voltage gain advantages of the asymmetric transis-
tors, this particular device architecture offers superior hot-carrier
reliability and transistor design flexibility. The availability of ret-
rograde wells enables construction of high-reliability complemen-
tary extended-drain MOSFETs for a third higher power supply
voltage.
Index Terms—Analog, antipunch-through, asymmetric,
BSIM3, compact modeling, CMOS, cutoff frequency, deep and
lightly doped drain extension (DLDD), doping-gradient-induced
barrier lowering (DGIBL), doping profile, drain-extended MOS,
drain-induced barrier lowering (DIBL), drift-diffusion, dual gate
oxide (DGO), empty-well, extended-drain, extended-drain MOS
(XD-MOS), gate-induced drain leakage, gate-induced source
leakage (GISL), graded-channel, halo, high-voltage, hot-carrier,
large-scale-integration (LSI), laterally diffused MOS (LDMOS),
matching, Medici, MOSFET, mixed-signal, noise, output
resistance, reflection coefficient, reliability, retrograde well,
scattering theory, single-pocket, STI, subcircuit, switching speed,
system-on-a-chip, T-gate, threshold adjust, transconductance,
trench, TSuprem-4, variability, vertical diffused MOS (VDMOS),
voltage gain.
Manuscript received March 22, 2010; revised June 18, 2010; accepted
June 21, 2010. Date of publication August 5, 2010; date of current version
September 22, 2010. The initial phase of this work was supported in part by
the State of California through matched funding under the Microelectronics
Innovation and Computer Research Opportunities Research Project 04-090.
The review of this paper was arranged by Editor A. Schenk.
The authors are with National Semiconductor Corporation, Santa Clara,
CA 95052-8090 USA (e-mail: constantin.bulucea@nsc.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2010.2057197
0018-9383/$26.00 © 2010 IEEE
2363
I. I NTRODUCTION
H ISTORICALLY, the planar MOSFET has been the first
major active device to be built and used in symmet-
ric input–output construction. This has been possible due its
input–output reversibility, allowing the simplest implementa-
tion of bidirectional sampling switches, and due also to its un-
precedented functional density in large-scale-integration (LSI)
circuits.
The circuit and device structure requirements for the in-
put and output terminals of amplifying or switching devices
are different in most applications, particularly in analog and
mixed-signal applications. This means that using symmetric
MOSFETs implies design compromises and diminished perfor-
mance in comparison with the ideal situation of using optimized
asymmetric devices. Still, the economics of large-scale integra-
tion has dictated the use of symmetric MOSFETs.
However, with advanced scaling, the output characteristics of
the transistor degrade toward diminished voltage gain, which is
critical to analog design. In large-scale integration of digital and
analog/mixed-signal/RF circuits such as in system-on-a-chip
systems, the economic balance changes in favor of accepting
the additional costs (masks and implants) for building better
optimized devices, such as asymmetric MOSFETs [1]–[4].
The asymmetric MOSFETs are not new. The MOS laterally
diffused transistors of both planar [5], [6] [laterally diffused
MOS (LDMOS), vertical diffused MOS (VDMOS)] and trench
(trench VDMOS) [7]–[9] construction are examples of well
known asymmetric power MOSFETs where the channels are
laterally nonuniform (diffused), and the source and drain con-
structions are different.
Asymmetric low-power MOSFETs using various implemen-
tations of graded channels or different source and drain re-
gions, or combinations of them, have also been proposed, built,
and analyzed [10]–[41]. In general, discussions emphasize the
advantages of asymmetric transistors over their conventional
symmetric counterparts, with little or no analysis of their lim-
itations and the optimum use in actual product development.
The terminology used to describe this class of MOSFETs is
quite nonuniform and includes designations such as asymmetric
(or asymmetrical), asymmetric halo, graded channel, lateral
asymmetric channel, laterally doped channel, single halo, sin-
gle pocket, etc. Although each designation has its own merits in
describing the nature of these transistors, we will use the simple
asymmetric MOSFET designation. We restrict it not to include
the LDMOS and VDMOS power transistors. Also, we restrict
2364 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010

our review and analysis to bulk devices, thus excluding silicon- II. D EVICE AND P ROCESS
on-insulator implementations [42]–[46]. A RCHITECTURE C ONSIDERATIONS
A conventional symmetric long-channel transistor is shut off
An asymmetric MOSFET can be generally described as a
over the entire length of its uniformly doped channel at gate
planar MOSFET having the following: 1) a laterally nonuni-
biases below the threshold voltage. At a closer analysis, the
form body profile (channel asymmetry) with or without
current flow in the channel only needs to be interrupted at
2) different source and drain regions (source/drain asymmetry).
a single location between the source and drain for the drain
Laterally nonuniform body profiles are typically implemented
current to be turned off. This can be done by providing the
with halo implants on the source-side of the channel, while
necessary threshold doping at that location.
different source and drain regions are created with different
In a systematic 2-D computer simulation analysis of the
masked implants over the source and drain regions or their
laterally nonuniformly doped long-channel MOSFET,
extensions.
Stockinger et al. [24] varied the position of the maximum
Attempting to build MOSFETs with channel asymmetry at
channel doping between the source and drain (i.e., the position
the minimum printable gate length typically involves aligning
where the channel current is interrupted), demonstrating that
of one mask edge to a position around the middle of the
the best drive/leakage performance is obtained when the
polygate regions, which is already printed at the limits of the
maximum channel doping is near the source and calling that
lithography capability. Although this has been the most typical
transistor structure “the peak device.”
implementation in research/development efforts, applying it to
The situation is more subtle in short-channel devices where
manufacturing is not a trivial task.
the graded nature of the channel doping differentiates the
A more realistic approach to exploiting the advantages of
asymmetric transistors from their symmetric counterparts.
asymmetric MOSFETs is to implement them for the secondary
Lundstrom’s scattering theory of the short-channel MOSFET
bias voltage of a given CMOS process, which is typically
[47]–[49] can be used in the analysis, as later discussed.
referred to as dual voltage or dual gate oxide (DGO) CMOS
Several circuit applications have been reported [50]–[63].
[64], [65]. The secondary voltage capability is obtained with
Yet, many subtleties of internal operation, compact modeling,
a longer gate and a thicker gate oxide than those of the pri-
and optimal use have largely remained uncovered, which has
mary bias voltage. For example, in a scaled CMOS process
precluded their entering into the mainstream circuit design.
designed for a 1.2-V primary power supply voltage, having
This paper reviews the physics, technology, and modeling of
0.13-μm minimum gate length and ∼2-nm physical gate oxide
complementary asymmetric MOSFETs specifically integrated
thickness, the asymmetric MOSFETs would be implemented
for analog and mixed-signal applications, with new insights
with gate lengths of 0.25 μm or more and a gate oxide of
from a recent development of a manufacturing process.
∼6 nm, allowing a secondary bias voltage of 2.5 V or more.
A brief discussion of the available choices in devising an
Obviously, aligning the mask edges of the halo or source/
asymmetric MOSFET architecture in terms of device, process,
drain extension implants to positions around the middle of the
and power supply voltages in Section II leads to our preferred
gate is no longer a lithography challenge at gate lengths that are
empty well implementation, used for illustration throughout the
at least two times larger than the minimum printable values.
entire paper.
Another major architecture consideration is the choice of the
Section III presents a top-level review of the advantages and
type of the doping profile of the well in which transistors are
challenges of asymmetric MOSFETs, in comparison with their
built. Typically, the well profiles of symmetric DGO transistors
symmetric counterparts, intentionally keeping the discussion at
in a scaled CMOS process are made of a high-energy main well
a qualitative level.
that is subsequently filled with lower energy implants designed
The manufacturing of the asymmetric and symmetric
to fend off the channel punch-through (antipunch-through im-
MOSFETs in the aforementioned preferred architecture is out-
plant) and to insure the nominal threshold voltage of the process
lined in Section IV, followed by a discussion of the limits
(threshold adjust implant). For CMOS processes with gate
in boosting the drive capability of the asymmetric MOSFETs
lengths larger than 0.25 μm, the halo implants are not required,
in Section V. Section VI analyzes the device physics of the
so that the threshold voltage VT is roughly determined as
asymmetric transistors in greater depth, using a combination
of drift-diffusion TCAD and physical reasoning based on the VT = αQV T Adjust + βQAP T (1)
scattering theory of the short-channel MOSFETs.
Section VII is dedicated to the analysis, based on statistically where QV T Adjust and QAP T are the areal doses of the
validated silicon data, of the switching speed performance and threshold adjust and antipunch-through implants, respectively,
scaling, followed by a similar analysis of the small-signal and α and β are locally calibrated geometry- and energy-
speed in Section VIII. The variability, matching, and noise dependent coefficients measured in voltage/dose units. The
are discussed in Section IX. All these analyses are carried out contribution of the main well implant has been neglected in (1)
comparatively for asymmetric and symmetric MOSFETs. due to the typical retrograde nature of this implant in modern
The challenges of and solutions to the compact modeling of CMOS processes, which implies that little or no dopant from
the asymmetric transistors are briefly discussed in Section X. this well reaches within the depth of the depletion region under
Section XI describes the implementation of high-voltage the channel.
extended-drain transistors in our preferred architecture, illus- The simplest and most widely used way to convert a nonhalo
trating their cost and reliability advantages. symmetric MOSFET to an asymmetric, or graded-channel,
BULUCEA et al.: PHYSICS, TECHNOLOGY, AND MODELING OF COMPLEMENTARY ASYMMETRIC MOSFETs
Fig. 1. Cross-section of an asymmetric n-channel MOSFET using the empty-
well architecture. The p-channel counterpart is complementary to the one
shown.
counterpart is to add a halo implant at the source end of the
channel. Obviously, this will add a third term, γQHalo , to
(1), thus increasing the threshold voltage. Hence, the threshold
adjust or the antipunch-through dose, or both, needs to be
reduced to insure the same threshold voltage. The antipunch-
through and threshold adjust implants can be both eliminated,
thus leaving the relatively stronger halo pocket at the source,
with the threshold voltage determined as
VT = γQHalo . (2)
The aforementioned process architecture has been preferred
in the process development used for illustration in this paper,
with the observation of a substantial increase of the channel
mobilities through diminished carrier-impurity scattering (next
section). This architecture will be heretofore referred to as
empty-well architecture for brevity.1
III. S TRUCTURE AND F IRST-O RDER P HYSICAL
M ODELING OF A SYMMETRIC MOSFETs
The basic device structure of an n-channel MOSFET with
channel and source–drain asymmetry using the empty-well
architecture is described in Fig. 1.
The channel asymmetry is created by using a halo implant
only on the source-side, while the source–drain asymmetry is
created by using a deep and lightly doped drain extension (deep
LDD, or DLDD) and a conventional or more heavily doped
source extension. Optionally, the n-channel transistors can be
isolated from the p-type substrate with a deep n well. The
p-channel structure is perfectly complementary to its n-channel
counterpart except that it does not have, nor does it need, a deep
well isolation.
In a first-order compact model representation, this transistor
can be seen as a combination of a threshold transistor, Q1 ,
representing the portion of the channel containing the graded
channel implant, and a main-channel transistor, Q0 , represent-
ing the rest of the channel, with the channels connected in
1 In sub-0.25-μm symmetric MOSFETs using halo implants, the threshold
adjust implant can be safely dropped [66], which actually improves the switch-
ing speed. The antipunch-through implant can be dropped too, but severe long-
range reverse-short-channel effects make this option less attractive.
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Fig. 2. First-order compact model of an asymmetric MOSFET. Q1 and Q0
are the threshold and main-channel transistor, of the two-transistor subcircuit,
respectively.
series and the gates and body regions each tied together, as
represented in Fig. 2.
The schematic representation of the device structure in Fig. 1,
along with the compact model in Fig. 2, is sufficient for a
first-order physical discussion of the essential features of the
asymmetric MOSFETs in comparison with their symmetric
counterparts. The symmetric MOSFETs used in our compari-
son later are nonhalo transistors built in the same process (see
Section IV), having the same gate oxide thickness, channel
width and channel length, and similar threshold voltages. The
discussion is intentionally kept at a qualitative level.
A. Greatly Improved Hot-Carrier Reliability
With no halo at the drain side of the channel and with a
deeper lightly doped extension, the electric field in the drain
region, in normal operation, is lower than in a symmetric tran-
sistor. Therefore, at high drain voltages, the transistor operates
farther away from the avalanche breakdown condition at the
drain-well junction, hence with fewer hot carriers around the
surface.
The aforementioned improvement is substantial. For a
quantitative illustration, our typical 3-V/0.3-μm asymmetric
n-channel transistors built in empty-well architecture measure
around 400 years extrapolated hot-carrier lifetimes for either
VT or IDsat (drain saturation current) degradation. These
lifetimes compare to 25 and 10 years in typical 3-V/0.4-μm
symmetric transistors, for VT and IDsat , respectively, at the
same threshold voltage and voltage stressing conditions. The
large reliability margin of the asymmetric transistors points to
the possibility to use them at subminimum DGO gate lengths,
e.g., 0.25 instead of 0.3 μm, for improved speed performance,
as discussed later in Section VII.
B. Increased Drain Saturation (“Drive”) Current
In long-channel devices, at a given gate voltage overdrive, the
main-channel transistor of the two-transistor model, Q0 , having
a weakly doped channel, is in a stronger inversion condition
than the threshold transistor Q1 . Therefore, it contributes with a
smaller channel resistance to the total resistance of the channel
in comparison with the situation when the entire channel is
doped at the level required for setting the threshold voltage.
Compared at the same gate voltage overdrive and drain voltage,
2366 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010

the drain current of the asymmetric transistor is substantially

larger than the one in its symmetric counterpart.
In short-channel devices, the scattering theory of the short-
channel MOSFET [47]–[49], calling for an increased electric
field within a mean free path from the source-channel barrier
can be used to understand the observed increased drive current
[38]. In the absence of the drain halo, the great majority of
the field lines originating from the positively ionized donors
in the drain region terminate on the oppositely charged ionized
acceptor in the source halo, increasing the electric field there
(n-channel case).
In our classification of transistors into long- and short-
channel, a short-channel transistor is conventionally defined
around the minimum gate length that can be controlled in
lithography and etching, or used with acceptable hot-carrier
reliability, in the manufacturing of the respective transistors. In
our review illustration, the minimum gate length is 0.13 μm
(lithography control limit) for the first voltage (1.2 V) and
0.30 μm (conservatively defined reliability limit) for the sec-
ondary voltage (3 V) of the CMOS process. Consequently,
secondary-voltage transistors with gate lengths around 0.30 μm
are referred to as short-channel transistors.

C. Larger Drain Saturation Voltage in Long-Channel Devices

A larger drain saturation voltage is observed in long-channel
MOSFETs, which is an undesirable property. This is a direct
consequence of the weak body doping around the drain region
caused by the absence of a halo implant there. As the drain
voltage is increased, the drain field easily pushes the boundary
of the drain depletion region at the surface, toward the source,
reducing the effective length of the channel and delaying the on-
set of the pinch-off condition. This trend eventually stops when
the boundary of the heavily doped source halo is approached,
and the device enters a region of strong saturation.
In short-channel asymmetric transistors, this effect is less
visible and may even be reversed.
D. Improved Saturation of the Drain Current (Larger Output
Resistance in Saturation)
Once the transistor enters the drain saturation regime, the
drain field can no longer push into the source halo region,
and a stronger saturation sets in (larger output resistance) in
comparison with a symmetric transistor. Moreover, with the
reduced field at the drain, the drain current has little or no
tendency to creep up due to impact ionization toward the end
of the drain voltage range.
Properties B–D are illustrated in Fig. 3(a) (long-channel) and
Fig. 3(b) (short-channel), based on our typical 3 V silicon. The
long-channel threshold voltages are 0.62 and 0.53 V for the
asymmetric and symmetric transistors, respectively.
The drain saturation voltage shown in these figures is con-
ventionally defined as
VDsat ≈ VG − VT (3)
for symmetric transistors [67], [68] and is calculated with an
empirical equation for asymmetric counterparts. Regardless of
Fig. 3. (a) Typical output I–V characteristics of (thick lines) long-channel
asymmetric and symmetric n-channel MOSFETs with L = 5 μm and W =
10 μm. (b) Typical output I–V characteristics of short-channel asymmetric and
symmetric MOSFETs with L = 0.3 μm and W = 10 μm. The arrows indicate
the drain current increase in asymmetric transistors compared to symmetric
counterparts biased at same gate overdrive, as marked. All characteristics are
at zero body bias, VB = 0 V.
the exact definition of VDsat , it is obvious from this illustra-
tion that in long-channel asymmetric MOSFETs of same gate
length, L and width W , VDsat is larger than the one calculated
with the commonly used approximation (3).
E. Increased Linear and Saturation Transconductance
Both long- and short-channel transistors turn on more effi-
ciently in asymmetric construction, offering an increased linear
transconductance, gm , with a higher peak value at the inflection
point of the ID (VD ) characteristics, as shown in Fig. 4(a)
(long-channel) and Fig. 4(b) (short-channel).
In short-channel devices built at the minimum gate length,
the transconductance is flatter (less peaked) around the maxi-
mum value, hence easier to capitalize on in applications (see
Section X).
The increased linear transconductance property is more sub-
tle in nature. No first-order model is proposed to explain it other
than observing that, for monotonically increasing ID (VG , VD )
functions, this property is mathematically expected, except
for the unlikely situation when the drain current increase in
asymmetric devices is the same at all drain voltages.
BULUCEA et al.: PHYSICS, TECHNOLOGY, AND MODELING OF COMPLEMENTARY ASYMMETRIC MOSFETs
Fig. 4. (a) Typical transfer I–V characteristics of (thick lines) long-channel
asymmetric and symmetric n-channel MOSFETs with L = 5 μm and W =
10 μm. (b) Typical transfer I–V characteristics of short-channel asymmetric
and symmetric MOSFETs with L = 0.3 μm and W = 10 μm. In all cases, the
drain current of the asymmetric transistors increases more rapidly around the
inflection point of the transfer characteristic, providing substantial transconduc-
tance advantage. All characteristics are at VB = 0 V.
The asymmetric transistors also show a higher saturation
transconductance, gmsat .
F. Increased Maximum Voltage Gain
Combination of increased output resistance (property D) and
increased saturation transconductance (property E) result in an
increased maximum voltage gain
AMax = gmsat · rout
which is particularly important in analog design.
G. Improved Small-Signal High-Frequency Behavior
Deriving directly from the transconductance comparison and
assuming similar gate capacitances, Cg , the small-signal cutoff
frequency [67]
gm
fT ≈
Cg
2367
is expected to be higher in transistors having channel asym-
metry than in their symmetric counterparts. With channel pro-
file changes leading to reduced gate capacitances, the cutoff
frequency is even higher. The maximum oscillation frequency
fmax being related to fT [68], tends to follow the same trend.
A more detailed discussion of these properties is provided in
Section VIII.
H. Larger Parameter Variability and Noise
The asymmetric transistors have larger parameter variability
and noise in comparison with their symmetric counterparts that
do not use halo implants. These limitations are discussed in
Section IX.
IV. M ANUFACTURING OF A SYMMETRIC AND S YMMETRIC
MOSFETs IN E MPTY-W ELL P ROCESS A RCHITECTURE
The fabrication process of the asymmetric MOSFETs used
in the introductory discussion before consists of a conventional
submicrometer DGO CMOS process with changes to provide
the following: 1) retrograde substrate wells (empty-well archi-
tecture); 2) graded channel; and 3) deeper and more lightly
doped drain extensions (DLDD) than the source extensions
for the DGO transistors, as represented in Fig. 5. Unlike a
conventional halo implant, the graded-channel (halo) implant
is applied only on the source-side of the channel, through a
dedicated mask.
The minimum gate length of this process is 0.13 μm, which
corresponds to a primary supply voltage and electrical gate ox-
ide thickness in inversion of 1.2 V and 2.8 nm, respectively. The
secondary supply voltage and electrical gate oxide thickness in
inversion are 3.0 V and 6.2 nm, respectively. Both oxides are
grown using an in situ steam generation process [69].
Aside from allowing the manufacturing of high-performance
reliable asymmetric transistors, the empty-well architecture has
the advantage of enabling multiple combinations of well and
LDD/halo implants for manufacturing of several types of “free
devices,” such as symmetric DGO MOSFETs, low-threshold-
voltage MOSFETs, low-cost bipolar transistors, complemen-
tary high-voltage MOSFETs, etc.
The complementary symmetric MOSFETs are particularly
required in the design of the bidirectional sampling switches
(transmission gates or T-gates), where the drain and source
functions change during circuit operation as the voltage applied
at the input of the switch increases or decreases.
(4) The simplest approach to integrate symmetric transistors into
a process architecture that is primarily designed for asymmetric
transistors is to apply the graded channel implant at both the
source and drain ends of the channel. Although used in the
past [54], this approach tends to yield unreliable symmetric
transistors due to the high electric field in the drain region. The
doping concentration of the graded channel implant is higher
than that of a conventional halo implant, which intensifies the
electric field around the drain end of the channel.
Differently from the aforementioned transistors, reliable
symmetric transistors are formed if the well profiles of the low-
(5)
voltage transistors, filled with all their implant components,
2368
Fig. 5. Simplified representation of the process architecture used in manufacturing transistors with channel and source–drain asymmetry in empty-well
architecture.
Fig. 6. Cross-section of a symmetric n-channel MOSFET combining the
filled wells of the low-voltage transistors and the deep lightly doped drain
extensions of the asymmetric empty-well transistors. The p-channel MOSFET
is perfectly complementary to the one shown.
are combined with the deep LDD implants of the asymmetric
transistors, as shown in Fig. 6. Compatible threshold voltages
are obtained, without the use of halo implants, due to the
relatively higher doping levels in the low-voltage wells. The
minimum gate lengths of transistors so built may be different
from those of asymmetric counterparts due to manufacturing
and hot-carrier reliability requirements. For example, in our
preferred empty-well architecture, the asymmetric transistors
had a minimum gate length of 0.3 μm for convenient manu-
facturing, while symmetric were restricted to a minimum gate
length of 0.4 μm for hot-carrier-lifetime considerations. The
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010
characteristics of these symmetric transistors are similar to
those of conventional foundry DGO transistors at comparable
voltage specifications [70].
Extended-drain transistors capable of operating at 12 V drain
voltage can be also manufactured as “free devices” through
combination of existing implants and masks, as separately
discussed in Section XI.
V. H OW M UCH B ETTER D RIVERS THE A SYMMETRIC
T RANSISTORS C AN B E IN C OMPARISON W ITH
T HEIR S YMMETRIC C OUNTERPARTS ?
As shown in Section III, the asymmetric transistors are better
drivers, at given gate overdrive, than their symmetric counter-
parts. The asymmetry can be further enhanced by providing
more heavily doped source extensions, thus reducing the para-
sitic voltage drop on the source series resistance. This results in
additional increase of the drive current, which naturally leads
to the question on how far the asymmetric drive performance
can be pushed. The answer to this question depends on the
specifics of the applications in which these transistors are used,
as described below.
In applications where the body terminal is permanently con-
nected to the source terminal and the drain is always at a higher
potential than the source, the source extension can be doped as
heavily as possible, with the benefit of greater drive current.
In applications where the body terminal is not connected to
any of the source, or the drain terminals and the drain terminal
BULUCEA et al.: PHYSICS, TECHNOLOGY, AND MODELING OF COMPLEMENTARY ASYMMETRIC MOSFETs
Fig. 7. GISL in reverse drain–source bias as a function of the drain saturation
current in forward drain–source bias for a typical n-channel asymmetric
MOSFET with various conditions of the source extension implant.
can be at a lower potential than the source, the source extension
needs to be doped at a moderate level to avoid the gate-induced
drain junction leakage of the reverse transistor. Except for
inventive circuit designs exploiting specific characteristics of
reversely biased transistors [62], [63], the intentional use of
such devices is not recommended due to their known degraded
punch-through behavior and hot-carrier reliability [11], [12].
However, transient situations of reverse biasing may occur
in circuit operation. In such situations, the source and drain
change their function in device operation, the source working
as a drain and vice-versa.
Holding the source and drain designations of the transistor
terminals unchanged, as determined by their layout, irrespec-
tive of relative bias, this effect will hereafter be referred to
as gate-induced source leakage, or GISL, for similarity with
the gate-induced drain leakage [68]. For a custom-designed
process, a tradeoff has to be made between having superior
driving capability in normal transistor operation and manage-
able source junction leakage in reverse transistor operation,
when the source is biased at a higher potential than the drain.
The GISL effect is best characterized through special drive-
leakage characteristics where the source leakage with reverse
drain–source bias, is plotted, in logarithmic scale, against the
drain saturation current in forward drain–source bias, in linear
scale. Fig. 7 shows the GISL characteristics of our empty-well
process for various implant conditions of the source extension
implant.
The GISL current is measured with the source and drain tied
together to differentiate the junction from the channel leakage,
and the body terminal is grounded. The leakage through the
drain junction has been determined to be unimportant from
prior measurements on the same circuit with the drain con-
nected to the power supply voltage (normal drain biasing).
The raw data set has been reduced to a same-threshold-voltage
equivalent data set through statistical modeling using the JMP
software [71]. One can see that the dose of the source ex-
tension implant is the primary controller of the drive/source-
leakage tradeoff, while the energy and the angle play secondary
roles.
2369
Fig. 8. Three-dimensional representation of the doping profile. The vector
data based on the highly nonuniform mesh of the simulator was processed
into a regular matrix format, using bicubic spline interpolation, before the final
visualization processing in MathCAD.
VI. I N -D EPTH D EVICE P HYSICS A NALYSIS
The typical I–V characteristics illustrated in Section III
show that the asymmetric transistors have larger drive cur-
rents and transconductance in comparison with their symmetric
counterparts. In the following two sections, this property is
discussed in greater physical detail.
A. Long-Channel Case
In long-channel devices, the increased drive current can be
easily understood using the two-transistor model, as already
discussed in Section III. Moreover, the empty-channel nature
of the channel transistor Q0 (Fig. 2) suggests that, with fewer
impurities in the channel, the increased carrier mobility is
expected to result in an increase in the drain current, at constant
gate overdrive. In addition, an important portion of the drain
current increase is explained by the favorable field structure in
these transistors from the point of carrier transmission over the
source-channel barrier of the threshold transistor Q1 . The high
field at the source end of the channel, required by the scattering
theory for maximizing the drain current [47]–[49], is present in
these transistors.
Being aware of the difficulties associated with probing the
limitations of the drift-diffusion theory in silicon, where the
saturation velocity vsat , entering the drift-diffusion equations,
and the thermal velocity vT , entering the scattering theory
equations, happen to be similar, we will not attempt to prove
the drift-diffusion theory wrong. On the contrary, we confirm
that, with appropriate coefficient calibration, accurate matching
between experimental data and the drift-diffusion simulations
can be obtained. Yet, the electrical field structure inside the
device, revealed by these simulations, provides considerable
arguments in support of the scattering theory.
Fig. 8 shows, in a 3-D representation, the net doping profile
of a 1-μm asymmetric transistor resulted from the simulation of
2370
Fig. 9. Distribution of the electric potential and lateral electric field at the surface of an (a) symmetric and (b) asymmetric n-channel MOSFET built in the
empty-well architecture described in Section IV. Shaded areas indicate depletion regions. Notice the strong electron extracting field at the inside edge of the
source-channel depletion region of the asymmetric MOSFET.
our empty-well process using the TSuprem IV process simulator
[72] with coefficients calibrated to the actual profiles described
by corroborated spreading-resistance probe and secondary ion
mass spectroscopy characterization.
Fig. 9(a) and (b) represent the distribution of the electric
potential and longitudinal electric field at the surface, calcu-
lated with the drift-diffusion equations using the Medici device
simulator [73] for VG = VT + 0.2 V and VD = 1.5 V, along
with simplified 1-D representations of the device structure
at the surface for the symmetric and asymmetric transistors,
respectively. The source-channel portion of each device is
subdivided into Source (S), Source Extension (SE), and Source
Halo (SH) regions of substantially different doping, in order
to ease understanding of the field structure in terms of the
classical transistor theory. Similarly, the drain-channel portions
are divided into Drain (D) and Drain Extension (DE) regions.
At low current levels, the drift-diffusion simulations are
believed to be fairly accurate, regardless of the drift-diffusion-
versus-scattering discussion, considering that the field is elec-
trostatically determined by the doping structure and the applied
voltages.
Starting with the simpler field situation of the symmetric
transistor [Fig. 9(a)], one can identify the essential features
of the field distribution. The two peaks of the longitudinal
electric field, Ex , at the source end of the channel can be easily
associated with the n+ (Source)/n (Source Extension) high-
low junction and the n (Source Extension)/p (Body) junction,
respectively. The same identification applies to the drain end of
the channel.
Continuing with the asymmetric transistor [Fig. 9(b)], one
notices a third field peak at the source end of the channel,
which is associated with the p+ (Source Halo)/p (Body) high-
low junction. No additional feature is noticed in the drain
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010
region, as expected in the absence of a halo doping there. A
strong electron extracting field is present at the channel edge
of the source-channel depletion region, which reduces back-
scattering of the electrons that have surmounted the potential
barrier.
In view of the scattering theory, the source/source-
extension/source-halo region can be seen as a near-ballistic
transistor corresponding to the threshold transistor Q1 of the
two-transistor compact model in Fig. 2. The function of a local
drain for this transistor is provided by the built-in field of
the graded halo doping, which extracts the electrons over the
source-channel barrier. From there on, the extracted electrons
are taken over by the conventional long-channel field-effect
mechanism of the main channel transistor Q0 in the two-
transistor compact model.
In the aforementioned physical interpretation, it is important
to realize that the drive current of the asymmetric transistor is
limited by the carrier emission over the barrier and the scatter-
ing phenomena taking place in transistor Q1 . In particular, the
magnitude of the built-in field in the source halo region, desir-
ably as high as possible, controls the channel backscattering (or
reflection) coefficient r and ultimately the drive current of the
whole transistor.
It is interesting to calculate the drain current of transistor
Q1 in the scattering-limited ballistic mode, with the reflection
coefficient of the electrons calculated as

1 − v vT
r=  ≈ 0.18. (6)
1 + v vT
In the aforementioned equation, the average velocities v are
calculated by the drift-diffusion simulator from the local current
densities, and vT is the thermal velocity in silicon, roughly
BULUCEA et al.: PHYSICS, TECHNOLOGY, AND MODELING OF COMPLEMENTARY ASYMMETRIC MOSFETs 2371

estimated at 1.5 × 107 cm/s, based on Assad et al.’s quantum–

mechanical calculations [49], assuming a gate length of 130 nm
for our threshold-channel transistor (matched compact mod-
eling value) and using the electron density of 5 × 1012 cm−2
calculated by the simulator.
The particular value of r quoted in (6) is calculated at a
position in the channel where the electric potential increases
by kT /q = 26 mV from the minimum value at the source-
extension/source-halo barrier, roughly corresponding to a
50-nm lateral distance from the location of that minimum
[Fig. 9(b)]. It is substantially better than r ≈ 0.4 reported before
for symmetric 0.30-μm MOSFETs [49]. This indicates a more
efficient carrier extraction at the source-channel barrier, as
expected for transistors with shorter gates and more favorable
field structure around the source-channel barrier.
Using the scattering theory equation for VD  kT /q,
one gets, with the aforementioned values and Cox = 4.7 × Fig. 10. Compared distributions of the electric potential at the surface of
10−3 F/m2 , at VG − VT = 0.2 V and VD = 1.5 V symmetric and asymmetric n-channel MOSFETs built in the empty-well archi-
tecture described in Section IV and having similar threshold voltages. Notice
  the barrier lowering induced by the doping gradient (DGIBL) in the source halo
1−r region of the asymmetric transistor.
ID1 /W = Cox vT (VG − VT ) = 98 A/m (7)
1+r
TABLE I
which represents the scattering-theory drain current of the RING OSCILLATOR STAGE DELAYS, 3-V MOSFETs
threshold transistor Q1 alone, at the specified gate overdrive
and drain voltage. This value is (1 − r)/(1 + r) = 70% of
the ballistic limit of the same transistor. However, the mea-
sured current of the composite transistor Q1 + Q2 , ID /W =
19.6 A/m, it is only 20% of the scattering-theory current of the
threshold transistor Q1 due to the effect of the main channel
transistor Q0 , which acts as a current-limiting series resistance.
In addition to limiting the current, the parasitic resistance
increases the drain saturation voltage, as already reported [49].
This is an alternate explanation of the observed increased drain
saturation voltage in long-channel asymmetric transistors (see
Section III). B. Short-Channel Case
Comparing the potential distribution in the symmetric and
asymmetric devices, a ΔΦ S = 120 mV lowering of the gate- In short-channel devices, the electron-extracting field around
controlled source-channel barrier at the surface is observed in the source-channel barrier is increased, as qualitatively dis-
the asymmetric device, which independently contributes to an cussed in Section III. Hence, the scattering theory and the
increase of the electron injection at the source. This effect is DGIBL effect can explain the observed increased drive current.
similar to the customary drain-induced barrier lowering (DIBL) The analysis is similar to the one already used for the long-
[68] but is produced by the built-in field in the halo region channel case.
rather than by the field from the drain bias. Hence, it is not
associated with a degraded output resistance of the transistor.
VII. S WITCHING S PEED P ERFORMANCE
We will call it doping-gradient-induced barrier lowering, or
DGIBL, for similarity with and to differentiate from the DIBL Having higher drive currents and transconductance (see
[68]. An explicit illustration of this effect is provided in Fig. 10, Figs. 3 and 4), the short-channel asymmetric transistors are
where the surface potential distributions in the symmetric and expected to be faster digital switchers than their symmetric
asymmetric devices are compared for transistors manufactured counterparts. This has been verified through compared ring-
in the same process and having similar threshold voltages. oscillator measurements, using 101-stage CMOS rings built
The DGIBL effect explains why asymmetric transistors, with asymmetric and symmetric 3-V transistors, each type of
while providing locally much higher dopant concentrations transistor having the minimum gate lengths allowed by the
to their body regions, can still be manufactured at the respective hot-carrier reliability requirements and widths opti-
same threshold voltage as their symmetric counterparts. mized for maximum switching speed.
Thompson et al. [74] have also observed changes in the thresh- Table I compares the stage delays and the standard de-
old voltage associated with dopant-controlled changes in the viations observed on ring oscillators built with symmetric
built-in potential barrier at the source-channel junction of short- and asymmetric 3-V transistors. The last row includes the
channel symmetric transistors using halo implants. data for even faster ring oscillators built with subminimum
2372
Fig. 11. Scaling of inverter stage delays with gate lengths in CMOS ring
oscillators built with symmetric and asymmetric transistors. The two minimum
gate lengths, L, specified on the figure are for the NMOS/PMOS transistors,
respectively. The marked percentage improvements refer to the respective
switching speeds (∼1/τ ).
(0.25 μm) gate length transistors that are still hot-carrier reli-
able, in our empty-well architecture (10 years threshold lifetime
versus 400 years for the conventionally defined minimum gate
length of 0.3 μm). The ring oscillators built with the conser-
vatively defined minimum-gate-length asymmetric transistors
switch 35% faster than those built with symmetric devices. The
similar comparison using subminimum gate lengths (0.25 μm)
asymmetric devices yields a 64% speed advantage.
In this earlier comparison, the minimum gate lengths of the
symmetric n-channel MOSFETs are slightly larger than those
of the asymmetric ones, i.e., 0.4 μm versus 0.3 μm. This the
due to the hot-carrier lifetime requirements, as the symmetric
transistors, having no halo implants, are built on more heavily
doped wells (see Fig. 6). Hence, a speed comparison at the
same gate length is in order, which is done by the extrapolation
of the available ring oscillator results down to 0.3 μm gate
lengths using Taur’s scaling equation [68]. The input and output
capacitances of the inverter stage, Cin and Cout are assumed
to be constant in the small range of gate lengths of interest.
The saturation current densities per unit width in each point of
the plot are obtained from 10-μm wide transistor test structures
available on the same die with the ring oscillator structure.
This same-gate-length comparison is included in Table I and
shown in Fig. 11, revealing a 24% switching speed advantage of
inverter stages built with asymmetric transistors over symmetric
counterparts having the same gate lengths. Table I and the chart
in Fig. 11 also include the ring oscillator data for the high-
speed asymmetric MOSFETs built at subnominal gate lengths
that still do not compromise the hot-carrier reliability. In this
case, the speed improvement over the ring oscillator built with
symmetric transistors is 51%.
VIII. S MALL -S IGNAL S PEED P ERFORMANCE
The small-signal cutoff frequency of transistors with channel
asymmetry has been analyzed in detail by device simulations
that estimate up to 36% improvement in comparison with
symmetric transistors of otherwise similar construction [33],
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010
Fig. 12. Measured cutoff frequency fT of symmetric and asymmetric
n-channel transistors compared at the same gate overdrive voltage and similar
gate lengths. The inset compares the maximum cutoff frequencies, fT max ,
of transistors with 0.4 μm gate lengths, where the value corresponding to the
asymmetric transistor, not available on the test pattern, is interpolated, on the
trend line, between the values available at 0.3 and 0.6 μm.
[36], [52]. This has been primarily associated with the increased
transconductance of the asymmetric transistors, as already
stated in Section II.
An improvement of up to 20% has also been reported,
based on device simulations, for the maximum frequency of
oscillation, fmax [36].
In our empty-well implementation, the measured fT im-
provement in asymmetric transistors is higher than in the
aforementioned estimations due to the additional advantages
of a reduced channel doping, which favors increased carrier
mobilities and reduced gate capacitances. Fig. 12 compares
the silicon results of the fT measurements for asymmetric and
symmetric transistors at the same gate overdrive voltage. One
can observe that, for similar gate lengths, the cutoff frequency
of asymmetric transistors is substantially higher than that of
their symmetric counterparts.
For a comparison at exactly the same gate length, we have
chosen L = 0.4 μm. The maximum cutoff frequency fT max is
directly available at this gate length for the symmetric transistor.
The corresponding value of fT max for the asymmetric transis-
tors was interpolated on the trend line, between the available
gate lengths, as shown in the inset of Fig. 12.
This same-gate-length comparison results in a 1.5 times
higher fTmax of the asymmetric transistor. However, with their
large margin in hot-carrier reliability and drain–source leakage,
the asymmetric transistors can be built at substantially smaller
gate lengths than 0.4 μm and even than their nominal minimum
gate length of 0.3 μm. For example, at 0.25 μm gate lengths,
the asymmetric transistors are more than two times faster than
0.4 μm symmetric counterparts, while still remaining compara-
ble in hot-carrier lifetime and drain–source leakage.
Even more important than the aforementioned is the compar-
ison at low currents in the subthreshold regime. From Fig. 12,
one can observe a 3.5 times increased cutoff frequency at
zero gate overdrive. This makes the asymmetric transistors
particularly attractive in low-power high-frequency applica-
tions, where they can compete with SiGe-base bipolar junction
transistors designed for the same voltage range.
BULUCEA et al.: PHYSICS, TECHNOLOGY, AND MODELING OF COMPLEMENTARY ASYMMETRIC MOSFETs 2373

IX. PARAMETER VARIABILITY, M ATCHING , AND N OISE

The halo implants, which are unavoidable in symmetric
MOSFETs beyond the 0.25 μm lithography node, are generally
known to cause higher variability and worse matching of elec-
trical properties of respective devices in comparison with those
of nonhalo counterparts [75]–[79]. They are also known to be
noisier [4]. The asymmetric transistors, having strong halos at
the source, suffer from the same limitations.
In minimum-size symmetric halo transistors, the statistical
variations of the doping impurity positioning in the halo im-
plants have been reported to account for about 15% increased
variability of the threshold voltage in comparison with devices
having ideally contained dopants [75], [76]. More recently,
variability in the 20% range was reported for heavily doped
long-channel symmetric halo transistors [78]. Fig. 13. Laterally dithered representations of threshold voltages for
minimum-size symmetric and asymmetric complementary MOSFETs. The
The increased variability of the transistors containing halo standard deviations for the asymmetric transistors are more than double with
implants, in general, is believed to be due to the contribution reference to their symmetric counterparts, for both types of transistors, when
of the DGIBL effect, which can be qualitatively explained as compared at similar threshold voltages.
follows, based on our device physics analysis in Section VI.
The high gradient of the doping concentration in the source
halo region, in the vicinity of the source-channel junction, re-
sponsible for the DGIBL effect, is the result of the combination
of very abrupt impurity profiles of opposite type in the source
extension and halo regions. As such, it has increased sensitivity
to the fluctuating details of the competing doping profiles
involved such as the implant conditions, silicon point defects,
stress effects and the statistical variations of the impurity posi-
tioning in the confined space of the source extension and halo
regions. Moreover, the angled implants used in halo transistors
involve dopant variability inherently associated with the grain-
boundary diffusion through the edges of the polysilicon gates.
These multiple sources of variability result in increased lot-to-
Fig. 14. Compared spectral densities of the drain current noise of asymmetric,
lot, die-to-die, and even same-die (mismatching) threshold volt- symmetric, and reversely biased asymmetric n-channel MOSFETs at W =
age variability in transistors having halo implants in comparison 10 μm, ID = 80 μA, measured at f = 145 Hz as functions of gate length,
to nonhalo transistors. L (median values of nine devices from one typical wafer).
The increased variability of the MOSFETs containing halo edges, excessive implant damage, etc. These requirements are
implants is also present in asymmetric MOSFETs. On one particularly critical in analog applications.
hand, the variability is expected to increase because, in order In cases when asymmetric MOSFETs are integrated for their
to set a given threshold voltage, the source-only halo implants voltage gain and speed advantages, symmetric counterparts
used in asymmetric MOSFETs have higher doses that those without halo implants need to be concurrently available for use
used in symmetric devices with the same threshold voltage. On in circuits where variability and matching are critical.
the other hand, the variability is expected to decrease, as there is The spectral densities of the 1/f (flicker) noise of our
no halo at the drain, thus eliminating one source of variability. symmetric and asymmetric MOSFETs are plotted against the
In our minimum-size asymmetric transistors, the variability gate length in Fig. 14, along with the same property of the
of the absolute threshold voltage measured on matching pairs reversely biased asymmetric devices. It is important to observe
was comparable to the figures reported before for symmetric that, when biased normally, the asymmetric devices have 10 to
halo transistors. However, it is important to observe that sym- 100 larger 1/f noise in comparison with symmetric transistors.
metric transistors not using halo implants, manufactured in the Also, unlike in their symmetric counterparts, the 1/f noise is
same process for the same threshold voltage, measured down to not scalable with the gate length.
two times smaller variability, as shown in Fig. 13. Contrary to the aforementioned, when biased reversely, the
Device variability and poor matching pose considerable chal- same asymmetric transistors are well behaved, i.e., their noise
lenges to the integration of transistors containing halo implants spectral density follows the 1/(L)2 trend of the symmetric
in general. In addition to precise control of the implantation transistors [80].2 One can see that the roughly constant value
steps, the spacer formation unit process and the processing
sequence around the application of the graded channel implant 2 This experiment is cited here only in support of the physical reasoning on
and LDD extension must be optimized to minimize variability the origin of the increased noise in asymmetric transistors. Otherwise, using
inducing effects, such as undesirable implants through spacer reversely biased asymmetric transistors is not recommended.
2374
Fig. 15. Measured and modeled output characteristics of n- and p-channel
transistors with with L = 5 μm and W = 10 μm, at VB = 0 V.
of the increased spectral density measured in normally biased
asymmetric transistors corresponds to the extrapolated spectral
density of symmetric transistors at L ≈ 0.13 μm, which is the
gate length of the threshold transistor Q1 in the first-order
transistor model shown in Fig. 2. This is a strong indication
that the observed nonscalable noise of the asymmetric transistor
comes from the threshold transistor Q1 .
As a consequence of their increased 1/f noise, asymmetric
transistors are not recommended in circuits where noise is
critical. Symmetric counterparts should be used instead.
X. C OMPACT M ODELING OF A SYMMETRIC MOSFETs
Accurate modeling of the asymmetric MOSFETs is of para-
mount importance in enabling the design community to lever-
age their superior analog performance. The unavailability of
commercial compact models and the challenges associated
with in-house modeling have actually contributed to the rather
limited use of asymmetric transistors in the industry versus their
superior electrical capabilities.
Based on the physical understanding of the device physics
presented in Section VI, we developed a subcircuit model based
on two BSIM3 [81] transistors, Q0 and Q1 , connected in series
(Fig. 2). The threshold transistor Q1 controls the subthreshold
and near-threshold regions, while the main channel transistor
Q0 controls the saturation region of the I–V characteristic.
Scaling across geometries requires the use of binning pa-
rameters, which brings further challenges, such as the need
to minimize discontinuities between adjacent bins and te-
dious generation of the corner models. Yet, good model ac-
curacy can be achieved, as shown in Fig. 15 for the output
characteristics.
The transconductance is modeled for the minimum channel
length transistor (L = 0.3 μm) and for a long-channel device
(L = 1 μm), as shown in Fig. 16. Notice that the transconduc-
tance dependence on the gate voltage is more sharply peaked in
longer channel transistors, which calls for a design tradeoff be-
tween exploiting the increased transconductance and reducing
the biasing sensivity of the circuit performance.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010
Fig. 16. Normalized transconductance, gm . L versus VGS for 10-μm-wide
3-V asymmetric transistors of short and long channels (L = 0.3 and 1 μm,
respectively) at VD = 0.1 V, VB = 0 V.
Fig. 17. Maximum voltage gain, gm . rout , versus channel length, L, for
10-μm-wide 3-V asymmetric transistors at two different gate overdrive volt-
ages, and VD = 1.5 V, VB = 0 V.
Fig. 17 shows the scaling of the maximum voltage gain,
gm . rout , with the channel length L, along with the expected
spread, at two different gate overdrive voltages, based on the
fast and slow corner models. The larger variability in the longer
channel devices (L > 1 μm) is due to the more pronouncedly
peaked transconductance and higher output resistance, both of
which are inherently more difficult to control and characterize.
The plot also reveals that the maximum voltage gain actually
decreases for very long channel devices (L > 1 μm), which
restricts the useful high range of device sizes.
Fig. 18 shows the measured and modeled values of Cgs
and Cgd in their dependence of the gate voltage, where the
rising portion of the Cgd plot appears to be shifted toward
lower voltages and to peak at some greater value than the usual
1/2W L Cox of a symmetric transistor.
While the rather unusual behavior of Cgd has been analyzed
in great detail in the compact modeling literature [82]–[84],
a simple physical model of it is still desirable. The physi-
cal structure of the asymmetric transistor (Fig. 1), combined
with the two-transistor model (Fig. 2), invite a straightforward
BULUCEA et al.: PHYSICS, TECHNOLOGY, AND MODELING OF COMPLEMENTARY ASYMMETRIC MOSFETs
Fig. 18. Normalized gate capacitances Cgd and Cgs versus the gate voltage
VGS at VDS = 0 V for a long-channel (L = 1 μm) asymmetric transistor. The
measured Cgd rises to more than 1/2 W L Cox at gate voltages between the
threshold voltages of the component transistors Q0 (threshold) and Q1 (main).
physical explanation of the capacitance characteristics, as de-
scribed later.
1) When the gate is biased negatively, below the threshold
voltages of both transistors Q0 and Q1 , the source and
drain regions and their extensions provide the lower
plates of the gate-to-source and gate-to-drain capacitors,
respectively, thus reducing Cgs and Cgd to their respec-
tive overlap plus fringing capacitance values.
2) As the gate voltage is increased to voltages still below the
threshold voltage of the asymmetric transistor, the chan-
nel transistor Q0 gradually turns on, while the threshold
transistor Q1 remains off. This situation can be visualized
as having the lower plate of the gate-to-drain capacitor
extended under the gate. In long-channel transistors, the
length of the channel transistor takes up almost the entire
length of the transistor, which makes Cgd approach the
total gate-to-channel capacitance, W L Cox .
3) When the threshold voltage of the threshold transistor Q1
is reached and exceeded, the lower plate of the gate-to-
source capacitor also extends into the channel, increasing
Cgs . Eventually, the channel becomes continuous from
the source to the drain and the charge in the channel is
partitioned between the source and drain at nearly equal
values of Cgd and Cgs at 1/2 W L Cox , as experimentally
observed.
The subcircuit model is also able to capture other
particularities of the asymmetric devices, such as the larger
saturation voltage in long channel devices (see Section III),
the independence of the 1/f noise of the channel length (see
Section VIII), etc.
Finally, additional efforts have been devoted to extracting
operating point information for the whole transistor, knowing
that commercial simulators provide this information only for
the individual transistors of the subcircuit model. The anno-
tation on the schematic includes analytical expressions for
the transistor transconductance, output conductance, and the
saturation voltage VDsat .
2375
XI. E XTENDED -D RAIN MOSFETs IN E MPTY-W ELL
I MPLEMENTATION (“XD-MOS”)
In addition to the primary and secondary voltage transistors,
e.g., transistors biased from 1.2- and 3.0-V power supplies,
analog and mixed-signal circuits require transistors capable to
sustain a third “high” voltage, e.g., 12 V. These transistors
are typically needed in EEPROM devices, high-voltage output
buffers, display drivers, etc.
Higher voltage transistors can be integrated either as true
high-voltage laterally diffused MOSFETs (LDMOSFETs),
with the addition of a body mask and implant for each type
of transistor and with the drain-side end of the gate termi-
nating on the isolation oxide [85]–[95] or as “free” high-
voltage extended-drain MOSFETs, also called drain-extended
MOSFETs, using the p-well as the body region and the n-well
as a drain extension (n-channel MOSFETs) [96]–[105].
Since the terminology and description of these transis-
tors vary and are somewhat inconsistent, we will use the
high-voltage LDMOSFET for the former and high-voltage
extended-drain MOSFET for the latter. Of the two varieties, the
high-voltage extended-drain MOSFET is preferred in VLSI
circuits due to cost advantages. The high-voltage extended-
drain MOSFET built in the empty-well architecture will
hereafter be referred to as high-voltage XD-MOSFET, for dif-
ferentiation from the one built with conventional (i.e., filled)
wells.
A reported difficulty with the high-voltage extended-drain
MOSFETs is their susceptibility to hot-carrier degradation
[106]–[109] because the electric field strength is at its maxi-
mum near the surface, as shown in Fig. 19(a) for an n-channel
device.
The device architecture requirement for a hot-carrier-
reliable extended-drain MOSFET is that the location of the
maximum impact ionization is a few carrier mean-free paths
below the surface, so that the carriers generated by impact
ionization cannot make it to the silicon/silicon dioxide interface
[110]–[113]. Specifically, the drain breakdown voltage and
the hot-carrier lifetime of n-channel MOSFETs are critically
dependent on the gate overlap of drain, LOV , the optimum
value of which has to be determined experimentally or by well
calibrated simulations.
Even if precisely optimized, transistors built in the conven-
tional extended-drain architecture remain sensitive to process
variations. The location of the maximum electric field can
easily move closer to the surface, thus exposing them to hot-
carrier degradation.
The empty-well architecture used in our preferred imple-
mentation of the asymmetric MOSFET design is ideally suited
for building complementary high-voltage transistors that are
naturally hot-carrier reliable. This stems from the electric field
strength being highest below the surface, where the retrograde
n- and p-wells are at their peak concentrations. Due to the
retrograde nature of the p- and n-type wells, the depletion
region extends more freely below the silicon/silicon dioxide
interface, in comparison with the situation in the conventional
devices, providing field relief at the surface, as shown in
Fig. 19(b). P -channel devices are built similarly, with a deep
2376
Fig. 19. (a) Cross-section of an n-channel high-voltage extended-drain MOSFET implemented in the conventional architecture with the electron flow and the
depletion region structure in forward conduction at high drain voltage. Drain breakdown occurs near the surface (simulation-based line drawing). (b) Cross-section
of an n-channel high-voltage extended-drain MOSFET implemented in the empty-well architecture (XD-MOSFET) with the electron flow and the field structure
in forward conduction at high drain voltage. Drain breakdown occurs in the bulk of the silicon structure, where the doping concentrations are at or near peak
values (simulation-based line drawing).
Fig. 20. Experimental output I–V characteristics of n- and p-channel high-
voltage extended-drain MOSFET having balanced threshold voltages at |VT | ≈
0.5 V, implemented in the empty-well architecture (XD-MOS).
n-well added under the structure to isolate the drain from the
substrate.
The output characteristics of experimental n- and p-channel
XD-MOSFETs are shown in Fig. 20 for LW W = LOV =
0.5 μm and L = 1.0 μm, where the distance between the source
edge of the gate and the drain well, L, is conventionally defined
as the channel length for both types of transistors.
Unlike the more common high-voltage extended-drain
MOSFETs, the characteristics of these transistors do not de-
pend, over the range of practical interest, on the gate over-
lap parameter LOV . Their breakdown voltage is controlled
by the well-to-well separation LW W , increasing as LW W is
increased. It eventually saturates at a limit value when the
intensification of the electric field associated with the proximity
of the p-well vanishes and the breakdown moves up to the
surface.
The threshold voltages are fairly well balanced through the
use of the same halo implants that control the threshold volt-
ages of the secondary-voltage (DGO) asymmetric MOSFETs.
Further performance optimization can be obtained through
parameters L, LW W , and LOV .
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010
XII. C ONCLUSION
The physics, technology, and modeling of complementary
asymmetric MOSFETs have been reviewed, covering both the
advantages (primarily switching speed, high-frequency behav-
ior, voltage gain, and reliability) and the problems (primarily
variability and noise) of this type of transistors, with the con-
clusion that both asymmetric and symmetric devices need to be
offered in the same process for uncompromised circuit design.
The essential features of the asymmetric transistors have
been illustrated with statistically validated transistor data from
a recent manufacturing implementation, where the transistors
for the secondary power supply voltage (DGO transistors)
are offered in asymmetric and symmetric constructions. This
implementation uses empty wells, i.e., retrograde wells with no
dopant fillers at surface and source-side-only halo implants for
threshold voltage and punch-through control.
The availability of silicon and simulation data for asymmetric
and symmetric transistors built in the same process and having
similar threshold voltages has allowed an in-depth comparison
of their operation leading to the observation of a DGIBL in
asymmetric transistors. This effect contributes to the observed
larger drain saturation current, at similar overdrive gate volt-
ages. It also increases the variability of asymmetric transistors
and of transistors containing halo implants, in general.
In addition, the GISL has been analyzed and shown to
be a limiting factor to the degree of asymmetry that can be
accepted in applications where the source and drain electrodes
change bias polarity and the body and source regions are not
permanently connected together.
Compact modeling of asymmetric transistors has been briefly
discussed and illustrated with compared model and silicon char-
acteristics for output I–V characteristics, transconductance, out-
put conductance, maximum voltage gain, and gate capacitances.
As a side benefit, the empty-well process architecture en-
ables construction of complementary high voltage extended-
drain MOSFETs for a third higher power supply voltage at
superior manufacturability and hot-carrier reliability compared
to extended-drain transistors built with conventional (i.e., filled)
wells.
BULUCEA et al.: PHYSICS, TECHNOLOGY, AND MODELING OF COMPLEMENTARY ASYMMETRIC MOSFETs
ACKNOWLEDGMENT
The authors would like to thank Senior Vice President
M. Yegnashankaran and Vice President R. Razouk for their
support through the process development that made this con-
tributing review possible. The encouragement and manage-
ment support of directors S. Desai, A. Shaikh, P. Chaparala,
D. Boisvert, C. Joyce, L. Smith, P. Hopper, and S. Adler
are also acknowledged. The process integration management
has been provided by W. Belcher and P. Johnson, while
D. Brisbin characterized the hot-carrier reliability. The ring
oscillator speed evaluations have been done by E. Mazotti,
with electronic testing provided by M. Poulter and M. Liu.
The 3-D visualization of the highly irregular doping data from
the process simulation has been provided by E. Russell. The
authors would also like to thank chief technologist D. Archer
for introducing them the device requirements of the analog
designers. Initial guidance received from Professor Y. Taur
is respectfully acknowledged along with help received from
interns K. Banoo (Purdue University) and W. Wang (University
of California, San Diego).
R EFERENCES
[1] D. Buss, B. L. Evans, J. Bellay, W. Krenik, B. Haroun, D. Leipold,
J.-Y. Yand, and T. Moise, “SOC CMOS technology for personal Internet
products,” IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 546–556,
Mar. 2003.
[2] K. Kuhn, R. Basco, D. Becher, M. Hattendorf, P. Packan, I. Post,
P. Vandervoorn, and I. Young, “A comparison of state-of-the-art NMOS
and SiGe HBT devices for analog/mixed-signal/RF circuit applications,”
in VLSI Symp. Tech. Dig., 2004, pp. 224–225.
[3] B. Murmann, P. Nikaeen, D. J. Connelly, and R. W. Dutton, “Im-
pact of scaling on analog performance and associated modeling
needs,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2160–2167,
Sep. 2006.
[4] F. Boeuf, “Outlook for 32/28/22 nm manufacturing—Future SoC
products and solutions,” in VLSI Symp. Tech. Dig.—Short Course, 2009,
pp. 3–51.
[5] Y. Tarui, Y. Hayashi, and T. Sekigawa, “Diffused self-aligned MOST:
A new approach for high-speed device,” in Proc. 1st Conf. Solid-State
Devices, Tokyo, Japan, 1994, pp. 617–620.
[6] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed.
New York: Wiley-Interscience, 2007, ch. 6.
[7] D. Ueda, H. Takagi, and K. Kano, “A new vertical power MOSFET
structure with extremely reduced on-resistance,” IEEE Trans. Electron
Devices, vol. ED-32, no. 1, pp. 2–6, Jan. 1985.
[8] C. Bulucea and R. Rossen, “Trench DMOS transistor technology for
high-current (100 A range) switching,” Solid State Electron., vol. 34,
no. 5, pp. 493–507, May 1991.
[9] T. Dyer, J. McGinty, A. Strachan, and C. Bulucea, “Monolithic inte-
gration of trench vertical DMOS (VDMOS) power transistors into a
BCD process,” in Proc. 17th Int. Symp. Power Semicond. Devices ICs,
Santa Barbara, CA, 2005, pp. 47–50.
[10] F. Bauer, S. C. Jain, J. Korec, V. Lauer, M. Offenberg, and P. Balk,
“Incompatibility of requirements for optimizing short channel behaviour
and long-term stability in MOSFETs,” Solid State Electron., vol. 31,
no. 1, pp. 27–33, Jan. 1988.
[11] T. N. Buti, S. Ogura, N. Rovedo, K. Tobimatsu, and C. F. Codella,
“Asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half-
micron n-MOSFET design for reliability and performance,” in IEDM
Tech. Dig., 1989, pp. 617–620.
[12] T. N. Buti, S. Ogura, N. Rovedo, and K. Tobimatsu, “A new asymmet-
rical halo source GOLD drain (HS-GOLD) deep sub-half-micrometer
n-MOSFET design for reliability and performance,” IEEE Trans.
Electron Devices, vol. 38, no. 8, pp. 1757–1764, Aug. 1991.
[13] T. Matsuki, F. Asakura, S. Saitoh, H. Matsumoto, M. Fukuma,
and N. Kawamura, “Laterally-doped channel (LDC) structure for
sub-quarter micron MOSFETs,” in VLSI Symp. Tech. Dig., 1991,
pp. 113–114.
2377
[14] L. T. Su, J. A. Yasaitis, and D. Antoniadis, “A high-performance scalable
sub-micron MOSFET for mixed analog/digital applications,” in IEDM
Tech. Dig., 1991, pp. 367–370.
[15] T. Horiuchi, T. Homma, Y. Murao, and K. Okumura, “An asymmetric
sidewall process for high performance LDD MOSFETs,” IEEE Trans.
Electron Devices, vol. 41, no. 2, pp. 186–190, Feb. 1994.
[16] A. Hiroki, S. Odanaka, and A. Hori, “A high performance 0.1 μm
MOSFET with asymmetric channel profile,” in IEDM Tech. Dig., 1995,
pp. 439–442.
[17] J. P. John, V. Ilderem, C. Park, J. Teplik, K. Klein, and S. Cheng,
“A low-voltage graded-channel MOSFET (L-GCMOS) for sub
1-Volt microcontroller application,” in VLSI Symp. Tech. Dig., 1996,
pp. 178–179.
[18] J. A. Babcock, C. E. Gill, J. M. Ford, D. Ngo, E. Spears, J. Ma,
H.-B. Liang, D. J. Spooner, and S. Cheng, “1/f noise in graded-channel
MOSFETs for low-power low-cost RFICs,” in Proc. Annu. Device Res.
Conf., 1997, pp. 122–123.
[19] S. Odanaka and A. Hiroki, “Potential design and transport property
of 0.1-μm MOSFET with asymmetric channel profile,” IEEE Trans.
Electron Devices, vol. 44, no. 4, pp. 595–600, Apr. 1997.
[20] J. Ma, H.-B. Liang, R. A. Pryorm, S. Cheng, M. H. Kaneshiro,
C. S. Kyono, and K. Papworth, “Graded-channel MOSFET
(GCMOSFET) for high performance, low voltage DSP applications,”
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 5, no. 4,
pp. 352–358, Dec. 1997.
[21] B. Cheng, V. R. Rao, B. Ikegami, and J. C. S. Woo, “Realization of
sub-100 nm asymmetric channel MOSFET with excellent short-channel
performance and reliability,” in Proc. ESSDERC Tech. Dig., 1998,
pp. 520–523.
[22] H. Shin and S. Lee, “An 0.1-μm asymmetric halo by large-angle-
tilt implant (AHLATI) MOSFET for high performance and reliabil-
ity,” IEEE Trans. Electron Devices, vol. 46, no. 4, pp. 820–822,
Apr. 1999.
[23] B. Cheng, A. Inani, V. R. Rao, and J. C. S. Woo, “Channel engineering
for high-speed sub-1.0 V power supply deep submicron CMOS,” in VLSI
Symp. Tech. Dig., 1999, pp. 69–70.
[24] M. Stockinger, A. Wild, and S. Selberherr, “Drive performance of an
asymmetric MOSFET structure: The peak device,” Microelectron. J.,
vol. 30, no. 3, pp. 229–233, Mar. 1999.
[25] A. Blaum, J. Victory, and C. McAndrew, “A simple physical extraction
method for RD –RS of asymmetric MOSFETs,” in Proc. IEEE Conf.
Microelectron. Test Struct., Mar. 1999, vol. 12, pp. 141–146.
[26] S. Mahapatra, V. R. Rao, C. D. Parikh, J. Vasi, B. Cheng, and
J. C. S. Woo, “A study of 100 nm channel length asymmetric
channel MOSFET by using charge pumping,” Microelectron. Eng.,
vol. 48, no. 1–4, pp. 193–196, Sep. 1999.
[27] B. Cheng, V. R. Rao, and J. C. S. Woo, “Exploration of velocity over-
shoot in a high-performance deep sub-0.1-μm SOI MOSFET with asym-
metric channel profile,” IEEE Electron Device Lett., vol. 20, no. 10,
pp. 538–540, Oct. 1999.
[28] T. Ghani, K. Mistry, P. Packan, M. Armstrong, S. Thompson, S. Tyagi,
and M. Bohr, “Asymmetric source/drain transistor structure for high
performance sub-50 nm gate length CMOS devices,” in VLSI Symp.
Tech. Dig., 2001, pp. 17–18.
[29] C.-S. Choi, K.-W. Kim, and W.-Y. Choi, “Design and analysis of a new
self-aligned asymmetric structure for deep sub-micrometer MOSFET,”
Solid State Electron., vol. 45, no. 9, pp. 1673–1678, Sep. 2001.
[30] D. G. Borse, K. N. M. Rani, N. K. Jha, A. N. Chandorkar,
J. Vasi, V. R. Rao, B. Cheng, and J. C. S. Woo, “Optimization and
realization of sub-100-nm channel length single halo p-MOSFETs,”
IEEE Trans. Electron Devices, vol. 49, no. 6, pp. 1077–1079,
Jun. 2002.
[31] H. Deshpande, B. Cheng, and J. Woo, “Channel engineering for analog
device design in deep submicron CMOS technology for system on chip
application,” IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1558–
1564, Sep. 2002.
[32] T. B. Hook, J. S. Brown, M. Breitwisch, D. Hoyniak, and
R. Mann, “High-performance logic and high-gain analog CMOS tran-
sistors formed by a shadow-mask technique with a single implant
step,” IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1623–1627,
Sep. 2002.
[33] T. Ewert, L. Vestling, and J. Olsson, “Investigation of the electrical
behavior of an asymmetric MOSFET,” Microelectron. Eng., vol. 65,
no. 4, pp. 428–438, Apr. 2003.
[34] F.-C. Wang and C. Bulucea, “Use of mask shadowing and angled implan-
tation in fabricating asymmetrical field-effect transistors for alleviating
short-channel effects,” U.S. Patent 6 566 204, May 20, 2003.
2378 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010
[35] H.-S. Huang, S.-Y. Chen, Z.-W. Jhou, and Y.-D. Zeng, “Comparison
of single and double pocket devices on deep submicron n-MOSFET
for mixed signal applications,” in Proc. Int. Symp. Nano Sci. Technol.,
Taiwan, 2004, pp. 20–21.
[36] K. Narasimhulu, M. P. Desai, S. G. Narendra, and V. R. Rao, “The
effect of lateral asymmetric channel doping on deep submicrom-
eter transistor capacitances and its influence on RF performance,”
IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1416–1423,
Sep. 2004.
[37] A. S. Roy, Y. S. Chauhan, C. C. Enz, and J.-M. Sallese, “Noise
modeling in lateral asymmetric MOSFET,” in IEDM Tech. Dig., 2006,
pp. 191–194.
[38] J. Yuan, S. S. Tan, Y. M. Lee1, J. Kim, R. Lindsay, V. Sardesai,
T. Hook, R. Amos, Z. Luo, W. Lee, S. Fang, T. Dyer, N. Rovedo,
R. Stierstorfer, Z. Yang, J. Li, K. Barton, H. Ng, J. Sudijono, J. Ku,
M. Hierlemann, and T. Schim, “A 45 nm low cost low power platform by
using integrated dual-stress-liner technology,” in VLSI Symp. Tech. Dig.,
2006, pp. 100–101.
[39] J. P. Kim, W. Y. Choi, J. Y. Song, S. W. Kim, J. D. Lee, and
B.-G. Park, “Design and fabrication of asymmetric MOSFETs using
a novel self-aligned structure,” IEEE Trans. Electron Devices, vol. 54,
no. 11, pp. 2969–2964, Nov. 2007.
[40] S. K. H. Fung, H. C. Lo, C. F. Cheng, W. Y. Lu, K. C. Wu,
K. H. Chen, D. H. Lee, Y. H. Liu, I. L. Wu, C. T. Li, C. H. Wu,
F. L. Hsiao, T. L. Chen, W. Y. Lien, C. H. Huang, P. W. Wang,
Y. H. Chiu, L. T. Lin, K. Y. Chen, H. J. Tao, H. C. Tuan, Y. J. Mii, and
Y. C. Sun, “45 nm CMOS technology with 3X hole mobility enhance-
ment and asymmetric transistor for high performance CPU application,”
in VLSI Symp. Tech. Dig., 2007, pp. 1035–1037.
[41] G. H. See, X. Zhou, K. Chandarasekaram, S. B. Chiah, Z. Zhu, C. Wei,
S. Lin, G. Zhu, and G. H. Lim, “A compact model satisfying
Gummel symmetry in higher order derivatives and applicable to asym-
metric MOSFETs,” IEEE Trans. Electron Devices, vol. 55, no. 2,
pp. 624–631, Feb. 2008.
[42] M. A. Pavanello, J. A. Martino, V. Dessard, and D. Flandre, “Ana-
log performance and application of graded-channel fully depleted SOI
MOSFETs,” Solid State Electron., vol. 44, no. 7, pp. 1219–1222,
Jul. 2000.
[43] M. A. Pavanello, J. A. Martino, and D. Flandre, “Analog circuit de-
sign using graded-channel silicon-on-insulator nMOSFETs,” Solid State
Electron., vol. 46, no. 8, pp. 1215–1225, Aug. 2002.
[44] V. Kilchytska, A. Neve, L. Vancaillie, D. Levacq, S. Adriansen,
H. Van Meer, K. De Meyer, C. Raynaud, M. Dehan, J.-P. Raskin, and
D. Flandre, “Influence of device engineering on the analog and RF
performance of SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 50,
no. 3, pp. 577–588, Mar. 2003.
[45] A. Cerdeira, M. A. Alemán, M. A. Pavanello, J. A. Martino,
L. Vancaillie, and D. Flandre, “Advantages of the graded-channel SOI
FD MOSFET for application as a quasi-linear resistor,” IEEE Trans.
Electron Devices, vol. 52, no. 5, pp. 967–972, May 2005.
[46] J. Hoentschel, A. Wei, M. Wiatr, A. Gehring, T. Scheiper, R. Mulfinger,
T. Feudel, T. Lingner, A. Poock, S. Muehle, C. Krueger, T. Herrmann,
W. Klix, R. Stenzel, R. Stephan, P. Huebler, T. Kammler, P. Shi, M. Raab,
D. Greenlaw, and M. Horstmann, “Implementation and optimization
of asymmetric transistors in advanced SOI CMOS technologies
for high performance microprocessors,” in IEDM Tech. Dig., 2008,
pp. 649–652.
[47] M. Lundstrom, “Scattering theory of the short-channel MOSFET,” in
IEDM Tech. Dig., 1996, pp. 387–390.
[48] M. Lundstrom, “Elementary scattering theory of the Si MOSFET,” IEEE
Electron Device Lett., vol. 18, no. 7, pp. 361–363, Jul. 1997.
[49] F. Assad, Z. Ren, S. Datta, M. Lundstrom, and P. Bendix, “Performance
limits of silicon MOSFETs,” in IEDM Tech. Dig., 1999, pp. 547–550.
[50] G. Yeap and A. Wild, “Introduction to low-power VLSI design,” Int. J.
High-Speed Electron. Syst., vol. 7, no. 2, pp. 223–248, 1996.
[51] A. Wild, J. Quigley, J. Feddeler, S. Ledford, J. Caravella, F. Shapiro,
B. Gilsdorf, M. Hong, D. Mietus, R. B. Davies, R. Parmar, J.-D. Tai,
J. Thomas, J. Quarberg, E. Hartung, T. Sawan, J. H. Carlquist,
K. Papworth, J. Buxo, M. Schriber, M. Berens, D. Warren, B. Smith,
M. Mazuelos, K. Bass, and L. Layton, “A 0.9 V microcontroller for
portable applications,” IEEE J. Solid-State Circuits, vol. 32, no. 7,
pp. 1049–1055, Jul. 1997.
[52] D. Lamey, T. Mackie, H.-B. Liang, J. Ma, G. Robert, C. Jasper, D. Ngo,
K. Papworth, S. Cheng, C. Wilcock, R. Gurrola, E. Spears, and B. Yeung,
“Improving manufacturability of an RF graded channel CMOS process
for wireless applications,” in Proc. SPIE Microelectron. Device Technol.
Conf., 1998, pp. 147–155.
[53] J. F. Chen, J. Tao, P. Fang, and C. Hu, “Performance and reliabil-
ity comparison between asymmetric and symmetric LDD devices and
logic gates,” IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 367–371,
Mar. 1999.
[54] F. Chai, C. Kyono, V. Ilderem, M. Kaneshiro, D. Zupac, S. Bigelow,
C. Ramiah, P. Dahl, R. Braithwaite, D. Morgan, S. Hildreth, and
G. Grynkewich, “Cost-effective 0.25 μm Leff BiCMOS technology
featuring graded-channel CMOS (GCMOS) and a quasi-self-aligned
(QSA) NPN for RF wireless applications,” in Proc. BCTM, 2000,
pp. 110–113.
[55] A. Akturk, N. Goldsman, and G. Metze, “Increased CMOS inverter
switching speed with asymmetrical doping,” Solid State Electron.,
vol. 47, no. 2, pp. 185–192, Feb. 2003.
[56] K. Narasimhulu, S. G. Narendra, and V. R. Rao, “Impact of lateral
asymmetric channel doping on deep submicron mixed-signal device and
circuit performance,” IEEE Trans. Electron Devices, vol. 50, no. 12,
pp. 2481–2489, Dec. 2003.
[57] J. J. Buller, R. van Bentum, J. Cheek, E. Ehrichs, M. Horstmann, and
S. Searles, “Opportunities and challenges in asymmetric device
implementation,” in Proc. IEEE Custom Integr. Circuits Conf., 2004,
pp. 229–232.
[58] B. Wang, H. Nguyen, J. Mavoori, A. Horch, Y. Ma, T. Humes, and
R. Paulsen, “Effect of layout orientation on the performance and re-
liability of high voltage N-LDMOS in standard submicron logic STI
CMOS process,” in Proc. Annu. Int. Rel. Phys. Symp., San Jose, CA,
2005, pp. 654–655.
[59] A. Bansal and K. Roy, “Asymmetric halo CMOSFET to reduce static
power dissipation with improved performance,” IEEE Trans. Electron
Devices, vol. 52, no. 3, pp. 397–405, Mar. 2005.
[60] D. V. Kumar, K. Narasimhulu, P. S. Reddy, M. Shojaei-Baghini,
D. K. Shrama, M. B. Patil, and V. R. Rao, “Evaluation of the impact of
layout on device and analog circuit performance with lateral asymmet-
ric channel MOSFETs,” IEEE Trans. Electron Devices, vol. 52, no. 7,
pp. 1603–1609, Jul. 2005.
[61] K. Narasimhulu, I. V. Setty, and V. R. Rao, “The effect of single-halo
doping on the low-frequency noise performance of deep submicrometer
MOSFETs,” IEEE Electron Device Lett., vol. 27, no. 12, pp. 995–997,
Dec. 2006.
[62] J.-J. Kim, A. Bansal, R. Rao, S.-H. Lo, and C.-T. Chuang, “Relaxing
conflict between read stability and writability in 6T SRAM cell using
asymmetric transistors,” IEEE Electron Device Lett., vol. 30, no. 8,
pp. 852–854, Aug. 2009.
[63] K. Nii, M. Yabuchi, Y. Tsukamoto, Y. Hirano, and T. Iwamatsu, “A 0.5 V
100 MHz PD-SOI SRAM with enhanced read stability and write margin
by asymmetric MOSFET and forward body bias,” in Proc. Int. Solid-
State Circuits Conf., 2010, pp. 356–357.
[64] K. K. O and J. Yasaitis, “Integration of two gate oxide thicknesses
in a 0.6-μm dual voltage mixed signal CMOS process,” IEEE Trans.
Electron Devices, vol. 42, no. 1, pp. 190–192, Jan. 1995.
[65] D. Buss, “Device issues in the integration of analog/RF functions in deep
submicron digital CMOS,” in IEDM Tech. Dig., 1999, pp. 423–426.
[66] C. Bulucea, F.-C. Wang, and P. Chaparala, “Field-effect transistors
for alleviating short-channel effects,” U.S. Patent 6 548 842, Apr. 15,
2003.
[67] A. S. Grove, Physics and Technology of Semiconductor Devices.
New York: Wiley, 1968.
[68] Y. Taur and T. K. Ning, Fundamentals of Modern VLSI Devices, 2nd ed.
Cambridge, U.K.: Cambridge Univ. Press, 2009.
[69] M. Langenbuch, R. Bottini, M. E. Vitali, and G. Ghidini, “In situ
steam generation (ISSG) versus standard steam technology: impact on
oxide reliability,” Microelectron. Reliab., vol. 45, no. 5/6, pp. 875–878,
May/Jun. 2005.
[70] K. K. Young, S. Y. Wu, C. C. Wu, C. H. Wang, C. T. Lin, J. Y. Cheng,
M. Chiang, S. H. Chen, T. C. Lo, Y. S. Chen, J. H. Chen, L. J. Chen,
S. Y. Hou, J. J. Law, T. E. Chang, C. S. Hou, J. Shih, S. M. Jeng,
H. C. Hsieh, Y. Ku, T. Yen, H. Tao, L. C. Chao, S. Shue, S. M. Jang,
T. C. Ong, C. H. Yu, M. S. Liang, C. H. Diaz, and J. Y. C. Sun, “A
0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for
high performance applications,” in IEDM Tech. Dig., 2000, pp. 563–566.
[71] J. Sall, L. Creighton, and A. Lehman, JMP Start Statistics: A Guide
to Statistics and Data Analysis Using JMP, 4th ed. Cary, NC: SAS
Publishing, 2007.
[72] Synopsis, Inc., Taurus TSuprem-4 User Guide, 2004.
[73] Synopsis, Inc., Taurus Medici User Guide, 2004.
[74] S. Thompson, P. Packan, and M. Bohr (1998). MOS scaling: Transistor
challenges for the 21st century. Intel Technol. J. [Online]. 2(3), pp. 1–2.
Available: http://www.intel.com/technology/itj/archive/1998.htm
BULUCEA et al.: PHYSICS, TECHNOLOGY, AND MODELING OF COMPLEMENTARY ASYMMETRIC MOSFETs
[75] T. Tanaka, T. Usuki, T. Futatsugi, Y. Momiyama, and T. Sugii, “Vth
fluctuation induced by statistical variation of pocket dopant profile,” in
IEDM Tech. Dig., 2000, pp. 271–274.
[76] T. Tanaka, T. Usuki, Y. Momiyama, and T. Sugii, “Direct measurement
of Vth fluctuation caused by impurity positioning,” in VLSI Symp. Tech.
Dig., 2000, pp. 136–137.
[77] K. Kuhn et al., “Managing process variations in Intel’s 45 nm CMOS
technology,” Intel Tech. J., vol. 12, no. 2, pp. 93–109, Jun. 2008.
[78] A. Cathignol, S. Bordez, A. Cros, K. Rochereau, and G. Ghibaudo, “Ab-
normally high local electrical fluctuations in heavily pocket-implanted
bulk long MOSFET,” Solid State Electron., vol. 53, no. 2, pp. 127–133,
Feb. 2009.
[79] J. A. Croon, E. Augendre, S. Decoutere, W. Sansen, and H. E. Maes,
“Influence of doping profile and halo implantation on the threshold
voltage mismatch of a 0.13 μm CMOS technology,” in Proc. ESSDERC,
2002, pp. 579–582.
[80] A. van der Ziel, Noise in Solid-State Devices and Circuits. New York:
Wiley, 1986.
[81] Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User’s Guide.
Norwell, MA: Kluwer, 1999.
[82] J. Jang, T. Arnborg, Z. Yu, and R. W. Dutton, “Circuit model for
power LDMOS including quasi-saturation,” in Proc. SISPAD, 1999,
pp. 15–18.
[83] A. C. T. Aarts, R. van der Hout, J. C. Y. Paasschens, A. J. Scholten,
M. Willensen, and D. B. M. Klaassen, “New fundamental insights into
capacitance modeling of laterally nonuniform MOS devices,” IEEE
Trans. Electron Devices, vol. 53, no. 2, pp. 270–277, Feb. 2006.
[84] A. S. Roy, Y. S. Chauhan, J.-M. Sallese, C. C. Enz, A. M. Ionescu, and
M. Declercq, “Partitioning scheme in lateral asymmetric MOST,” in
Proc. ESSDERC, 2006, pp. 307–310.
[85] S. C. Sun and J. D. Plummer, “A monolithic 200-V CMOS analog
switch,” IEEE J. Solid-State Circuits, vol. SC-11, no. 6, pp. 809–817,
Dec. 1977.
[86] S. C. Sun and J. D. Plummer, “Modeling of the on-resistance of LDMOS,
VDMOS, and VMOS power transistors,” IEEE Trans. Electron Devices,
vol. ED-27, no. 2, pp. 356–367, Feb. 1980.
[87] M. Amato and V. Rumennik, “Comparison of lateral and vertical DMOS
specific on-resistance,” in IEDM Tech. Dig., 1985, pp. 736–739.
[88] O. Kwon, T. Elfand, T. Ng, S. Malhi, R. Todd, and J. Lee, “Optimized
60-V lateral DMOS devices for VLSI power applications,” in VLSI
Symp. Tech. Dig., 1991, pp. 115–116.
[89] P. G. Y. Tsui, P. V. Gilbert, and S. W. Sun, “Integration of power LDMOS
into a low-voltage 0.5 μm BiCMOS technology,” in IEDM Tech. Dig.,
1992, pp. 27–30.
[90] M. Smayling, J. Reynolds, D. Redwine, S. Keller, and G. Falessi, “A
modular merged technology process including submicron CMOS logic,
nonvolatile memories, linear functions, and power components,” in Proc.
IEEE Custom Integr. Circuits Conf., 1993, pp. 24.5.1–24.5.4.
[91] C. Duvvury, J. Rodriguez, C. Jones, and M. Smyling, “Integration for
ESD robustness of high voltage power MOSFETs,” in IEDM Tech. Dig.,
1994, pp. 407–410.
[92] P. G. Y. Tsui, P. V. Gilbert, and S. W. Sun, “A versatile half-micron com-
plementary BiCMOS technology for microprocessor-based smart power
applications,” IEEE Trans. Electron Devices, vol. 42, no. 3, pp. 564–570,
Mar. 1995.
[93] C. Duvvury, D. Briggs, J. Rodriguez, F. Carvajal, A. Young, and
M. Smayling, “Efficient NPN operation in high voltage NMOSFET for
ESD robustness,” in IEDM Tech. Dig., 1995, pp. 345–348.
[94] R. Versari, A. Pieracci, S. Manxini, C. Contiero, and B. Ricco, “Hot-
carrier reliability in LDMOS transistors,” in IEDM Tech. Dig., 1997,
pp. 371–374.
[95] R. Versari and A. Pieracci, “Experimental study of hot-carrier effects
in LDMOS transistors,” IEEE Trans. Electron Devices, vol. 46, no. 6,
pp. 1228–1233, Jun. 1999.
[96] W. G. Meyer, G. W. Dick, K. H. Olson, K. H. Lee, and J. A. Shimer,
“Integrable high voltage CMOS: Devices, process application,” in IEDM
Tech. Dig., 1985, pp. 732–735.
[97] G. M. Dolni, O. H. Schade, Jr., B. Goldsmith, and
L. A. Goodman, “Enhanced CMOS for analog-digital power IC
applications,” IEEE Trans. Electron Devices, vol. ED-33, no. 12,
pp. 1985–1991, Dec. 1986.
[98] J. Haas, K. Au, L. C. Martin, T. L. Portlock, and T. Sakurai, “High
voltage CMOS LCD driver using low voltage CMOS process,” in Proc.
Custom Integr. Circuits Conf., 1989, pp. 14.6.1–14.6.4.
[99] O.-K. Kwon, T. Elfand, W. T. Ng, S. Mahli, R. Todd, and J. K. Lee,
“Optimized 60-V lateral DMOS devices for VLSI applications,” in VLSI
Symp. Tech. Dig., 1991, pp. 115–116.
2379
[100] T. Elfand, T. Keller, S. Keller, and J. Rodriguez, “Optimized
complementary 40 V power LDMOS-FETs use existing fabricating
steps in submicron CMOS technology,” in IEDM Tech. Dig., 1994,
pp. 399–402.
[101] Y. Q. Li, T. Salama, M. Seufert, P. Schvan, and M. King, “Inte-
gration of high-voltage NMOS devices into a submicron BiCMOS
process using simple structural changes,” in IEDM Tech. Dig., 1994,
pp. 403–406.
[102] P. M. Santos, A. P. Casimiro, M. I. C. Simas, and M. Lança, “CMOS
compatible HV gate-shifted LDD-NMOS,” IEEE Trans. Electron
Devices, vol. 48, no. 5, pp. 1013–1015, May 2001.
[103] J. C. Mitros, C. Tsai, H. Shichijo, K. Kunz, A. Morton, D. Goodpaster,
D. Mosher, and T. R. Efland, “High-voltage drain extended MOS transis-
tors for 0.18-μm logic CMOS process,” IEEE Trans. Electron Devices,
vol. 48, no. 8, pp. 1751–1755, Aug. 2001.
[104] P. Moens, B. Vlachakis, F. Bauwens, and L. De Schepper, “Spatial distri-
bution of interface traps in DeMOS transistors,” IEEE Electron Device
Lett., vol. 25, no. 8, pp. 577–579, Aug. 2004.
[105] P. Moens, F. Bauwens, and M. Tack, “Electron trapping and interface
trap generation in drain extended PMOS transistors,” in Proc. IEEE Int.
Rel. Phys. Symp., 2005, pp. 555–559.
[106] J. F. Chen, K.-M. Wu, K.-W. Lin, Y.-K. Su, and S. L. Hsu, “Hot-carrier
reliability in submicrometer 40 V LDMOS transistors with thick gate
oxide,” in Proc. Int. Rel. Phys. Symp., 2005, pp. 560–564.
[107] B. Wang, H. Nguyen, J. Mavoori, A. Horch, Y. Ma, T. Humes, and
R. Paulsen, “Effect of layout orientation on the performance and reliabil-
ity of high voltage N-LDMOS in standard submicron logic STI CMOS
process,” in Proc. Annu. Int. Rel. Symp., 2005, pp. 654–655.
[108] D. Brisbin, A. Strachan, and P. Chaparala, “Optimizing the hot carrier re-
liability of N-LDMOS transistor arrays,” Microelectron. Reliab., vol. 45,
no. 7/8, pp. 1021–1032, Jul./Aug. 2005.
[109] R. A. Bianchi, F. Monsieur, F. Blanchet, C. Raynaud, and O. Noblanc,
“High voltage devices integration into advanced CMOS technologies,”
in IEDM Tech. Dig., 2008, pp. 137–140.
[110] C. Bulucea, “Avalanche injection into the oxide in silicon gate-controlled
devices—I. Theory,” Solid State Electron., vol. 18, no. 4, pp. 363–374,
Apr. 1975.
[111] C. Bulucea, “Avalanche injection into the oxide in silicon gate-controlled
devices—II. Experimental results,” Solid State Electron., vol. 18, no. 5,
pp. 381–391, May 1975.
[112] T. H. Ning, C. M. Osburn, and H. N. Yu, “Emission probability of hot
electrons from silicon into silicon dioxide,” J. Appl. Phys., vol. 48, no. 1,
pp. 286–293, Jan. 1977.
[113] P. E. Cottrell, R. R. Troutman, and T. H. Ning, “Hot-electron emission
in n-channel IGFETs,” IEEE Trans. Electron Devices, vol. ED-26, no. 4,
pp. 520–533, Apr. 1979.
Constantin Bulucea (S’69–M’70–SM’88–F’04) re-
ceived the M.S. and Ph.D. degrees in electrical engi-
neering from the Polytechnic Institute of Bucharest,
Bucharest, Romania, in 1962 and 1974, respec-
tively. In 1969, he was awarded a one-year gov-
ernment scholarship for studies at the University of
California, Berkeley, where he received the second
M.S. degree in electrical engineering.
From 1965 to 1986, he worked with the rapidly
growing semiconductor industry of his country, hold-
ing various positions from Staff Engineer to Director
of Research and Development. During that period, he published reference
contributions to the physical electronics of surface breakdown and hot-carrier-
injection in silicon devices. In 1987, he joined Siliconix, Santa Clara, CA,
where he brought to completion the development of the world’s highest current
transistor switch of the time in trench DMOS technology. Since 1990, he has
been with National Semiconductor Corporation, Santa Clara, CA, where he
currently holds a Chief Technologist position, leading IC technology develop-
ment programs that integrate submicrometer CMOS and bipolar devices for
analog and mixed-signal circuits/systems. He has published over 50 papers in
the areas of device physics and engineering (1962–1980), technology of power
DMOS transistors (1987–1990), and VLSI devices (1991 to present). In the
aforementioned areas, he has 30 U.S. patents, with several others pending.
Dr. Bulucea has served one full Technical Committee term of the VLSI
Technology Symposium and the Bipolar Circuits and Technology Meeting
and is currently the analog and mixed-signal technology Editor of the IEEE
E LECTRON D EVICES L ETTERS. He is an honorary member of the Romanian
Academy.
2380
Sandeep R. Bahl (S’84–M’93–SM’99) received the
B.S. degree from Rensselaer Polytechnic Institute,
Troy, NY, in 1985, and the M.S. and Ph.D. degrees
in electrical engineering from the Massachusetts
Institute of Technology, Cambridge, in 1988 and
1993, respectively.
From 1993 to 2005, he worked with Hewlett
Packard and Agilent Technologies in Palo Alto, CA.
Since 2005, he has been with National Semiconduc-
tor Corporation, Santa Clara, CA. He made contri-
butions to electronic and optical devices in III–V
materials and silicon. Among these, he conducted the research phase of the
InGaP HBT, which is now used in Agilent products, and codeveloped the next-
generation analog CMOS process at National Semiconductor Corporation. He
has authored or coauthored 32 journal articles and conference presentations
and holds 16 patents. His current interest is the development of energy-efficient
transistor technology for power applications.
Dr. Bahl was a recipient of the STAR awards at both Hewlett-Packard and
Agilent Technologies and received the Best Student Paper Award at the Indium
Phosphide and Related Materials Conference. He is a member of Tau Beta Pi
and Eta Kappa Nu and is an officer of the Santa Clara, CA chapter of the IEEE
Electron Devices Society.
William D. French was born in Northern Ireland,
in 1967. He received the B.Eng. and Ph.D. degrees
from the Department of Electrical and Electronic
Engineering, Queen’s University of Belfast, Belfast,
Northern Ireland, in 1989 and 1993, respectively. His
Ph.D. thesis was on the 2-D simulation of silicon-on-
insulator MOSFETs.
He was a Research Fellow in Queen’s University
on high-speed silicon-on-insulator bipolar transistors
before joining Silvaco International, Santa Clara, CA
in 1995 as an Applications Engineer for Technology
CAD (TCAD). In 2004, he joined National Semiconductor Corporation, Santa
Clara, as a TCAD Device Engineer and is currently the Manager of the TCAD
group. He is responsible for the process and device simulations for all process
development within National Semiconductor Corporation. His interests include
submicrometer CMOS process and device physics, LDMOS design, bipolar
device physics, and RF spiral inductor simulation and design.
Jeng-Jiun Yang (M’96) received the B.S. degree in chemistry from National
Taiwan University, Taipei, Taiwan, in 1978, and the Ph.D. degree in physical
chemistry from the University of California, Los Angeles, in 1984.
In 1982, she was a Guest Scientist at the Max Plank Institut für Quantenoptik,
Garching, Germany. Between 1984 and 1987, she held postdoctoral research
positions with the Department of Chemistry, Oregon State University, Corvallis,
and AT&T Bell Laboratories, Murray Hill, NJ. Since 1987, she has been
working with the IC industry of the Silicon Valley, CA, as a Professional
Contributor at Integrated Device Technology, Santa Jose, CA (1987–1997),
Maxim Integrated Products, Sunnyvale, CA (1997), and National Semiconduc-
tor Corporation, Santa Clara, CA (1997 to present). Her experience in the field
includes CMOS process development, device physics, device bench/electronic
characterization, and ESD/latch-up engineering.
Pascale Francis received the M.S.E.E. and Ph.D.
degrees in electrical engineering from the Catholic
University of Louvain, Louvain-la-Neuve, Belgium,
in 1991 and 1996, respectively. Her doctoral research
was on gate-all-around SOI/CMOS device character-
ization and modeling in harsh environments, such as
high temperature and irradiation.
In 1996, she was the recipient of a fellowship from
the Japanese Association of University Women and
spent three months with the NEC Research Laborato-
ries, Tsukuba, Japan. She then joined National Semi-
conductor Corporation, Santa Clara, CA, where she held various positions since
1996 in process and device characterization and modeling. She is currently a
Senior Engineering Manager in the Spice Modeling group. Her interests span
multiple areas, such as deep submicrometer CMOS for analog applications,
high-frequency passive devices (inductors, transformers, varactors, etc.), high-
voltage and high-power silicon LDMOS transistors, GaN HEMTs, etc. She
authored or coauthored more than 20 publications in IEEE or international
journals and conferences.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010
Tikno Harjono received the B.S. and M.S. degrees
in electrical engineering from Santa Clara Univer-
sity, Santa Clara, CA, in 1988 and 1990, respectively.
He was a Research Intern at Xerox Palo Alto
Research Center, Palo Alto, CA, while he was work-
ing toward the M.S. degree. In 1990, he joined the
Device Modeling Group at Signetics/Philips Semi-
conductors, Sunnyvale, CA. From 1996 to 1999, he
worked with Sipex Corporation, Milpitas, CA. In
1999, he joined the Advanced Process Technology
Development Group of National Semiconductor
Corporation, Santa Clara, CA, as a Device Engineer.
Mr. Harjono is a member of Tau Beta Pi.
Vijay Krishnamurthy received the B.Tech. degree
in electrical engineering from the Indian Institute
of Technology, Chennai, India, in 1997, and the
Ph.D. degree in electrical and computer engineer-
ing from Purdue University, West Lafayette, IN, in
2002, where he worked on design and optimization
of large-area high-speed MSM photodetectors on
intermediate temperature grown GaAs.
In 2000, he was with the IBM T.J. Watson Re-
search Center, Yorktown Heights, NY and worked on
noise characterization of photoreceivers for 10-GB
Ethernet applications. Since 2004, he has been with National Semiconductor
Corporation, Santa Clara, CA. His current work and research interests include
compact modeling of DMOS/HV-MOS devices for power switching appli-
cations and low-frequency noise characterization and modeling of advanced
CMOS devices.
Dr. Krishnamurthy was the recipient of the IEEE Lasers and Electro-Optics
Society Graduate Student Fellowship in November 2000.
Jon Tao received the B.S. and M.S. degrees in elec-
trical engineering from Peking University, Beijing,
China, in 1984 and 1987, respectively, and the Ph.D.
degree in electrical engineering from the University
of California, Berkeley, in 1995.
From 1987 to 1990, he was an Assistant Professor
with the Institute of Microelectronics, Peking Uni-
versity. From 1995 to 2006, he worked for Siliconix,
Advanced Micro Devices, and RF Micro Devices in
the fields of process technology, process integration,
device reliability, RFCMOS, and passives modeling
and characterization. Since 2006, he has been with National Semiconductor
Corporation, Santa Clara, CA. His area of interest is active and passive
devices physics, modeling, characterization, and spiral inductors in CMOS
technologies. He has published over 40 journal and conference papers, and is
the holder of several patents related to device physics and process technologies.
Courtney Parker (M’91) received the B.S. and M.S.
degrees in electrical engineering from the University
of Maine, Orono, in 1989 and 1991, respectively, and
the M.B.A. degree from the University of Southern
Maine, Portland, in 2010.
He is currently an Integration Engineer with the
Process Development Group of National Semicon-
ductor Corporation, Santa Clara, CA, with a focus on
submicrometer CMOS and BiCMOS technologies.