Contributions from DOJ till Present

1.Training Sessions
 Basic Counter Logic on Zync board
 RTL Code For 4bit Free Runing counter.
 Generated Bit file.
 Tested on Zync Board using LED.

 4-bit Mod-13 Counter

 RTL Code For 4-bit Mod-13 counter.
 Synthesizable Testbench For Checking simulation of the same.

 6 bit parity checker

 RTL Code For a 6-bit parity checker.
 Synthesizable Testbench For Checking simulation of the same.

 4 bit adder using 2 bit adders

 RTL Code For a 2-bit adder
 RTL Code to instantiate 2-bit adder for implementing 4-bit adder
 Synthesizable Testbench For Checking simulation of the same.

 Fill the 8 internal registers based on i/p address.

 Non-overlapping State Machine for (1) 01111110 (2) 101010

 Sequence Detecting 1,2,3 and 4. Input is 2bits and valid comes in every 4
clk cycle. And it can start with any no. and also generate a error flag when
sequence is lost.

 File IO Operation
 Writing and reading from external file in different formats (binary,
hexadecimal, signed decimal).

 BRAM IP CORE
 Infer BRAM
 Instantiate different BRAM using different modes (NO CHANGE,
WRITE FIRST, READ FIRST).

 Memory Controllers + Constraints

 To write an FSM.
 Address generation logic.
 state changing.
  Ping pong memory controlller.
 What are different types of Constraints.
 How to time constraint your design.
 How to increase the maximum frequency of your design.
 False Path.

 CLOCK DOMAIN CROSSING

 To write a FSM.
 Address generation logic.
 state changing.
 PING PONG memory Controller.
 Two Clock Domain (Write and Read clocks are of different
frequencies).
 Constraints for Both clocks, calculation of Maximum Frequency for
the Design.

 Correlation
 Signed numbers are stored in a Memory (ROM) from 0 to 7 locations.
 Writing and reading signed numbers from a Memory(RAM_SDP)
from 0 to 127 locations in a circular fashion.
 While writing from an external file alternate data is written into the
memory.
 Complex Multiplication of signed numbers.
 Output of Complex multiplier is provided to accumulator to get sum of
8 outputs each time.
 Calculate ((I2) +(Q2)) for sum of 8 samples and Calculate its
maximum value.
 Write in a file the Maximum value with the position/iteration on which
maximum value is captured.

 AXI FIFO IP CORE

 Understand the logic of AXI FIFO.
 How full and empty signal is going high and low and how valid and
ready signal woks.

2. PROJECT – Venus (UE)

 Standalone Test for 5MHz, 10MHz and 20MHz
 SRIO(FPGA) validation with treq_data sent from DSP.
Status :- Data sent from DSP side same data received to FPGA SRIO.
Tested and working.

 Integration Test for 5MHz, 10MHz and 20MHz

 RF validation with Sine Tone of 1MHz and 500KHz sent from
WaveGuru and received back to WaveGuru.
  Capture IQ samples from ILA result and plot it on Matlab Tool and
verify whether it is 1MHz or 500KHz sine tone or not.
Status:- Tested and working.
 RF validation with LTE FRAME sent from WaveGuru and received
back to WaveGuru. Validated on WaveGuru on terminal based on
CRC = Passed.
Status :- Tested and working.
 Find out the best value of Delay Register on which perfect spectrum
comes on VSA with least noise Reg 0x6 => 9A. for all B.W.
5,10,20MHz.

 Bit Tagging and Control Signals

 LSB bits of DAC_DATA append into the LSB bits of ADC_DATA

and top of that add some control signals.
Status :- Tested and Working.
 Compiler Directives based common build for 1.4MHz, 3MHz, 5MHz,
10MHz, 20MHz for VENUS.
Status :- Not yet Tested.

 B.W. Identifier using counter based on RF sample clk is done. On the counter
value we has defined a fixed value of db_inst signal.
Status :-

3. PROJECT – Jupiter (eNB)

 eNB PPS_PULSE Synchronization
 Open the gate to SRIO when external pps pulse will come.
 After this change in logic its gate will also open if internal pps pulse
come but this first check for the external pps and wait for 10sec if not
come then it will take internal pps to open the gate.

 eNB for BROADBAND Project (100MHz B.W.), Ref Clk = 307.2MHz

 Tx Standalone Test
 For Contiguous with multi carrier is done and tested. Centre
carrier at 800MHz and left and right are 780.2MHz and
819.8MHz respectively. Decoding is happening on VSA.
 For Non – Contiguous with multi carrier is done and tested
with spacing of 39.8MHz. Center carrier at 800MHz and left
and right are 761.2MHz and 839.8MHz respectively. Decoding
is happening on VSA.
 Integration Test
  For integration test spectrum is coming but some samples are
missing still working on it. It is on hold.

 Bring up Tx path for Jupiter FMC2 or J3.

 TX Standalone Test
 Previously GT lanes are Cross connected at this time RX, ORX
and Deframer Status is 32,32 and 33 respectively.
 LTE FRAME not coming on VSA
 DECODING IS FAILED.
 After change the GT lanes direct connected at this time RX,
ORX and Deframer Status is 32, 32 and 104 respectively.
 LTE FRAME coming on VSA
 DECODING IS happening on VSA
 It is not consistent.

 GPIO based Reset functionality

 Implement logic for GPIO Based reset or software reset.

 Validate jup_eNB_v2 Board for FMC1 or J4

 Standalone test
 Validate jup_eNB_v2_001 and jup_eNB_v2_003 transmitter
(TX1/TX2) and receiver (RX1/RX2) path with standalone test
and loopback test(TX1----RX1/TX2----RX2).
 Integration Test

 3.6. Circular Buffer implementation

 Circular Buffer Implementation for 5MHz,10MHz and 20MHz
with buffer Depth 512.
 Validate jup_eNB_v1_006 transmitter (TX1/TX2) and receiver
(RX1/RX2) path with standalone test and loopback test(TX1---
-RX1/TX2----RX2).

 3.7. DUC Implementation using TCL command

 Generated build 5 MHz, 10 MHz, 20MHz after changing the Device
Clk from 122.88MSPS to 61.44MSPS with Dhiraj.

4. Supporting Side
4.1 Flash board according to their requirement for Venus, Jupiter AD9361 and
AD9371/75.