EX NO:

DATE:

INVERTER USING L-EDIT

AIM:
To draw CMOS INVERTER layout using l-edit and to extract the layout parameters.

SOFTWARE TOOLS REQUIRED:

TANNER TOOLS
- L-EDIT
-T-SPICE

L-EDIT
L-edit is an integrated circuit physical design tool from Tanner EDA. This tool allows to draw
the layout of an IC, look at cross-sections, perform DRC and LVS. There are some design kits
that come with L-edit including the AMI/On-Semiconductor 0.8um kit, which we will use in
this document.

PROCEDURE:
Step 1:
1. Launch L-edit, Start a design, and Setup the Technology
a. -launch L-edit using: Start – All Programs – Tanner EDA – Tanner Tools v12.6 –
L-Edit v12.6
2. Create a new layout design:
a. File – New
b. select “Layout”
c. under “Copy TDB…”, select <empty> from the bottom dialog
d. Click “OK”
 3. Load in the mamin08 design kit:
- File – Replace Setup Browse to:
…\Documents\Tanner EDA\Tanner Tools v12.6\L-Edit and LVS\Tech\Mosis
-select the “mamin08.tbd” file (this stands for Mosis/AMI N-well 0.8um)
- Click “OK”, and “OK” again.
Notice that all of the layers available in the 0.8um AMI design kit are now in the drawing
palette on the left.
4. Verify the technology rule options:
- Setup – Design
You should see the design setup options. If everything worked, you should see the following.
Notice that Lambda is equal to 0.5um. This is important because the design rules for DRC
are specified in terms of lambda.

5. Save your design

- Now we can click “save” and give the design a descriptive name and location.
Step 2: Inspect the design rules for the kit
The design rules for this kit are located on the MOSIS website at:
http://www.mosis.com/Technical/Designrules/scmos/scmos-main.html
Step 3: Create layout for the CMOS inverter
Let’s create a CMOS inverter with
Ln=Lp=1um, Wn=3um, Wp=3um.
We should write down the conversion between microns and Lambda so that the design
rules make sense:
Ln = 1u = 2 lambda
Lp = 1u = 2 lambda
Wn = 3u = 6 lambda
Wp = 3u = 6 lambda
TO DRAW LAYOUT OF NMOS
The process that we are using is N-well CMOS. This means that the blank screen we see is p-
type silicon. We explicitly draw active regions on the screen to open up the field-oxide to
insert diffusion regions. This means we can think of the screen as p-type silicon with FOX
everywhere on it to begin with. In order to create the NMOS structure, we use three layers:
Active - This tells the process where to implant the n-type ions (P or As). We should
implant into the Poly to reduce its resistance. The “Width” of the N-Select dictates the width
of the transistor (Wn)
N-Select - This layer tell where the field-oxide should be opened up for the active
regions. This layer must overlay the active region.
Poly - This specifies the gate of the device. Under the poly will be thin oxide forming
MOS structure. The “Length” of the Poly dictates the length of transistor (Ln).
Display Notes
- We can setup the default units to use (micron vs. lambda) in the upper corner of
the screen.
- We can setup the grid display and snap using the “Setup – Design” menu and “Grid”
tab
Entry Notes:
- We enter a rectangle by first selecting the layer and then clicking on the square
icon.
 - We can enter rulers in the design to measure the rectangles as they are entered.
We can set the display options of the ruler on the “Setup – Design” menu on the “Drawing”
tab.
1) Enter an N-select rectangle that is 9um x 5um
2) Enter an Active rectangle that is 7um x 3um centered within the N-select
3) Create a Poly rectangle that is 1um x 5um. The design should look like this:

4) Run DRC to make sure the dimensions are not violating any design rules
- Click on the DRC button in the upper left corner of the screen (little green play
arrow).
Finally the DRC should be run:
5) View the Cross Section of the layout:
- Tools – Cross-Section - we need to specify an *.xst file (if not already loaded).
This can be found in the same directory as the original *.tbd file.
The file is called “mamin08.XST”. Browse and select:
…\Documents\Tanner EDA\Tanner Tools v12.6\L-Edit and
LVS\Tech\Mosis\mamin08.xst
- In the dialog that comes up, we can specify the cross-section point using the
up/down arrows or by selecting “pick” - Under “Exaggeration”, check the box that says
“center to window”
- Click “OK”, the FOX that exists everywhere except in the active region and the thin
oxide under the poly can be seen.
6) Enter the Body Diffusion point for the NMOS - In order to enter a body contact, we need
to tell the tool that we are going to create a p+ diffusion region. We do this using the active
and P-select layers. Put a substrate diffusion region next to the NMOS as follows:

7) Enter the contact windows for the NMOS - we do this using the Active Contact layer
8) Enter Metal 1 to connect the Source and Body of the NMOS together and put a little
Metal1 over the Drain contact to connect to later.
LAYOUT FOR PMOS
A PMOS device is made in a similar manner as the NMOS except that we need to specify the
N-well and use P-select instead of N-select.
1) Enter the PMOS N-well, P-select, Active, Poly, Active Contact, and Metal 1 as follows:
Connecting the Inverter
Metal and Poly are connected together by simply drawing \rectangles that are adjacent to
or overlap another rectangle of the same type (i.e., M1 to M1, Poly to Poly). Connect the
inverter together as shown in the following figure:
- We typically put horizontal strips across the chip to route VDD and VSS to multiple
devices. These are called power supply “rails”.
- Connect the gates together using Poly and then route the signal up to Metal 1 using
a Poly Contact - Connect the drains together using Metal 1
- Label the 4-nodes of the inverter using the Drawing Ports button. (VDD, VSS, VIN,
VOUT)

VDD

PMOS
In Out

NMOS

Perform a Final DRC on the Design

Extract a SPICE Netlist of Layout
Click on the “Extract Connectivity” button - in the Extract dialog that appears, specify the
extract definition file at:
…\Documents\Tanner EDA\Tanner Tools v12.6\L-Edit and
LVS\Tech\Mosis\mamin08.ext
- specify the output name and location for the spice Netlist to be generated:
…..inverter_amin08.spc
- check the “open spice file after extracting” box - on the “output” tab, check the
“write node name aliases”
- click “Run”
- extracted spice Netlist seen is as follows:
the Length and Width of the transistors is what we wanted (W/L=3u/1u) . The node name
aliases shows up that our inverter is connected correctly.

RESULT:
Thus the INVERTER layout was drawn using l-edit and layout parameters are
extracted.
EX NO:
DATE:

NAND GATE USING L-EDIT

AIM:
To draw CMOS NAND GATE layout using l-edit and to extract the layout parameters.

SOFTWARE TOOLS REQUIRED:

TANNER TOOLS
- L-EDIT
-T-SPICE

LAYOUT OF NAND GATE:

1. Step1 and step2 is followed same as that of the cmos inverter which have already been
done .
2. Draw PMOS and NMOS with the procedure that we have already followed in the cmos
inverter .
3. The same PMOS and NMOS layout using duplicate selected objects icon in toolbaris
duplicated and see that there should be minimum gap between two as per the mosis rules .
4. The PMOS and NMOS are flipped against vertical axis as below.
5. Now connect the both with the metal to get the layout of NAND GATE and name the
ports.
6. Now the layout looks as shown in the figure below.

7. Now extract the circuit parameters from L-Edit to T-Spice using mamin08.xst file and
extracted parameters are as show below in the figure.
RESULT:
Thus the NAND GATE layout was drawn using l-edit and layout parameters are
extracted.
EX NO:
DATE:

NOR GATE USING L-EDIT

AIM:
To draw CMOS NOR GATE layout using l-edit and to extract the layout parameters.

SOFTWARE TOOLS REQUIRED:

TANNER TOOLS
- L-EDIT
-T-SPICE

LAYOUT OF NOR GATE:

1. Step1 and step2 is followed same as that of the cmos inverter which have already been done
.
2. Draw PMOS and NMOS with the procedure that we have already followed in the cmos
inverter .
3. The same PMOS and NMOS layout using duplicate selected objects icon in toolbaris
duplicated and see that there should be minimum gap between two as per the mosis rules .
4. The PMOS and NMOS are flipped against vertical axis as below.
1. Now connect the both with the metal to get the layout of NOR GATE and name the
ports.
2. Now the layout looks as shown in the figure below.

3. Now extract the circuit parameters from L-Edit to T-Spice using mamin08.xst file and
extracted parameters are as show below in the figure.
RESULT:
Thus the NOR GATE layout was drawn using l-edit and layout parameters are
extracted.