CXLLN

Hardware Description

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1.1 CXLLN
This topic describes the version, application, functions, working principle,
front panel, and technical specifications of the CXLLN
(1xSTM-16/STM-4/STM-1 SCC unit, cross-connect unit, timing unit, and line
unit integrated board). This topic also describes how to configure and
commission the CXLLN.
5.4.1 Version Description
The CXLLN is available in one functional version, namely, Q5. The CXLLN
supports the intelligent fan.
5.4.2 Application
The CXLLN provides service processing, service grooming, clock
input/output, and communication control functions in the OptiX OSN system.
5.4.3 Functions and Features
The CXLLN processes SDH signals, controls communication, grooms
services, and inputs/outputs clock signals.
5.4.4 Working Principle and Signal Flow
The CXLLN consists of the synchronous timing module, O/E converting
module, MUX/DEMUX module, SDH overhead processing module,
communication and control module, cross-connect module, and power
module.
5.4.5 Front Panel
The front panel of the CXLLN board has indicators, an optical interface, a bar
code, functional button switches, a laser safety class label.
5.4.6 Jumpers and DIP Switches
The CXLLN has jumpers, which are used to set the enable state of the battery,
and a DIP switch, which is used to set the running state of the equipment.
5.4.7 Valid Slots
The CXLLN must be installed in a valid slot in the subrack. Otherwise, the
CXLLN cannot work normally.
5.4.8 Feature Code
The number code that follows the board name in the bar code is the feature
code of the board. The feature code of the CXLLN indicates the type of
optical interface. The CXLLN supports optical modules of different
configurations. Therefore, no specific feature code is provided.
5.4.9 Configuring and Commissioning the Board
After you select a correct board, you need to configure and commission the
board. The following tasks need to be performed: checking the hardware of
the board, configuring the board, commissioning the board, and checking the
operation of the board.
5.4.10 Parameter Settings
The physical slot that houses the CXLLN is different from the logical slot
displayed on the U2000. You can set the parameters for the CXLLN by using
the U2000.
 5.4.11 Maintaining the Board
This topic describes the alarms and faults that may occur when the board
operates. This topic also provides the methods and precautions to be taken for
rectifying the faults.
5.4.12 List of Alarms
This topic lists the alarms that may occur when the board operates. The alarms
are reported according to the logical board on the U2000.
5.4.13 List of Performance Events
This topic lists the performance events that may occur when the board
operates. The performance events are reported according to the logical board
on the U2000.
5.4.14 Technical Specifications
The technical specifications of the CXLLN include the parameters specified
for optical interfaces, cross-connect capacity, clock access capability, laser
safety class, mechanical specifications, and power consumption.

1.1.1 Version Description

The CXLLN is available in one functional version, namely, Q5. The CXLLN
supports the intelligent fan.

1.1.2 Application
The CXLLN provides service processing, service grooming, clock
input/output, and communication control functions in the OptiX OSN system.
The CXL provides the other boards in the system with the timing information,
processes the SDH signals, grooms the services between line boards or
tributary boards, communicates with the other boards in the system, and
performs the configuration and management functions for the other boards in
the system.
Figure 5-22 shows the position of the CXL in the system.
 Figure 1-1 Position of the CXL in the system

CXL
Line O/E Line
SDH converting
processing unit unit

Auxiliary
Auxiliary interface
SCC unit unit

Cross-connect and -48 V/-60 V

PIU
timing unit

PDH and other

service signals

1.1.3 Functions and Features

The CXLLN processes SDH signals, controls communication, grooms
services, and inputs/outputs clock signals.

1.1.3.0.1 SDH Processing Unit

Table 5-41 provides the functions and features of the SDH processing unit of
the CXLLN.

Table 1-1 Functions and features of the SDH processing unit of the CXLLN
Function and Feature CXLLN

Basic functions Transmits and receives

1xSTM-1/STM-4/STM-16 optical signals.
Function and Feature
Specifications of the optical interface
Specifications of the optical module
Service processing
Overhead processing
Alarms and performance events
CXLLN
The STM-1/STM-4/STM-16 optical module
can be used.
 At the STM-1 level, the standard I-1, S-1.1,
L-1.1, L-1.2, and Ve-1.2 optical interfaces
are supported. The optical interfaces of I-1,
S-1.1, L-1.1, and L-1.2 types comply with
ITU-T G.957, and the optical interface of
the Ve-1.2 type complies with the standards
defined by Huawei.
 At the STM-4 level, the standard I-4, S-4.1,
L-4.1, L-4.2, and Ve-4.2 optical interfaces
are supported. The optical interfaces of the
I-4, S-4.1, L-4.1, and L-4.2 types comply
with ITU-T G.957, and the optical interface
of the Ve-4.2 type complies with the
standards defined by Huawei.
 At the STM-16 level, the standard I-16,
S-16.1, L-16.1, and L-16.2 optical interfaces
are supported. The optical interfaces of the
I-16, S-16.1, L-16.1, and L-16.2 types
comply with ITU-T G.957.
 Supports the detection and query of the
information about the optical module.
 Provides the ALS function. The optical
interface supports the setting of the on/off
state of a laser.
 Supports the swappable optical modules,
thus facilitating the maintenance and
upgrade of the optical modules.
 The STM-1 module supports the
VC-12/VC-3/VC-4 services.
 The STM-4 module supports the
VC-12/VC-3/VC-4 and VC-4-4c
concatenation services.
 The STM-16 module supports the
VC-12/VC-3/VC-4 and
VC-4-4c/VC-4-8c/VC-4-16c concatenation
services.
 Processes the section overheads of the
STM-1/STM-4/STM-16 signals.
 Supports the transparent transmission and
termination of the path overheads.
 Supports the setting and query of the J0, J1,
J2 and C2 bytes.
 Supports one channel of ECC
communication.
Reports various alarms and performance
events, which facilitates the management and
maintenance of the equipment.
 Function and Feature CXLLN

Protection schemes Supports the following protection schemes:

 Two-fiber ring MSP
 Four-fiber ring MSP
 Linear MSP
 SNCP
 SNCMP
 SNCTP

Maintenance features  Supports inloops and outloops at optical

interfaces.
 Supports warm resets and cold resets. The
warm reset does not affect services.
 Supports the query of the manufacturing
information of the board.
 Supports the in-service loading of the
FPGA.
 Supports the upgrade of the board software
without affecting services.
 The Q5CXLLN supports the PRBS
function.

1.1.3.0.2 SCC Unit

Table 5-42 provides the functions and features of the SCC unit of the CXLLN.

Table 1-2 Functions and features of the SCC unit of the CXLLN
Function and Feature CXLLN

Basic functions Configures and monitors services, monitors

the service performance, and collects the
information about the performance events and
alarms.
 Function and Feature CXLLN

Specifications of the interfaces  Provides one 10M/100M compatible

Ethernet NM interface, which is accessed
through the SAP.
 Provides one 10M/100M Ethernet port,
which is used for implementing the
inter-board communication.
 Provides one 10M Ethernet port, which is
used for implementing the communication
between the active and standby SCC boards.
 Provides the RS232 OAM interface, which
is accessed through the SEI and is used for
connecting a PC or workstation. Supports
the remote maintenance by using the RS232
DCE modem.
 Supports the receiving of the check result of
the NE ID and provides the interface for
querying the check result.
 Provides one orderwire interface and two
NNI phone interfaces, which are accessed
through the SEI.
 Provides four broadcast data ports
(serial1–4), which are accessed through the
SEI.

DCC processing capability Processes 40 channels of DCC signals.

Fan alarm management Manages fan alarms.

PIU management Supports the in-service check function for the

PIU and supports the failure check function
for the lightning protection module of the PIU.

Protection schemes Supports the 1+1 Hot Backup for the

Cross-Connect, Timing and SCC Units.

1.1.3.0.3 Cross-Connect Unit

Table 5-43 provides the functions and features of the cross-connect unit of the
CXLLN.
 Table 1-3 Functions and features of the cross-connect unit of the CXLLN
Function and Feature CXLLN

Basic functions  Realizes 60 Gbit/s higher order

cross-connection at the VC-4 level and 20
Gbit/s lower order cross-connection at the
VC-3 or VC-12 level when the board is
installed on the new backplane.
 Realizes 20 Gbit/s higher order
cross-connection at the VC-4 level and 20
Gbit/s lower order cross-connection at the
VC-3 or VC-12 level when the board is
installed on the old backplane.

Fast emergency channel Provides two 4 Mbit/s HDLC fast emergency

channels, which are used for the MSP
switching, SNCP switching, TPS, or other
functions.

Service processing  Dynamically grooms services.

 Adds or deletes services without
interrupting other services.
 Supports the SNCP protection at the VC-4,
VC-3 and VC-12 levels.
 Supports a maximum of 1184 SNCP groups.
 The STM-4 optical module supports the
VC-4-4c concatenation services.
 The STM-16 optical module supports the
VC-4-4c, VC-4-8c, and VC-4-16c
concatenation services.

Protection schemes Supports the 1+1 Hot Backup for the

Cross-Connect, Timing and SCC Units
(non-revertive, by default).

1.1.3.0.4 Clock Unit

Table 5-44 provides the functions and features of the clock unit of the
CXLLN.

Table 1-4 Functions and features of the clock unit of the CXLLN
Function and Feature CXLLN

Basic functions Provides the standard system synchronization

clock.

Other functions  Supports the extraction, insertion, and

management of the SSM and clock ID.
 Supports the transmission of the DCC
overhead information at two external clock
interfaces.
 Function and Feature CXLLN

Input and output  Inputs two-channel 2048 kHz or 2048 kbit/s

timing signals and selects the external
timing source.
 Outputs two-channel 2048 Hz or 2048 kbit/s
timing signals.

1.1.4 Working Principle and Signal Flow

The CXLLN consists of the synchronous timing module, O/E converting
module, MUX/DEMUX module, SDH overhead processing module,
communication and control module, cross-connect module, and power
module.
Figure 5-23 shows the functional block diagram of the Q5CXLLN.

Figure 1-2 Functional block diagram of the Q5CXLLN

Synchronous
timing module T1 Line unit
38 MHz (SETS) T2
OSC Tributary unit
SETG T3 SEI
T4
(clock external output) SEI
T0 Frame header
155 MHz Service unit
PLL T0 (reference clock)
Service unit
155 MHz High-speed
155 Mbit/s/
STM-1/ SDH overhead bus
4x155 Mbit/s/ Another CXL
STM-4/ 16x155 Mbit/s processing module Cross-connect Higher order cross-
O/E
STM-16 DEMUX data unit connect unit High-speed
bus Another cross-
RST MST MSA HPT
STM-1/ connect unit
E/O High-speed bus
STM-4/
STM-16 MUX Lower order
O/E 155 Mbit/s/
4x155 Mbit/s/ K1/K2 cross-connect unit
converting insertion/
16x155 Mbit/s
module extraction
data Cross-connect module
Laser
Performance
shutdown High-speed bus Cross-connect
report K1/K2 byte DCC
unit B
Laser K1/K2 byte DCC DCC
Line unit
control processing processing
Communication over ETH
channels
Other units
Communication between the active
Communication and control module and standby boards
Another CXL
ETH port SAP
OAM interface
SEI
Power monitor

F&f interface
Phone
Phoneinterface
interface
Boot SEI
Flash RAM NVRAM S1-S4 interface
ROM
+3.3 V Power Fuse -48 V/-60 V
module -48 V/-60 V
Power
module

1.1.4.0.5 Synchronous Timing Module

The synchronous timing module provides the system clock (T0) for the
service board, the control unit, and the cross-connect unit in centralized
timing distribution mode. This module also selects one from the reference
clock sources as the reference clock for synchronous timing. The reference
clock sources are from the line board (T1), the tributary board (T2), or the
external synchronous clock source (T3). The synchronous system clock
 source (T0) and 2 Mbit/s external synchronous source (T4) are generated. The
boards adopt the 1+1 hot backup. Hence, both the active and standby boards
trace the same reference source.
The synchronous timing module can extract the clock from three types of
timing signals:
 Timing signal (T1) from the STM-N line
 Timing signal (T2) from the PDH line
 Reference signal (T3) from the external synchronous clock source (2
MHz or 2 Mbit/s)
The timing module outputs the following timing signals:
 T0, system clock (38 MHz)
 T4, external timing output signal (2 Mbit/s or 2 MHz)

1.1.4.0.6 O/E Converting Module

 Converts the received optical signals into electrical signals, in the receive
direction.
 Converts the electrical signals into SDH optical signals, and then sends
the SDH optical signals to fibers for transmission, in the transmit
direction.
 The SPI detects the R_LOS alarm and provides the laser shut down
function.

1.1.4.0.7 MUX/DEMUX Module

 In the receive direction, the DEMUX part demultiplexes the high rate
electrical signals into multiple parallel electrical signals, and recovers the
clock signal at the same time.
 In the transmit direction, the MUX part multiplexes the parallel electrical
signals received from the SDH overhead processing module into high
rate electrical signals.

1.1.4.0.8 SDH Overhead Processing Module

this module includes the RST, MST, MSA, and HPT sub-modules. This
module provides the inloop and outloop functions.
 RST sub-module
− In the receive direction, the RST sub-module terminates the
regenerator section overhead (RSOH). That is, the RST sub-module
detects the frame alignment bytes (A1 and A2), descrambles all the
bytes except the first line of the RSOH, restores and checks the
regenerator section trace byte (J0), and checks the B1 byte.
− In the transmit direction, the RST sub-module generates the RSOH.
That is, the RST sub-module writes bytes such as A1, A2, and J0,
calculates and writes the B1 byte, and scrambles all the bytes except
the first line of the RSOH.
 MST sub-module
− In the receive direction, the MST sub-module terminates the
multiplex section overhead (MSOH). That is, the MST sub-module
generates the multiplex section-alarm indication signal (MS_AIS)
alarm and detects the multiplex section-remote defect indication
 (MS_RDI) alarm after detecting the K2 byte, and detects the
multiplex section-remote error indication (MS_REI) alarm and
generates the B2-excessive errors (B2_EXC) alarm after checking the
B2 byte.
− In the transmit direction, the MST sub-module generates the MSOH.
That is, the MST sub-module writes bytes such as E2, D4-D12, K1,
K2, S1, and M1, and calculates and writes the B2 byte.
 MSA sub-module
− In the receive direction, the MSA sub-module de-interleaves the
administration unit group (AUG), divides an AUG into N AU-4s,
detects the administration unit-loss of pointer (AU_LOP) alarm and
the administration unit-alarm indication signal (AU_AIS) alarm, and
performs pointer justifications.
− In the transmit direction, the MSA sub-module assembles the AUG
and generates the AU-4. N AU-4s are multiplexed into an AUG
through byte interleaving.
 HPT sub-module
− In the receive direction, the HPT sub-module terminates the path
overhead (POH). That is, the HPT sub-module detects the higher
order path-remote error indication (HP_REI) alarm after checking the
B3 byte, generates the higher order path-trace identifier mismatch
(HP_TIM) alarm and the higher order path-signal label mismatch
(HP_SLM) alarm and detects the higher order path-remote defect
indication (HP_RDI) alarm after detecting the J1 and C2 bytes, and
generates the higher order path-unequipped (HP_UNEQ) alarm after
detecting the C2 byte.
− In the transmit direction, the HPT sub-module generates the POH.
That is, the HPT sub-module writes bytes such as J1 and C2, and
calculates and writes the B3 byte.

1.1.4.0.9 Communication and Control Module

 Traces the clock signal from the active and standby cross-connect units.
 Implements the laser controlling function.
 Selects the clock signal and frame header signal from the active and
standby cross-connect units.
 Controls the indicators on the board.
 Provides the CPU control unit, which controls and monitors the other
functional modules. The unit also initializes the other functional modules
after it is powered on.
 Provides the ETH port, which functions as the 10M/100M Ethernet port
for network management.
 Provides the OAM interface, which functions as the serial port for
network management. This port can be used as the MODEM port and
thus can be configured as a serial port for connecting to the MODEM
port that is in the running state.
 Provides the COM interface, which functions as the commissioning port.
 Provides the Ethernet port, namely, a 10 Mbit/s Ethernet port, for
inter-board communication between the active and standby CXL units.
1.1.4.0.10 Cross-Connect Module
The cross-connect module consists of two parts:
 SNCP module, which tests relative alarms and reports the alarms to the
software to trigger the protection switching such as the SNCP switching
and MSP switching.
 Higher order and lower order cross-connect module, which performs the
functions of higher order and lower order cross-connect units.

1.1.4.0.11 Power Module

It converts the –48 V/–60 V power supply into the DC voltages that the
modules of the board require.

1.1.4.0.12 Other Functions

 Responses to and processes the K bytes.
 Collects the performance data of the optical module and disables the
output of the optical module.
 Collects and processes DCC signal of each board.
 Inserts the DCC signal back into each line board after processing.
 Monitors the power supply of the board.
 Performs the reset of the units.
 Mutes alarms.

1.1.5 Front Panel

The front panel of the CXLLN board has indicators, an optical interface, a bar
code, functional button switches, a laser safety class label.

1.1.5.0.13 Diagram of the Front Panel

Figure 5-24 shows the appearance of the front panel of the Q5CXLLN.
 Figure 1-3 Front panel of the Q5CXLLN

CXLLN
STAT
ACTX
ACTC
PROG
SRVX
SRVL
SYNC
ALMC

CLASS 1
LASER
PRODUCT

OUT1
IN1

RESET

ALM CUT

CXLLN

1.1.5.0.14 Indicators
The front panel of the board has the following indicators:
 Board hardware status indicator (STAT) – two colors (red and green)
 Active/Standby state indicator of the cross-connect unit (ACTX) – one
color (green)
 Active/Standby state indicator of the SCC unit (ACTC) – one color
(green)
 Board software status indicator (PROG) – two colors (red and green)
 Service alarm indicator of the cross-connect unit (SRVX) – three colors
(red, green, and yellow)
 Service alarm indicator of the line unit (SRVL) – three colors (red, green,
and yellow)
 Synchronization clock status indicator (SYNC) – two colors (red and
green)
 Alarm mute indicator (ALMC) – one color (yellow)
 For the meanings of the status of the indicators, see 19 Indicators.

1.1.5.0.15 Interfaces
The front panel of the CXLLN has one optical interface and two switches.
Table 5-45 describes the types and usage of the interfaces and switches of the
CXLLN.

Table 1-5 Optical interface and switches of the CXLLN

Interface/Swit Type of Usage
ch Interface/Swit
ch

IN LC Receives optical signals.

OUT LC Transmits optical signals.

RESET Warm reset Press the switch to perform a warm reset for the SCC unit.
switch

ALM CUT Alarm cut Press the switch to mute the alarm. Press the switch for
switch five seconds to mute the alarm permanently. Press the
switch again for five seconds to resume the alarm sound.

1.1.6 Jumpers and DIP Switches

The CXLLN has jumpers, which are used to set the enable state of the battery,
and a DIP switch, which is used to set the running state of the equipment.

The jumpers and DIP switch are used for test and maintenance. Do not change
the setting of the jumper at random. Otherwise, the board may become faulty.

Figure 5-25 shows the jumpers and DIP switch of the Q5CXLLN.
Figure 1-4 Positions of the jumpers and DIP switch of the Q5CXLLN

Power
module

SW1
123 4

J24

3 21

CPU

CF 1
card 2 J10
3

Table 5-46 lists the jumpers of the Q5CXLLN.

Table 1-6 Jumpers of the Q5CXLLN

Jumper Function Description

J10 To enable the 1–2: If jumper bits (positions) 1 and 2 are capped, the
battery battery is enabled.
2–3: If jumper bits (positions) 2 and 3 are capped, the
database and clock are cleared.

J24 To use the  1–2: If jumper bits (positions) 1 and 2 are capped, the
maximum DCC maximum of 40 DCC channels are used.
channels  2–3: If jumper bits (positions) 2 and 3 are capped, the
maximum of 80 DCC channels are used.

Table 5-47 lists the DIP switch of the CXLLN.

Table 1-7 DIP switch of the CXLLN

DIP Switch Function Description

SW1 To set the running  When a DIP switch bit is at the on position, it
state of the board indicates the binary value 1.
 The DIP switch is a four-bit DIP switch. The values of
the DIP switch bits are queued in the descending order
of the switch bit numbers. The DIP switch bit
numbered 4 is the most significant bit. For details,
refer to Table 5-48.
 Table 1-8 DIP switch SW1
Value Description

0b0000 Indicates the running state when the watchdog is started. It is the default
state.

0b0011 Indicates the commissioning state when the watchdog is stopped.

0b0100 Indicates the running state when the watchdog is stopped.

0b1011 Erases the database.

0b1100 Erases the NE software, including the patches.

0b1101 Erases the database and NE software, including the patches.

0b1110 Erases the database, NE software, and NE.ini file.

0b1111 Erases the extended BIOS and system parameter area in the file system
and flash memory.

1.1.7 Valid Slots

The CXLLN must be installed in a valid slot in the subrack. Otherwise, the
CXLLN cannot work normally.
The CXLLN can be installed in slots 9 and 10 in the subrack.
By default, slot 9 houses the active board and slot 10 houses the standby
board.

1.1.8 Feature Code

The number code that follows the board name in the bar code is the feature
code of the board. The feature code of the CXLLN indicates the type of
optical interface. The CXLLN supports optical modules of different
configurations. Therefore, no specific feature code is provided.

1.1.9 Configuring and Commissioning the Board

After you select a correct board, you need to configure and commission the
board. The following tasks need to be performed: checking the hardware of
the board, configuring the board, commissioning the board, and checking the
operation of the board.

1.1.9.0.16 Checking the Hardware of the Board

Required: Check the hardware of the board.
 The labels on the front panel of the board must be correct and clear.
 The daughter board of the board must be properly installed.
 All the components on both surfaces of the board must be available and
intact.
 Required: Check whether the active board and standby board are installed in
the correct slots.
Required: Check whether the board is properly installed. The board must be
pushed to the bottom of the subrack along the guide rails, and the front panel
of the board must be properly locked. For the method for installing a board,
see Replacing Boards Onsite.
Required: Check the status of the indicators of the board when and after the
board is powered on. For the meanings of the status of the indicators, see 19
Indicators.
Required: Check whether the version of the board software matches the
version of the NE software and the version of the U2000 software. Ensure that
the version of the board software is correct.
Required: Check the micro switch of the board. When the front panels of the
active and standby cross-connect boards are locked, the active/standby
switching can be realized if you unlock the front panel of the active board.
Required: Check the status of the ALM switch.
1. Press the switch to mute the current alarm sound.
2. Press the switch for five seconds to mute the alarm sound permanently.
In this case, the alarm mute indicator (ALMC) turns on (in yellow).
3. Press the switch again for five seconds to resume the alarm sound. In this
case, the ALMC indicator turns off.
----End

1.1.9.0.17 Configuring the Board

Required: Add the logical board. For details, see Adding Boards.
Required: Set parameters for the CXL on the U2000. The following parameters
need to be set:
 Clock synchronization status
 Clock source priority
 Phase-locked source output by external clock
 Clock source switching
 Clock subnet configuration
For the method for setting the parameters, see Configuring Clocks.
Optional: Configure services. For details, see Configuring the SDH Services.
Required: Set parameters for the GSCC on the U2000.
If the parameter settings of the GSCC are available on the U2000, download
the parameter settings to the GSCC. Otherwise, perform the following
operations:
 Set the NE ID. For details, see Setting the NE ID.
 Set the NE name, date, and time. For details, see Setting the NE Name,
Date, and Time.
Required: Set parameters for the line board on the U2000.
Set the SDH interface.
  J0 byte: Generally, use the default value. The default value of the J0 to be
sent is HuaWei SBS and the default value of the J0 to be received
is Disabled.
 J1 byte: The setting of the J1 byte on the interconnected equipment must
be consistent. Generally, use the default value. The default value of the
J1 to be sent is HuaWei SBS and the default value of the J1 to be
received is Disabled.
 C2 byte: The setting of the C2 byte on the interconnected equipment
must be consistent. Set the C2 byte according to the actual service type.
Generally, use the default value, which is TUG structure.
 Laser status: Set this parameter to Open when you configure and
commission the board.
For details, see 23.7 Checking Board Parameters.
Optional: Configure a protection subnet. For details, see Configuring the
Protection Subnet.
----End

1.1.9.0.18 Commissioning the Board

Required: Commission the CXL.
 Check the setting of the jumper that controls the debugging status of the
board. For the description of the jumper, see "Jumpers and DIP
Switches".
 Check and commission the circuit status on the data ports, including the
F&f debugging serial port and OAM NM port. For details, see 23.4
Configuring the F&f Debugging Serial Port and OAM NM Port.
 Check the configurations of the data ports.
− For the configuration of the broadcast data port, see Configuring the
Broadcast Data Service.
− For the configuration of the F1 codirectional data port, see
Configuring the F1 Data Service.
 Test the 1+1 protection provided by the cross-connect, timing, and SCC
board. For details, see Testing the 1+1 Protection of the Cross-Connect
and Timing Board.
 Test the frequency accuracy of the free-run clock. For details, see 23.5
Testing the Frequency Accuracy of the Free-Run Clock.
 Test the clock holdover accuracy. For details, see 23.6 Testing the Clock
Holdover Accuracy.
Optional: Commission the line board.
 Test the specifications of the optical interface. For details, see Testing
Specifications of Optical Interfaces.
 Test the network protection switching. For details, see Testing SDH
Network Protection Switching.
 Test the point-to-point BER. For details, see Testing the Point-to-Point
BER.
----End
1.1.9.0.19 Checking the Operation of the Board
Required: Check the status of the indicators on the front panel of the board to
ensure that the board starts to work normally. When all the indicators are on
and green, the board operates normally. For the meanings of the status of the
indicators, see 19.2 Alarm Indicators on the Boards.
Required: Query the alarms and performance events of the board. Modify the
connections or configurations of the board according to the alarms and
performance events until the alarms are cleared. For the method for querying
the alarms and performance events of a board, see Viewing the Current
Alarms.
----End

1.1.10 Parameter Settings

The physical slot that houses the CXLLN is different from the logical slot
displayed on the U2000. You can set the parameters for the CXLLN by using
the U2000.

1.1.10.0.20 Displayed Slots

The CXLLN occupies one slot in the subrack.
When the Q5CXLLN is installed on the new backplane, the logical boards for
the Q5CXLLN are the Q2SLN, UCXL, and GSCC. Table 5-49 lists the slots
for the logical boards displayed on the U2000.

Table 1-9 Logical slots displayed on the U2000 for the Q5CXLLN (when the old
backplane is used)
Board Logical Board Logical Slot

CXLLN Q2SLN Slot 9 or slot 10

UCXL Slot 80 or slot 81

GSCC Slot 82 or slot 83

When the Q5CXLLN is installed on the old backplane, the logical boards for
the Q5CXLLN are the Q2SLN, ECXL, and GSCC. Table 5-50 lists the slots
for the logical boards displayed on the U2000.

Table 1-10 Logical slots displayed on the U2000 for the Q5CXLLN (when the
old backplane is used)
Board Logical Board Logical Slot

CXLLN Q2SLN Slot 9 or slot 10

ECXL Slot 80 or slot 81

GSCC Slot 82 or slot 83

1.1.10.0.21 Board Parameters
You can set the following main parameters for the CXLLN by using the
U2000:
 J0 byte
 J1 byte
 J2 byte
 C2 byte
 Clock parameters
For the description of each parameter, see 22 Parameter Settings.

1.1.11 Maintaining the Board

This topic describes the alarms and faults that may occur when the board
operates. This topic also provides the methods and precautions to be taken for
rectifying the faults.

1.1.11.0.22 Troubleshooting
Table 5-51 lists the faults that occur on the CXLLN frequently and the
troubleshooting methods.

Table 1-11 Methods used to troubleshoot the faults that occur on the CXLLN
frequently
Fault Symptom Common Fault Troubleshooting Method
Cause

Service unavailable  The type of logical See 23.2 Troubleshooting Service

board is not Unavailability.
consistent with the
type of the board that
is installed on the
NE.
 The service
configuration is
incorrect.
 The running status of
the other boards on
the NE is incorrect.

Clock tracing failure  The clock source See 23.3 Troubleshooting the Clock
priority table is Tracing Failure.
incorrectly
configured.

ECC failure  The running status of  Check whether the running status
the board becomes of the board is correct. See 19.2
abnormal. Alarm Indicators on the Boards to
 The optical fibers are obtain the meanings of the status
incorrectly of the indicators.
connected.  Check whether the optical fibers
are correctly connected.
 Fault Symptom Common Fault Troubleshooting Method
Cause

Power supply alarm
The jumper that
controls the input
voltage is incorrectly
set.
Check whether the jumper that
controls the input voltage is
correctly set. For information on
how to set the jumper, see 5.4.6
Jumpers and DIP Switches.

Failure of the connection  An incorrect network  For information on the connection

between the NMS computer cable is used to
and the equipment connect the NMS
computer to the
equipment.
 The IP address of the  Ensure that the IP address of the
NMS computer and
the IP address of the
equipment are not in
the same network
segment.
of the network cable, see
Checking Connection Between the
U2000 Computer and the
Equipment.
NMS computer and the IP address
of the equipment are correctly set.
For details, see Setting the IP
Address of the PC.

1.1.11.0.23 Replacing the Board

See General Precautions to get familiar with the precautions to be taken for replacing
a board before you replace the board.

For information on how to replace the CXLLN, see Replacing a CXL Board.

1.1.12 List of Alarms

This topic lists the alarms that may occur when the board operates. The alarms
are reported according to the logical board on the U2000.

1.1.12.1 Q5CXLLN

1.1.12.1.24 ECXL (a backplane of the previous version)

APS_FAIL APS_INDI BD_STATUS
CHIP_FAIL BUS_ERR CHIP_ABN
EXT_SYNC_LOS CLK_NO_TRACE_MODE COMMUN_FAIL
HSC_UNAVAIL FPGA_ABN HARD_BAD
LPS_UNI_BI_M K1_K2_M K2_M
NO_BD_SOFT LTI MS_APS_INDI_EX
OTH_HARD_FAIL OOL OTH_BD_STATUS
SWITCH_DISABLE POWER_ABNORMAL S1_SYN_CHANGE
SYNC_F_M_SWITCH SYN_BAD SYNC_C_LOS
TEST_STATUS SYNC_LOCKOFF TEMP_OVER
 W_OFFLINE W_R_FAIL TIME_NOT_SUPPORT
TIME_NO_TRACE_MOD TIME_LOS TIME_FORCE_SWITCH
E
EXT_TIME_LOC NP1_SW_INDI NP1_SW_FAIL
RPS_INDI

1.1.12.1.25 UCXL (a backplane of the later version)

APS_FAIL APS_INDI BD_STATUS
CHIP_FAIL BUS_ERR CHIP_ABN
EXT_SYNC_LOS CLK_NO_TRACE_MODE COMMUN_FAIL
HARD_BAD EXT_TIME_LOC FPGA_ABN
K2_M HSC_UNAVAIL K1_K2_M
MS_APS_INDI_EX LPS_UNI_BI_M LTI
NP1_SW_INDI NO_BD_SOFT NP1_SW_FAIL
PATCH_NOT_CONFIRM OOL PATCH_ERR
PRBS_TEST PATCHFILE_NOTEXIST POWER_ABNORMAL
SYN_BAD RPS_INDI S1_SYN_CHANGE
SYNC_LOCKOFF SYNC_C_LOS SYNC_F_M_SWITCH
TIME_FORCE_SWITCH TEMP_OVER TEST_STATUS
W_OFFLINE TIME_LOS TIME_NO_TRACE_MOD
E
TIME_NOT_SUPPORT

1.1.12.1.26 GSCC
APS_MANUAL_STOP BD_AT_LOWPOWER BD_NOT_INSTALLED
BD_STATUS BOOTROM_BAD CFCARD_FAILED
CFCARD_OFFLINE CFCARD_W_R_DISABLED COMMUN_FAIL
DBMS_ERROR DBMS_PROTECT_MODE DCC_CHAN_LACK
FPGA_ABN HARD_BAD HSC_UNAVAIL
MSSW_DIFFERENT NE_POWER_OVER NESF_LOST
NESTATE_INSTALL LAN_LOC PATCH_ERR
PATCH_PKGERR PATCH_NOT_CONFIRM PATCHFILE_NOTEXIST
 POWER_ABNORMAL POWER_FAIL REG_MM
RINGMAPM_MM RTC_FAIL SECU_ALM
SQUTABM_MM SWDL_ACTIVATED_TIME SWDL_AUTOMATCH_IN
OUT H
SWDL_INPROCESS SWDL_CHGMNG_NOMAT SWDL_COMMIT_FAIL
CH
SWDL_NEPKGCHECK TEMP_OVER SWDL_ROLLBACK_FAIL
SYNC_FAIL BIOS_STATUS WRG_BD_TYPE
CFCARD_FULL PATCH_DEACT_TIMEOUT NP1_MANUAL_STOP
PATCH_ACT_TIMEOU STORM_CUR_QUENUM_O LCS_DAYS_OF_GRACE
T VER
LCS_EXPIRED LCS_FILE_NOT_EXIST SYSLOG_COMM_FAIL
SEC_RADIUS_FAIL NE_CFG_CONFLICT

1.1.12.1.27 Q2SLN
R_LOS R_LOF R_LOF
R_LOC B1_EXC B1_SD
J0_MM B2_EXC B2_SD
MS_AIS MS_RDI MS_REI TF
IN_PWR_ABN OUT_PWR_ABN LSR_WILL_DIE
LSR_COOL_ALM TEM_HA TEM_LA
LASER_MOD_ERR LASER_SHUT LSR_NO_FITED
TEST_STATUS ALM_ALS TC_DEG
FSELECT_STG OH_LOOP TC_EXC
TC_LTC NO_BD_SOFT TC_INCAIS
TC_RDI TC_ODI TC_OEI
TC_UNEQ TC_REI TC_TIM
TR_LOC ALM_AU3AIS ALM_AU3B3OVER
BD_STATUS T_LOSEX COMMUN_FAIL
ALM_AU3RDI ALM_AU3B3SD POWER_ABNORMAL
ALM_AU3TIM ALM_AU3REI ALM_AU3LOP
AU_LOP ALM_AU3UNEQ ALM_AU3SLM
HP_UNEQ HP_TIM AU_AIS
B3_EXC HP_RDI HP_SLM
 C2_PDI B3_SD HP_REI
HP_LOM FPGA_ABN C2_VCAIS
LP_REI_VC12 LOOP_ALM SLAVE_WORKING
LP_UNEQ_VC12 LP_SLM_VC12 LP_RDI_VC12
BIP_SD TU_AIS_VC12 LP_TIM_VC12
LP_RDI_VC3 BIP_EXC TU_LOP_VC12
LP_TIM_VC3 LP_REI_VC3 TEMP_OVER
TU_LOP_VC3 LP_UNEQ_VC3 LP_SLM_VC3
PS B3_EXC_VC3 TU_AIS_VC3
R_OOF MOD_TYPE_MISMATCH B3_SD_VC3
BIP8_ECC AU_CMM LSR_INVALID
SPARE_PATH_ALM W_R_FAIL CHIP_FAIL
TIME_NOT_SUPPORT

1.1.13 List of Performance Events

This topic lists the performance events that may occur when the board
operates. The performance events are reported according to the logical board
on the U2000.

1.1.13.2 Q5CXLLN

1.1.13.2.28 GSCC
XCSTMPMAX XCSTMPMIN XCSTMPCUR
CPUUSAGEMAX CPUUSAGEMIN CPUUSAGECUR
MEMUSAGEMAX MEMUSAGEMIN MEMUSAGECUR

1.1.13.2.29 Q2SLN
AUPJCHIGH AUPJCLOW AUPJCNEW
HPBBE HPCSES HPES
HPFEBBE HPFECSES HPFEES
HPFESES HPFEUAS HPSES
HPUAS MSBBE MSCSES
MSES MSFEBBE MSFECSES
MSFEES MSFESES MSFEUAS
 MSSES MSUAS OSPICCVCUR
OSPICCVMAX OSPICCVMIN OSPITMPCUR
OSPITMPMAX OSPITMPMIN RPLCUR
RPLMAX RPLMIN RSBBE
RSCSES RSES RSOFS
RSOOF RSSES RSUAS
TCBBE TCFEBBE TCOBBE
TLBCUR TLBMAX TLBMIN
TPLCUR TPLMAX TPLMIN

1.1.14 Technical Specifications

The technical specifications of the CXLLN include the parameters specified
for optical interfaces, cross-connect capacity, clock access capability, laser
safety class, mechanical specifications, and power consumption.

1.1.14.2.30 Parameters Specified for Optical Interfaces

The CXLLN supports the STM-1, STM-4, and STM-16 optical modules.
Table 5-52 lists the parameters specified for the optical interfaces of the
CXLLN when the STM-1 optical module is used.

Table 1-12 Parameters specified for the optical interfaces of the CXLLN when
the STM-1 optical module is used
Parameter Value

Nominal bit rate 155520 kbit/s

Line code pattern NRZ

Application code I-1 S-1.1 L-1.1 L-1.2 Ve-1.2

Transmission 0 to 2 2 to 15 20 to 40 60 to 80 80 to 100
distance (km)

Operating 1260 to 1261 to 1263 to 1480 to 1480 to

wavelength range 1360 1360 1360 1580 1580
(nm)

Type of fiber Single-mode Single-mode Single-mode Single-mode Single-mode

LC LC LC LC LC

Mean launched -15 to -8 -15 to -8 -5 to 0 -5 to 0 -3 to 0

optical power
(dBm)

Receiver -23 -28 -34 -34 -34

sensitivity (dBm)
 Parameter Value

Minimum -8 -8 -10 -10 -10

overload (dBm)

Minimum 8.2 8.2 10 10 10

extinction ratio
(dB)

Maximum -20 dB – – – 1 1
spectral width
(nm)

Minimum side – – – 30 30
mode suppression
ratio (dB)

Table 5-53 lists the parameters specified for the optical interfaces of the
CXLLN when the STM-4 optical module is used.

Table 1-13 Parameters specified for the optical interfaces of the CXLLN when
the STM-4 optical module is used
Parameter Value

Nominal bit rate 622080 kbit/s

Line code pattern NRZ

Application code I-4 S-4.1 L-4.1 L-4.2 Ve-4.2

Transmission 0 to 2 2 to 15 20 to 40 50 to 80 80 to 100
distance (km)

Operating 1261 to 1274 to 1280 to 1480 to 1480 to

wavelength range 1360 1356 1335 1580 1580
(nm)

Type of fiber Single-mode Single-mode Single-mode Single-mode Single-mode

LC LC LC LC LC

Mean launched -15 to -8 -15 to -8 -3 to -2 -3 to -2 -3 to -2

optical power
(dBm)

Receiver -23 -28 -28 -28 -34

sensitivity (dBm)

Minimum -8 -8 -8 -8 -13
overload (dBm)

Minimum 8.2 8.2 10 10 10.5

extinction ratio
(dB)

Maximum -20 dB – – 1 1 1
spectral width
(nm)
 Parameter Value

Minimum side – – 30 30 30
mode suppression
ratio (dB)

Table 5-54 lists the parameters specified for the optical interfaces of the
CXLLN when the STM-16 optical module is used.

Table 1-14 Parameters specified for the optical interfaces of the CXLLN when
the STM-16 optical module is used
Parameter Value

Nominal bit rate 2488320 kbit/s

Line code pattern NRZ

Application code I-16 S-16.1 L-16.1 L-16.2

Transmission 0 to 2 2 to 15 25 to 40 50 to 80
distance (km)

Operating 1266 to 1260 to 1360 1280 to 1335 1500 to 1580

wavelength range 1360
(nm)

Type of fiber Single-mode Single-mode LC Single-mode LC Single-mode LC

LC

Mean launched -10 to -3 -5 to 0 -2 to +3 -2 to +3

optical power
(dBm)

Receiver -18 -18 -27 -28

sensitivity (dBm)

Minimum -3 0 -9 -9
overload (dBm)

Dispersion 12 - - 1200 to 1600

tolerance (ps/nm)

Minimum 8.2 8.2 8.2 8.2

extinction ratio
(dB)

Maximum -20 dB – 1 1 1
spectral width
(nm)

Minimum side – 30 30 30
mode suppression
ratio (dB)

Table 5-55 lists the parameters specified for the optical interfaces of the
CXLLN when the STM-16 colored optical module is used.
 Table 1-15 Parameters specified for the optical interfaces of the CXLLN when
the STM-16 colored optical module is used
Parameter Value

CWDM

Nominal bit rate 2488320 kbit/s

Type of fiber Single-mode LC

Transmission distance 80
(km)

Launched optical power 0 to 5

range (dBm)

Operating wavelength 1471 to 1611, in steps of 20

range (nm)

Receiver sensitivity -28

(dBm)

Minimum overload -9
(dBm)

Maximum allowed 1600

dispersion (ps/nm)

Minimum extinction 8.2

ratio (dB)

Maximum -20 dB 1
spectral width (nm)

Minimum side mode 30

suppression ratio (dB)

1.1.14.2.31 Cross-Connect Capacity

The cross-connect capacity of the Q5CXLLN is as follows:
 Higher order cross-connect capacity:
− In the case of the new backplane: 60 Gbit/s
− In the case of the old backplane: 20 Gbit/s
 Lower order cross-connect capacity: 20 Gbit/s
 Access capacity:
− In the case of the new backplane: 22.5 Gbit/s
− In the case of the old backplane: 18.75 Gbit/s

If a label that contains "Enhanced Subrack" is affixed to the equipment, it indicates

that the subrack uses the new backplane.

1.1.14.2.32 Clock Access Capability

The clock access capability of the CXLLN is as follows:
  External input clock: two channels of 2048 kbit/s or 2048 kHz external
clock signals
 External output clock: two channels of 2048 kbit/s or 2048 kHz external
clock signals

1.1.14.2.33 Laser Safety Class

The safety class of the laser on the board is Class 1. The maximum launched
optical power of the optical interfaces is less than 10 dBm (10 mW).

1.1.14.2.34 Mechanical Specifications

The mechanical specifications of the CXLLN are as follows:
 Dimensions (mm): 25.4 (W) x 220 (D) x 254.1 (H)
 Weight of the Q5CXLLN (kg): 1.0

1.1.14.2.35 Power Consumption

The maximum power consumption of the Q5CXLLN at room temperature
(25°C) is 32 W.