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S 1 8 D G
• Low rDS(on) provides higher efficiency and
extends battery life S 2 7 D
• Low thermal impedance copper leadframe S 3 6 D
D
SOIC-8 saves board space G 4 5 D
P-Channel MOSFET
• Fast switching speed
• High performance trench technology
o
ABSOLUTE MAXIMUM RATINGS (TA = 25 C UNLESS OTHERWISE NOTED)
Parameter Symbol Maximum Units
Drain-Source Voltage VDS -30
V
Gate-Source Voltage VGS ±25
o
a TA=25 C -9.5
Continuous Drain Current o
ID
TA=70 C -8.3 A
b
Pulsed Drain Current IDM ±50
a
Continuous Source Current (Diode Conduction) IS -2.1 A
o
a TA=25 C 3.1
Power Dissipation o
PD W
TA=70 C 2.6
o
Operating Junction and Storage Temperature Range TJ, Tstg -55 to 150 C
o
SPECIFICATIONS (TA = 25 C UNLESS OTHERWISE NOTED)
Limits
Parameter Symbol Test Conditions Unit
Min Typ Max
Static
Drain-Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = -250 uA -30
V
Gate-Threshold Voltage VGS(th) VDS = VGS, ID = -250 uA -1 -1.6 -3
Gate-Body Leakage IGSS VDS = 0 V, VGS = ±4.5 V ±200 nA
VDS = -24 V, VGS = 0 V -1
Zero Gate Voltage Drain Current IDSS uA
VDS = -24 V, VGS = 0 V, T J = 55oC -5
A
On-State Drain Current ID(on) VDS = -5 V, VGS = -10 V -50 A
VGS = -10 V, ID = -9.5 A 16 19
A
Drain-Source On-Resistance rDS(on) VGS = -4.5 V, ID = -7.5 A 26 30 mΩ
o
VGS = -10 V, ID = -9.5 A, TJ = 55 C 20 29
A
Forward Tranconductance g fs VDS = -15 V, ID = -9.5 A 31 S
Diode Forward Voltage VSD IS = -2.1 A, VGS = 0 V -0.7 -1.2 V
b
Dynamic
Total Gate Charge Qg 12.8 20
VDS = -15 V, VGS = -4.5 V,
Gate-Source Charge Qgs 4.5 nC
ID = -9.5 A
Gate-Drain Charge Qgd 5
Switching
Turn-On Delay Time td(on) 15 26
Rise Time tr VDD = -15 V, RL = 15 Ω , ID = -1 A, 12 21
nS
Turn-Off Delay Time td(off) VGEN = -10 V, RG = 6Ω 62 108
Fall-Time tf 46 71
Notes
a. Pulse test: PW <= 300us duty cycle <= 2%.
b. Guaranteed by design, not subject to production testing.
Analog Power (APL) reserves the right to make changes without further notice to any products herein. APL makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does APL assume any liability arising out of the application or
use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in APL data sheets and/or specifications can and do vary in different applications and
actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. APL does not convey any license under its patent rights nor the rights of others. APL products are not designed,
intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the APL product could create a situation where personal injury or death may occur.
Should Buyer purchase or use APL products for any such unintended or unauthorized application, Buyer shall indemnify and hold APL and its
officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that APL was negligent regarding the design or manufacture of the part. APL is an Equal Opportunity/Affirmative Action Employer.
20 0 .0 16
3 .5
0 .0 0 8
10
3
0
0
0 10 20 30 40 50
0 0 .5 1 1.5 2 2 .5 3 3 .5 4
1.6 0 .0 6
VGS = 10V 0 .0 5
Normalized RDS(on)
1.4
Resistance (Ω )
ID = 9.5A
0 .0 4
1.2
0 .0 3
1.0
0 .0 2
0.8
0 .0 1
R
0.6
0
- 50 - 25 0 25 50 75 100 125 150
0 2 4 6 8 10
VGS Gate to Source Voltage (V)
T J Juncation T emperature (ºC)
Figure 3. On-Resistance Variation with Temperature
Figure 4. On-Resistance Variation with
Gate to Source Voltage
60
100
VD=VG -55C
50
ID Drain Current (A)
25C
I Source Current (A)
40
10
30
125C T J = 150 C
20
T J = 25C
1
10
0
0 1 2 3 4 5 6
0 .1
VGS Ga te to S o urc e Vo lta ge (V)
0 0 .2 0 .4 0 .6 0 .8 1 1 .2
8
1500
Capacitance (pF)
6
1000
4 Coss
2 500 Crss
0
0 5 10 15 20 25 30 0
0 5 10 15 20
Qg, Total Gate Charge (nC)
VDS (V)
Figure 7. Gate Charge Characteristics Figure 8. Capacitance Characteristics
100 limited ID 50
RDS(ON) 10 us
100 us 45
10 40
35
ID Curren
1ms
POWER (W
10ms 30
1
100 25
1s 20
1 10s 15
0.1
100s
10
DC
5
0.01
0
0.1 1 10 100
0.001 0.1 TIME(S) 10 1000
VDS Drain to Source Voltage (V)
Figure 9. Maximum Safe Operating Area Figure 10. Single Pulse Maximum Power Dissipation
1. Duty C yc a l D = t1/t2
0.01 2. P e r Unit B a s e R θJ A
=70C /W
Single Pulse
3. T J M - T A = P DM Z θjc
4. S ure fa c e M o unte d
0.001
0.0001 0.001 0.01 0.1 1 10 100 1000
Square Wave Pulse Duration (S)
Figure 11. Transient Thermal Response Curve
Package Information
SO-8: 8LEAD
H x 45°
Ordering information
• AM4835EP-T1-XX
– A: Analog Power
– M: MOSFET
– 4835: Part number
– E: ESD Protected
– P: P-Channel
– T1: Tape & reel
– XX: Blank: Standard
PF: Leadfree