World Academy of Science, Engineering and Technology
International Journal of Computer and Information Engineering
Vol:5, No:12, 2011
Implementation of Parallel Interface for
Microprocessor Trainer
Moe Moe Htun, Khin Htar Nwe
Abstract—In this paper, parallel interface for microprocessor
trainer was implemented. A programmable parallel–port device such
as the IC 8255A is initialized for simple input or output and for
handshake input or output by choosing kinds of modes. The hardware
connections and the programs can be used to interface
microprocessor trainer and a personal computer by using IC 8255A.
The assembly programs edited on PC’s editor can be downloaded to
the trainer.
International Science Index, Computer and Information Engineering Vol:5, No:12, 2011 waset.org/Publication/5447
Keywords—Parallel I/O ports, parallel interface, trainer, two
8255 ICs.
I. INTRODUCTION
D EVELOPMENTS in computer technology area have increased
the importance of computer control and interfacing system.
The interfacing system is also consisting of hardware,
software, or both that allows two dissimilar components to
interact. The control and that system are microprocessor
control, microcontroller control and the computer aided
control/interfacing. Computer aided control and interfacing
can be implemented by serial port, parallel port prepared by
special purposes. The parallel port can be very useful
input/output channel for connecting our own circuits to
personal computer and other devices. Interfacing between the
microprocessor trainer and PC uses the address decoder device
and programmable input/output device. This paper covers both
hardware and software, including how to design the
microprocessor trainer that connect to the port as well as how
to write programs to input/output and download from the other
computer.
II. RELATED WORK
The 8255A Programmable Peripheral Interface (PPI) IC
provides all the facilities for interfacing parallel inputs/outputs.
It can be programmed to three simple I/O ports (mode0), two
handshaking I/O ports (mode1), or bidirectional I/O port with
five handshaking signals (mode2). It has 24 lines of digital
input/output, two groups of twelve lines, or three groups of
Moe Moe Htun, Lecturer, at the Department of Electrical Communication,
Technological University (Hinthata), Myanmar and the author was graduated
from the University of Computer Studies, Yangon. (phone: 0943033207; e-
mail: dmmhtun@ gmail.com).
Khin Htar Nwe,,Lecturer, at the Hardware Department, Computer
University (Lashio), Myanmar, the author was graduated from the University
of Computer Studies, Yangon. (phone: 0949281527 ;e-mail:
khinhtarnwe@gmail.com).
International Scholarly and Scientific Research & Innovation 5(12) 2011
eight lines. The two groups of input/output pins are Group A
and Group B. Each of these two groups contains a subgroup of
eight input/output called 8-bit port and another subgroup of
four lines called a 4-bit port. Thus Group A contains an 8-bit
port A along with a 4-bit port C upper (PortC4-PortC7) and
Group B contains an 8-bit port B and a
4-bit port C lower (PC0- PC3). The Group A and Group B
block receive control from the CPU and issues commands to
their respective ports. The 8255A consists of a buffer and
address decoder circuit. The buffer circuit buffers the signals
between the 8255A and the Microprocessor Trainer board, and
the address decoder circuit assigns the 8255A an address on
the address bus. Data is transmitted or received by the buffer
on execution of input or output instructions by the CPU.
The chip select, CS is to communicate between CPU and
8255. RD, read control enables the CPU to read the data in the
ports or the status word through data bus buffer to the device
controlling the 8255. WR is write control and the CPU can
write data on to the ports or on to the control register through
the data bus buffer. RESET is a high on pin clears the control
register and all ports are set to the input mode. A0 and A1, the
input address lines allow the selection of one of three ports or
the control register. [3], [12].
The 74LS138, 3-to-8 line decoder, 16-pin IC decodes one-
of-eight lines, based upon the conditions at the three binary
select inputs and the three enable inputs. Two active-low and
one active-high enable inputs reduce the need for external
gates or inverters when expanding. The features of 74LS-138
are designed specifically for high speed, memory decoders and
data transmission systems. [14].
The parallel port’s hardware includes the back- panel
connector and the circuits and the system’s expansion bus.
[13].
III. CONTRIBUTION
Most of the interfacing using 8255IC describes simple input
and output, strobed input and output, and handshake input and
output. In this paper, I initialize a programmable parallel-port
device for simple input or output and for handshake input or
output by choosing kinds of modes and how parallel data is
sent to a microprocessor trainer from a personal computer on a
handshake basis. I concentrate on the devices and the hardware
connections. And also include the input/output operation by
using the program.
1494 scholar.waset.org/1307-6892/5447
 World Academy of Science, Engineering and Technology
International Journal of Computer and Information Engineering
Vol:5, No:12, 2011

IV. HARDWARE DESIGN OF THE MICROCONTROLLER-BASED

PARALLEL I/O INTERFACE SYSTEM
The hardware and the software implementation will be
summarized. In the Microprocessor Trainer system, the
program debugger, a kind of DMA (Direct Memory Access)
controller, is contained in one of the hardware module. There
are totally six modules (CPU module, Memory module, User
Interface module, DMA module, PIO (Parallel Input /Output)
module and Power Supply module) in the Trainer system and
all modules are provided as separate chip, linked together via
bus connections on a printed circuit board and supplied 5V DC
power. The complete block diagram of the system is shown in
Fig.1.
The Microprocessor Trainer used the 16-bit wide address
bus (A0 to A15) and the data bus (D0 to D7) which connect all
International Science Index, Computer and Information Engineering Vol:5, No:12, 2011 waset.org/Publication/5447

of the modules and used four control signals such as

MEMWR, MEMRD, IOWR and IORD. Memory read
(MEMRD) and memory write (MEMWR) are used to connect
the address lines to the memory module. And the I/O read
Fig.1 Complete Block Diagram of Microprocessor Trainer
(IORD) and I/O write (IOWR) are also used to connect to the
I/O CPU and CPU modules to control the keypad, display
modules and the input/output data. These four memories and VDD

I/O control lines are connected with DMA module and the VDD
+
C25 C26
system buses are used by the main processor and the DMA 47uF 10n
GND
controller alternatively.
The main part which involved in the parallel input/ output
interface system are two IC8255A, 74LS138, eight 7-
VDD VDD
segments, parallel printer port . 8255A has two address lines, D[0..15]
26

26
U26 U27
indicating that it has 4 read/write registers within it which the D0 34
D0 PA0
4 PA0 D0 34
D0 PA0
4 PD0
VC C

VC C
VDD D1 33 3 PA1 D1 33 3 PD1
D2 32 D1 PA1 2 PA2 D2 32 D1 PA1 2 PD2
CPU has to address. The address bits from PIO chips are D3
D4
31
30
D2
D3
PA2
PA3
1
40
PA3
PA4
PA[0..7]
D3
D4
31
30
D2
D3
PA2
PA3
1
40
PD3
PD4
PD[0..7]
D5 D4 PA4 PA5 D5 D4 PA4 PD5
connected to the 74LS138 decoder of the address lines to R61
2.2k
R62 R63 R65
2.2k 2.2k 2.2k D6
D7
29
28
27
D5
D6
PA5
PA6
39
38
37
PA6
PA7
D6
D7
29
28
27
D5
D6
PA5
PA6
39
38
37
PD6
PD7
D7 PA7 D7 PA7
decode the address from the 16 address bits from the trainer. IORD
IORD
IOWR
5
RD PB0
18 PB0
PB1
IORD
IOWR
5
RD PB0
18 PE0
PE1
IOWR 36 19 36 19
WR PB1 WR PB1
The 74LS138 is used to produce chip selects signals for 8255 9
8 A0
A1
PB2
PB3
20
21
PB2
PB3
PB[0..7]
9
8 A0
A1
PB2
PB3
20
21
PE2
PE3
PE[0..7]
35 22 PB4 35 22 PE4
RESET
and other I/O devices. This will generate the appropriate VDD
6 RESET
CS
PB4
PB5
PB6
23
24
PB5
PB6
6 RESET
CS
PB4
PB5
PB6
23
24
PE5
PE6
R64 25 PB7 25 PE7
output to drive the chip selects of the respective chips. The 1k U19 PB7 PB7
16

74LS138 14 PC0 14 PF0

6 PC0 15 PC1 PC0 15 PF1
block diagrams are as shown in Fig. 2(a) and Fig. 2(b). G1 PC1 PC1
VC C

15 16 PC2 16 PF2
Y0 14 PC2 17 PC3 PC2 17 PF3
Y1 PC3 PC[0..7] PC3 PF[0..7]
A4 1 13 13 PC4 13 PF4
At first, in one of the 8255 PIO device, port C is initialized A5 2
A6 3
A Y2
B Y3
12
11
PC4
PC5
12
11
PC5
PC6
PC4
PC5
12
11
PF5
PF6
C Y4 PC6 PC6
G N D

G N D

PC7 PF7
in mode 1 for handshaking data transfer and Port A is used as 4
Y5
Y6
10
9
7
PC7
10
PC7
10

8255 8255
G2A Y7
the data port. Port C 4 is used as the strobed line for the printer
7

5
G2B
G N D

port (Pin number 1). The acknowledge pin (Port C 7) is

8

connected to the printer port of pin number 10. The input A[0..15]
A0
A1

buffer full, IBF signal on Port C5 of the PIO chip would

normally be used as the busy pin of the printer port or parallel
port (pin number 11). In addition, the other 8255A PIO is set
Fig. 2(a) Circuit Diagram of Simple Input/ Output
up in mode 0 because of the data coming from the printer port
can be seen. And that Port A is used to connect to eight LEDs.
And then the variables are initialized.

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 World Academy of Science, Engineering and Technology
International Journal of Computer and Information Engineering
Vol:5, No:12, 2011

B. Controlling with Assembly Software by using C#.Net

T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
T38
T39
T40

T10
T1
T2
T3
T4
T5
T6
T7
T8
T9

T1
T2
T3
T4
T5
T6
T7
T8
T9
POWER
1
2
3
4
5
6
7
8
9
D9 10
D10 11
D11 12
D12 13
D13 14
D14 15
D15 16
MEMWR 17
MEMRD 18
19
20
A0 21
A1 22
A2 23
A3 24
A4 25
A5 26
A6 27
A7 28
A8 29
A9 30
A10 31
A11 32
A12 33
A13 34
A14 35
A15 36
DMA ACK37
DMA REQ38
KEY INT 39
RESET 40

1
2
3
4
5
6
7
8
9
10
J2
BUS
J1

D0
D1
D2
D3
D4
D5
D6
D7
D8

VDD
IOWR
IORD
1. Flow of the Download Program
This software is written on the PC to download the test
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7

PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
download program from it. First a number of lines are
40
39
38
37

18
19
20
21
22
23
24
25

14
15
16
17
13
12
11
10
4
3
2
1
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
calculated to get a line in the test download program and
T1 T1
PC0 1 T2 PF0 1 T2
PC1 2 T3 PF1 2 T3
3 3
VDD

VCC GND PC2 T4 PF2 T4

26 7 PC3 4 T5 PF3 4 T5
RESET

PORTC
5 5

extract byte count, address MSB, address LSB and data type.

PORTF
PC4 T6 PF4 T6

8255
U27

WR

PC5 6 PF5 6
RD

CS
D0
D1
D2
D3
D4
D5
D6
D7

T7 T7
A0
A1

PC6 7 T8 PF6 7 T8
PC7 8 T9 PF7 8 T9
34
33
32
31
30
29
28
27

5
36
9
8
35
6

9 T10 9 T10

If the data type is equal to 01, the data byte is sent zero and
10 10

J5

J8
D0
D1
D2
D3
D4
D5
D6
D7

A0
A1

A5

PB0
PB1
PB2
1
2
3
T1
T2
T3
T4
PE0
PE1
PE2
1
2
3
T1
T2
T3
T4
sent the address MSB, sent the address LSB and sent the data

PORTB
PB3 4 T5 PE3 4 T5

type 01- the end of the signal. The length or byte count,

PORTE
PB4 5 T6 PE4 5 T6
PB5 6 T7 PE5 6 T7
PB6 7 T8 PE6 7 T8
PB7 8 T9 PE7 8 T9
9 9

address MSB, address LSB are converted to hex numbers after

T10 T10
10 10
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

J4

J7
checking the data type is equal to 00. Sending the start signal,
40
39
38
37

18
19
20
21
22
23
24
25

14
15
16
17
13
12
11
10
4
3
2
1

IOWR

T1
IORD

PA0 1 T2 T1
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7

PA1 2 T3 PD0 1 T2
PA2 3 T4 PD1 2 T3
PORTA

4 3

checking the busy signal, and sending strobed signal use write
PA3 T5 PD2 T4

PORTD
PA4 5 PD3 4
VDD

VCC GND T6 T5
26 7 PA5 6 T7 PD4 5 T6
RESET

PA6 7 T8 PD5 6 T7
8255
U26

8 7
WR

PA7 PD6
RD

CS
D0
D1
D2
D3
D4
D5
D6
D7

T9 T8
A0
A1

port program.
9 T10 PD7 8 T9
10 9 T10
34
33
32
31
30
29
28
27

5
36
9
8
35
6

10
J3

J6
D0
D1
D2
D3
D4
D5
D6
D7

After sending the data and strobed signal, the ACK is

A0
A1

A6
IOWR
IORD

C26
10n

checked. If the ACK isn’t send from the PIO, the counter is
2.2k
R65
International Science Index, Computer and Information Engineering Vol:5, No:12, 2011 waset.org/Publication/5447

VDD

47uF
C25
2.2k
R63

counted until three times. If the number of count is three, the

VDD

+
2.2k
R62

R64
1k

message is displayed that the port is busy. But if not, the start
2.2k
R61

GND
VDD

signal is sent again using write port program. This process is

RESET
IOWR
IORD

shown as a flow chart in Fig6 (a) and Fig.6 (b).

Fig. 2(b) Circuit Diagram of Parallel Input/ Output (continued) The hex file format in the test download program is the first
character (:) indicates the start of a record (start code, ASCII
V. HARDWARE AND SOFTWARE IMPLEMENTATION OF PARALLEL
colon “:”) and the next two characters, 10 (10h) indicate the
INTERFACE
record length (byte count, two hex digit pairs) in the data field.
A. Controlling with Assembly Software It is at least 0 to most 16 bit, 16 (0x10) bytes of data. The next
characters E100 give load address. It is address type (four hex
1. Flow of the Parallel Port Driver digits). The next two characters indicate the record type (two
This program is written on the memory module, EEPROM hex digits), 00 to 05, defining the type of the data field. Then
in the trainer to read data from the printer port, to send the we have the actual data. The last two characters 6F are a
ACK to the PC to tell it has been accepted and send it the next checksum (sum of all bytes += 6F), two hex digits.
data and to store the data. Before storing the data in the word Record types in this program are 00 is data record, 01 - End
counter, the data length is divided by two to get a word count. of file record and 04 is extended linear address record. The
All of bits in sending data can’t be read at one time since the rests are 02 - extended segment address record, 03 - start
data bits are 16 bits. Thus the data is read twice when it is sent segment address record and 05 - start linear address record.
from the PC and then it gets the data as a word.
In sending address type, it also uses the polling method. The 2. Flow of the Write Port
In write port program, the port of PIO is checked whether
address lines include the 16 bits address. So it can’t be sent at
busy or not. And if the port is busy, the time is also checked to
one time and stored in the address counter. So the data is
be time out or not. The timer operates during five seconds. If it
stored in the MSB address counter and LSB address counter,
by shifting eight times to the left. The address counter is is overtime, the error message is displayed. If the PIO port
increased and the word counter is decreased. If the word isn’t busy, the data is sent. The strobed pulse signal is
counter is not zero, the data will be reread again from the generated after 5µs. And then the ACK from the PIO is
printer port by polling. If the word counter is zero, all of the checked. Fig.8 shows the flow chart of write port.
data from the printer port has been read. The Fig.3 (a) and Fig.3
3. Flow of Running Light
(b) show the flow charts of the parallel port driver.
The running light test is used to able to see with LEDs when
2. Flow of the Polling the program is downloaded from the PC to the trainer. In
In polling method, the input buffer full flag (IBF) of the PIO is testing, the eight LEDs are running when the program is
read to poll the data transfer from the printer port. If the IBF is downloaded. As a result of running light test program, the
set, the PIO device reads the data from the parallel port. After
reading the data, the IBF is reset. The Fig. 4 is shown flow
chart of polling.
3. Flow of the Acknowledge
Before using the ACK pin, first it is cleared and wait to read
the data. It is shown by Fig.5 of flow chart of acknowledge.

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 World Academy of Science, Engineering and Technology
International Journal of Computer and Information Engineering
Vol:5, No:12, 2011

download process can be checked by LEDs lighting. The

Start
running light test is shown as flow chart of Fig.9 and Fig.7 is
the circuit diagram of LED display module.
Initialize 8255 PIO
4. Flow of Input Test
It is written to test the input/output data transfer from the
microprocessor trainer and shown in Fig. 10 of flow chart of
Initialize Variables
input test.
5. Flow of bit test program
Read Printer Port It is written to be clear the PIO chips for using the Port C
A
(polling) bits for status. Thus Port C is making turn to on and off while
the parallel port of the 8255 PIO chips are doing correctly.
Fig.11 is the flow chart of bit test.
Is it “:” ?
No C
Yes
International Science Index, Computer and Information Engineering Vol:5, No:12, 2011 waset.org/Publication/5447

Send Acknowledge
Signal to PC (ACK) Store in Address
Counter LSB

Read Printer Send Acknowledge

Port (Polling) Signal to PC (ACK)

Store Data in Read Printer

Word Counter Port (Polling)

Yes
Is it Stop Signal? halt
Divide Word Counter
By 2 to get word No

Read Printer Port

(Polling)
Send Acknowledge
Signal to PC
Store in Data MSB
Register
Read Printer Port
(Polling) Read Printer Port
(Polling)

Store in Address
Counter MSB Store in Data LSB
Register

Send Acknowledge
Signal to PC (ACK) Increase Address
Counter

Read Printer Decrease Word

Port (Polling) Counter

C Word Counter = 0?
No
Yes
Fig.3 (a) Flow Chart of Parallel Port Driver
A
Fig. 3(b) Flow Chart of Parallel Port Driver (Continued)

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 World Academy of Science, Engineering and Technology
International Journal of Computer and Information Engineering
Vol:5, No:12, 2011

Polling
Download

Read Input Buffer

Full Flag (IBF) Get Number of Lines

B Get a Line
Is it Set ?
No
Yes
Extract
Byte Count
Read Data Port Address MSB
Address LSB
Data Type
International Science Index, Computer and Information Engineering Vol:5, No:12, 2011 waset.org/Publication/5447

Return

No
Fig. 4 Flow Chart of Polling Is Data Type = Is Data Type =
00? 01?
Yes Yes
Convert Length, Send Byte: 0
Address MSB, Address Send Address
LSB to MSB
Hex Number Send Address
LSB
Send Type: 01
Ack Send Start Signal
“:” (Write Port) Exit

Clear Acknowledge
Received Ack Signal Yes
Pin A
from the Device?

No

Wait Count + +

No Yes
Count = 3? Abort
Set Acknowledge
Pin
Fig. 6(a) Flow Chart of Download

Wait

Return

Fig. 5 Flow Chart of Acknowledge

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 World Academy of Science, Engineering and Technology
International Journal of Computer and Information Engineering
Vol:5, No:12, 2011

Send Record Length

Write Port
No
Device Acknowledge? Abort

Yes
No
Is Port Busy?
Send
Address MSB
Yes

No
Has Time Out?
Send
Address MSB
Yes
International Science Index, Computer and Information Engineering Vol:5, No:12, 2011 waset.org/Publication/5447

Send Display Error Message

Record Type

Send Data to
Return Printer Port LPT1
Is Data Length > 0? No
B

Yes
Generate Strobed pulse
Send Data byte
No
No Device
Decrease Data Length
Has Time Out? Acknowledged ?

Fig. 6(b) Flow Chart of Download (Continued) Yes

Yes
Display Error Message
Return

Return
VDD

GND R3 R4 R5 R6 R7 R8 R9 R10
4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k
Q2SA733 Q2SA733 Q2SA733 Q2SA733 Q2SA733 Q2SA733 Q2SA733 Q2SA733
Fig. 8 Flow Chart of Write Port
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
R11 R12 R13 R14 R15 R16 R17 R18
4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k
Dg

Da
Db

Dg

Da
Db

Dg

Da
Db

Dg

Da
Db
Ag

Aa
Ab

Ag

Aa
Ab

Ag

Aa
Ab

Ag

Aa
Ab

Df

Df

Df

Df
Af

Af
Af

Af
1
2
3
4
5

1
2
3
4
5

1
2
3
4
5

1
2
3
4
5

1
2
3
4
5

1
2
3
4
5

1
2
3
4
5

1
2
3
4
5

LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8

Ae10
Ad 9
8
Ac 7
6

Ae10
Ad 9
8
Ac 7
6

Ae10
Ad 9
8
Ac 7
6

Ae10
Ad 9
8
Ac 7
6

D e1 0
Dd 9
8
Dc 7
6

D e1 0
Dd 9
8
Dc 7
6

D e1 0
Dd 9
8
Dc 7
6

D e1 0
Dd 9
8
Dc 7
6

U4 VDD
74LS573
20

R19 R20 R21 R22

GND 1 4.7k 4.7k 4.7k Q11 4.7k Q12
VCC

11 OC Q9 Q10 Q2SC945 Q2SC945

LATC DIO0 C
2 19 C1 Q2SC945 Q2SC945
DIO1 3 D1 Q1 18 C2
DIO2 4 D2 Q2 17 C3
DIO3 5 D3 Q3 16 C4
DIO4 6 D4 Q4 15
DIO5 7 D5 Q5 14 U2 VDD VDD U3 VDD VDD
DIO6 8 D6 Q6 13 74LS573 74LS573
20

20
GND

DIO7 9 D7 Q7 12 U6 U8
D8 Q8 GND 1 ULN2004A GND 1 ULN2004A
VCC

VCC

OC OC
9

11 4.7k 11 47
C C
10

DIO0 2 19 1 16 R23 Aa DIO0 2 19 1 16 R24 Da

C OM

C OM

DIO1 3 D1 Q1 18 2 1B 1C 15 R25 Ab DIO1 3 D1 Q1 18 2 1B 1C 15 R26 Db

C1 DIO2 4 D2 Q2 17 3 2B 2C 14 R27 Ac DIO2 4 D2 Q2 17 3 2B 2C 14 R28 Dc
C1 DIO3 D3 Q3 3B 3C Ad DIO3 D3 Q3 3B 3C Dd
5 16 4 13 R29 5 16 4 13 R30
C2 DIO4 6 D4 Q4 15 5 4B 4C 12 R31 Ae DIO4 6 D4 Q4 15 5 4B 4C 12 R32 De
C2 D5 Q5 5B 5C D5 Q5 5B 5C
DIO5 7 14 6 11 R33 Af DIO5 7 14 6 11 R34 Df
C3 DIO6 8 D6 Q6 13 7 6B 6C 10 R35 Ag DIO6 8 D6 Q6 13 7 6B 6C 10 R36 Dg
GND

GND

C3 DIO7 D7 Q7 7B 7C DIO7 D7 Q7 7B 7C
9 12 9 12
GND

GND

C4 D8 Q8 D8 Q8
C4
10

10
8

DIO[0..8]
DIO[0..15]

LATD

LATA

Fig. 7 Circuit Diagram of LED Display Module

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 World Academy of Science, Engineering and Technology
International Journal of Computer and Information Engineering
Vol:5, No:12, 2011

Start Start

Set up I/O Port Load Control Address

As Output

Set up 8255
Load LED Pattern

Wait
Count = 8

Store in Register R3 Set Port C7

Output Register Wait

International Science Index, Computer and Information Engineering Vol:5, No:12, 2011 waset.org/Publication/5447

R3 to Port A

Clear Port C7
Shift R3 Left

Fig. 11 Flow chart of bit test

Wait

Decrease Count VI. CONCLUSION

The design concept for the parallel port- based interfacing
No Yes system has been defined. This interfacing system is perfect to
Count = 0?
input/output or parallel input/output from the microprocessor
Fig. 9 Flow Chart of Running Light trainer. And it is also perfect to download any program from
the PC to the microprocessor trainer. It is the best low cost,
good quality interfacing. In this paper, it is impossible to make
the interfacing systems with only the hardware design. It is
able to make both the hardware and software or the driver that
control them are just used.
Start
Two 8255A chips are used. One is used as the printer
interface and another is used to handle all other parallel I/O
activities. The circuit is constructed and tested electrically
Initialize Ports (mode0) Port B input
Port A output without any chips installed. A driver program is loaded into
EEPROM that configures the parallel ports for handshake data
transfer. A test downloading program is then loaded and it is
shown out from DMA to the display. The input/output test
Read Port B
program is also loaded under control of the CPU and outputted
with eight LEDs.
This paper helps to the learners who are familiar with the
Wait peripheral parallel input/output chip. It would be a good tool
for learners to learn about the instructions written in
microprocessor trainer complier.
Write Port A In this paper, there are a few tests and a few programs can
be downloaded from the PC. Thus, as an extension, the
learners who learn the microprocessor trainer can download a
Fig. 10 Flow Chart of Input Test lot of programs as needed and can use this chip as a serial port
to interface the peripherals and to download programs from
the PC.

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 World Academy of Science, Engineering and Technology
International Journal of Computer and Information Engineering
Vol:5, No:12, 2011

ACKNOWLEDGMENT
First of all, the author would like to express Her Gratitude
to Professor Dr. Nilar Thein, Rector of University of
Computer Studies, Yangon, for overall supporting during her
paper and encouragement for this paper.
The author would like to express Her Deep Appreciation to
Pro Rector U Kyaw Swa Soe, University of Computer Studies,
Yangon, for providing the facilities, guidance, invaluable
advice and supervision throughout her paper.
The author would like to thank Deputy Director General U
Win Khine Moe, Myanmar Science and Technological
Research Department who advise her to do this paper.
The author is also grateful to Professor Daw New Ni,
University of Computer Studies, Yangon, for this suggestion
and helpful advice throughout her paper.
International Science Index, Computer and Information Engineering Vol:5, No:12, 2011 waset.org/Publication/5447

The author is also grateful to Dr. Mi Mi Thet Thwin,

Rector, University of Computer Studies, Mandalay, for their
kind permission to use the required laboratory instruments in
this research and gave valuable suggestions at the seminars
and made it possible for me to complete the whole paper.
The author is very thankful to Professor Dr. Win Aye,
Computer University (Mandalay) for her invaluable guidance,
advice, encouragement for this paper.
The author is particularly indebted to the volunteers, who
participated in this study and would like to thank to all who
have responded so willing to her request for technical
assistance in the preparation of this paper.
Lastly, the author has great pleasure in expressing her
gratitude to her family for their constant encouragement.

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