Implementation challenges designing with

Multiple Supply Voltages

Disclaimer: Presentation to this forum is not an endorsement of any specific proposed format

Herve Menager
Si2-Accelera Low Power Workshop
October 5th 2006
Outline

What has changed in Low Power

implementation
New IP(s), New methods
Requirements from the tools
Tools MSV support
Missing pieces
Q&A

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Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
Low power implementation : What’s new ?
Becoming mainstream:
– For 65nm and below , Low power is crucial for low/high performance.
So far:
– For dynamic power
• Reducing power dissipation source when not needed.
• Minimize switching capacitances.
– For static power
• Use of multiple Vt(s) synthesis / optimization
More recently:
– Reducing supply reduces power, but also makes circuit slower. To meet both
chip performance requirements and power goals, use voltage islands and
voltage and frequency scaling.
– Leakage can also be addressed by suppressing current when not needed.

Æ Island of voltages increases the difficulty on implementation

techniques.
Æ Intrusive on functionality
Æ Impact across design tasks ( Design-In and Implementation )

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Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
Design implementation challenges
New cells and their use model
– Level Shifters
– Retention logic
– Isolation logic
– Micro Switches
Impacts at all levels of the design flow
– Interface logic design, partitioning
– Verification of power modes
– Checks on interfaces between Power domains
– Placement of IP in context voltage islands
– Floorplanning with switches, Irdrop across switches, transient
behavior.
– DFT
– Verification (STA, LVS, analysis)
Conceptual shift : Power nets become functional signals

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Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
 Interface Logic
For power switching Voltage islands are turned ON/OFF with on-chip
Control switches
– Impact on power distribution and floorplanning
VDD always VDD switched
– Takes area and leaks
– Control signal has implementation constraints.

Cannot directly connect output of a powered down

VDDL VDDH
block.
0 Static

X
Current
?
– Can propagate unwanted data in the logic driven
? – Floating input will potentially generate short
circuit current.

With Multiple Supplies Cannot directly connect VDDL and VDDH cells
– Output of VDDL gate can’t be raised higher than
VDDL VDDH

Static
VDDL
Current
– When connected to VDDH gate, PMOS will never
be completely cut-off Š Static Current

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Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
Methodology and design flow impacted

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Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
Tool Requirements
Cell level understanding
– Library data : power switches, LS, isolation, retention, …
– Voltage / Temp dependency characterization

IP description
– Hard IP view to associate pins to power nets.
– Information about isolation.
– Re-use aspects

Design intent
– What hierarchy to what power domain, at what supply
– What the power modes are
– What block can be turned off
– What block require retention
– Level shifting done in both directions or only low to high supply
– Where in the hierarchy should the LS / isolation be inserted

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Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
Tools MSV support

Ad hoc up to recently
Interface logic insertion
Floorplanning with multiple supply areas
Checks on interfaces, logical , physical
Placement of LS and isolation logic, always-on logic, etc
Power distribution integrity
– Irdrop across switches steady state
– Dynamic analysis at turn on.
– Wake-up time and rush current

Infrastructure for STA

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Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
Short Term need (1) - Common Format
No formal repository ( format or language) for capturing the
low power constraints for a design.
The information scattered in the SoC architect's mind,
power is not usually explicit in functional descriptions.
Many implementation tools now need to understand this
information and add value with it.
Today recaptured as many times as required. Recipe for
disaster.
Need to converge on a design specification for low power.
– Used by all EDA providers, allowing all EDA tools to
read the same information from a common source
– Industry standard

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Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
Short Term need ( 2) – Fill hole in Verification

Low leakage design techniques have created a real

paradigm shift.
Power and ground nets are now becoming functional nets.
They are not all explicitly in RTL or netlist levels.
Proper connection of any other functional nets is verified by
functional simulation….against the RTL or netlist.
Being able to verify the power down modes , retention,
recovery at power-on, etc in the context of RTL simulation is
becoming mandatory.
Verification tools should be power modes aware.

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Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
Longer term need (3) – Steer towards more
automation with DFP tools
Shifter, clamps, switches, retention, power control logic are
today added manually
Isolation logic is similar to test logic.
– LS or clamps ~ scan flops, jtag cells or ctag shells
– Power control blocks ~ test control blocks

DFT tools insert automatically this logic and their control

blocks from test strategy specification
Automatic creation of low power logic, similarly to DFT
needed
Requires a standard, similar to DFT 's IEEE standards.
Should be solved at industry level.

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Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
Conclusion
We have some basic level of tool support
We need :
– Placeholder for library IP description ( .lib is a natural candidate)
– Placeholder for “Complementary to RTL” information for low power design
intent creation.
Upf, Cpf, or xyzpf : competition on formats is not a value differentiator.
We need one only!
If not there, we’ll get back to internal format.
Instead, compete on the tool’s low power features using this
standardized information.
Competition on formats is a handicap to the design community.
Move fast to converge. Start with what is out there already.

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Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
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Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006