84961

SN54/74LS05
HEX INVERTER
HEX INVERTER
VCC
LOW POWER SCHOTTKY
14 13 12 11 10 9 8
* * *
* * * J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
14
GND 1
* OPEN COLLECTOR OUTPUTS
N SUFFIX
PLASTIC
14 CASE 646-06
1
D SUFFIX
SOIC
14
1 CASE 751A-02
ORDERING INFORMATION
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC
GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
VOH Output Voltage — High 54, 74 5.5 V
IOL Output Current — Low 54 4.0 mA
74 8.0
FAST AND LS TTL DATA

5-1
SN54/74LS05
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input
p LOW Voltage
g for
VIL Input LOW Voltage V
74 0.8 All Inputs
VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
IOH Output HIGH Current 54, 74 100 µA VCC = MIN, VOH = MAX
54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table
20 µA VCC = MAX, VIN = 2.7 V

IIH Input HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V
Power Supply Current
ICC Total, Output HIGH 2.4 mA VCC = MAX
Total, Output LOW 6.6
AC CHARACTERISTICS (TA = 25°C)

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tPLH Turn-Off Delay, Input to Output 17 32 ns VCC = 5.0 V
tPHL Turn-On Delay, Input to Output 15 28 ns CL = 15 pF, RL = 2.0 kΩ

5-2
SN54/74LS10
TRIPLE 3-INPUT NAND GATE
TRIPLE 3-INPUT NAND GATE

VCC
LOW POWER SCHOTTKY
14 13 12 11 10 9 8
J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
14
GND 1
N SUFFIX
PLASTIC
14 CASE 646-06
1
D SUFFIX
SOIC
14
1 CASE 751A-02
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC

74 4.75 5.0 5.25
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
74 8.0

5-1
SN54/74LS10

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs
54 2.5 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table


IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX

ICC Total, Output
p HIGH 1.2 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tPLH Turn-Off Delay, Input to Output 9.0 15 ns VCC = 5.0 V
tPHL Turn-On Delay, Input to Output 10 15 ns CL = 15 pF

5-2
SN54/74LS11
TRIPLE 3-INPUT AND GATE
TRIPLE 3-INPUT AND GATE

VCC
LOW POWER SCHOTTKY
14 13 12 11 10 9 8
J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
GND 14
1
N SUFFIX
PLASTIC
14 CASE 646-06
1
D SUFFIX
SOIC
14
1 CASE 751A-02
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC

74 4.75 5.0 5.25
74 0 25 70
74 8.0

5-1
SN54/74LS11

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



ICC Total, Output

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i

5-2
SN54/74LS13
SCHMITT TRIGGERS SN54/74LS14
DUAL GATE/HEX INVERTER
The SN54LS / 74LS13 and SN54LS / 74LS14 contain logic gates / inverters
which accept standard TTL input signals and provide standard TTL output
levels. They are capable of transforming slowly changing input signals into SCHMITT TRIGGERS
sharply defined, jitter-free output signals. Additionally, they have greater noise DUAL GATE/ HEX INVERTER
margin than conventional inverters.
Each circuit contains a Schmitt trigger followed by a Darlington level shifter LOW POWER SCHOTTKY
and a phase splitter driving a TTL totem pole output. The Schmitt trigger uses
positive feedback to effectively speed-up slow input transitions, and provide
different input threshold voltages for positive and negative-going transitions.
This hysteresis between the positive-going and negative-going input
thresholds (typically 800 mV) is determined internally by resistor ratios and is
J SUFFIX
essentially insensitive to temperature and supply voltage variations. CERAMIC
CASE 632-08
14
LOGIC AND CONNECTION DIAGRAMS 1
SN54 / 74LS13
VCC
14 13 12 11 10 9 8
N SUFFIX
PLASTIC
14 CASE 646-06
1
1 2 3 4 5 6 7 D SUFFIX
SOIC
GND 14
1 CASE 751A-02
SN54 / 74LS14
VCC
14 13 12 11 10 9 8 ORDERING INFORMATION
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC
1 2 3 4 5 6 7
GND

74 4.75 5.0 5.25
74 0 25 70
74 8.0

5-1
SN54/74LS13 • SN54/74LS14

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
VT+ Positive-Going Threshold Voltage 1.5 2.0 V VCC = 5.0 V
VT– Negative-Going Threshold Voltage 0.6 1.1 V VCC = 5.0 V
VT+ – VT– Hysteresis 0.4 0.8 V VCC = 5.0 V
54 2.5 3.4 V
VOH Output HIGH Voltage VCC = MIN µA VIN = VIL
MIN, IOH = – 400 µA,
74 2.7 3.4 V
54, 74 0.25 0.4 V VCC = MIN, IOL = 4.0 mA, VIN = 2.0 V
VOL Output LOW Voltage
74 0.35 0.5 V VCC = MIN, IOL = 8.0 mA, VIN = 2.0 V
IT+ Input Current at Positive-Going Threshold – 0.14 mA VCC = 5.0 V, VIN = VT+
IT– Input Current at Negative-Going Threshold – 0.18 mA VCC = 5.0 V, VIN = VT–
1.0 20 µA VCC = MAX, VIN = 2.7 V
IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX, VOUT = 0 V
LS13 2.9 6.0
Total Output HIGH
Total,
ICC LS14 8.6 16 mA
A VCC = MAX
LS13 4.1 7.0
Total Output LOW
Total,
LS14 12 21

Max
S b l
Symbol P
Parameter LS13 LS14 U i
Unit T
Test C di i
Conditions
tPLH Propagation Delay, Input to Output 22 22 ns VCC = 5.0 V
tPHL Propagation Delay, Input to Output 27 22 ns CL = 15 pF
3V
VIN 1.6 V
0.8 V
0V
tPHL tPLH
VOUT 1.3 V 1.3 V
Figure 1. AC Waveforms

5-2
SN54/74LS13 • SN54/74LS14
5
VCC = 5 V
TA = 25°C
V O , OUTPUT VOLTAGE (VOLTS)

4
0
0 0.4 0.95 1.2 1.8 2
VIN, INPUT VOLTAGE (VOLTS)
Figure 2. VIN versus VOUT Transfer Function
2
TA = 25°C
V T , THRESHOLD VOLTAGE (VOLTS)
VT+
∆ V T, HYSTERESIS (VOLTS)
1.6
1.2
VT–
0.8
∆ VT
0.4
0
4.5 4.75 5 5.25 5.5
VCC, POWER SUPPLY VOLTAGE (VOLTS)
Figure 3. Threshold Voltage and Hysteresis

versus Power Supply Voltage
1.9
V T , THRESHOLD VOLTAGE (VOLTS)
1.7 VT+
∆ V T, HYSTERESIS (VOLTS)
1.5
1.3
1.1
0.9 VT–
∆ VT
0.7
– 55° 0° 25° 75° 125°
TA, AMBIENT TEMPERATURE (°C)
Figure 4. Threshold Voltage Hysteresis

versus Temperature

5-3
SN54/74LS20
DUAL 4-INPUT NAND GATE
DUAL 4-INPUT NAND GATE

VCC
LOW POWER SCHOTTKY
14 13 12 11 10 9 8
J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
GND 14
1
N SUFFIX
PLASTIC
14 CASE 646-06
1
D SUFFIX
SOIC
14
1 CASE 751A-02
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC

74 4.75 5.0 5.25
74 0 25 70
74 8.0

5-1
SN54/74LS20

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



ICC Total, Output

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i

5-2
SN54/74LS30
8-INPUT NAND GATE
8-INPUT NAND GATE

VCC
LOW POWER SCHOTTKY
14 13 12 11 10 9 8
J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
14
GND 1
N SUFFIX
PLASTIC
14 CASE 646-06
1
D SUFFIX
SOIC
14
1 CASE 751A-02
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC

74 4.75 5.0 5.25
74 0 25 70
74 8.0

5-1
SN54/74LS30

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i

5-2
SN54/74LS47
BCD TO 7-SEGMENT
DECODER/DRIVER
The SN54 / 74LS47 are Low Power Schottky BCD to 7-Segment Decod-
er / Drivers consisting of NAND gates, input buffers and seven AND-OR-IN-
VERT gates. They offer active LOW, high sink current outputs for driving BCD TO 7-SEGMENT
indicators directly. Seven NAND gates and one driver are connected in pairs DECODER/ DRIVER
to make BCD data and its complement available to the seven decoding
AND-OR-INVERT gates. The remaining NAND gate and three input buffers LOW POWER SCHOTTKY
provide lamp test, blanking input / ripple-blanking output and ripple-blanking
input.
The circuits accept 4-bit binary-coded-decimal (BCD) and, depending on
the state of the auxiliary inputs, decodes this data to drive a 7-segment display
indicator. The relative positive-logic output levels, as well as conditions
required at the auxiliary inputs, are shown in the truth tables. Output J SUFFIX
configurations of the SN54 / 74LS47 are designed to withstand the relatively CERAMIC
high voltages required for 7-segment indicators. CASE 620-09
These outputs will withstand 15 V with a maximum reverse current of 16
1
250 µA. Indicator segments requiring up to 24 mA of current may be driven
directly from the SN74LS47 high performance output transistors. Display
patterns for BCD input counts above nine are unique symbols to authenticate
input conditions.
The SN54 / 74LS47 incorporates automatic leading and / or trailing-edge N SUFFIX
zero-blanking control (RBI and RBO). Lamp test (LT) may be performed at any PLASTIC
time which the BI / RBO node is a HIGH level. This device also contains an 16 CASE 648-08
overriding blanking input (BI) which can be used to control the lamp intensity 1
by varying the frequency and duty cycle of the BI input signal or to inhibit the
outputs.
• Lamp Intensity Modulation Capability (BI/RBO) D SUFFIX
• Open Collector Outputs
16
SOIC
• Lamp Test Provision 1 CASE 751B-03
• Leading / Trailing Zero Suppression
• Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
SN54LSXXJ Ceramic
VCC f g a b c d e
SN74LSXXN Plastic
16 15 14 13 12 11 10 9 SN74LSXXD SOIC
LOGIC SYMBOL
7 1 2 6 3 5
1 2 3 4 5 6 7 8
A B C D LT RBI
B C LT BI / RBO RBI D A GND
PIN NAMES LOADING (Note a)
HIGH LOW BI/
a b c d e f g RBO
A, B, C, D BCD Inputs 0.5 U.L. 0.25 U.L.
RBI Ripple-Blanking Input 0.5 U.L. 0.25 U.L.
LT Lamp-Test Input 0.5 U.L. 0.25 U.L. 13 12 11 10 9 15 14 4
BI / RBO Blanking Input or 0.5 U.L. 0.75 U.L.
Ripple-Blanking Output 1.2 U.L. 2.0 U.L. VCC = PIN 16
a, to g Outputs Open-Collector 15 (7.5) U.L. GND = PIN 8
NOTES:
a) 1 Unit Load (U.L.) = 40 µA HIGH, 1.6 mA LOW.
b) Output current measured at VOUT = 0.5 V
The Output LOW drive factor is 7.5 U.L. for Military (54) and 15 U.L. for Commercial (74) Temperature Ranges.

5-1
SN54/74LS47
LOGIC DIAGRAM
a a
b b
B
INPUT
C c c
D
OUTPUT
d d
BLANKING INPUT OR
RIPPLE-BLANKING
OUTPUT e e
f f
LAMP-TEST
INPUT
RIPPLE-BLANKING
INPUT g g
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
NUMERICAL DESIGNATIONS — RESULTANT DISPLAYS
TRUTH TABLE
INPUTS OUTPUTS
DECIMAL
OR LT RBI D C B A BI/RBO a b c d e f g NOTE
FUNCTION
0 H H L L L L H L L L L L L H A
1 H X L L L H H H L L H H H H A
2 H X L L H L H L L H L L H L
3 H X L L H H H L L L L H H L
4 H X L H L L H H L L H H L L
5 H X L H L H H L H L L H L L
6 H X L H H L H H H L L L L L
7 H X L H H H H L L L H H H H
8 H X H L L L H L L L L L L L
9 H X H L L H H L L L H H L L
10 H X H L H L H H H H L L H L
11 H X H L H H H H H L L H H L
12 H X H H L L H H L H H H L L
13 H X H H L H H L H H L H L L
14 H X H H H L H H H H L L L L
15 H X H H H H H H H H H H H H
BI X X X X X X L H H H H H H H B
RBI H L L L L L L H H H H H H H C
LT L X X X X X H L L L L L L L D
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
NOTES:
(A) BI/RBO is wire-AND logic serving as blanking Input (BI) and/or ripple-blanking output (RBO). The blanking out (BI) must be open or held
at a HIGH level when output functions 0 through 15 are desired, and ripple-blanking input (RBI) must be open or at a HIGH level if blanking
of a decimal 0 is not desired. X = input may be HIGH or LOW.
(B) When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a LOW level regardless of the state of
any other input condition.
(C) When ripple-blanking input (RBI) and inputs A, B, C, and D are at LOW level, with the lamp test input at HIGH level, all segment outputs
go to a HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition).
(D) When the blanking input/ripple-blanking output (BI/RBO) is open or held at a HIGH level, and a LOW level is applied to lamp test input,
all segment outputs go to a LOW level.

5-2
SN54/74LS47
74 4.75 5.0 5.25
74 0 25 70
IOH Output Current — High BI / RBO 54, 74 – 50 µA
IOL Output Current — Low BI / RBO 54 1.6 mA
BI / RBO 74 3.2
VO (off) Off-State Output Voltage a to g 54, 74 15 V
IO (on) On-State Output Current a to g 54 12 mA
On-State Output Current a to g 74 24

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
Guaranteed Input HIGH Theshold Voltage
for All Inputs
p LOW Threshold Voltage
g
74 0.8 for All Inputs
VCC = MIN,, IOH = – 50 µA,
µ ,
VOH Output HIGH Voltage,
Voltage BI / RBO 24
2.4 42
4.2 V
VIN = VIN or VIL per Truth Table
Output
p LOW Voltage
g 54, 74 0.25 0.4 V IOL = 1.6 mA VCC = MIN,, VIN = VIN or
VOL
BI / RBO 74 0.35 0.5 V IOL = 3.2 mA VIL per Truth Table
Off-State Output Current VCC = MAX, VIN = VIN or VIL per Truth
IO (off) 250 µA
a thru g Table, VO (off) = 15 V
On-State Output
p Voltage
g 54, 74 0.25 0.4 V IO (on) = 12 mA VCC = MAX, VIN = VIH
VO (on) or VIL per Truth
T th Table
T bl
a thru g 74 0.35 0.5 V IO (on) = 24 mA
Input LOW Current BI / RBO – 1.2
IIL mA VCC = MAX, VIN = 0.4 V
Any Input except BI / RBO – 0.4
IOS BI / RBO Output Short Circuit Current (Note 1) – 0.3 –2.0 mA VCC = MAX, VOUT = 0 V
ICC Power Supply Current 7.0 13 mA VCC = MAX

Limits
Symbol
S b l Parameter
P Min Typ Max Unit
U i Test
T Conditions
C di i
tPHL Propagation Delay, Address 100 ns
tPLH Input to Segment Output 100 ns VCC = 5.0 V
tPHL Propagation Delay, RBI Input 100 ns CL = 15 pF
tPLH To Segment Output 100 ns
AC WAVEFORMS
VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V
tPHL tPLH tPHL tPLH
VOUT 1.3 V 1.3 V VOUT 1.3 V 1.3 V
Figure 1 Figure 2

5-3
SN54/74LS73A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These
dual flip-flops are designed so that when the clock goes HIGH, the inputs are
enabled and data will be accepted. The logic level of the J and K inputs may DUAL JK NEGATIVE
be allowed to change when the clock pulse is HIGH and the bistable will per- EDGE-TRIGGERED FLIP-FLOP
form according to the truth table as long as minimum set-up times are ob-
served. Input data is transferred to the outputs on the negative-going edge of LOW POWER SCHOTTKY
the clock pulse.
LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX

CERAMIC
CASE 632-08
14
1
Q Q
13 (8) 12 (9)
N SUFFIX
CLEAR PLASTIC
2 (6)
K 14 CASE 646-06
J
3 (10) 14 (7) 1
1 (15)
CLOCK (CP)
D SUFFIX
SOIC
14
1 CASE 751A-02
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC
MODE SELECT — TRUTH TABLE
INPUTS OUTPUTS
OPERATING MODE
CD J K Q Q
LOGIC SYMBOL
Reset (Clear) L X X L H
Toggle H h h q q
Load “0” (Reset) H l h L H
Load “1” (Set) H h l H L 14 J Q 12 7 J Q 9
Hold H l l q q
1 CP 5 CP
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
3 K C Q 13 10 K C Q 8
X = Don’t Care D D
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time
l, h (q) = prior to the HIGH to LOW clock transition. 2 6
VCC = PIN 4
GND = PIN 11

5-1
SN54/74LS73A

74 4.75 5.0 5.25
74 0 25 70
74 8.0

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs

J, K 20
Clear 60 µA VCC = MAX, VIN = 2.7 V
Clock 80
J, K 0.1
Clear 0.3 mA VCC = MAX, VIN = 7.0 V
Clock 0.4
J, K – 0.4
IIL Input LOW Current mA VCC = MAX, VIN = 0.4 V
Clear, Clock – 0.8
ICC Power Supply Current 6.0 mA VCC = MAX
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
fMAX Maximum Clock Frequency 30 45 MHz Figure 1
VCC = 5.0
50V
tPLH Propagation
p g Delay,
y, 15 20 ns
Figure 1 CL = 15 pF
tPHL Clock to Output 15 20 ns
AC SETUP REQUIREMENTS (TA = 25°C)

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tW Clock Pulse Width High 20 ns Figure 1
tW Clear Pulse Width 25 ns Figure 2
VCC = 5
5.0
0V
ts Setup Time 20 ns
Figure 1
th Hold Time 0 ns

5-2
SN54/74LS73A
AC WAVEFORMS
J or K * 1.3 V
th(L) = 0 th(H) = 0
ts(L) ts(H)
tW(L)
CP
1.3 V 1.3 V 1.3 V
tW(H)
1
tPHL fMAX tPLH
Q
1.3 V 1.3 V
tPLH tPHL
1.3 V 1.3 V
Q
*The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays, Data

Set-Up and Hold Times, Clock Pulse Width
tW
SET
1.3 V 1.3 V
tW
CLEAR
1.3 V 1.3 V
tPLH tPHL
1.3 V 1.3 V
Q
tPHL tPLH
Q
1.3 V 1.3 V
Figure 2. Set and Clear to Output Delays,

Set and Clear Pulse Widths

5-3
SN54/74LS75
4-BIT D LATCH SN54/74LS77
The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as tem-
porary storage for binary information between processing units and input /out-
put or indicator units. Information present at a data (D) input is transferred to
the Q output when the Enable is HIGH and the Q output will follow the data
input as long as the Enable remains HIGH. When the Enable goes LOW, the
information (that was present at the data input at the time the transition oc-
curred) is retained at the Q output until the Enable is permitted to go HIGH. 4-BIT D LATCH
The SN54 / 74LS75 features complementary Q and Q output from a 4-bit
LOW POWER SCHOTTKY
latch and is available in the 16-pin packages. For higher component density
applications the SN54 / 74LS77 4-bit latch is available in the 14-pin package
with Q outputs omitted.
CONNECTION DIAGRAMS DIP (TOP VIEW)
Q0 Q1 Q1 E0–1 GND Q2 Q2 Q3 J SUFFIX

CERAMIC
16 15 14 13 12 11 10 9
CASE 620-09
16
1
SN54 / 74LS75
N SUFFIX
PLASTIC
16 CASE 648-08
1 2 3 4 5 6 7 8
Q0 D0 D1 E2–3 VCC D2 D3 Q3 1
Q0 Q1 E0–1 GND NC Q2 Q3
D SUFFIX
14 13 12 11 10 9 8
SOIC
16
1 CASE 751B-03
SN54 / 74LS77
J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
14
D0 D1 E2–3 VCC D2 D3 NC 1

HIGH LOW
N SUFFIX
D1–D4 Data Inputs 0.5 U.L. 0.25 U.L.
PLASTIC
E0–1 Enable Input Latches 0, 1 2.0 U.L. 1.0 U.L.
14 CASE 646-06
E2–3 Enable Input Latches 2, 3 2.0 U.L. 1.0 U.L.
Q1–Q4 Latch Outputs (Note b) 10 U.L. 5 (2.5) U.L. 1
Q1–Q4 Complimentary Latch Outputs (Note b) 10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 Unit Load (U.L.) = 40 µA HIGH. D SUFFIX
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) SOIC
Temperature Ranges. 14
1 CASE 751A-02
TRUTH TABLE
(Each latch)
tn tn + 1 NOTES:
tn = bit time before enable SN54LSXXJ Ceramic
D Q negative-going transition SN74LSXXN Plastic
H H tn+1 = bit time after enable SN74LSXXD SOIC
negative-going transition
L L

5-1
SN54/74LS75
LOGIC SYMBOLS
SN54/74LS75 SN54/74LS77
2 3 6 7 1 2 5 6
D0 D1 D2 D3 D0 D1 D2 D3
13 E0–1 12 E0–1 VCC = PIN 4
VCC = PIN 5
E2–3 E2–3 GND = PIN 11
4 GND = PIN 12 3
NC = PIN 7, 10
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q0 Q1 Q2 Q3
16 1 15 14 10 11 9 8 14 13 9 8

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs

D Input 20 µA VCC = MAX, VIN = 2.7 V

E Input 80
D Input 0.1 mA VCC = MAX, VIN = 7.0 V
E Input 0.4
D Input – 0.4
E Input –1.6
ICC Power Supply Current 12 mA VCC = MAX

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tPLH 15 27
Propagation Delay, Data to Q ns
tPHL 9.0 17
tPLH 12 20
tPHL 7.0 15 50V
VCC = 5.0
tPLH 15 27 CL = 15 pF
Propagation Delay, Enable to Q ns
tPHL 14 25
tPLH 16 30
tPHL 7.0 15

5-2
SN54/74LS77

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs

D Input 20 µA VCC = MAX, VIN = 2.7 V

E Input 80
D Input 0.1 mA VCC = MAX, VIN = 7.0 V
E Input 0.4
D Input – 0.4
E Input –1.6

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tPLH 11 19
tPHL 9.0 17 VCC = 5.0 V
tPLH 10 18 CL = 15 pF
tPHL 10 18

5-3
SN54/74LS75 D SN54/74LS77
LOGIC DIAGRAM
DATA
Q (SN54/74LS75 ONLY)
Q
ENABLE
TO OTHER LATCH

74 4.75 5.0 5.25
74 0 25 70
74 8.0
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tW Enable Pulse Width High 20 ns
ts Setup Time 20 ns VCC = 5.0
50V
th Hold Time 0 ns
AC WAVEFORMS
D 1.3 V 1.3 V
ts th
1.3 V 1.3 V 1.3 V

E
tPLH
tPLH 1.3 V tPHL 1.3 V

Q
tPHL
Q tPHL 1.3 V tPLH 1.3 V
tPHL tPLH
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the
clock transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH-to-LOW that the logic level must be
maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may
be released prior to the clock transition from HIGH-to-LOW and still be recognized.

5-4
SN54/74LS85
4-BIT MAGNITUDE
COMPARATOR
The SN54 / 74LS85 is a 4-Bit Magnitude Camparator which compares two
4-bit words (A, B), each word having four Parallel Inputs (A0 – A3, B0 – B3); A3,
B3 being the most significant inputs. Operation is not restricted to binary 4-BIT MAGNITUDE
codes, the device will work with any monotonic code. Three Outputs are COMPARATOR
provided: “A greater than B” (OA > B), “A less than B” (OA < B), “A equal to B”
(OA = B). Three Expander Inputs, IA > B, IA < B, IA = B, allow cascading without LOW POWER SCHOTTKY
external gates. For proper compare operation, the Expander Inputs to the
least significant position must be connected as follows: IA < B= IA > B = L, IA = B
= H. For serial (ripple) expansion, the OA > B, OA B, IA < B, and IA = B Inputs of the next most
significant comparator, as shown in Figure 1. Refer to Applications section of
data sheet for high speed method of comparing large words. J SUFFIX
The Truth Table on the following page describes the operation of the CERAMIC
CASE 620-09
SN54 / 74LS85 under all possible logic conditions. The upper 11 lines describe 16
the normal operation under all conditions that will occur in a single device or 1
in a series expansion scheme. The lower five lines describe the operation
under abnormal conditions on the cascading inputs. These conditions occur
when the parallel expansion technique is used.
• Easily Expandable N SUFFIX
• Binary or BCD Comparison PLASTIC
CASE 648-08
• OA > B, OA < B, and OA = B Outputs Available 16
1

VCC A3 B2 A2 A1 B1 A0 B0 D SUFFIX
SOIC
16 15 14 13 12 11 10 9 16
1 CASE 751B-03
NOTE:
The Flatpak version has the ORDERING INFORMATION
same pinouts (Connection
Diagram) as the Dual In-Line SN54LSXXJ Ceramic
Package. SN74LSXXN Plastic
SN74LSXXD SOIC
1 2 3 4 5 6 7 8
B3 IAB OA>B OA=B OAB OA>B 5
IA = B A = B Expander Inputs 1.5 U.L. 0.75 U.L. 2 IA B A < B, A > B, Expander Inputs 0.5 U.L. 0.25 U.L. 3 IA=B OA=B 6
OA > B A Greater Than B Output (Note b) 10 U.L. 5 (2.5) U.L.
OA < B B Greater Than A Output (Note b) 10 U.L. 5 (2.5) U.L.
VCC = PIN 16
OA = B A Equal to B Output (Note b) 10 U.L. 5 (2.5) U.L.
GND = PIN 8
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.

5-1
SN54/74LS85
LOGIC DIAGRAM
A3 (15)
B3
(1)
(5)
OA>B
(13)
A2
B2
(14)
(2)
AB
(12)
A1
B1
(11)
(7)
OAB IAB OAB3 X X X X X X H L L
A3<B3 X X X X X X L H L
A3=B3 A2>B2 X X X X X H L L
A3=B3 A2<B2 X X X X X L H L
A3=B3 A2=B2 A1>B1 X X X X H L L
A3=B3 A2=B2 A1<B1 X X X X L H L
A3=B3 A2=B2 A1=B1 A0>B0 X X X H L L
A3=B3 A2=B2 A1=B1 A0<B0 X X X L H L
A3=B3 A2=B2 A1=B1 A0=B0 H L L H L L
A3=B3 A2=B2 A1=B1 A0=B0 L H L L H L
A3=B3 A2=B2 A1=B1 A0=B0 X X H L L H
H = HIGH Level
A3=B3 A2=B2 A1=B1 A0=B0 H H L L L L
L = LOW Level
A3=B3 A2=B2 A1=B1 A0=B0 L L L H H L
X = IMMATERIAL

74 4.75 5.0 5.25
74 0 25 70
74 8.0

5-2
SN54/74LS85
A n3
A n2
A n1
B n3
B n2
B n1
An
Bn
A0 A1 A2 A3 B0 B1 B2 B3
A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3
L IA > B OA > B IA > B OA > B A>B
L IA < B SN54/74LS85 OA < B IA < B SN54/74LS85 OA < B A<B
H IA = B OA = B IA = B OA = B A=B
L = LOW LEVEL
H = HIGH LEVEL
Figure 1. Comparing Two n-Bit Words
APPLICATIONS
Figure 2 shows a high speed method of comparing two 24-bit words with only two levels of device delay. With the technique
shown in Figure 1, six levels of device delay result when comparing two 24-bit words. The parallel technique can be expanded
to any number of bits, see Table 1.
Table 1
WORD LENGTH NUMBER OF PKGS. NOTE:
1 – 4 Bits 1 The SN54/74LS85 can be used as a 5-bit comparator
only when the outputs are used to drive the A0–A3 and
5 – 24 Bits 2–6
B0–B3 inputs of another SN54/74LS85 as shown in
25 – 120 Bits 8 – 31 Figure 2 in positions #1, 2, 3, and 4.
INPUTS
(LSB) (MSB)
L IA > B OA > B A19 IA > B OA > B
L IA < B #5 OA < B B19 IA < B #1 OA < B
H IA = B OA = B L IA = B OA = B NC
INPUTS
A5 A6 A7 A8 B5 B6 B7 B8 A10 A11 A12 A13 B10 B11 B12 B13 A15 A16 A17 A18 B15 B16 B17 B18
A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3
A4 IA > B OA > B A9 IA > B OA > B A14 IA > B OA > B
B4 IA B OA > B
IA < B #6 OA < B OUTPUTS
IA = B OA = B
MSB = MOST SIGNIFICANT BIT

LSB = LEAST SIGNIFICANT BIT
L = LOW LEVEL
H = HIGH LEVEL
NC = NO CONNECTION
Figure 2. Comparison of Two 24-Bit Words

5-3
SN54/74LS85

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs
54 25
2.5 35
3.5 V VCC = MIN
MIN,, IOH = MAX,
MAX, VIN = VIH
VOH O
Output HIGH Voltage
V l

Input HIGH Current

A < B, A > B 20 µA VCC = MAX, VIN = 2.7 V
IIH Other Inputs 60
A < B, A > B 0.1
mA VCC = MAX, VIN = 7.0 V
Other Inputs 0.3
Input LOW Current
IIL A < B, A > B – 0.4 mA VCC = MAX, VIN = 0.4 V
Other Inputs – 1.2
IOS Output Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tPLH Any A or B to A < B, A > B 24 36 ns
tPHL 20 30
tPLH Any A or B to A = B 27 45 ns
tPHL 23 45
tPLH A B 14 22 ns VCC = 5.0

50V
tPHL 11 17 CL = 15 pF
tPLH A = B to A = B 13 20 ns
tPHL 13 26
tPLH A > B or A = B to A < B 14 22 ns

tPHL 11 17
AC WAVEFORMS
1.3 V 1.3 V VIN 1.3 V 1.3 V

VIN
tPHL tPLH tPHL tPLH
VOUT
1.3 V 1.3 V VOUT 1.3 V 1.3 V
Figure 3 Figure 4

5-4
SN54/74LS86
QUAD 2-INPUT
EXCLUSIVE OR GATE
QUAD 2-INPUT
EXCLUSIVE OR GATE
LOW POWER SCHOTTKY
VCC
14 13 12 11 10 9 8
J SUFFIX
CERAMIC
CASE 632-08
14
1 2 3 4 5 6 7 1
GND
N SUFFIX
PLASTIC
14 CASE 646-06
1
TRUTH TABLE
IN OUT
A B Z D SUFFIX
L L L SOIC
14
1 CASE 751A-02
L H H
H L H
H H L
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC

74 4.75 5.0 5.25
74 0 25 70
74 8.0

5-1
SN54/74LS86

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tPLH Propagation Delay, 12 23
ns
tPHL Other Input LOW 10 17 VCC = 5.0 V
tPLH Propagation Delay, 20 30 CL = 15 pF
ns
tPHL Other Input HIGH 13 22

5-2
SN54/74LS90
SN54/74LS92
DECADE COUNTER; SN54/74LS93
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
DECADE COUNTER;
The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed
4-bit ripple type counters partitioned into two sections. Each counter has a di-
vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or 4-BIT BINARY COUNTER
divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi- LOW POWER SCHOTTKY
tion on the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of
the counters have a 2-input gated Master Reset (Clear), and the LS90 also
has a 2-input gated Master Set (Preset 9).
• Low Power Consumption . . . Typically 45 mW J SUFFIX
• High Count Rates . . . Typically 42 MHz CERAMIC
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve, CASE 632-08
Binary 14
1
• Input Clamp Diodes Limit High Speed Termination Effects

HIGH LOW N SUFFIX
PLASTIC
CP0 Clock (Active LOW going edge) Input to 0.5 U.L. 1.5 U.L.
CASE 646-06
÷2 Section 14
CP1 Clock (Active LOW going edge) Input to 0.5 U.L. 2.0 U.L. 1
÷5 Section (LS90), ÷6 Section (LS92)
÷8 Section (LS93) D SUFFIX
MR1, MR2 Master Reset (Clear) Inputs 0.5 U.L. 0.25 U.L. SOIC
14
MS1, MS2 Master Set (Preset-9, LS90) Inputs 0.5 U.L. 0.25 U.L. CASE 751A-02
1
Q0 Output from ÷2 Section (Notes b & c) 10 U.L. 5 (2.5) U.L.
Q1, Q2, Q3 Outputs from ÷5 (LS90), ÷6 (LS92), 10 U.L. 5 (2.5) U.L.
÷8 (LS93) Sections (Note b)
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. SN54LSXXJ Ceramic
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74) SN74LSXXN Plastic
b. Temperature Ranges. SN74LSXXD SOIC
c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.
d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.
LOGIC SYMBOL
LS90 LS92 LS93

6 7
1 2
MS
14 CP0 14 CP0 14 CP0
1 CP1 1 CP1 1 CP1
MR Q0 Q1 Q2 Q3 MR Q0 Q1 Q2 Q3 MR Q0 Q1 Q2 Q3
1 2 1 2 1 2
2 3 12 9 8 11 6 7 12 11 9 8 2 3 12 9 8 11
VCC = PIN 5 VCC = PIN 5 VCC = PIN 5
GND = PIN 10 GND = PIN 10 GND = PIN 10
NC = PINS 4, 13 NC = PINS 2, 3, 4, 13 NC = PIN 4, 6, 7, 13

5-1
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
LOGIC DIAGRAM CONNECTION DIAGRAM

DIP (TOP VIEW)
LS90
6
MS1 CP1 1 14 CP0
MS2
7
MR1 2 13 NC
S S S S
J DQ J DQ J DQ R DQ
14 MR2 3 12 Q0
CP0 CP CP CP CP
NC 4 11 Q3
KC Q KC Q KC Q SC Q
D D D D
VCC 5 10 GND
1
CP1 MS1 6 9 Q1
2
MR1 MS2 7 8 Q2
12 9 8 11
MR2
3 Q0 Q1 Q2 Q3
NC = NO INTERNAL CONNECTION
= PIN NUMBERS NOTE:
VCC = PIN 5 The Flatpak version has the same
GND = PIN 10 pinouts (Connection Diagram) as
the Dual In-Line Package.

DIP (TOP VIEW)
LS92
CP1 1 14 CP0
NC 2 13 NC
J Q J Q J Q J Q
14
CP0 NC 3 12 Q0
CP CP CP CP
KC Q KC Q KC Q KC Q NC 4 11 Q1
D D D D
VCC 5 10 GND
1
CP1 MR1 6 9 Q2
6
MR1 12 11 9 8 MR2 7 8 Q3
MR2
7 Q0 Q1 Q2 Q3
= PIN NUMBERS NOTE:

DIP (TOP VIEW)
LS93
CP1 1 14 CP0
J Q J Q J Q J Q MR1 2 13 NC
14
CP0 CP CP CP CP
MR2 3 12 Q0
KC Q KC Q KC Q KC Q
D D D D
NC 4 11 Q3
1
CP1 VCC 5 10 GND
2
MR1 NC 6 9 Q1
12 9 8 11
MR2
3 Q0 Q1 Q2 Q3 NC 7 8 Q2
= PIN NUMBERS NC = NO INTERNAL CONNECTION

VCC = PIN 5 NOTE:
GND = PIN 10 The Flatpak version has the same
pinouts (Connection Diagram) as

5-2
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
FUNCTIONAL DESCRIPTION
The LS90, LS92, and LS93 are 4-bit ripple type Decade, C. Divide-By-Two and Divide-By-Five Counter — No external
Divide-By-Twelve, and Binary Counters respectively. Each interconnections are required. The first flip-flop is used as a
device consists of four master/slave flip-flops which are binary element for the divide-by-two function (CP0 as the
internally connected to provide a divide-by-two section and a input and Q0 as the output). The CP1 input is used to obtain
divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight binary divide-by-five operation at the Q3 output.
(LS93) section. Each section has a separate clock input which
initiates state changes of the counter on the HIGH-to-LOW
LS92
clock transition. State changes of the Q outputs do not occur
simultaneously because of internal ripple delays. Therefore, A. Modulo 12, Divide-By-Twelve Counter — The CP1 input
decoded output signals are subject to decoding spikes and must be externally connected to the Q0 output. The CP0 in-
should not be used for clocks or strobes. The Q0 output of put receives the incoming count and Q3 produces a sym-
each device is designed and specified to drive the rated metrical divide-by-twelve square wave output.
fan-out plus the CP1 input of the device. B. Divide-By-Two and Divide-By-Six Counter —No external
A gated AND asynchronous Master Reset (MR1 • MR2) is interconnections are required. The first flip-flop is used as a
provided on all counters which overrides and clocks and binary element for the divide-by-two function. The CP1 in-
resets (clears) all the flip-flops. A gated AND asynchronous put is used to obtain divide-by-three operation at the Q1
Master Set (MS1 • MS2) is provided on the LS90 which and Q2 outputs and divide-by-six operation at the Q3 out-
overrides the clocks and the MR inputs and sets the outputs to put.
nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices LS93
may be operated in various counting modes. A. 4-Bit Ripple Counter — The output Q0 must be externally
connected to input CP1. The input count pulses are applied
LS90 to input CP0. Simultaneous divisions of 2, 4, 8, and 16 are
A. BCD Decade (8421) Counter — The CP1 input must be ex- performed at the Q0, Q1, Q2, and Q3 outputs as shown in
ternally connected to the Q0 output. The CP0 input receives the truth table.
the incoming count and a BCD count sequence is pro-
B. 3-Bit Ripple Counter— The input count pulses are applied
duced.
to input CP1. Simultaneous frequency divisions of 2, 4, and
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3 8 are available at the Q1, Q2, and Q3 outputs. Independent
output must be externally connected to the CP0 input. The use of the first flip-flop is available if the reset function coin-
input count is then applied to the CP1 input and a divide-by- cides with reset of the 3-bit ripple-through counter.
ten square wave is obtained at output Q0.

5-3
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
LS90 LS92 AND LS93

MODE SELECTION MODE SELECTION
RESET / SET INPUTS OUTPUTS RESET
OUTPUTS
INPUTS
MR1 MR2 MS1 MS2 Q0 Q1 Q2 Q3
MR1 MR2 Q0 Q1 Q2 Q3
H H L X L L L L
H H X L L L L L H H L L L L
X X H H H L L H L H Count
L X L X Count H L Count
X L X L Count L L Count
L X X L Count H = HIGH Voltage Level
X L L X Count L = LOW Voltage Level
H = HIGH Voltage Level X = Don’t Care
X = Don’t Care
LS90 LS92 LS93

BCD COUNT SEQUENCE TRUTH TABLE TRUTH TABLE
OUTPUT OUTPUT OUTPUT
COUNT COUNT COUNT
Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
0 L L L L 0 L L L L 0 L L L L
1 H L L L 1 H L L L 1 H L L L
2 L H L L 2 L H L L 2 L H L L
3 H H L L 3 H H L L 3 H H L L
4 L L H L 4 L L H L 4 L L H L
5 H L H L 5 H L H L 5 H L H L
6 L H H L 6 L L L H 6 L H H L
7 H H H L 7 H L L H 7 H H H L
8 L L L H 8 L H L H 8 L L L H
9 H L L H 9 H H L H 9 H L L H
NOTE: Output Q0 is connected to Input
10 L L H H 10 L H L H
CP1 for BCD count. 11 H L H H 11 H H L H
NOTE: Output Q0 is connected to Input 12 L L H H
CP1. 13 H L H H
14 L H H H
15 H H H H
CP1.

5-4
SN54/74LS90 • SN54/74LS92 • SN54/74LS93

74 4.75 5.0 5.25
74 0 25 70
74 8.0

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs


Input LOW Current
MS, MR – 0.4
IIL CP0 – 2.4 mA VCC = MAX, VIN = 0.4 V
CP1 (LS90, LS92) – 3.2
CP1 (LS93) – 1.6

5-5
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, CL = 15 pF)

Limits
LS90 LS92 LS93
S b l
Symbol P
Parameter Min Typ Max Min Typ Max Min Typ Max U i
Unit
fMAX CP0 Input Clock Frequency 32 32 32 MHz
tPLH Propagation Delay, 10 16 10 16 10 16
ns
tPHL CP0 Input to Q0 Output 12 18 12 18 12 18
tPLH 32 48 32 48 46 70
CP0 Input to Q3 Output ns
tPHL 34 50 34 50 46 70
tPLH 10 16 10 16 10 16
tPHL 14 21 14 21 14 21
tPLH 21 32 10 16 21 32
tPHL 23 35 14 21 23 35
tPLH 21 32 21 32 34 51
tPHL 23 35 23 35 34 51
tPLH MS Input to Q0 and Q3 Outputs 20 30 ns
tPHL MS Input to Q1 and Q2 Outputs 26 40 ns
tPHL MR Input to Any Output 26 40 26 40 26 40 ns

Limits
LS90 LS92 LS93
S b l
Symbol P
Parameter Min Max Min Max Min Max U i
Unit
tW CP0 Pulse Width 15 15 15 ns
tW MS Pulse Width 15 ns
tW MR Pulse Width 15 15 15 ns
trec Recovery Time MR to CP 25 25 25 ns
RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH-to-LOW in order to recognize
and transfer HIGH data to the Q outputs
AC WAVEFORMS
*CP 1.3 V 1.3 V 1.3 V

tW
tPHL tPLH
Q 1.3 V 1.3 V
Figure 1
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.
MR & MS 1.3 V 1.3 V MS 1.3 V 1.3 V

tW trec tW trec
CP 1.3 V CP 1.3 V
tPHL tPLH
Q0 • Q3
Q 1.3 V (LS90) 1.3 V
Figure 2 Figure 3

5-6
SN54/74LS90
SN54/74LS92
DECADE COUNTER; SN54/74LS93
4-BIT BINARY COUNTER
DECADE COUNTER;
The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed
4-bit ripple type counters partitioned into two sections. Each counter has a di-
vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or 4-BIT BINARY COUNTER
divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi- LOW POWER SCHOTTKY
tion on the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of
the counters have a 2-input gated Master Reset (Clear), and the LS90 also
has a 2-input gated Master Set (Preset 9).
• Low Power Consumption . . . Typically 45 mW J SUFFIX
• High Count Rates . . . Typically 42 MHz CERAMIC
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve, CASE 632-08
Binary 14
1

HIGH LOW N SUFFIX
PLASTIC
CASE 646-06
÷2 Section 14
CP1 Clock (Active LOW going edge) Input to 0.5 U.L. 2.0 U.L. 1
÷5 Section (LS90), ÷6 Section (LS92)
÷8 Section (LS93) D SUFFIX
MR1, MR2 Master Reset (Clear) Inputs 0.5 U.L. 0.25 U.L. SOIC
14
MS1, MS2 Master Set (Preset-9, LS90) Inputs 0.5 U.L. 0.25 U.L. CASE 751A-02
1
Q0 Output from ÷2 Section (Notes b & c) 10 U.L. 5 (2.5) U.L.
Q1, Q2, Q3 Outputs from ÷5 (LS90), ÷6 (LS92), 10 U.L. 5 (2.5) U.L.
÷8 (LS93) Sections (Note b)
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. SN54LSXXJ Ceramic
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74) SN74LSXXN Plastic
b. Temperature Ranges. SN74LSXXD SOIC
c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.
d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.
LOGIC SYMBOL
LS90 LS92 LS93

6 7
1 2
MS
14 CP0 14 CP0 14 CP0
1 CP1 1 CP1 1 CP1
MR Q0 Q1 Q2 Q3 MR Q0 Q1 Q2 Q3 MR Q0 Q1 Q2 Q3
1 2 1 2 1 2
2 3 12 9 8 11 6 7 12 11 9 8 2 3 12 9 8 11
VCC = PIN 5 VCC = PIN 5 VCC = PIN 5
GND = PIN 10 GND = PIN 10 GND = PIN 10
NC = PINS 4, 13 NC = PINS 2, 3, 4, 13 NC = PIN 4, 6, 7, 13

5-1
SN54/74LS90 • SN54/74LS92 • SN54/74LS93

DIP (TOP VIEW)
LS90
6
MS1 CP1 1 14 CP0
MS2
7
MR1 2 13 NC
S S S S
J DQ J DQ J DQ R DQ
14 MR2 3 12 Q0
CP0 CP CP CP CP
NC 4 11 Q3
KC Q KC Q KC Q SC Q
D D D D
VCC 5 10 GND
1
CP1 MS1 6 9 Q1
2
MR1 MS2 7 8 Q2
12 9 8 11
MR2
3 Q0 Q1 Q2 Q3
= PIN NUMBERS NOTE:

DIP (TOP VIEW)
LS92
CP1 1 14 CP0
NC 2 13 NC
J Q J Q J Q J Q
14
CP0 NC 3 12 Q0
CP CP CP CP
KC Q KC Q KC Q KC Q NC 4 11 Q1
D D D D
VCC 5 10 GND
1
CP1 MR1 6 9 Q2
6
MR1 12 11 9 8 MR2 7 8 Q3
MR2
7 Q0 Q1 Q2 Q3
= PIN NUMBERS NOTE:

DIP (TOP VIEW)
LS93
CP1 1 14 CP0
J Q J Q J Q J Q MR1 2 13 NC
14
CP0 CP CP CP CP
MR2 3 12 Q0
KC Q KC Q KC Q KC Q
D D D D
NC 4 11 Q3
1
CP1 VCC 5 10 GND
2
MR1 NC 6 9 Q1
12 9 8 11
MR2
3 Q0 Q1 Q2 Q3 NC 7 8 Q2
= PIN NUMBERS NC = NO INTERNAL CONNECTION

VCC = PIN 5 NOTE:
GND = PIN 10 The Flatpak version has the same
pinouts (Connection Diagram) as

5-2
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
The LS90, LS92, and LS93 are 4-bit ripple type Decade, C. Divide-By-Two and Divide-By-Five Counter — No external
Divide-By-Twelve, and Binary Counters respectively. Each interconnections are required. The first flip-flop is used as a
device consists of four master/slave flip-flops which are binary element for the divide-by-two function (CP0 as the
internally connected to provide a divide-by-two section and a input and Q0 as the output). The CP1 input is used to obtain
divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight binary divide-by-five operation at the Q3 output.
(LS93) section. Each section has a separate clock input which
initiates state changes of the counter on the HIGH-to-LOW
LS92
clock transition. State changes of the Q outputs do not occur
simultaneously because of internal ripple delays. Therefore, A. Modulo 12, Divide-By-Twelve Counter — The CP1 input
decoded output signals are subject to decoding spikes and must be externally connected to the Q0 output. The CP0 in-
should not be used for clocks or strobes. The Q0 output of put receives the incoming count and Q3 produces a sym-
each device is designed and specified to drive the rated metrical divide-by-twelve square wave output.
fan-out plus the CP1 input of the device. B. Divide-By-Two and Divide-By-Six Counter —No external
A gated AND asynchronous Master Reset (MR1 • MR2) is interconnections are required. The first flip-flop is used as a
provided on all counters which overrides and clocks and binary element for the divide-by-two function. The CP1 in-
resets (clears) all the flip-flops. A gated AND asynchronous put is used to obtain divide-by-three operation at the Q1
Master Set (MS1 • MS2) is provided on the LS90 which and Q2 outputs and divide-by-six operation at the Q3 out-
overrides the clocks and the MR inputs and sets the outputs to put.
nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices LS93
may be operated in various counting modes. A. 4-Bit Ripple Counter — The output Q0 must be externally
connected to input CP1. The input count pulses are applied
LS90 to input CP0. Simultaneous divisions of 2, 4, 8, and 16 are
A. BCD Decade (8421) Counter — The CP1 input must be ex- performed at the Q0, Q1, Q2, and Q3 outputs as shown in
ternally connected to the Q0 output. The CP0 input receives the truth table.
the incoming count and a BCD count sequence is pro-
B. 3-Bit Ripple Counter— The input count pulses are applied
duced.
to input CP1. Simultaneous frequency divisions of 2, 4, and
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3 8 are available at the Q1, Q2, and Q3 outputs. Independent
output must be externally connected to the CP0 input. The use of the first flip-flop is available if the reset function coin-
input count is then applied to the CP1 input and a divide-by- cides with reset of the 3-bit ripple-through counter.
ten square wave is obtained at output Q0.

5-3
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
LS90 LS92 AND LS93

MODE SELECTION MODE SELECTION
RESET / SET INPUTS OUTPUTS RESET
OUTPUTS
INPUTS
MR1 MR2 MS1 MS2 Q0 Q1 Q2 Q3
MR1 MR2 Q0 Q1 Q2 Q3
H H L X L L L L
H H X L L L L L H H L L L L
X X H H H L L H L H Count
L X L X Count H L Count
X L X L Count L L Count
L X X L Count H = HIGH Voltage Level
X L L X Count L = LOW Voltage Level
H = HIGH Voltage Level X = Don’t Care
X = Don’t Care
LS90 LS92 LS93

BCD COUNT SEQUENCE TRUTH TABLE TRUTH TABLE
OUTPUT OUTPUT OUTPUT
COUNT COUNT COUNT
Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
0 L L L L 0 L L L L 0 L L L L
1 H L L L 1 H L L L 1 H L L L
2 L H L L 2 L H L L 2 L H L L
3 H H L L 3 H H L L 3 H H L L
4 L L H L 4 L L H L 4 L L H L
5 H L H L 5 H L H L 5 H L H L
6 L H H L 6 L L L H 6 L H H L
7 H H H L 7 H L L H 7 H H H L
8 L L L H 8 L H L H 8 L L L H
9 H L L H 9 H H L H 9 H L L H
10 L L H H 10 L H L H
CP1 for BCD count. 11 H L H H 11 H H L H
NOTE: Output Q0 is connected to Input 12 L L H H
CP1. 13 H L H H
14 L H H H
15 H H H H
CP1.

5-4
SN54/74LS90 • SN54/74LS92 • SN54/74LS93

74 4.75 5.0 5.25
74 0 25 70
74 8.0

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs


Input LOW Current
MS, MR – 0.4
IIL CP0 – 2.4 mA VCC = MAX, VIN = 0.4 V
CP1 (LS90, LS92) – 3.2
CP1 (LS93) – 1.6

5-5
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, CL = 15 pF)

Limits
LS90 LS92 LS93
S b l
Symbol P
Parameter Min Typ Max Min Typ Max Min Typ Max U i
Unit
tPLH Propagation Delay, 10 16 10 16 10 16
ns
tPHL CP0 Input to Q0 Output 12 18 12 18 12 18
tPLH 32 48 32 48 46 70
tPHL 34 50 34 50 46 70
tPLH 10 16 10 16 10 16
tPHL 14 21 14 21 14 21
tPLH 21 32 10 16 21 32
tPHL 23 35 14 21 23 35
tPLH 21 32 21 32 34 51
tPHL 23 35 23 35 34 51
tPLH MS Input to Q0 and Q3 Outputs 20 30 ns
tPHL MS Input to Q1 and Q2 Outputs 26 40 ns
tPHL MR Input to Any Output 26 40 26 40 26 40 ns

Limits
LS90 LS92 LS93
S b l
Symbol P
Parameter Min Max Min Max Min Max U i
Unit
tW MS Pulse Width 15 ns
tW MR Pulse Width 15 15 15 ns
trec Recovery Time MR to CP 25 25 25 ns
RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH-to-LOW in order to recognize
and transfer HIGH data to the Q outputs
AC WAVEFORMS
*CP 1.3 V 1.3 V 1.3 V

tW
tPHL tPLH
Q 1.3 V 1.3 V
Figure 1
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.
MR & MS 1.3 V 1.3 V MS 1.3 V 1.3 V

tW trec tW trec
CP 1.3 V CP 1.3 V
tPHL tPLH
Q0 • Q3
Q 1.3 V (LS90) 1.3 V
Figure 2 Figure 3

5-6
with Clear and Complementary Outputs
DM74LS123 Dual Retriggerable One-Shot
March 1991

Y Compensated for VCC and temperature variations
General Description Y Triggerable from CLEAR input
The DM74LS123 is a dual retriggerable monostable multivi- Y DTL, TTL compatible
brator capable of generating output pulses from a few nano-
seconds to extremely long duration up to 100% duty cycle.
Y Input clamp diodes
Each device has three inputs permitting the choice of either
leading edge or trailing edge triggering. Pin (A) is an active- Functional Description
low transition trigger input and pin (B) is an active-high tran- The basic output pulse width is determined by selection of
sition trigger input. The clear (CLR) input terminates the out- an external resistor (RX) and capacitor (CX). Once triggered,
put pulse at a predetermined time independent of the timing the basic pulse width may be extended by retriggering the
components. The clear input also serves as a trigger input gated active-low transition or active-high transition inputs or
when it is pulsed with a low level pulse transition (ß). To be reduced by use of the active-low or CLEAR input. Retrig-
obtain the best trouble free operation from this device gering to 100% duty cycle is possible by application of an
please read the operating rules as well as the NSC one-shot input pulse train whose cycle time is shorter than the output
application notes carefully and observe recommendations. cycle time such that a continuous ‘‘HIGH’’ logic state is
maintained at the ‘‘Q’’ output.
Features
Y DC triggered from active-high transition or active-low
transition inputs
Y Retriggerable to 100% duty cycle
Connection Diagram Function Table
Dual-In-Line Package Inputs Outputs

CLEAR A B Q Q
L X X L H
X H X L H
X X L L H
H L u É ß
H v H É ß
u L H É ß
H e High Logic Level
L e Low Logic Level
X e Can Be Either Low or High
u e Positive Going Transition
v e Negative Going Transition
É e A Positive Pulse
ß e A Negative Pulse
TL/F/6386 – 1
Order Number DM74LS123M or DM74LS123N
See NS Package Number M16A or N16E
C1995 National Semiconductor Corporation TL/F/6386 RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required, Note: The ‘‘Absolute Maximum Ratings’’ are those values
please contact the National Semiconductor Sales beyond which the safety of the device cannot be guaran-
Office/Distributors for availability and specifications. teed. The device should not be operated at these limits. The
Supply Voltage 7V parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
Input Voltage 7V
The ‘‘Recommended Operating Conditions’’ table will define
Operating Free Air Temperature Range 0§ C to a 70§ C the conditions for actual device operation.
Storage Temperature b 65§ C to a 150§ C
Recommended Operating Conditions

Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH High Level Input Voltage 2 V
VIL Low Level Input Voltage 0.8 V
IOH High Level Output Current b 0.4 mA
IOL Low Level Output Current 8 mA
tW Pulse Width A or B High 40
(Note 6) A or B Low 40 ns
Clear Low 40
REXT External Timing Resistor 5 260 kX
CEXT External Timing Capacitance No Restriction mF
CWIRE Wiring Capacitance
50 pF
at REXT/CEXT Terminal
TA Free Air Operating Temperature 0 70 §C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 1)
VI Input Clamp Voltage VCC e Min, II e b18 mA b 1.5 V
VOH High Level Output VCC e Min, IOH e Max
2.7 3.4 V
Voltage VIL e Max, VIH e Min
VOL Low Level Output VCC e Min, IOL e Max
0.35 0.5
Voltage VIL e Max, VIH e Min V
IOL e 4 mA, VCC e Min 0.25 0.4
II Input Current @ Max VCC e Max, VI e 7V
0.1 mA
Input Voltage
IIH High Level Input Current VCC e Max, VI e 2.7V 20 mA
IIL Low Level Input Current VCC e Max, VI e 0.4V b 0.4 mA
IOS Short Circuit VCC e Max b 20 b 100 mA
Output Current (Note 2)
ICC Supply Current VCC e Max (Notes 3,4 and 5) 12 20 mA
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Quiescent ICC is measured (after clearing) with 2.4V applied to all clear and A inputs, B inputs grounded, all outputs open, CEXT e 0.02 mF, and
REXT e 25 kX.
Note 4: ICC is measured in the triggered state with 2.4V applied to all clear and B inputs, A inputs grounded, all outputs open, CEXT e 0.02 mF, and REXT e 25 kX.
Note 5: With all outputs open and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V is applied to the clock.
Note 6: TA e 25§ C and VCC e 5V.
2
Switching Characteristics at VCC e 5V and TA e 25§ C
RL e 2 kX
From (Input) CL e 15pF CL e 15pF
Symbol Parameters Units
To (Output) CEXT e 0 pF, REXT e 5 kX CEXT e 1000 pF, REXT e 10 KX
Min Max Min Max
tPLH Propagation Delay Time
A to Q 33 ns
Low to High Level Output
B to Q 44 ns
tPHL Propagation Delay Time
A to Q 45 ns
High to Low Level Output
B to Q 56 ns
Clear to Q 45 ns
Clear to Q 27 ns
tWQ(Min) Minimum Width of Pulse
A or B to Q 200 ns
at Output Q
tW(out) Output Pulse Width A or B to Q 4 5 ms
Operating Rules
1. An external resistor (RX) and an external capacitor (CX) 3. For CX ll 1000 pF the output pulse width (TW) is de-
are required for proper operation. The value of CX may fined as follows:
vary from 0 to any necessary value. For small time con- TW e KRX CX
stants high-grade mica, glass, polypropylene, polycarbon- where [RX is in kX]
ate, or polystyrene material capacitors may be used. For
[CX is in pF]
large time constants use tantalum or special aluminum
capacitors. If the timing capacitors have leakages ap- [TW is in ns]
proaching 100 nA or if stray capacitance from either ter- K & 0.37
minal to ground is greater than 50 pF the timing equations 4. The multiplicative factor K is plotted as a function of CX
may not represent the pulse width the device generates. below for design considerations:
2. When an electrolytic capacitor is used for CX a switching
diode is often required for standard TTL one-shots to pre-
vent high inverse leakage current. This switching diode is
not needed for the ’LS123 one-shot and should not be
used. In general the use of the switching diode is not
recommended with retriggerable operation.
Furthermore, if a polarized timing capacitor is used on the
’LS123 the negative terminal of the capacitor should be
connected to the ‘‘CEXT’’ pin of the device (Figure 1 ).
TL/F/6386 – 2
FIGURE 2
TL/F/6386 – 8
FIGURE 1
3
Operating Rules (Continued)
5. For CX k 1000 pF see Figure 3 for TW vs CX family
curves with RX as a parameter:
TL/F/6386 – 7
FIGURE 7
9. Under any operating condition CX and RX must be kept
TL/F/6386 – 3 as close to the one-shot device pins as possible to mini-
FIGURE 3 mize stray capacitance, to reduce noise pick-up, and to
6. To obtain variable pulse widths by remote trimming, the reduce I-R and Ldi/dt voltage developed along their
following circuit is recommended: connecting paths. If the lead length from CX to pins (6)
and (7) or pins (14) and (15) is greater than 3 cm, for
example, the output pulse width might be quite different
from values predicted from the appropriate equations. A
non-inductive and low capacitive path is necessary to
ensure complete discharge of CX in each cycle of its
operation so that the output pulse width will be accurate.
TL/F/6386 – 4
10. The CEXT pins of this device are internally connected to
FIGURE 4 the internal ground. For optimum system performance
Note: ‘‘Rremote’’ should be as close to the device pin as possible. they should be hard wired to the system’s return ground
7. The retriggerable pulse width is calculated as shown be- plane.
low: 11. VCC and ground wiring should conform to good high-fre-
T e TW a tPLH e K c RX c CX a tPLH quency standards and practices so that switching tran-
The retriggered pulse width is equal to the pulse width sients on the VCC and ground return leads do not cause
plus a delay time period (Figure 5). interaction between one-shots. A 0.01 mF to 0.10 mF
bypass capacitor (disk ceramic or monolithic type) from
VCC to ground is necessary on each device. Further-
more, the bypass capacitor should be located as close
to the VCC-pin as space permits.
For further detailed device characteristics and output performance
please refer to the NSC one-shot application note AN-372.
TL/F/6386 – 5
FIGURE 5
8. Output pulse width variation versus VCC and tempera-
tures: Figure 6 depicts the relationship between pulse
width variation versus VCC, and Figure 7 depicts pulse
width variation versus temperatures.
TL/F/6386 – 6
FIGURE 6
4
Physical Dimensions inches (millimeters)
16-Lead Small Outline Molded Package

Order Number DM74LS123M
NS Package Number M16A
5
Physical Dimensions inches (millimeters) (Continued)
16-Lead Molded Dual-In-Line Package (N)

Order Number DM74LS123N
NS Package Number N16E
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor

Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, Kowloon
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Italiano Tel: (a49) 0-180-534 16 80 Fax: (852) 2736-9960
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
SN54/74LS125A
QUAD 3-STATE BUFFERS SN54/74LS126A
VCC E D O E D O
14 13 12 11 10 9 8
QUAD 3-STATE BUFFERS
LOW POWER SCHOTTKY
1 2 3 4 5 6 7
E D O E D O GND
LS125A J SUFFIX
CERAMIC
CASE 632-08
VCC E D O E D O 14
1
14 13 12 11 10 9 8
N SUFFIX
PLASTIC
14 CASE 646-06
1
1 2 3 4 5 6 7
E D O E D O GND
D SUFFIX
LS126A SOIC
14
1 CASE 751A-02
TRUTH TABLES
LS125A LS126A
INPUTS INPUTS
SN54LSXXXJ Ceramic
E D OUTPUT E D OUTPUT
SN74LSXXXN Plastic
L L L H L L SN74LSXXXD SOIC
L H H H H H
H X (Z) L X (Z)

X = Don’t Care
(Z) = High Impedance (off)

74 4.75 5.0 5.25
74 0 25 70
IOH Output Current — High 54 – 1.0 mA
74 – 2.6
IOL Output Current — Low 54 12 mA
74 24

5-1
SN54/74LS125A • SN54/74LS126A

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs
54 2.4 V VCC = MIN,, IOH = MAX,, VIN = VIH
74 2.4 V or VIL per Truth Table
54, 74 0.25 0.4 V IOL = 12 mA VCC = VCC MIN,

74 0.35 0.5 V IOL = 24 mA per Truth Table
IOZH Output Off Current HIGH 20 µA VCC = MAX, VOUT = 2.4 V

IOZL Output Off Current LOW – 20 µA VCC = MAX, VOUT = 0.4 V
LS125A 20 VIN = 0 V, VE = 4.5 V
ICC Power Supply Current mA VCC = MAX
LS126A 22 VIN = 0 V, VE = 0 V

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tPLH LS125A 9.0 15
tPLH Propagation
P p g i D Delay,
l y, LS126A 9.0 15
ns Fi
Figure 2
tPHL Data to Output LS125A 7.0 18
tPHL LS126A 8.0 18 VCC = 5.0
50V
CL = 45 pF
Output
p Enable Time LS125A 12 20 RL = 667 Ω
tPZH ns Figures 4
4, 5
to HIGH Level LS126A 16 25
Output
p Enable Time LS125A 15 25
tPZL ns Figures 3
3, 5
to LOW Level LS126A 21 35
Output
p Disable Time LS125A 20
tPHZ ns Figures 4
4, 5
from HIGH Level LS126A 25 VCC = 5.0
50V
CL = 5.0
5 0 pF
Output
p Disable Time LS125A 20 RL = 667 Ω
tPLZ ns FIgures 3
3, 5
from LOW Level LS126A 25

5-2
SN54/74LS125A • SN54/74LS126A
VIN VIN
1.3 V 1.3 V 1.3 V 1.3 V
tPLH tPHL tPHL tPLH
VOUT
1.3 V 1.3 V 1.3 V 1.3 V
VOUT
Figure 1 Figure 2
VE VE
1.3 V 1.3 V 1.3 V 1.3 V

VE VE
tPZL tPLZ tPZH tPHZ

> VOH
VOUT ≈ 1.3 V
1.3 V 1.3 V ≈ 1.3 V
VOUT
VOL 0.5 V
0.5 V
Figure 3 Figure 4
VCC
RL
SW1
TO OUTPUT
UNDER TEST
5 kΩ
CL SW2
Figure 5
SWITCH POSITIONS
SYMBOL SW1 SW2
tPZH Open Closed
tPZL Closed Open
tPLZ Closed Closed
tPHZ Closed Closed

5-3
SN54/74LS139
DUAL 1-OF-4 DECODER/
DEMULTIPLEXER
The LSTTL/MSI SN54/74LS139 is a high speed Dual 1-of-4 Decoder /De-
multiplexer. The device has two independent decoders, each accepting two
inputs and providing four mutually exclusive active LOW Outputs. Each
decoder has an active LOW Enable input which can be used as a data input DUAL 1-OF-4 DECODER /
for a 4-output demultiplexer. Each half of the LS139 can be used as a function DEMULTIPLEXER
generator providing all four minterms of two variables. The LS139 is
fabricated with the Schottky barrier diode process for high speed and is LOW POWER SCHOTTKY
completely compatible with all Motorola TTL families.
• Schottky Process for High Speed
• Multifunction Capability
• Two Completely Independent 1-of-4 Decoders
• Active Low Mutually Exclusive Outputs J SUFFIX
• Input Clamp Diodes Limit High Speed Termination Effects CERAMIC
• ESD > 3500 Volts
16
CASE 620-09
1
VCC Eb AOb A1b O0b O1b O2b O3b
16 15 14 13 12 11 10 9
N SUFFIX
PLASTIC
NOTE:
16 CASE 648-08
The Flatpak version
has the same pinouts 1
(Connection Diagram) as
1 2 3 4 5 6 7 8 D SUFFIX
Ea A0a A1a O0a O1a O2a O3a GND SOIC
16
1 CASE 751B-03
HIGH LOW
A0, A1 Address Inputs 0.5 U.L. 0.25 U.L. ORDERING INFORMATION
E Enable (Active LOW) Input 0.5 U.L. 0.25 U.L. SN54LSXXXJ Ceramic
O0 – O 3 Active LOW Outputs (Note b) 10 U.L. 5 (2.5) U.L. SN74LSXXXN Plastic
NOTES: SN74LSXXXD SOIC
Temperature Ranges.
LOGIC SYMBOL
LOGIC DIAGRAM
1 2 3 15 14 13
Ea A0a A1a Eb A0b A1b
1 2 3 15 14 13
E A0 A1 E A0 A1
DECODER a DECODER b
O0 O1 O2 O3 O0 O1 O2 O3
VCC = PIN 16 4 5 6 7 12 11 10 9
GND = PIN 8
= PIN NUMBERS
VCC = PIN 16
GND = PIN 8
4 5 6 7 12 11 10 9
O0a O1a O2a O3a O0b O1b O2b O3b

5-1
SN54/74LS139
The LS139 is a high speed dual 1-of-4 decoder/demultiplex- demultiplexer application.
er fabricated with the Schottky barrier diode process. The Each half of the LS139 generates all four minterms of two
device has two independent decoders, each of which accept variables. These four minterms are useful in some applica-
two binary weighted inputs (A0, A1) and provide four mutually tions, replacing multiple gate functions as shown in Fig. a, and
exclusive active LOW outputs (O0 – O3). Each decoder has an thereby reducing the number of packages required in a logic
active LOW Enable (E). When E is HIGH all outputs are forced network.
HIGH. The enable can be used as the data input for a 4-output
E E
A0 O0 A0 O0
A1 A1
TRUTH TABLE
E E
INPUTS OUTPUTS A0 O1 A0 O1
E A0 A1 O0 O1 O2 O3 A1 A1
E E
H X X H H H H
A0 O2 A0 O2
L L L L H H H A1 A1
L H L H L H H
L L H H H L H E E
A0 O3 A0 O3
L H H H H H L
A1 A1
X = Don’t Care Figure a

74 4.75 5.0 5.25
74 0 25 70
74 8.0

5-2
SN54/74LS139

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs
54 25
2.5 35
3.5 V MIN,, IOH = MAX,
VCC = MIN MAX, VIN = VIH
VOH O
Output HIGH Voltage
V l



Levels of Limits
S b l
Symbol P
Parameter Delay Min Typ Max U i
Unit T
Test C
Conditions
di i
tPLH Propagation Delay 2 13 20
ns
tPHL Address to Output 2 22 33
tPLH Propagation Delay 3 18 29 VCC = 5.0
50V
ns
tPHL Address to Output 3 25 38 CL = 15 pF
ns
tPHL Enable to Output 2 21 32
AC WAVEFORMS
1.3 V 1.3 V VIN

VIN 1.3 V 1.3 V
tPHL tPLH tPHL tPLH

VOUT
1.3 V 1.3 V VOUT 1.3 V 1.3 V
Figure 1 Figure 2

5-3
SN54/74LS151
8-INPUT MULTIPLEXER
The TTL / MSI SN54 / 74LS151 is a high speed 8-input Digital Multiplexer.
It provides, in one package, the ability to select one bit of data from up to eight
sources. The LS151 can be used as a universal function generator to
generate any logic function of four variables. Both assertion and negation
outputs are provided. 8-INPUT MULTIPLEXER
• Schottky Process for High Speed
LOW POWER SCHOTTKY
• Multifunction Capability
• On-Chip Select Logic Decoding
• Fully Buffered Complementary Outputs
J SUFFIX
CERAMIC
CASE 620-09
CONNECTION DIAGRAM DIP (TOP VIEW) 16
1
VCC I4 I5 I6 I7 S0 S1 S2
16 15 14 13 12 11 10 9
N SUFFIX
PLASTIC
16 CASE 648-08
1
1 2 3 4 5 6 7 8
I3 I2 I1 I0 Z Z E GND
D SUFFIX
SOIC
16
1 CASE 751B-03
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
PIN NAMES LOADING (Note a) SN74LSXXXD SOIC
HIGH LOW
S0 – S2 Select Inputs 0.5 U.L. 0.25 U.L.
E Enable (Active LOW) Input 0.5 U.L. 0.25 U.L. LOGIC SYMBOL
I0 – I7 Multiplexer Inputs 0.5 U.L. 0.25 U.L.
Z Multiplexer Output (Note b) 10 U.L. 5 (2.5) U.L.
Z Complementary Multiplexer Output 10 U.L. 5 (2.5) U.L. 7 4 3 2 1 15 14 13 12
(Note b)
NOTES: E I0 I1 I2 I3 I4 I5 I6 I7
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. 11 S0
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) 10 S1
Temperature Ranges. 9 S2
Z Z
6 5
VCC = PIN 16
GND = PIN 8

5-1
SN54/74LS151
LOGIC DIAGRAM
I0 I1 I2 I3 I4 I5 I6 I7
9 4 3 2 1 15 14 13 12
S2
10
S1
11
S0
7
E
VCC = PIN 16
GND = PIN 8 6 5
= PIN NUMBERS
Z Z
The LS151 is a logical implementation of a single pole, Z = E ⋅ (I0 ⋅ S0 ⋅ S1 ⋅ S2 + ⋅ I1 ⋅ S0 ⋅ S1 ⋅ S2 + I2 ⋅ S0 ⋅ S1 ⋅ S2
8-position switch with the switch position controlled by the + I3 ⋅ S0 ⋅ S1 ⋅ S2 + I4 ⋅ S0 ⋅ S1 ⋅ S2 + I5 ⋅ S0 ⋅ S1 ⋅ S2 + I6 ⋅ S0
state of three Select inputs, S0, S1, S2. Both assertion and ⋅ S1 ⋅ S2 + I7 ⋅ S0 ⋅ S1 ⋅ S2).
negation outputs are provided. The Enable input (E) is active The LS151 provides the ability, in one package, to select
LOW. When it is not activated, the negation output is HIGH from eight sources of data or control information. By proper
and the assertion output is LOW regardless of all other inputs. manipulation of the inputs, the LS151 can provide any logic
The logic function provided at the output is: function of four variables and its negation.
TRUTH TABLE
E S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 Z Z
H X X X X X X X X X X X H L
L L L L L X X X X X X X H L
L L L L H X X X X X X X L H
L L L H X L X X X X X X H L
L L L H X H X X X X X X L H
L L H L X X L X X X X X H L
L L H L X X H X X X X X L H
L L H H X X X L X X X X H L
L L H H X X X H X X X X L H
L H L L X X X X L X X X H L
L H L L X X X X H X X X L H
L H L H X X X X X L X X H L
L H L H X X X X X H X X L H
L H H L X X X X X X L X H L
L H H L X X X X X X H X L H
L H H H X X X X X X X L H L
L H H H X X X X X X X H L H
X = Don’t Care

5-2
SN54/74LS151

74 4.75 5.0 5.25
74 0 25 70
74 8.0

Limits
Symbol
S b l Parameter
P Min Typ Max Unit
U i Test
T Conditions
C di i
All Inputs
54 0.7 Guaranteed Input LOW Voltage for
74 0.8 All Inputs
54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH

IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX

Limits
Symbol
S b l Parameter
P Min Typ Max Unit
U i Test
T Conditions
C di i
tPLH Propagation Delay 27 43
ns
tPHL Select to Output Z 18 30
ns
tPHL Select to Output Z 20 32
ns
tPHL Enable to Output Z 20 32 VCC = 5.0
50V
tPLH Propagation Delay 15 24 CL = 15 pF
ns
tPHL Enable to Output Z 18 30
ns
tPHL Data to Output Z 16 26
ns
tPHL Data to Output Z 12 20
AC WAVEFORMS
VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V
tPHL tPLH tPHL tPLH
VOUT 1.3 V 1.3 V VOUT 1.3 V 1.3 V
Figure 1 Figure 2

5-3
SN54/74LS155
DUAL 1-OF-4 DECODER/ SN54/74LS156
DEMULTIPLEXER
The SN54 / 74LS155 and SN54 / 74LS156 are high speed Dual 1-of-4
Decoder/Demultiplexers. These devices have two decoders with common
2-bit Address inputs and separate gated Enable inputs. Decoder “a” has an
DUAL 1-OF-4 DECODER /
Enable gate with one active HIGH and one active LOW input. Decoder “b” has
two active LOW Enable inputs. If the Enable functions are satisfied, one DEMULTIPLEXER
output of each decoder will be LOW as selected by the address inputs. The LS156-OPEN-COLLECTOR
LS156 has open collector outputs for wired-OR (DOT-AND) decoding and LOW POWER SCHOTTKY
function generator applications.
The LS155 and LS156 are fabricated with the Schottky barrier diode
process for high speed and are completely compatible with all Motorola TTL
families.
• Schottky Process for High Speed J SUFFIX
• Multifunction Capability CERAMIC
• Common Address Inputs CASE 620-09
• True or Complement Data Demultiplexing 16
1
N SUFFIX
PLASTIC
16 CASE 648-08
VCC Eb Eb A0 O3b O2b O1b O0b
16 15 14 13 12 11 10 9
NOTE: D SUFFIX
The Flatpak version SOIC
16
has the same pinouts 1 CASE 751B-03
1 2 3 4 5 6 7 8 SN54LSXXXJ Ceramic
Ea Ea A1 O3a O2a O1a O0a GND SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL

HIGH LOW 1 2 13 3 14 15
A0, A1 Address Inputs 0.5 U.L. 0.25 U.L.

Ea, Eb Enable (Active LOW) Inputs 0.5 U.L. 0.25 U.L.
Ea Enable (Active HIGH) Input 0.5 U.L. 0.25 U.L.
E E
O0 – O3 Active LOW Outputs (Note b) 10 U.L. 5 (2.5) U.L. A0 A0
DECODER a DECODER b
NOTES: A1 A1
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. 0 1 2 3 0 1 2 3
Temperature Ranges. The HIGH level drive for the LS156 must be established by an external
resistor. 7 6 5 4 9 10 11 12
VCC = PIN 16
GND = PIN 8

5-1
SN54/74LS155 • SN54/74LS156
LOGIC DIAGRAM
Ea Ea A0 A1 Eb Eb
1 2 13 3 14 15
VCC = PIN 16
GND = PIN 8 7 6 5 4 9 10 11 12
= PIN NUMBERS
O0a O1a O2a O3a O0b O1b O2b O3b
The LS155 and LS156 are Dual 1-of-4 Decoder/Demulti- AND the minterm functions by tying outputs together. Any
plexers with common Address inputs and separate gated number of terms can be wired-AND as shown below.
Enable inputs. When enabled, each decoder section accepts
the binary weighted Address inputs (A0, A1) and provides four f = (E + A0 + A1) ⋅ (E + A0 + A1) ⋅ (E + A0 + A1) ⋅
mutually exclusive active LOW outputs (O0 – O3). If the Enable (E + A0 + A1)
requirements of each decoder are not met, all outputs of that where E = Ea + Ea; E = Eb + Eb
decoder are HIGH.
Each decoder section has a 2-input enable gate. The E E
enable gate for Decoder “a” requires one active HIGH input A0 O0 A0 O0
A1 A1
and one active LOW input (Ea•Ea). In demultiplexing applica-
tions, Decoder “a” can accept either true or complemented E E
data by using the Ea or Ea inputs respectively. The enable gate A0 O1 A0 O1
for Decoder “b” requires two active LOW inputs (Eb•Eb). The A1 A1
LS155 or LS156 can be used as a 1-of-8 Decoder/Demulti- E E
plexer by tying Ea to Eb and relabeling the common connection A0 O2 A0 O2
A1 A1
as (A2). The other Eb and Ea are connected together to form
the common enable. E E
The LS155 and LS156 can be used to generate all four A0 O3 A0 O3
minterms of two variables. These four minterms are useful in A1 A1
some applications replacing multiple gate functions as shown
in Fig. a. The LS156 has the further advantage of being able to Figure a
TRUTH TABLE
ADDRESS ENABLE “a” OUTPUT “a” ENABLE “b” OUTPUT “b”
A0 A1 Ea Ea O0 O1 O2 O3 Eb Eb O0 O1 O2 O3
X X L X H H H H H X H H H H
X X X H H H H H X H H H H H
L L H L L H H H L L L H H H
H L H L H L H H L L H L H H
L H H L H H L H L L H H L H
H H H L H H H L L L H H H L
X = Don’t Care

5-2
SN54/74LS155

74 4.75 5.0 5.25
74 0 25 70
74 8.0

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
ns Figure 1
tPHL Address, Ea or Eb to Output 19 30
tPLH Propagation Delay 17 26 VCC = 5.0

50V
ns Figure 2
tPHL Address to Output 19 30 CL = 15 pF
ns Figure 1
tPHL Ea to Output 18 27
AC WAVEFORMS
VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V
tPHL tPLH tPHL tPLH
VOUT 1.3 V 1.3 V VOUT 1.3 V 1.3 V
Figure 1 Figure 2

5-3
SN54/74LS156

74 4.75 5.0 5.25
74 0 25 70
VOH Output Voltage — High 54, 74 5.5 V
74 8.0

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs
IOH Output HIGH Current 54, 74 100 µA VCC = MIN, VOH = MAX



Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
ns Figure 1
tPHL Address, Ea or Eb to Output 34 51
50V
VCC = 5.0
ns Figure 2 CL = 15 pF
tPHL Address to Output 34 51
RL = 2.0 kΩ
ns Figure 1
tPHL Ea to Output 32 48
AC WAVEFORMS
VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V
tPHL tPLH tPHL tPLH
VOUT 1.3 V 1.3 V VOUT 1.3 V 1.3 V
Figure 1 Figure 2

5-4
SN54/74LS175
QUAD D FLIP-FLOP
The LSTTL / MSI SN54 / 74LS175 is a high speed Quad D Flip-Flop. The
device is useful for general flip-flop requirements where clock and clear inputs
are common. The information on the D inputs is stored during the LOW to
HIGH clock transition. Both true and complemented outputs of each flip-flop
are provided. A Master Reset input resets all flip-flops, independent of the
Clock or D inputs, when LOW.
QUAD D FLIP-FLOP
The LS175 is fabricated with the Schottky barrier diode process for high
speed and is completely compatible with all Motorola TTL families. LOW POWER SCHOTTKY
• Edge-Triggered D-Type Inputs
• Buffered-Positive Edge-Triggered Clock
• Clock to Output Delays of 30 ns
• Asynchronous Common Reset
• True and Complement Output
• Input Clamp Diodes Limit High Speed Termination Effects J SUFFIX
CERAMIC
CASE 620-09
VCC Q3 Q3 D3 D2 Q2 Q2 CP 1
16 15 14 13 12 11 10 9
NOTE:
N SUFFIX
The Flatpak version
has the same pinouts PLASTIC
(Connection Diagram) as 16 CASE 648-08
1
1 2 3 4 5 6 7 8
MR Q0 Q0 D0 D1 Q1 Q1 GND
D SUFFIX
SOIC
PIN NAMES LOADING (Note a) 16
1 CASE 751B-03
HIGH LOW
D0 – D3 Data Inputs 0.5 U.L. 0.25 U.L.
CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L. ORDERING INFORMATION
MR Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L.
Q0 – Q3 True Outputs (Note b) 10 U.L. 5 (2.5) U.L. SN54LSXXXJ Ceramic
Q0 – Q 3 Complemented Outputs (Note b) 10 U.L. 5 (2.5) U.L. SN74LSXXXN Plastic
SN74LSXXXD SOIC
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
LOGIC SYMBOL
LOGIC DIAGRAM 4 5 12 13
MR CP D3 D2 D1 D0
1 9 13 12 5 4
D0 D1 D2 D3
9 CP
D Q D Q D Q D Q 1 MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
CP Q CP Q CP Q CP Q
CD CD CD CD
3 2 6 7 11 10 14 15
14 15 11 10 6 7 3 2
VCC = PIN 16 VCC = PIN 16
Q3 Q3 Q2 Q2 Q1Q1 Q0 Q0
GND = PIN 8 GND = PIN 8
= PIN NUMBERS

5-1
SN54/74LS175
The LS175 consists of four edge-triggered D flip-flops with LOW input on the Master Reset (MR) will force all Q outputs
individual D inputs and Q and Q outputs. The Clock and LOW and Q outputs HIGH independent of Clock or Data
Master Reset are common. The four flip-flops will store the inputs.
state of their individual D inputs on the LOW to HIGH Clock The LS175 is useful for general logic applications where a
(CP) transition, causing individual Q and Q outputs to follow. A common Master Reset and Clock are acceptable.
TRUTH TABLE
Inputs (t = n, MR = H) Outputs (t = n+1) Note 1
D Q Q
L L H
H H L
Note 1: t = n + 1 indicates conditions after next clock.

74 4.75 5.0 5.25
74 0 25 70
74 8.0

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



5-2
SN54/74LS175

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
fMAX Maximum Input Clock Frequency 30 40 MHz
tPLH 20 30
Propagation Delay, MR to Output ns VCC = 5.0
50V
tPHL 20 30
CL = 15 pF
tPLH 13 25
Propagation Delay, Clock to Output ns
tPHL 16 25

Limits
S b l
Symbol P
Unit T
Test C di i
Conditions
tW Clock or MR Pulse Width 20 ns
ts Data Setup Time 20 ns
VCC = 5
5.0
0V
th Data Hold Time 5.0 ns
trec Recovery Time 25 ns
AC WAVEFORMS
1/fmax
tw
CP 1.3 V 1.3 V tW
ts(H) t MR 1.3 V 1.3 V
th(H) s(L) th(L)
trec
D * 1.3 V 1.3 V 1.3 V 1.3 V
CP
tPLH tPHL tPHL
Q
Q 1.3 V 1.3 V 1.3 V 1.3 V
tPHL tPLH tPLH
Q 1.3 V 1.3 V
Q 1.3 V 1.3 V
*The shaded areas indicate when the input is permitted to

*change for predictable output performance.
Figure 1. Clock to Output Delays, Clock Pulse Width, Figure 2. Master Reset to Output Delay, Master Reset
Frequency, Setup and Hold Times Data to Clock Pulse Width, and Master Reset Recovery Time
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required nition. A negative HOLD TIME indicates that the correct logic
for the correct logic level to be present at the logic input prior to level may be released prior to the clock transition from LOW to
the clock transition from LOW to HIGH in order to be recog- HIGH and still be recognized.
nized and transferred to the outputs.
RECOVERY TIME (trec) — is defined as the minimum time
HOLD TIME (th) — is defined as the minimum time following required between the end of the reset pulse and the clock
the clock transition from LOW to HIGH that the logic level must transition from LOW to HIGH in order to recognize and transfer
be maintained at the input in order to ensure continued recog- HIGH Data to the Q outputs.

5-3
SN54/74LS175
QUAD D FLIP-FLOP
The LSTTL / MSI SN54 / 74LS175 is a high speed Quad D Flip-Flop. The
device is useful for general flip-flop requirements where clock and clear inputs
are common. The information on the D inputs is stored during the LOW to
HIGH clock transition. Both true and complemented outputs of each flip-flop
are provided. A Master Reset input resets all flip-flops, independent of the
Clock or D inputs, when LOW.
QUAD D FLIP-FLOP
The LS175 is fabricated with the Schottky barrier diode process for high
speed and is completely compatible with all Motorola TTL families. LOW POWER SCHOTTKY
• Edge-Triggered D-Type Inputs
• Buffered-Positive Edge-Triggered Clock
• Clock to Output Delays of 30 ns
• Asynchronous Common Reset
• True and Complement Output
CERAMIC
CASE 620-09
VCC Q3 Q3 D3 D2 Q2 Q2 CP 1
16 15 14 13 12 11 10 9
NOTE:
N SUFFIX
The Flatpak version
(Connection Diagram) as 16 CASE 648-08
1
1 2 3 4 5 6 7 8
MR Q0 Q0 D0 D1 Q1 Q1 GND
D SUFFIX
SOIC
PIN NAMES LOADING (Note a) 16
1 CASE 751B-03
HIGH LOW
CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L. ORDERING INFORMATION
MR Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L.
Q0 – Q3 True Outputs (Note b) 10 U.L. 5 (2.5) U.L. SN54LSXXXJ Ceramic
Q0 – Q 3 Complemented Outputs (Note b) 10 U.L. 5 (2.5) U.L. SN74LSXXXN Plastic
SN74LSXXXD SOIC
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
LOGIC SYMBOL
LOGIC DIAGRAM 4 5 12 13
MR CP D3 D2 D1 D0
1 9 13 12 5 4
D0 D1 D2 D3
9 CP
D Q D Q D Q D Q 1 MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
CP Q CP Q CP Q CP Q
CD CD CD CD
3 2 6 7 11 10 14 15
14 15 11 10 6 7 3 2
VCC = PIN 16 VCC = PIN 16
Q3 Q3 Q2 Q2 Q1Q1 Q0 Q0
GND = PIN 8 GND = PIN 8
= PIN NUMBERS

5-1
SN54/74LS175
The LS175 consists of four edge-triggered D flip-flops with LOW input on the Master Reset (MR) will force all Q outputs
individual D inputs and Q and Q outputs. The Clock and LOW and Q outputs HIGH independent of Clock or Data
Master Reset are common. The four flip-flops will store the inputs.
state of their individual D inputs on the LOW to HIGH Clock The LS175 is useful for general logic applications where a
(CP) transition, causing individual Q and Q outputs to follow. A common Master Reset and Clock are acceptable.
TRUTH TABLE
Inputs (t = n, MR = H) Outputs (t = n+1) Note 1
D Q Q
L L H
H H L
Note 1: t = n + 1 indicates conditions after next clock.

74 4.75 5.0 5.25
74 0 25 70
74 8.0

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



5-2
SN54/74LS175

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
fMAX Maximum Input Clock Frequency 30 40 MHz
tPLH 20 30
Propagation Delay, MR to Output ns VCC = 5.0
50V
tPHL 20 30
CL = 15 pF
tPLH 13 25
Propagation Delay, Clock to Output ns
tPHL 16 25

Limits
S b l
Symbol P
Unit T
Test C di i
Conditions
tW Clock or MR Pulse Width 20 ns
VCC = 5
5.0
0V
AC WAVEFORMS
1/fmax
tw
CP 1.3 V 1.3 V tW
ts(H) t MR 1.3 V 1.3 V
th(H) s(L) th(L)
trec
D * 1.3 V 1.3 V 1.3 V 1.3 V
CP
tPLH tPHL tPHL
Q
Q 1.3 V 1.3 V 1.3 V 1.3 V
tPHL tPLH tPLH
Q 1.3 V 1.3 V
Q 1.3 V 1.3 V

SETUP TIME (ts) — is defined as the minimum time required nition. A negative HOLD TIME indicates that the correct logic
for the correct logic level to be present at the logic input prior to level may be released prior to the clock transition from LOW to
the clock transition from LOW to HIGH in order to be recog- HIGH and still be recognized.
the clock transition from LOW to HIGH that the logic level must transition from LOW to HIGH in order to recognize and transfer
be maintained at the input in order to ensure continued recog- HIGH Data to the Q outputs.

5-3
SN54/74LS192
SN54/74LS193
PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT BINARY PRESETTABLE BCD / DECADE
UP/DOWN COUNTER UP/ DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/ DOWN COUNTER
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the
SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate LOW POWER SCHOTTKY
Count Up and Count Down Clocks are used and in either counting mode the
circuits operate synchronously. The outputs change state synchronous with
the LOW-to-HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are
provided which are used as the clocks for a subsequent stages without extra J SUFFIX
logic, thus simplifying multistage counter designs. Individual preset inputs CERAMIC
allow the circuits to be used as programmable counters. Both the Parallel CASE 620-09
16
Load (PL) and the Master Reset (MR) inputs asynchronously override the 1
clocks.
• Low Power . . . 95 mW Typical Dissipation
• High Speed . . . 40 MHz Typical Count Frequency
• Synchronous Counting N SUFFIX
• Asynchronous Master Reset and Parallel Load PLASTIC
CASE 648-08
• Individual Preset Inputs 16
• Cascading Circuitry Internally Provided 1
D SUFFIX
CONNECTION DIAGRAM DIP (TOP VIEW) SOIC
16
VCC P0 MR TCD TCU PL P2 P3 1 CASE 751B-03
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version SN54LSXXXJ Ceramic
has the same pinouts SN74LSXXXN Plastic
(Connection Diagram) as SN74LSXXXD SOIC
1 2 3 4 5 6 7 8
P1 Q1 Q0 CPD CPU Q2 Q3 GND LOGIC SYMBOL
11 15 1 10 9
HIGH LOW
PL P0 P1 P2 P3
CPU Count Up Clock Pulse Input 0.5 U.L. 0.25 U.L. 5 CPU TCU 12
CPD Count Down Clock Pulse Input 0.5 U.L. 0.25 U.L.
MR Asynchronous Master Reset (Clear) Input 0.5 U.L. 0.25 U.L.
4 CPD TCD 13
PL Asynchronous Parallel Load (Active LOW) Input 0.5 U.L. 0.25 U.L.
MR Q0 Q1 Q2 Q3
Pn Parallel Data Inputs 0.5 U.L. 0.25 U.L.
Qn Flip-Flop Outputs (Note b) 10 U.L. 5 (2.5) U.L.
TCD Terminal Count Down (Borrow) Output (Note b) 10 U.L. 5 (2.5) U.L. 14 3 2 6 7
TCU Terminal Count Up (Carry) Output (Note b) 10 U.L. 5 (2.5) U.L.
VCC = PIN 16
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. GND = PIN 8

5-1
SN54/74LS192 • SN54/74LS193
STATE DIAGRAMS
0 1 2 3 4 LS192 LOGIC EQUATIONS 0 1 2 3 4

FOR TERMINAL COUNT
TCU = Q0 ⋅ Q3 ⋅ CPU
15 5 15 5
TCD = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ CPD
14 6 14 6
LS193 LOGIC EQUATIONS
FOR TERMINAL COUNT
13 7 13 7
TCU = Q0 ⋅ Q1⋅ Q2⋅ Q3 ⋅ CPU
TCD = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ CPD
12 11 10 9 8 12 11 10 9 8
COUNT UP
COUNT DOWN
LS192 LS193
LOGIC DIAGRAMS
P0 P1 P2 P3
PL 11 15 1 10 9
(LOAD)
5
CPU 12 TCU
(UP COUNT) (CARRY
OUTPUT)
SD SD SD SD
Q Q Q Q
T T T T
CD Q CD Q CD Q CD Q
13 TCD
CPD 4
(BORROW
(DOWN OUTPUT)
COUNT) 14
MR
(CLEAR) 3 2 6 7
Q0 Q1 Q2 Q3
VCC = PIN 16 LS192

GND = PIN 8
= PIN NUMBERS

5-2
SN54/74LS192 • SN54/74LS193
LOGIC DIAGRAMS (continued)
P0 P1 P2 P3
PL 11 15 1 10 9
(LOAD)
5
CPU TCU
12
(UP COUNT) (CARRY
OUTPUT)
SD SD SD SD
Q Q Q Q
T T T T
CD Q CD Q CD Q CD Q
13 TCD
CPD 4
(BORROW
(DOWN OUTPUT)
COUNT) 14
MR
(CLEAR) 3 2 6 7
Q0 Q1 Q2 Q3
LS193
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS

5-3
SN54/74LS192 • SN54/74LS193
The LS192 and LS193 are Asynchronously Presettable The Terminal Count Up (TCU) and Terminal Count Down
Decade and 4-Bit Binary Synchronous UP / DOWN (Revers- (TCD) outputs are normally HIGH. When a circuit has reached
able) Counters. The operating modes of the LS192 decade the maximum count state (9 for the LS192, 15 for the LS193),
counter and the LS193 binary counter are identical, with the the next HIGH-to-LOW transition of the Count Up Clock will
only difference being the count sequences as noted in the cause TCU to go LOW. TCU will stay LOW until CPU goes
State Diagrams. Each circuit contains four master/slave HIGH again, thus effectively repeating the Count Up Clock,
flip-flops, with internal gating and steering logic to provide but delayed by two gate delays. Similarly, the TCD output will
master reset, individual preset, count up and count down go LOW when the circuit is in the zero state and the Count
operations. Down Clock goes LOW. Since the TC outputs repeat the clock
Each flip-flop contains JK feedback from slave to master waveforms, they can be used as the clock input signals to the
such that a LOW-to-HIGH transition on its T input causes the next higher order circuit in a multistage counter.
slave, and thus the Q output to change state. Synchronous Each circuit has an asynchronous parallel load capability
switching, as opposed to ripple counting, is achieved by permitting the counter to be preset. When the Parallel Load
driving the steering gates of all stages from a common Count (PL) and the Master Reset (MR) inputs are LOW, information
Up line and a common Count Down line, thereby causing all present on the Parallel Data inputs (P0, P3) is loaded into the
state changes to be initiated simultaneously. A LOW-to-HIGH counter and appears on the outputs regardless of the
transition on the Count Up input will advance the count by one; conditions of the clock inputs. A HIGH signal on the Master
a similar transition on the Count Down input will decrease the Reset input will disable the preset gates, override both Clock
count by one. While counting with one clock input, the other inputs, and latch each Q output in the LOW state. If one of the
should be held HIGH. Otherwise, the circuit will either count by Clock inputs is LOW during and after a reset or load operation,
twos or not at all, depending on the state of the first flip-flop, the next LOW-to-HIGH transition of that Clock will be
which cannot toggle as long as either Clock input is LOW. interpreted as a legitimate signal and will be counted.
MODE SELECT TABLE

MR PL CPU CPD MODE
H X X X Reset (Asyn.)
L L X X Preset (Asyn.)
L H H H No Change
L H H Count Up
L H H Count Down
X = Don’t Care
= LOW-to-HIGH Clock Transition

5-4
SN54/74LS192 • SN54/74LS193

74 4.75 5.0 5.25
74 0 25 70
74 8.0

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
fMAX Maximum Clock Frequency 25 32 MHz
tPLH CPU Input to 17 26
ns
tPHL TCU Output 18 24
tPLH CPD Input to 16 24

ns
tPHL TCD Output 15 24 50V
VCC = 5.0
tPLH 27 38 CL = 15 pF
Clock to Q ns
tPHL 30 47
tPLH 24 40
PL to Q ns
tPHL 25 40
tPHL MR Input to Any Output 23 35 ns

5-5
SN54/74LS192 • SN54/74LS193

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tW Any Pulse Width 20 ns
VCC = 5
5.0
0V
SETUP TIME (ts) is defined as the minimum time required for tion. A negative HOLD TIME indicates that the correct logic
the correct logic level to be present at the logic input prior to the level may be released prior to the PL transition from
PL transition from LOW-to-HIGH in order to be recognized and LOW-to-HIGH and still be recognized.
transferred to the outputs.
RECOVERY TIME (trec) is defined as the minimum time
HOLD TIME (th) is defined as the minimum time following the required between the end of the reset pulse and the clock
PL transition from LOW-to-HIGH that the logic level must be transition from LOW-to-HIGH in order to recognize and
maintained at the input in order to ensure continued recogni- transfer HIGH data to the Q outputs.

5-6
SN54/74LS192 • SN54/74LS193
AC WAVEFORMS
tW
CPU or CPD 1.3 V 1.3 V
tPLH
tPHL
Q 1.3 V 1.3 V
Figure 1
CPU or CPD 1.3 V Pn 1.3 V
tPHL tPLH tPHL tPLH
TCU or TCD 1.3 V Qn 1.3 V
NOTE: PL = LOW
Figure 2 Figure 3
Pn 1.3 V
PL 1.3 V
tw
tW trec
PL 1.3 V
tPLH tPHL CPU or CPD 1.3 V
tPHL
1.3 V
Qn
Q 1.3 V
Figure 4 Figure 5
Pn 1.3 V 1.3 V
th(H) th(L)
ts(H) ts(L) MR 1.3 V
PL 1.3 V
tW trec
CPU or CPD 1.3 V

Qn Q=P Q=P
tPHL
* The shaded areas indicate when the input is permitted Q 1.3 V

* to change for predictable output performance
Figure 6 Figure 7

5-7
SN54/74LS240
SN54/74LS241
OCTAL BUFFER/LINE DRIVER SN54/74LS244
WITH 3-STATE OUTPUTS
The SN54 / 74LS240, 241 and 244 are Octal Buffers and Line Drivers
designed to be employed as memory address drivers, clock drivers and
bus-oriented transmitters/receivers which provide improved PC board OCTAL BUFFER / LINE DRIVER
density. WITH 3-STATE OUTPUTS
• Hysteresis at Inputs to Improve Noise Margins LOW POWER SCHOTTKY
• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW)
J SUFFIX
SN54 / 74LS240 CERAMIC
VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 CASE 732-03
20
20 19 18 17 16 15 14 13 12 11
1
N SUFFIX
PLASTIC
CASE 738-03
20
1
1 2 3 4 5 6 7 8 9 10
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
DW SUFFIX
SN54 / 74LS241 SOIC
20
CASE 751D-03
VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 1
20 19 18 17 16 15 14 13 12 11
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
1 2 3 4 5 6 7 8 9 10
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
SN54 / 74LS244
VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND

5-1
SN54/74LS240 • SN54/74LS241 • SN54/74LS244
TRUTH TABLES
SN54 / 74LS240 SN54 / 74LS244

INPUTS INPUTS
OUTPUT OUTPUT
1G, 2G D 1G, 2G D
L L H L L L
L H L L H H
H X (Z) H X (Z)
SN54 / 74LS241
INPUTS INPUTS
OUTPUT OUTPUT
1G D 2G D
L L L H L L
L H H H H H
H X (Z) L X (Z)
X = Immaterial
Z = HIGH Impedance

74 4.75 5.0 5.25
74 0 25 70

54 – 12 mA
74 – 15

74 24

5-2
SN54/74LS240 • SN54/74LS241 • SN54/74LS244

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs
VT+–VT– Hysteresis 0.2 0.4 V VCC = MIN

54, 74 2.4 3.4 V VCC = MIN, IOH = – 3.0 mA
54, 74 2.0 V VCC = MIN, IOH = MAX


IOS Output Short Circuit Current (Note 1) – 40 – 225 mA VCC = MAX
Total, Output HIGH 27
Total, Output LOW LS240 44

ICC A
mA VCC = MAX
LS241/244 46
Total at HIGH Z LS240 50
LS241/244 54

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tPLH Propagation Delay, Data to Output 9.0 14
ns
tPHL LS240 12 18
tPLH Propagation Delay, Data to Output 12 18 CL = 45 pF,

F
ns
tPHL LS241 / 244 12 18 RL = 667 Ω
tPZH Output Enable Time to HIGH Level 15 23 ns
tPZL Output Enable Time to LOW Level 20 30 ns
tPLZ Output Disable Time from LOW Level 15 25 ns CL = 5.0 p
pF,,
tPHZ Output Disable Time from HIGH Level 10 18 ns RL = 667 Ω

5-3
SN54/74LS240 • SN54/74LS241 • SN54/74LS244
AC WAVEFORMS
VIN 1.3 V 1.3 V

VCC
tPLH tPHL
VOUT 1.3 V 1.3 V RL
Figure 1 SW1
TO OUTPUT
UNDER TEST
VIN 1.3 V 1.3 V

tPHL tPLH 5 kΩ
VOUT 1.3 V 1.3 V CL* SW2
Figure 2
VE
1.3 V 1.3 V SWITCH POSITIONS
VE
tPZL tPLZ SYMBOL SW1 SW2
VOUT 1.3 V ≈ 1.3 V tPZH Open Closed
VOL
0.5 V tPZL Closed Open
Figure 3 tPLZ Closed Closed

tPHZ Closed Closed
Figure 5
VE
1.3 V 1.3 V
VE
tPZH tPHZ
≥VOH
VOUT 1.3 V ≈ 1.3 V
0.5 V
Figure 4

5-4
54LS244/DM74LS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers
August 1989
54LS244/DM74LS244 Octal TRI-STATEÉ

Buffers/Line Drivers/Line Receivers
Y Typical IOL (sink current)
General Description 54LS 12 mA
These buffers/line drivers are designed to improve both the 74LS 24 mA
performance and PC board density of TRI-STATE buffers/ Y Typical IOH (source current)
drivers employed as memory-address drivers, clock drivers,
54LS b 12 mA
and bus-oriented transmitters/receivers. Featuring 400 mV
74LS b 15 mA
of hysteresis at each low current PNP data line input, they Y Typical propagation delay times
provide improved noise rejection and high fanout outputs
Inverting 10.5 ns
and can be used to drive terminated lines down to 133X.
Noninverting 12 ns
Y Typical enable/disable time 18 ns
Features Y Typical power dissipation (enabled)
Y TRI-STATE outputs drive bus lines directly
Inverting 130 mW
Y PNP inputs reduce DC loading on bus lines Noninverting 135 mW
Y Hysteresis at data inputs improves noise margins
Connection Diagram
Dual-In-Line Package
TL/F/8442 – 1
Order Number 54LS244DMQB, 54LS244FMQB, 54LS244LMQB,
DM74LS244WM or DM74LS244N
See NS Package Number E20A, J20A, M20B, N20A or W20A
Function Table
Inputs Output
G A Y
L L L
L H H
H X Z
L e Low Logic Level
H e High Logic Level
X e Either Low or High Logic Level
Z e High Impedance
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation TL/F/8442 RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required, Note: The ‘‘Absolute Maximum Ratings’’ are those values
please contact the National Semiconductor Sales beyond which the safety of the device cannot be guaran-
Office/Distributors for availability and specifications. teed. The device should not be operated at these limits. The
Supply Voltage 7V parametric values defined in the ‘‘Electrical Characteristics’’
Input Voltage 7V table are not guaranteed at the absolute maximum ratings.
Operating Free Air Temperature Range The ‘‘Recommended Operating Conditions’’ table will define
54LS b 55§ C to a 125§ C the conditions for actual device operation.
DM74LS 0§ C to a 70§ C
Storage Temperature Range b 65§ C to a 150§ C
Recommended Operating Conditions

54LS244 DM74LS244
Symbol Parameter Units
Min Nom Max Min Nom Max
VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
VIL Low Level Input Voltage 0.7 0.8 V
IOH High Level Output Current b 12 b 15 mA
IOL Low Level Output Current 12 24 mA
TA Free Air Operating Temperature b 55 125 0 70 §C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 1)
VI Input Clamp Voltage VCC e Min, II e b18 mA b 1.5 V
HYS Hysteresis (VT a b VTb) VCC e Min
0.2 0.4 V
Data Inputs Only
VOH High Level Output Voltage VCC e Min, VIH e Min DM74
2.7
VIL e Max, IOH e b1 mA
VCC e Min, VIH e Min 54LS/DM74
2.4 3.4 V
VIL e Max, IOH e b3 mA
VCC e Min, VIH e Min 54LS/DM74
2
VIL e 0.5V, IOH e Max
VOL Low Level Output Voltage VCC e Min IOL e 12 mA 54LS/DM74 0.4
VIL e Max V
IOL e Max DM74 0.5
VIH e Min
IOZH Off-State Output Current, VCC e Max VO e 2.7V
20 mA
High Level Voltage Applied VIL e Max
VIH e Min
IOZL Off-State Output Current, VO e 0.4V
b 20 mA
Low Level Voltage Applied
II Input Current at Maximum VCC e Max VI e 7V (DM74)
0.1 mA
Input Voltage VI e 10V (54LS)
IIH High Level Input Current VCC e Max VI e 2.7V 20 mA
IIL Low Level Input Current VCC e Max VI e 0.4V b 0.5 b 200 mA
54LS b 50
IOS Short Circuit Output Current VCC e Max (Note 2) b 225 mA
DM74 b 40
ICC Supply Current VCC e Max, Outputs High 13 23

Outputs Open Outputs Low 27 46 mA
Outputs Disabled 32 54
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2
Switching Characteristics at VCC e 5V, TA e 25§ C (see Section 1 for Test Waveforms and Output Load)
Symbol Parameter Conditions 54LS Max DM74LS Max Units
tPLH Propagation Delay Time CL e 45 pF
18 18 ns
Low to High Level Output RL e 667X
tPHL Propagation Delay Time CL e 45 pF
18 18 ns
High to Low Level Output RL e 667X
tPZL Output Enable Time to CL e 45 pF
30 30 ns
Low Level RL e 667X
tPZH Output Enable Time to CL e 45 pF
23 23 ns
High Level RL e 667X
tPLZ Output Disable Time CL e 5 pF
25 25 ns
from Low Level RL e 667X
tPHZ Output Disable Time CL e 5 pF
18 18 ns
from High Level RL e 667X
tPLH Propagation Delay Time CL e 150 pF
21 ns
Low to High Level Output RL e 667X
tPHL Propagation Delay Time CL e 150 pF
22 ns
High to Low Level Output RL e 667X
tPZL Output Enable Time to CL e 150 pF
33 ns
Low Level RL e 667X
tPZH Output Enable Time to CL e 150 pF
26 ns
High Level RL e 667X
Note: 54LS Output Load is CL e 50 pF for tPLH, tPHL, tPZL and tPZH.
3
Physical Dimensions inches (millimeters)
Ceramic Leadless Chip Carrier Package (E)

Order Number 54LS244LMQB
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (J)

Order Number 54LS244DMQB
NS Package Number J20A
4
20-Lead Wide Small Outline Molded Package (M)

Order Number DM74LS244WM
NS Package Number M20B
20-Lead Molded Dual-In-Line Package (N)

Order Number DM74LS244N
NS Package Number N20A
5
54LS244/DM74LS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers
20-Lead Ceramic Flat Package (W)

Order Number 54LS244FMQB
NS Package Number W20A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor

Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, Kowloon
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Italiano Tel: (a49) 0-180-534 16 80 Fax: (852) 2736-9960
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
SN54/74LS245
OCTAL BUS TRANSCEIVER
The SN54 / 74LS245 is an Octal Bus Transmitter/Receiver designed for
8-line asynchronous 2-way data communication between data buses.
Direction Input (DR) controls transmission of Data from bus A to bus B or bus
B to bus A depending upon its logic level. The Enable input (E) can be used
to isolate the buses. OCTAL BUS TRANSCEIVER
• Hysteresis Inputs to Improve Noise Immunity
LOW POWER SCHOTTKY
• 2-Way Asynchronous Data Bus Communication
• Input Diodes Limit High-Speed Termination Effects
LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW)

J SUFFIX
VCC E B1 B2 B3 B4 B5 B6 B7 B8
CERAMIC
20 19 18 17 16 15 14 13 12 11 CASE 732-03
20
1
N SUFFIX
PLASTIC
CASE 738-03
20
1 2 3 4 5 6 7 8 9 10
1
DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
DW SUFFIX
SOIC
TRUTH TABLE 20
CASE 751D-03
1
INPUTS
OUTPUT
E DIR
L L Bus B Data to Bus A
L H Bus A Data to Bus B
H X Isolation SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
L = LOW Voltage Level SN74LSXXXDW SOIC
X = Immaterial

74 4.75 5.0 5.25
74 0 25 70

54 – 12 mA
74 – 15

74 24

5-1
SN54/74LS245

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs
VT+–VT– Hysteresis 0.2 0.4 V VCC = MIN

54, 74 2.4 3.4 V VCC = MIN, IOH = – 3.0 mA
54, 74 2.0 V VCC = MIN, IOH = MAX


A or B, DR or E 20 µA VCC = MAX, VIN = 2.7 V
IIH I
Input HIGH Current
C DR or E 0.1 mA VCC = MAX, VIN = 7.0 V
A or B 0.1 mA VCC = MAX, VIN = 5.5 V
IOS Output Short Circuit Current (Note 1) – 40 – 225 mA VCC = MAX
Total, Output HIGH 70
ICC mA VCC = MAX
Total, Output LOW 90
Total at HIGH Z 95
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, TRISE / TFALL ≤ 6.0 ns)

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tPLH 8.0 12
Propagation Delay, Data to Output ns
tPHL 8.0 12
CL = 45 pF,
tPZH Output Enable Time to HIGH Level 25 40 ns RL = 667 Ω
tPZL Output Enable Time to LOW Level 27 40 ns
tPLZ Output Disable Time from LOW Level 15 25 ns CL = 5.0 p
pF,,
tPHZ Output Disable Time from HIGH Level 15 25 ns RL = 667 Ω

5-2
SN54/74LS273
OCTAL D FLIP-FLOP WITH CLEAR
The SN54 / 74LS273 is a high-speed 8-Bit Register. The register consists of
eight D-Type Flip-Flops with a Common Clock and an asynchronous active
LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3
inch lead spacing.
• 8-Bit High Speed Register OCTAL D FLIP-FLOP
• Parallel Register WITH CLEAR
• Common Clock and Master Reset
LOW POWER SCHOTTKY

VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
20 19 18 17 16 15 14 13 12 11
J SUFFIX
CERAMIC
CASE 732-03
20
1
1 2 3 4 5 6 7 8 9 10 N SUFFIX
MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND PLASTIC
CASE 738-03
20
1
HIGH LOW
CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L.
D0 – D7 Data Inputs 0.5 U.L. 0.25 U.L. DW SUFFIX
MR Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L. SOIC
20
CASE 751D-03
Q0 – Q7 Register Outputs (Note b) 10 U.L. 5 (2.5) U.L. 1
NOTES:
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
TRUTH TABLE SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
MR CP Dx Qx
SN74LSXXXDW SOIC
L X X L
H H H
H L L
H = HIGH Logic Level
L = LOW Logic Level
X = Immaterial
LOGIC DIAGRAM 3 4 7 8 13 14 17 18
11 D0 D1 D2 D3 D4 D5 D6 D7
CP
CP D CP D CP D CP D CP D CP D CP D CP D
1 CD Q CD Q CD Q CD Q CD Q CD Q CD Q CD Q
MR
VCC = PIN 20
GND = PIN 10
= PIN NUMBERS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19

5-1
SN54/74LS273
The SN54 / 74LS273 is an 8-Bit Parallel Register with a independent of the other inputs. Information meeting the setup
common Clock and common Master Reset. and hold time requirements of the D inputs is transferred to the
When the MR input is LOW, the Q outputs are LOW, Q outputs on the LOW-to-HIGH transition of the clock input.

74 4.75 5.0 5.25
74 0 25 70
74 8.0

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
fMAX Maximum Input Clock Frequency 30 40 MHz Figure 1
tPHL Propagation Delay, MR to Q Output 18 27 ns Figure 2
tPLH 17 27
Propagation Delay, Clock to Output ns Figure 1
tPHL 18 27

5-2
SN54/74LS273

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tw Pulse Width, Clock or Clear 20 ns Figure 1
ts Data Setup Time 20 ns Figure 1
th Hold Time 5.0 ns Figure 1
trec Recovery Time 25 ns Figure 2
AC WAVEFORMS
1/f max tW
tW MR 1.3 V
CP 1.3 V 1.3 V 1.3 V 1.3 V trec
ts(H) ts(L) CP 1.3 V

th(H) th(L)
tPHL
D * 1.3 V 1.3 V 1.3 V Qn 1.3 V 1.3 V
tPLH tPLH
tPHL
Qn 1.3 V 1.3 V Qn 1.3 V 1.3 V
tPHL tPLH

DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required recognition. A negative HOLD TIME indicates that the correct
for the correct logic level to be present at the logic input prior to logic level may be released prior to the clock transition from
the clock transition from LOW-to-HIGH in order to be recog- LOW-to-HIGH and still be recognized.
the clock transition from LOW-to-HIGH that the logic level transition from LOW-to-HIGH in order to recognize and
must be maintained at the input in order to ensure continued transfer HIGH data to the Q outputs.

5-3
SN54/74LS373
OCTAL TRANSPARENT LATCH SN54/74LS374
WITH 3-STATE OUTPUTS;
OCTAL D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH
The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus
organized system applications. The flip-flops appear transparent to the data WITH 3-STATE OUTPUT
(data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW POWER SCHOTTKY
LOW, the data that meets the setup times is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state.
The SN54 / 74LS374 is a high-speed, low-power Octal D-type Flip-Flop fea-
turing separate D-type inputs for each flip-flop and 3-state outputs for bus ori-
J SUFFIX
ented applications. A buffered Clock (CP) and Output Enable (OE) is common CERAMIC
to all flip-flops. The SN54 / 74LS374 is manufactured using advanced Low CASE 732-03
Power Schottky technology and is compatible with all Motorola TTL families. 20
• Eight Latches in a Single Package 1
• 3-State Outputs for Bus Interfacing

• Hysteresis on Latch Enable N SUFFIX
• Edge-Triggered D-Type Inputs PLASTIC
• Buffered Positive Edge-Triggered Clock 20
CASE 738-03
• Hysteresis on Clock Input to Improve Noise Margin 1

DW SUFFIX
PIN NAMES LOADING (Note a) SOIC
20
HIGH LOW CASE 751D-03
1
LE Latch Enable (Active HIGH) Input 0.5 U.L. 0.25 U.L.
CP Clock (Active HIGH going edge) Input 0.5 U.L. 0.25 U.L.
OE Output Enable (Active LOW) Input 0.5 U.L. 0.25 U.L. ORDERING INFORMATION
O0 – O7 Outputs (Note b) 65 (25) U.L. 15 (7.5) U.L.
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
NOTES:
SN74LSXXXDW SOIC
a) 1 TTL Units Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
(74) Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military (54) and
65 U.L. for Commercial (74) Temperature Ranges.

SN54 / 74LS373 SN54 / 74LS374
VCC O7 D7 D6 O6 O5 D5 D4 O4 LE VCC O7 D7 D6 O6 O5 D5 D4 O4 CP
20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10 NOTE: 1 2 3 4 5 6 7 8 9 10
OE O0 D0 D1 O1 O2 D2 D3 O3 GND The Flatpak version OE O0 D0 D1 O1 O2 D2 D3 O3 GND
has the same pinouts

5-1
SN54/74LS373 • SN54/74LS374
TRUTH TABLE
LS373 LS374
Dn LE OE On Dn LE OE On
H H L H H L H
L H L L L L L
X L L Q0 X X H Z*
X X H Z*
X = Immaterial
Z = High Impedance
* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).
LOGIC DIAGRAMS
SN54LS / 74LS373 3 4 7 8 13 14 17 18
VCC = PIN 20
D0 D1 D2 D3 D4 D5 D6 D7 GND = PIN 10
= PIN NUMBERS
D D D D D D D D
LATCH Q Q Q Q Q Q Q Q
ENABLE G G G G G G G G
11
LE
OE
1
O0 O1 O2 O3 O4 O5 O6 O7
2 5 6 9 12 15 16 19
SN54LS / 74LS374
3 4 7 8 13 14 17 18
11 D0 D1 D2 D3 D4 D5 D6 D7
CP
Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
OE
1 O0 O1 O2 O3 O4 O5 O6 O7
2 5 6 9 12 15 16 19

74 4.75 5.0 5.25
74 0 25 70
74 – 2.6
74 24

5-2
SN54/74LS373 • SN54/74LS374

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



Limits
LS373 LS374
S b l
Symbol P
Parameter Min Typ Max Min Typ Max U i
Unit T
Test C
Conditions
di i
ns
tPHL Data to Output 12 18
CL = 45 pF,
pF
F
tPLH Clock or Enable 20 30 15 28 RL = 667 Ω
ns
tPHL to Output 18 30 19 28
tPZH 15 28 20 28
Output Enable Time ns
tPZL 25 36 21 28
tPHZ 12 20 12 20
Output Disable Time ns CL = 5.0 pF
tPLZ 15 25 15 25

Limits
LS373 LS374
Symbol
S b l Parameter
P Min Max Min Max Unit
U i
tW Clock Pulse Width 15 15 ns
ts Setup Time 5.0 20 ns
th Hold Time 20 0 ns
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required HOLD TIME (th) — is defined as the minimum time following
for the correct logic level to be present at the logic input prior to the LE transition from HIGH-to-LOW that the logic level must
LE transition from HIGH-to-LOW in order to be recognized and be maintained at the input in order to ensure continued
transferred to the outputs. recognition.

5-3
SN54/74LS373
AC WAVEFORMS
tW tW
LE 1.3 V
ts th
Dn
tPLH tPHL
OUTPUT
Figure 1
OE 1.3 V 1.3 V OE 1.3 V 1.3 V

tPZL tPLZ tPZH tPHZ
VOH
VOUT 1.3 V 1.3 V 1.3 V
VOUT 1.3 V
VOL 0.5 V
0.5 V
Figure 2 Figure 3
AC LOAD CIRCUIT
VCC
SWITCH POSITIONS
RL
SYMBOL SW1 SW2
tPZH Open Closed
SW1
tPZL Closed Open
tPLZ Closed Closed
TO OUTPUT
UNDER TEST tPHZ Closed Closed
5.0 kΩ
CL* SW2
* Includes Jig and Probe Capacitance.
Figure 4

5-4
SN54/74LS374
AC WAVEFORMS
tWH tWL
OE 1.3 V 1.3 V
CP 1.3 V 1.3 V 1.3 V
ts th tPZL tPLZ
Dn 1.3 V VOUT 1.3 V ≈ 1.3 V

VOL
tPLH tPHL
0.5 V
OUTPUT 1.3 V 1.3 V Figure 6
Figure 5
OE 1.3 V 1.3 V
tPZH tPHZ
≥ VOH
VOUT 1.3 V ≈ 1.3 V
0.5 V
Figure 7
AC LOAD CIRCUIT
VCC
SWITCH POSITIONS
RL
SYMBOL SW1 SW2
tPZH Open Closed
SW1
tPZL Closed Open
tPLZ Closed Closed
TO OUTPUT
5.0 kΩ
CL* SW2
Figure 8

5-5
SN54/74LS373
OCTAL TRANSPARENT LATCH SN54/74LS374
WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH
The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus
organized system applications. The flip-flops appear transparent to the data WITH 3-STATE OUTPUT
(data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW POWER SCHOTTKY
LOW, the data that meets the setup times is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state.
The SN54 / 74LS374 is a high-speed, low-power Octal D-type Flip-Flop fea-
turing separate D-type inputs for each flip-flop and 3-state outputs for bus ori-
J SUFFIX
ented applications. A buffered Clock (CP) and Output Enable (OE) is common CERAMIC
to all flip-flops. The SN54 / 74LS374 is manufactured using advanced Low CASE 732-03
Power Schottky technology and is compatible with all Motorola TTL families. 20
• Eight Latches in a Single Package 1
• 3-State Outputs for Bus Interfacing

• Hysteresis on Latch Enable N SUFFIX
• Edge-Triggered D-Type Inputs PLASTIC
• Buffered Positive Edge-Triggered Clock 20
CASE 738-03
• Hysteresis on Clock Input to Improve Noise Margin 1

DW SUFFIX
PIN NAMES LOADING (Note a) SOIC
20
HIGH LOW CASE 751D-03
1
LE Latch Enable (Active HIGH) Input 0.5 U.L. 0.25 U.L.
CP Clock (Active HIGH going edge) Input 0.5 U.L. 0.25 U.L.
OE Output Enable (Active LOW) Input 0.5 U.L. 0.25 U.L. ORDERING INFORMATION
O0 – O7 Outputs (Note b) 65 (25) U.L. 15 (7.5) U.L.
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
NOTES:
SN74LSXXXDW SOIC
a) 1 TTL Units Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
(74) Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military (54) and
65 U.L. for Commercial (74) Temperature Ranges.

SN54 / 74LS373 SN54 / 74LS374
VCC O7 D7 D6 O6 O5 D5 D4 O4 LE VCC O7 D7 D6 O6 O5 D5 D4 O4 CP
20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10 NOTE: 1 2 3 4 5 6 7 8 9 10
OE O0 D0 D1 O1 O2 D2 D3 O3 GND The Flatpak version OE O0 D0 D1 O1 O2 D2 D3 O3 GND
has the same pinouts

5-1
SN54/74LS373 • SN54/74LS374
TRUTH TABLE
LS373 LS374
Dn LE OE On Dn LE OE On
H H L H H L H
L H L L L L L
X L L Q0 X X H Z*
X X H Z*
X = Immaterial
Z = High Impedance
* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).
LOGIC DIAGRAMS
SN54LS / 74LS373 3 4 7 8 13 14 17 18
VCC = PIN 20
D0 D1 D2 D3 D4 D5 D6 D7 GND = PIN 10
= PIN NUMBERS
D D D D D D D D
LATCH Q Q Q Q Q Q Q Q
ENABLE G G G G G G G G
11
LE
OE
1
O0 O1 O2 O3 O4 O5 O6 O7
2 5 6 9 12 15 16 19
SN54LS / 74LS374
3 4 7 8 13 14 17 18
11 D0 D1 D2 D3 D4 D5 D6 D7
CP
Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
OE
1 O0 O1 O2 O3 O4 O5 O6 O7
2 5 6 9 12 15 16 19

74 4.75 5.0 5.25
74 0 25 70
74 – 2.6
74 24

5-2
SN54/74LS373 • SN54/74LS374

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



Limits
LS373 LS374
S b l
Symbol P
Parameter Min Typ Max Min Typ Max U i
Unit T
Test C
Conditions
di i
ns
tPHL Data to Output 12 18
CL = 45 pF,
pF
F
tPLH Clock or Enable 20 30 15 28 RL = 667 Ω
ns
tPHL to Output 18 30 19 28
tPZH 15 28 20 28
Output Enable Time ns
tPZL 25 36 21 28
tPHZ 12 20 12 20
Output Disable Time ns CL = 5.0 pF
tPLZ 15 25 15 25

Limits
LS373 LS374
Symbol
S b l Parameter
P Min Max Min Max Unit
U i
tW Clock Pulse Width 15 15 ns
ts Setup Time 5.0 20 ns
th Hold Time 20 0 ns
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required HOLD TIME (th) — is defined as the minimum time following
for the correct logic level to be present at the logic input prior to the LE transition from HIGH-to-LOW that the logic level must
LE transition from HIGH-to-LOW in order to be recognized and be maintained at the input in order to ensure continued
transferred to the outputs. recognition.

5-3
SN54/74LS373
AC WAVEFORMS
tW tW
LE 1.3 V
ts th
Dn
tPLH tPHL
OUTPUT
Figure 1
OE 1.3 V 1.3 V OE 1.3 V 1.3 V

tPZL tPLZ tPZH tPHZ
VOH
VOUT 1.3 V 1.3 V 1.3 V
VOUT 1.3 V
VOL 0.5 V
0.5 V
Figure 2 Figure 3
AC LOAD CIRCUIT
VCC
SWITCH POSITIONS
RL
SYMBOL SW1 SW2
tPZH Open Closed
SW1
tPZL Closed Open
tPLZ Closed Closed
TO OUTPUT
5.0 kΩ
CL* SW2
Figure 4

5-4
SN54/74LS374
AC WAVEFORMS
tWH tWL
OE 1.3 V 1.3 V
CP 1.3 V 1.3 V 1.3 V
ts th tPZL tPLZ
Dn 1.3 V VOUT 1.3 V ≈ 1.3 V

VOL
tPLH tPHL
0.5 V
OUTPUT 1.3 V 1.3 V Figure 6
Figure 5
OE 1.3 V 1.3 V
tPZH tPHZ
≥ VOH
VOUT 1.3 V ≈ 1.3 V
0.5 V
Figure 7
AC LOAD CIRCUIT
VCC
SWITCH POSITIONS
RL
SYMBOL SW1 SW2
tPZH Open Closed
SW1
tPZL Closed Open
tPLZ Closed Closed
TO OUTPUT
5.0 kΩ
CL* SW2
Figure 8

5-5
SN54/74LS00
QUAD 2-INPUT NAND GATE
QUAD 2-INPUT NAND GATE

LOW POWER SCHOTTKY
VCC
14 13 12 11 10 9 8
J SUFFIX
CERAMIC
CASE 632-08
1 2 3 4 5 6 7 14
1
GND
N SUFFIX
PLASTIC
14 CASE 646-06
1
D SUFFIX
SOIC
14
1 CASE 751A-02
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC

74 4.75 5.0 5.25
74 0 25 70
74 8.0

5-2
SN54/74LS00

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i

5-3
SN54/74LS02
QUAD 2-INPUT NOR GATE
QUAD 2-INPUT NOR GATE

VCC
LOW POWER SCHOTTKY
14 13 12 11 10 9 8
J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
GND 14
1
N SUFFIX
PLASTIC
14 CASE 646-06
1
D SUFFIX
SOIC
14
1 CASE 751A-02
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC

74 4.75 5.0 5.25
74 0 25 70
74 8.0

5-1
SN54/74LS02

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i

5-2
SN54/74LS04
HEX INVERTER
HEX INVERTER
VCC
LOW POWER SCHOTTKY
14 13 12 11 10 9 8
J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
14
GND 1
N SUFFIX
PLASTIC
14 CASE 646-06
1
D SUFFIX
SOIC
14
1 CASE 751A-02
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC

74 4.75 5.0 5.25
74 0 25 70
74 8.0

5-1
SN54/74LS04

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



ICC Total, Output

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i

5-2
SN54/74LS08
QUAD 2-INPUT AND GATE
QUAD 2-INPUT AND GATE

VCC
LOW POWER SCHOTTKY
14 13 12 11 10 9 8
J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
14
GND 1
N SUFFIX
PLASTIC
14 CASE 646-06
1
D SUFFIX
SOIC
14
1 CASE 751A-02
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC

74 4.75 5.0 5.25
74 0 25 70
74 8.0

5-1
SN54/74LS08

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i

5-2
SN54/74LS32
QUAD 2-INPUT OR GATE
QUAD 2-INPUT OR GATE

VCC
LOW POWER SCHOTTKY
14 13 12 11 10 9 8
J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
14
GND 1
N SUFFIX
PLASTIC
14 CASE 646-06
1
D SUFFIX
SOIC
14
1 CASE 751A-02
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC

74 4.75 5.0 5.25
74 0 25 70
74 8.0

5-1
SN54/74LS32

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs



Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i

5-2
SN54/74LS74A
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL cir-
cuitry to produce high speed D-type flip-flops. Each flip-flop has individual
clear and set inputs, and also complementary Q and Q outputs. DUAL D-TYPE POSITIVE
Information at input D is transferred to the Q output on the positive-going EDGE-TRIGGERED FLIP-FLOP
edge of the clock pulse. Clock triggering occurs at a voltage level of the clock
pulse and is not directly related to the transition time of the positive-going LOW POWER SCHOTTKY
pulse. When the clock input is at either the HIGH or the LOW level, the D input
signal has no effect.
J SUFFIX
LOGIC DIAGRAM (Each Flip-Flop) CERAMIC
CASE 632-08
14
1
SET (SD)
4 (10)
Q
5 (9)
CLEAR (CD)
1 (13) N SUFFIX
PLASTIC
CLOCK 14 CASE 646-06
3 (11)
Q 1
6 (8)
D
2 (12)
D SUFFIX
SOIC
14
1 CASE 751A-02
SN54LSXXJ Ceramic
MODE SELECT — TRUTH TABLE SN74LSXXN Plastic
SN74LSXXD SOIC
INPUTS OUTPUTS
OPERATING MODE
SD SD D Q Q
Set L H X H L
LOGIC SYMBOL
Reset (Clear) H L X L H
*Undetermined L L X H H 4 10
Load “1” (Set) H H h H L
Load “0” (Reset) H H l L H
2 D SD Q 5 12 D SD Q 9
* Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
if SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum then 3 11
CP CP
we cannot guarantee to meet the minimum level for VOH.
H, h = HIGH Voltage Level 6 8
L, I = LOW Voltage Level
CD Q CD Q
X = Don’t Care
i, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time 1 13
i, h (q) = prior to the HIGH to LOW clock transition.
VCC = PIN 14
GND = PIN 7

5-1
SN54/74LS74A

74 4.75 5.0 5.25
74 0 25 70
74 8.0

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs

Input High Current

Data, Clock 20 µA VCC = MAX, VIN = 2.7 V
IIH Set, Clear 40
Data, Clock 0.1
mA VCC = MAX, VIN = 7.0 V
Set, Clear 0.2
Input LOW Current
IIL Data, Clock – 0.4 mA VCC = MAX, VIN = 0.4 V
Set, Clear – 0.8
IOS Output Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX
ICC Power Supply Current 8.0 mA VCC = MAX

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
fMAX Maximum Clock Frequency 25 33 MHz Figure 1
50V
VCC = 5.0
tPLH 13 25 ns
Clock Clear
Clock, Clear, Set to Output Figure 1 CL = 15 pF
tPHL 25 40 ns

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tW (H) Clock 25 ns Figure 1
tW (L) Clear, Set 25 ns Figure 2
Data Setup
p Time — HIGH 20 ns VCC = 5.0
50V
ts Figure 1
Data Setup Time — LOW 20 ns
th Hold Time 5.0 ns Figure 1

5-2
SN54/74LS74A
AC WAVEFORMS
D* 1.3 V 1.3 V
th(H)
th(L)
ts(L) tW(H) ts(H)
tW(L)
1.3 V 1.3 V
CP
1
fMAX
tPHL tPLH
Q
1.3 V 1.3 V
tPHL
tPLH
1.3 V 1.3 V
Q
*The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays, Data

Set-Up and Hold Times, Clock Pulse Width
tW
SET
1.3 V 1.3 V
tW
CLEAR
1.3 V 1.3 V
tPLH tPHL
1.3 V 1.3 V
Q
tPHL tPLH
Q
1.3 V 1.3 V
Figure 2. Set and Clear to Output Delays,

Set and Clear Pulse Widths

5-3
SN54/74LS138
1-OF-8 DECODER/
DEMULTIPLEXER
The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder /
Demultiplexer. This device is ideally suited for high speed bipolar memory
chip select address decoding. The multiple input enables allow parallel ex-
pansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 1-OF-8 DECODER /
decoder using four LS138s and one inverter. The LS138 is fabricated with the DEMULTIPLEXER
Schottky barrier diode process for high speed and is completely compatible
with all Motorola TTL families. LOW POWER SCHOTTKY
• Demultiplexing Capability
• Multiple Input Enable for Easy Expansion
• Typical Power Dissipation of 32 mW
• Active Low Mutually Exclusive Outputs
CERAMIC
CONNECTION DIAGRAM DIP (TOP VIEW) CASE 620-09
16
VCC O0 O1 O2 O3 O4 O5 O6 1
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version N SUFFIX
(Connection Diagram) as CASE 648-08
the Dual In-Line Package. 16
1
1 2 3 4 5 6 7 8
A0 A1 A2 E1 E2 E3 O7 GND
D SUFFIX
SOIC
HIGH LOW 16
1 CASE 751B-03
A0 – A2 Address Inputs 0.5 U.L. 0.25 U.L.
E1, E2 Enable (Active LOW) Inputs 0.5 U.L. 0.25 U.L.
E3 Enable (Active HIGH) Input 0.5 U.L. 0.25 U.L. ORDERING INFORMATION
O0 – O7 Active LOW Outputs (Note b) 10 U.L. 5 (2.5) U.L.
SN54LSXXXJ Ceramic
NOTES:
SN74LSXXXN Plastic
SN74LSXXXD SOIC
Temperature Ranges.
LOGIC DIAGRAM
LOGIC SYMBOL
A2 A1 A0 E1 E2 E3
3 2 1 4 5 6 VCC = PIN 16 1 2 3 456
GND = PIN 8
12 3
= PIN NUMBERS
A0 A1 A2 E
O0 O1 O2 O3 O4 O5 O6 O7
15 14 13 12 11 10 9 7
VCC = PIN 16
GND = PIN 8
7 9 10 11 12 13 14 15
O7 O6 O5 O4 O3 O2 O1 O0

5-1
SN54/74LS138
The LS138 is a high speed 1-of-8 Decoder/Demultiplexer pansion of the device to a 1-of-32 (5 lines to 32 lines) decoder
fabricated with the low power Schottky barrier diode process. with just four LS138s and one inverter. (See Figure a.)
The decoder accepts three binary weighted inputs (A0, A1, A2) The LS138 can be used as an 8-output demultiplexer by
and when enabled provides eight mutually exclusive active using one of the active LOW Enable inputs as the data input
LOW Outputs (O0 – O7). The LS138 features three Enable in- and the other Enable inputs as strobes. The Enable inputs
puts, two active LOW (E1, E2) and one active HIGH (E3). All which are not used must be permanently tied to their appropri-
outputs will be HIGH unless E1 and E2 are LOW and E3 is ate active HIGH or active LOW state.
HIGH. This multiple enable function allows easy parallel ex-
TRUTH TABLE
INPUTS OUTPUTS
E1 E2 E3 A0 A1 A2 O0 O1 O2 O3 O4 O5 O6 O7
H X X X X X H H H H H H H H
X H X X X X H H H H H H H H
X X L X X X H H H H H H H H
L L H L L L L H H H H H H H
L L H H L L H L H H H H H H
L L H L H L H H L H H H H H
L L H H H L H H H L H H H H
L L H L L H H H H H L H H H
L L H H L H H H H H H L H H
L L H L H H H H H H H H L H
L L H H H H H H H H H H H L
X = Don’t Care
A0
A1
A2
LS04
A3
A4
H
123 123 123 123
A0 A1 A2 E A0 A1 A2 E A0 A1 A2 E A0 A1 A2 E
LS138 LS138 LS138 LS138

O0 O1 O2 O3 O4 O5 O6 O7 O0 O1 O2 O3 O4 O5 O6 O7 O0 O1 O2 O3 O4 O5 O6 O7 O0 O1 O2 O3 O4 O5 O6 O7
O0 O31
Figure a

5-2
SN54/74LS138

74 4.75 5.0 5.25
74 0 25 70
74 8.0

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs
54 25
2.5 35
3.5 V VCC = MIN
MIN,, IOH = MAX,
MAX, VIN = VIH
VOH O
Output HIGH Voltage
V l



Levels of Limits
S b l
Symbol P
Parameter Delay Min Typ Max U i
Unit T
Test C
Conditions
di i
ns
tPHL Address to Output 2 27 41
ns
tPHL Address to Output 3 26 39 50V
VCC = 5.0
tPLH Propagation Delay E1 or E2 2 12 18 CL = 15 pF
ns
tPLH Propagation Delay E3 3 17 26
ns
AC WAVEFORMS
1.3 V 1.3 V VIN

VIN 1.3 V 1.3 V
tPHL tPLH tPHL tPLH

VOUT
1.3 V 1.3 V VOUT 1.3 V 1.3 V
Figure 1 Figure 2

5-3

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SN54/74LS05

GUARANTEED OPERATING RANGES

FAST AND LS TTL DATA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

20 µA VCC = MAX, VIN = 2.7 V

AC CHARACTERISTICS (TA = 25°C)

FAST AND LS TTL DATA

TRIPLE 3-INPUT NAND GATE

GUARANTEED OPERATING RANGES

FAST AND LS TTL DATA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

20 µA VCC = MAX, VIN = 2.7 V

Power Supply Current

AC CHARACTERISTICS (TA = 25°C)

FAST AND LS TTL DATA

TRIPLE 3-INPUT AND GATE

GUARANTEED OPERATING RANGES

FAST AND LS TTL DATA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

20 µA VCC = MAX, VIN = 2.7 V

Power Supply Current

AC CHARACTERISTICS (TA = 25°C)

FAST AND LS TTL DATA

GUARANTEED OPERATING RANGES

FAST AND LS TTL DATA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

AC CHARACTERISTICS (TA = 25°C)

VOUT 1.3 V 1.3 V

FAST AND LS TTL DATA

V O , OUTPUT VOLTAGE (VOLTS)

Figure 2. VIN versus VOUT Transfer Function

Figure 3. Threshold Voltage and Hysteresis

Figure 4. Threshold Voltage Hysteresis

FAST AND LS TTL DATA

DUAL 4-INPUT NAND GATE

GUARANTEED OPERATING RANGES

FAST AND LS TTL DATA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

20 µA VCC = MAX, VIN = 2.7 V

Power Supply Current

AC CHARACTERISTICS (TA = 25°C)

FAST AND LS TTL DATA

8-INPUT NAND GATE

GUARANTEED OPERATING RANGES

FAST AND LS TTL DATA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

20 µA VCC = MAX, VIN = 2.7 V

AC CHARACTERISTICS (TA = 25°C)

FAST AND LS TTL DATA

FAST AND LS TTL DATA

NUMERICAL DESIGNATIONS — RESULTANT DISPLAYS

FAST AND LS TTL DATA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

AC CHARACTERISTICS (TA = 25°C)

VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V

tPHL tPLH tPHL tPLH

VOUT 1.3 V 1.3 V VOUT 1.3 V 1.3 V

FAST AND LS TTL DATA

LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX