Lecture-51

Mode 1 (Strobed Input/ Output Mode)

In this mode data can be transformed to and from 8255A with
the use of handshaking signals or strobes. In mode-1, PORT A &
PORT B use the lines of PORT C to generate or accept these
handshaking signals. This mode is required for data transfer if the I/O
device is not fast enough and needs data transfer in interrupt driven
mode. The mode-1 functional conditions are as follows:
1. Both the groups - Group A & Group B can be programmed
independently in mode-1.
2. Each group contains an 8-bit data port and a 4-bit control/data
port.
3. The 8-bit data ports can be programmed as either in input
mode or in output mode independently. Both input & output are
latched.
4. The 4-bit control port is used for generating control signals &
checking status of the 8-bit data port of the group. These bits
are no longer available for I/O operations.

Strobed Input Mode:

Fig.9.12a and 9.12b illustrate an 8255 set up with Group A & Group B
both in input strobed mode i.e., mode-1.
Input control signal definitions:
The functions of the PORT C lines for Group A as determined by the
mode are as described below:
PC4 (STB A): Input strobe pulse for PORT A. When STBA is pulsed
LOW the data presented to the PORT A lines is latched into PORT A
latch.
PC5 (IBF A): Input buffer full for PORT A. This line goes HIGH after
the data is strobed into PORT A buffer by the STBA signal. The bit
becomes LOW by the rising edge of the RD input, i.e, when CPU
reads data from PORT A. This signal is used to identify when data is
written into PORT A by an external device.
PC3 (INTR A): Interrupt request for PORT A. A high on this output
can be used to interrupt the CPU when an input device is requesting
service. This signal will go HIGH after IBF A line goes HIGH, STB A
is HIGH and internal interrupt enable flag is set. The interrupt enable
flag is controlled by the bit set/reset of bit 4 of PORT C (PC4). When
this signal is set, INTR will follow IBF A. If the bit reset, INTR A will
always be low. INTR A can, therefore, be used as a maskable
interrupt to the CPU to indicate a data transfer into port A.
Group A
Mode 1 Input
8
PORT A PA7-PA0
INTE
A F/F PC4 STBA
PC5 IBFA

RD
PC3 INTRA
2
PC7, PC6 I/O

Fig.9.12a 8255A Group A Programmed in Mode-1 Strobed Input Mode

The control word to program PORT A in strobed input mode is
D7 D6 D5 D4 D3 D2 D1 D0
Mode Group A PA PCU Gp B PB PCL
1 0 1 1 1/0 X X X

PORT B may be programmed in mode-0 or in mode-1. In case PC4

bit is reset, the interrupt INTRA will be disabled. If the group A is
programmed in strobed input mode, the unused PORT C (Upper)
lines PC6 & PC7 are not used as control or status lines and, therefore,
they can be used as either input or output. Bit-3 of the control word
determines whether these lines are input or output.

Similarly, PORT C lines for Group B control are as described below:

PC2 (STB B): Input strobe pulse for PORT B.
PC1 (IBF B): Input buffer full for PORT B.
PC0 (INTR B): Interrupt request for PORT B.
Interrupt enable flag is set/reset by PC2
Group B
Mode 1 Input
8
PORT B PB7-PB0
INTE
B F/F PC2 STBB
PC1 IBFB

RD
PC0 INTRB
1
PC3 I/O

Fig.9.12b 8255A Group B Programmed in Mode-1 Strobed Input Mode

The control word to program PORT B in strobed input mode is
D7 D6 D5 D4 D3 D2 D1 D0
Mode Group A PA PCU Gp B PB PCL
1 X X X X 1 1 1/0

PORT A may be programmed in other mode. In case PC2 bit is reset,

the interrupt INTRB will be disabled. The unused PCL line PC3 can be
programmed in input or output. Bit-0 of the control word determines
whether these lines are input or output.

Strobed Input Mode:

Let us consider an input device is to be interfaced with the processor
through 8255A group A. PORT A is programmed in input mode to get
the data. The input device is generating a short duration pulse
(strobe) after putting the data on data lines. This strobe is connected
to PC4 line. Fig.9.13 shows the timing diagram under strobed input
mode. The peripheral device that is inputting the data puts the data at
PORT A pins and then sends a low strobe to indicate to the 8255A
that data is available. This strobe connected to PC4 loads the data
into the input PORT A buffer. The 8255A acknowledges receiving the
data by sending IBF HIGH back to the peripheral device. The external
device may accept this signal as an acknowledgment and makes
strobe signal back HIGH. If the external device does not have the
feature to accept the IBF signal, then on its own the device puts the
strobe signal back to HIGH. In either case, the INTR A signal is set
high provided the internal INTE flip-flop was initially set to enable the
interrupt. This INTR signal interrupts the CPU provided the concerned
interrupt of 8085A has been unmasked earlier. As and when the
processor is interrupted, the control is transferred to interrupt service
subroutine. In ISS, the processor inputs the data into a register by
generating a low RD. The INTR is reset to low disabling the interrupt
at the start of low RD. The IBF is reset to low at the rising edge of RD
or at instant of RD going high again.

STBA

IBFA

INTRA

RD

PA7-PA0 Valid Data

Fig.9.13 Timing Waveform of Group A Programmed in Mode-1 Input Mode

The same procedure is repeated as and when the device is ready

with the new data for the processor.

Example-4
In previous lecture, we discussed how an ADC0809 can be
interfaced with processor using 8255A chip programmed in mode 0.
 The ADC can also be interfaced with the processor in interrupt I/O
mode using 8255A programmed in mode 1 (Strobed input mode).
The necessary hardware is shown in fig.9.14.
In this case also, the conversion is initiated by making SOC
pulse Low High Low. The processor enters into halt state and
waits for the conversion to be over. When the conversion is over,
EOC signal becomes high. This signal is differentiated and inverted
and connected to PC4. This signal acts as a strobe for PORT A.
+5V
Vref+ Vcc

PA7-PA0 D7-D0
PORT A
8 IN0 Vin

SOC ADD A
PC5 PC0
IBFA ALE ADD B
PORT C PC4
PC0 EOC ADD C
RST6.5 PC1
OE

GATE
TM1 OUT CLK
CLK Vref- GND
1.5 MHz

Fig.9.14 Interfacing of ADC0809 using 8255A in Mode ‘1’

Since the data is already available at port lines (OE becoming

High), the data is latched in PORT A buffer. The IBF signal becomes
high and interrupt is generated. The control is transferred to ISS
where the data is read from PORT A and the control is returned to
main programme. This process is repeated every time conversion is
initiated. The waveforms during data conversion are shown in fig.915.
 ALE/ SOC

OE/ EOC

Differentiator
Output

Inverter Output
STBA

D7-D0 Digital Equivalent

Fig.9.15 Waveforms during Conversion Process in Mode-1

The flow chart for the data conversion process is shown in fig.9.16
 START

Initialize 8255A PPI

and 8253 PIT RST6.5

Load TM1 with 03H

and Trigger via PC1 Read Dats via PORT A

Unmask RST6.5 Enable Interrupt

Enable INTEA F/F Return

Using PC4

Issue Start of Conversion

Pulse via PC0

Enable Interrupt

Halt

Fig.9.16 Flow Chart of ADC0809 Interfaced using 8255A in Mode ‘1’