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of Operational Amplifiers
Willy Sansen
KULeuven, ESAT-MICAS
Leuven, Belgium
willy.sansen@esat.kuleuven.be
VDD ro
M7 Av = gm1
2
IB
if ro2 = ro4 = ro
v- v+
3 M2
M1 1
vOUT BW =
ro
2π (CL+Cn1)
2 1 CL 2
M3 M4 gm1
GBW =
VSS 2π (CL+Cn1)
gm1 IB
GBW = gm1 =
2π CL VGS1-VT
IB
v- v+ IB 1
GBWmax =
CL CL VGS1-VT 2π CL
IB = 10 µA CL = 1 pF GBWmax ≈ 10 MHz
[8]
GBW.CL
FOM = = 1000 [800]
IB MHzpF/mA
VDD gm1
M7 GBW =
2π (CL+Cn1)
IB
v- v+ gm3
M1
3 M2 fnd =
2π Cn2
vOUT
Cn2 ≈ 2CGS3+ CDB3+ CDB1
2 1 CL
≈ 4 CGS3
M3 M4
fT3
VSS fnd ≈
4
f
- 3 M2 +
M1 2x f
0o
vOUT -90o
fnd 2fnd
Cn2 2 1 gm3
M3 M4 fnd =
2π Cn2
GBW GBW
PM = 90o - arctan + arctan ≈ 85o
fnd 2 fnd
Willy Sansen 10-05 066
Single stage CMOS OTA : Design 1
IDS ? W ? L ?
gm = GBW 2π CL = 1.2 mS
VGS-VT gm
VGS-VT = 0.2 V IDS = gm 2 = 10 = 0.12 mA
W IDS Lp = Ln = 1 µm GAIN !
L = K'(VGS-VT)2 =100 Wp = 100 µm; Wn = 50 µm
Willy Sansen 10-05 067
Table of contents
RL CL cause
two poles
2 1 M6
M3 M4 Cn1 split by Cc
VSS
M7 1 : B gm1 gm6
M5 Av1 = Av2 =
5
go24 gLo6
vOUT BW =
go24
v- v+ 4
3 M2 Cc 2π Av2Cc
M1
RL CL gm1
GBW =
2π Cc
2 1 M6
M4 Cn1
gm6 1
M3 fnd ≈
2π CLn4 Cn1
1+
Cc
Willy Sansen 10-05 0611
Miller CMOS OTA : poles and zero
Cc
fd fz Pole splitting
1pF
starts at
0.1pF
fnd
Cct Cn1
f Cct ≈ ≈ 20 fF
10fF
1k 1M Hz Av2
|Av| Av0
1000 Cc = 0
but is sufficient
for Cc = 1pF
100
10 Cc = 1pF
gm6
BW fz =
1
GBW 2π Cc
0.1 f
1k 1M
Willy Sansen 10-05 0612
Table of contents
gm1
GBW = GBW = 100 MHz and CL = 2 pF
2π Cc
gm6 1
fnd ≈
2π CLn4 Cn1
1+
Cc
choosing Cc = 1 pF ?
gm1
Choose Cc ≈ 3 Cn1 GBW =
2π Cc
gm6 1
3GBW ≈
2π CLn4 1.3
gm6 CL
≈ 4
gm1 Cc
gm gm6min =
gm6
3 GBW (2π CL)
gm1
gm6min
Cc
Ccopt ≈ 4 CL
1 K’ = 20 µA/V2
0.8
Cn1 ~ gm6 VGS-VT = 0.2 V
0.6
0.4 L = 10 µm
0.2 gm6
0
0.01 0.1 1 10 100
pF Cc
Cn1 = 0.4 pF
Area gm6min =
Area M6
gm6
gm6min gm6opt ≈ 1.3 gm6min
+ 30 %
Willy Sansen 10-05 0619
Miller CMOS OTA : Design vs IDS1
Area
Area M6
Area Cc
CL
gm1
gm1 CL = α Cc α≈2
GBW =
2π Cc
Cc = β Cn1 = β CGS6 β≈3
gm6 1
fnd = fnd = γ GBW γ≈2
2π CL 1 + Cn1/Cc
CGS = kW k = 2 10 -11 F/cm
fnd gm6 1
GBW = =
γ 2π CL γ (1 + 1/ β)
gm6 1 W 17 10-5
GBW = gm =
2π kW6 α β γ (1 + 1/ β) L 1 + 2.8 104 L /VGST
fT6 W, L in cm
1 1 8.5 106
GBW = L in cm
2π L6 α β γ (1 + 1/ β) 1 + 2.8 104 L6 / VGST6
fT6 1 1.35
GBW = fT =
L 1 + 2.8 104 L / VGST
α β γ (1 + 1/ β)
L in cm
fT in MHz
GBW is not determined by CL, only by fT
fT is determined by L (and VGST) !!!
If VGST = 0.2 V, vsat takes over for L < 65 nm (If 0.5 V for L < 0.15 µm)
• Choose α β γ
• Find minimum fT6 for specified GBW
• Choose maximum channel length L6 (max. gain)
for a chosen VGS6-VT
• W6 is calculated from CL ,
and determines IDS6
• Cc is calculated from CL through α
• gm1 and IDS1 are calculated from Cc
• Noise is determined by gm1 or Cc
fT6 fT
GBW = = i (1 - e - i ) ≈ i for small i
α β γ (1 + 1/ β) fTH
2 µ kT/q
fTH =
2π L2
• Choose α β γ
• Find minimum fT6 for specified GBW
• Choose channel length L6 (max. gain), which gives fTH6
• Calculate i6
• W6 is calculated from CL ,
and determines IDST6 and IDS6
• Cc is calculated from CL through α
• gm1 and IDS1 are calculated from Cc
• Noise is determined by gm1 or Cc
Willy Sansen 10-05 0628
Design Ex. for GBW = 1 MHz & CL = 5 pF
• Choose α β γ 2 3 2
• Minimum fT6 for GBW = 1 MHz fT6 = 16 MHz
• Maximum channel length L6 L6 = 0.5 µm
gives fTH6 fTH6 = 2 GHz
• Inversion coefficient i is i = 0.008
• W6 is calculated from CL , W6 = 417 µm
and determines IDST6 (K’n = 70 µA/V2) IDST6 = 0.33 mA
and determines IDS6 IDS6 = 2.7 µA
and determines Cn1 (k = 2 fF/µm) Cn1 = 0.83 pF
• Cc is calculated from CL through α Cc = 2.5 pF
• gm1 and IDS1 are calculated from Cc IDS1 = 1.6 µA
Willy Sansen 10-05 0629
Table of contents
1. Introductory analysis
1.1 DC currents and voltages on all nodes
1.2 Small-signal parameters of all transistors
2. DC analysis
2.1 Common-mode input voltage range vs supply Voltage
2.2 Output voltage range vs supply Voltage
2.3 Maximum output current (sink and source)
VICM
3V
2V VDD
1V VICMmax
0V
VICM
-1V
-2V VSS
VICMmin
-3V
0 1V 2V ±2.5V 3V 4V VDD = |VSS|
1V
4
vOUT
0V
VOUT
-1V RL CL
-2V VSS
VOUTmin
-3V
0 1V 2V ±2.5V 3V 4V VDD = |VSS|
1 : B
VDD Switch input :
M7
M5
5
v+ > 1
3 v- > 0
IB1 4 vOUT
v- IB1 C
c
M1
RL CL ∆VOUT
SR =
2 ∆t
1 M6
M3 M4 IB1
VSS SR =
Cc
vIN vIN
t t
vOUT vOUT
VOUTmax
SR
SR SR
SR t t
SR
SR SR Tmax
≈4 VOUTmax ≈
VOUTmaxfmax 4 fmax 4
Vp VOUT
SR
2 VOUTmax ≈
4 fmax
1.5
SR = 2.2 V/µs
1
0.5
0 f
0 0.2M 0.4M 0.6M 0.8M 1MHz
VDD
IB IB SR
1:n 2π GBW
n:1
v- v+
M1 M2
= x (n+1)
M3 M4
vOUT
CL
M5 M6
VSS
Ref. Schmoock, JSSC Dec.75, 407-411
VDD
M5
IB
SRint =
IDS5 Cc
IB C
4 vOUT IDS5
c SRext = is larger !
CL
CL
gm6 CL IDS5
=4 =
1 M6 gm1 Cc IDS1
M4 2IDS1
IDS5
VSS ≈2
CL Cc
vIN
Av10 Av with CL
closed loop
f
fd fz GBW fnd
Willy Sansen 10-05 0647
Miller CMOS OTA : Noise density 1
dvin22 Cc
dvin1 2
1 4 vOUT
vin vn1
go24 Cn1 gLo6 CL
2 4/3 2 2/3
dvin1 ≈ 4kT g df dvin2 ≈ 4kT g df
m1 m6
dvin22
dvneq22 =
dvin12 |Av1|2
2/3
4kT df
Av102 gm6 gm1
Av10 =
dvneq22 go24
go24
fz =
f 2πCc
fz GBW fnd
2 4 kT
vnieq =
3 Cc
Cc = 1pF vRs= 74 µVRMS
Willy Sansen 10-05 0650
Noise density vs integrated noise
A 4/3
dvni 2
= 4kT df
gm
∞
dvni2 4kT
f 2
vni = ∫ 1 + (f/ BW) 2
=
3Cc
BW BWn 0
SR = 2.2 V/µs
VDD = 5 V
ITOT = 27 µA
OUT IB
370 MHzpF/mA
VDD
Find
gm6 IDS6 W6 Cn1 = CGS6 Cc gm1 IDS1 dvineq2 vinRMS