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A NINE-LEVEL INVERTER USING ONE VOLTAGE SOURCE AND

REDUCED COMPONENTS USING CAPACITOR BALANCING


TECHNIQUE

Mr.S.Balamurugan N.Gautham Sharma


Assistant professor PG Student
Dept of Electrical and Electronics Engineering Power Electronics and drives
Alagappa Chettiar Government College of Alagappa Chettiar Government College of
Engineering and Technology Engineering and Technology
Karaikudi Karaikudi

ABSTRACT better electromagnetic interference, and


frequency. Demerits of inverters are less
In this project, a new method of
efficiency, high cost, and high switching
nine-level inverter is proposed. The
losses. To overcome these demerits, were
inverter employs only one input source and
going to the multilevel inverter topologies.
reduced number of switches. Instead of
Multilevel inverter output voltage produce
using many voltage sources, four
a staircase output waveform, this
capacitors is used. Lower total harmonic
waveform look like a sinusoidal
distortion can be obtained with sinusoidal
waveform. The multilevel inverter output
pulse width modulation methods. In this
voltage having less number of harmonics
method capacitors are naturally balanced
compare to the conventional bipolar
by its arrangement. In previous years Multi
inverter output voltage. If the multilevel
level inverters using more than one voltage
inverter output increase to N level, the
source and power devices and also the size
harmonics reduced to the output voltage
of the device is also large. The voltage
value to zero. The multilevel inverters are
stress on power devices is relatively
mainly classified as Diode clamped Flying
reduced, which increases its range of
capacitor inverter and cascaded multi level
applications also. Self voltage balancing
inverter. The most attractive features of
ability of the capacitors is used in this nine
multilevel inverters are as follows.
level inverter is the main advantage of this
project. By using this proposed  They can generate output voltages
methodology nine levels in the output is with extremely low distortion and
obtained. The theoretical analysis, lower order harmonics.
comparison with the existing methods and  They draw input current with very
simulation results of the proposed nine- low distortion.
level inverter is also done.  They can operate with a less
INTRODUCTION switching frequency.

Basically Inverter is a device that Multilevel inverter output voltage produce


converts DC power to AC power at desired a staircase output waveform, this
output voltage because of other advantages waveform look like a sinusoidal
such as high power quality, lower order waveform. The multilevel inverter output
harmonics, lower switching losses, and voltage having less number of harmonics
compare to the conventional bipolar operation in the linear region, other than
inverter output voltage. If the multilevel for the unavoidable transition from
inverter output increase to N level, the conducting to non -conducting, makes an
harmonics reduced to the output voltage undesirable loss of efficiency and an
value to zero. unbearable rise in switching power
dissipation. To control the flow of power
Cascaded H-bridge topology has in the converter, the switches alternate
simple circuit and easy to understand. A between these two states. This happens
multilevel inverter has four main rapidly enough that the inductors and
advantages over the conventional bipolar capacitors at the input and output
inverter. First, the voltage stress on each nodes of the converter average or filter
switch is decreased due to series the switched signal. The switched
connection of the switches. Therefore, the component is attenuated and the desired dc
rated voltage and consequently the total or low frequency ac component is retained.
power of the inverter could be safely This process is called Pulse Width
increased. Second, the rate of change of Modulation, since the desired average
voltage (dv/dt) is decreased due to the value is controlled by modulating the
lower voltage swing of each switching width of the pulses.
cycle. Third, harmonic distortion is
reduced due to more output levels. The fundamental methods of pulse-
Fourth, lower acoustic noise and width modulation are divided into the
electromagnetic interference (EMI) is traditional voltage-source and current-
obtained. regulated methods. Voltage-source
methods more easily lend themselves to
The features of multilevel cascade is given digital signal processor or programmable
by logic device implementation.
 It is much more suitable to high- CLASSIFICATION OF MULTILEVEL
voltage, high-power applications INVERTER CONTROL SCHEMES
than the conventional inverters.
 It switches each device only once
per line cycle and generates a
multistep staircase voltage
waveform approaching a pure
sinusoidal output voltage by
increasing the number of levels.

MODULATION TECHNIQUES FOR


MULTILEVEL INVERTER

Mainly the power electronic


converters are operated in the “switched
mode”. This means the switches within the Fig.1.Modulation Methods
converter are always in either one of the
two states - turned off or turned on. Any
PROPOSED NINE-LEVEL INVERTER bidirectional switches, and a capacitor
TOPOLOGY voltage divider formed by C1, C2,C3 and
C4,as shown in figure. The modified H-
bridge topology is significantly
advantageous over other topologies, i.e.,
less power switch, power diodes, and less
capacitor for inverters of the same number
of levels. The power generated by the
inverter can be used for any usage.

Proper switching of the inverter can


produce nine output-voltage-levels (Vdc,
3Vdc/4, Vdc/2, Vdc/4, 0,,Vdc/4, Vdc/2, -
Fig.2.Block Diagram of proposed system 3Vdc/4,- Vdc) from the dc supply voltage.
The nine-level inverter employing The proposed inverter’s operation can be
one voltage source and two capacitors is divided into nine switching states. The
implemented. The number of switches used required nine levels of output voltage were
is also reduced. Capacitor balancing generated as follows:
technique is involved instead of using two or OPERATION OF NINE LEVELS
more voltage sources. In this proposed
system capacitor natural balancing technique Maximum positive output (Vdc): S1 is
is used. Lower THD of output voltage is ON, connecting theload positive terminal to
obtained and the voltage stress on the power Vdc, and S4 is ON, connecting the load
switches in the back-stage is relatively negative terminal to ground. All other
relieved. It makes full use of the conversion controlled switches are OFF; the voltage
of series and parallel connections of one applied to the load terminals is Vdc.
voltage source and two capacitors to realize
Three-fourth positive output (3Vdc/4):
nine output levels.
The bi-directional switch S5 is ON,
CIRCUIT TOPOLOGY connecting the load positive terminal, and
S4 is ON, connecting the load negative
terminal to ground. All other controlled
switches are OFF; the voltage applied to the
load terminals is 3Vdc/4.

Half of the positive output (Vdc/2): The


bidirectional switch S6 is ON, connecting
the load positive terminal, and S4 is ON,
connecting the load negative terminal to
round. All other controlled switches are
Fig.3.Proposed Single-Phase Nine-Level OFF; the voltage applied to the load
Inverter terminals is Vdc/2.

It comprises a single-phase One-fourth of the positive output


conventional H-bridge inverter, three (Vdc/4): The bidirectional switch S7 is ON,
connecting the load positive terminal, and Table shows the switching combinations
S4 is ON, connecting the load negative that generated the nine output-voltage
terminal to ground. All other controlled levels are (Vdc, 3Vdc/4, Vdc/2, Vdc/4,0,
switches are OFF; the voltage applied to the Vdc/4, Vdc/2, -3Vdc/4,-Vdc)
load terminals is Vdc/4.
V0 S1 S2 S3 S4 S5 S6 S7
Zero output: This level can be produced Vdc ON OFF OFF ON OFF OFF OFF
by two switching combinations; switches 3Vdc/4 OFF OFF OFF ON ON OFF OFF
S3 and S4 are ON, or S1 andS2are ON, and Vdc/2 OFF OFF OFF ON OFF ON OFF
all other controlled switches are OFF; Vdc/4 OFF OFF OFF ON OFF OFF ON
terminal ab is a short circuit, and the 0 ON ON OFF OFF OFF OFF OFF
voltage applied to theload terminals is zero. -Vdc/4 OFF ON OFF OFF ON OFF OFF
One-fourth negative output (−Vdc/4): -Vdc/2 OFF ON OFF OFF OFF ON OFF
The bidirectional switch S5 is ON, -3Vdc/4 OFF ON OFF OFF OFF OFF ON
connecting the load positive terminal, and -Vdc OFF ON ON OFF OFF OFF OFF
S2 is ON, connecting the load negative
terminal toVdc. All other controlled Table.1.Switching Sequence For The
switches are OFF; the voltageapplied to the Output Voltage
load terminals is −Vdc/4.
Forward current path at level Vdc/2
Half of the negative output (−Vdc/2): The
bidirectional switch S6 is ON, connecting
the load positive terminal, and S2 is ON,
connecting the load negative terminal to
ground. All other controlled switches are
OFF; the voltage applied to the load
terminals is −Vdc/2.

Three-fourth negative output (−3Vdc/4):


The bidirectional switch S7 is ON,
connecting the load positive terminal, and
S2 is ON, connecting the load negative
terminal to ground. All other controlled
switches are OFF; the voltage applied to the
Fig.4.Forward current path at level Vdc/2
load terminals is −3Vdc/4.
SIMULATION AND EXPERIMENTAL
Maximum negative output (−Vdc): S2 is
RESULTS
ON, connecting the load negative terminal
to Vdc, and S3 is ON, connecting the load Analysis of proposed system
positive terminal to ground. All other
controlled switches are OFF; the voltage In order to improve the performance of the
applied to the load terminals is −Vdc. inverter, the nine level inverter with
reduced switch count is proposed which
comprises a single-phase conventional H-
bridge inverter, three bidirectional switches, OUTPUT VOLTAGE AND CURRENT
and a capacitor voltage divider formed by WAVEFORMS:
C1, C2,C3 and C4.The modified H-bridge
topology is significantly advantageous over
other topologies, i.e., less power switch,
power diodes, and less capacitor for
inverters of same number of levels.

Fig.7.Output of nine level voltage


aveform. Y axis denoted as Voltage and
the X axis denoted as Time.

Fig.5.Simulation diagram of proposed nine-


level inverter Fig.8.Output of nine level current
waveform. Y axis denoted as current and
SWITCHING PATTERNS FOR PWM the X axis denoted as Time.
GENERATION

Fig.6.Simulation waveforms of driving


Fig.9.Total harmonic distortion of nine
signals for PWM generation level output voltage. The THD of the output
voltage is 11.19%
SIMULATION RESULTS OF THE
FOUR CAPACITORS VOLTAGES
Power Vs efficiency waveform:

Efficiency of the proposed


system is calculated and compared
with existing system.
higher than the existing system. All
Efficiency the merits and the feasibility of
100 proposed topology are evaluated by a
Efficiency(%)

simulation model.
90
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80
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