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92% Start-up Time Reduction by Variation-Tolerant Chirp Injection (CI) and

Negative Resistance Booster (NRB) in 39MHz Crystal Oscillator


Shunta Iguchi, Hiroshi Fuketa, Takayasu Sakurai, and Makoto Takamiya
University of Tokyo, Tokyo, Japan

Abstract and a layout of the proposed XO with CI and NRB. Table I


To reduce the start-up time of a crystal oscillator (XO), a shows a performance summary of the proposed XO with CI
chirp injection (CI) and a negative resistance booster (NRB) and NRB.
are proposed. By combining CI and NRB, the measured Fig. 6 shows a measured time dependence of the chirp
start-up time of a 39-MHz XO in 180-nm CMOS is reduced by frequency of the chirp generator. The chirp frequency crosses
92% from 2.1ms to 158μs, which is the shortest time in the the XO frequency (= 39MHz) across the best and the worst
published XO’s. The measured start-up time variations due to corners. Based on the results, tCI is fixed to 40μs.
the ±20% supply voltage change or the temperature change are Optimum gate width of Inv3 and tNRB for NRB are discussed.
less than 13%. Fig. 7 shows a measured gate ratio dependence of tSTART and
the steady-state power in the XO with NRB at infinite tNRB. CI
Introduction is disabled. The gate width of Inv3 is normalized to that of Inv1.
To reduce the power consumption of RF transceivers, an By increasing the gate ratio, |RN| is increased and tSTART is
intermittent operation and an agile transition between a sleep reduced at the cost of increasing power. The gate ratio of 13 is
mode and an active mode are required. The start-up time used for NRB. In this case, tSTART is reduced by 87%, while the
(tSTART) of the RF transceiver from the sleep mode to the active power increases by a factor of 4.9. Fig. 8 shows a measured
mode is limited by a crystal oscillator (XO) for the RF carrier tNRB dependence of tSTART in the XO with NRB. By increasing
generation, because tSTART of XO is the longest in the RF tNRB, tSTART is decreased and saturated at tNRB > 160μs. To
transceiver due to a high Q ( > 10000) of a quartz crystal. The reduce the power overhead due to NRB, tNRB of 164μs is used.
long tSTART prevents the agile mode transition and increases Fig. 9 shows measured start-up waveforms of the
power consumption of the RF transceiver. Therefore, in this conventional XO (Fig. 2 (a)) and the proposed XO with CI and
paper, new start-up time reduction techniques for a 39-MHz NRB (Fig. 2 (d)). By combining CI and NRB, tSTART is reduced
XO are proposed. by 92% from 2.1ms to 158μs.
To compare the variation tolerance of the 4 XO’s in Fig. 2,
Start-up Time Reduction Techniques VDD and the temperature are varied. Fig. 10 (a) shows a
Fig. 1 shows a strategy to reduce tSTART of a conventional measured VDD dependence of tSTART at 25ºC. The typical VDD is
Pierce XO shown in Fig. 2 (a). tSTART is determined by the 1.5V and VDD is varied ±20%. Fig. 10 (b) shows a measured
negative resistance (|RN|) and the internal noise (VNOISE) [1]. To VDD dependence of relative variations of tSTART. The variation
reduce tSTART in this paper, VNOISE is increased by the proposed of tSTART is normalized by tSTART at VDD of 1.5V. tSTART
chirp injection (CI), and |RN| is temporarily increased by the variation of CFI is much larger than that of CI, because CFI is
proposed negative resistance booster (NRB). calibrated at VDD of 1.5V and the RO frequency changes with
In the previously reported constant frequency injection (CFI) VDD, which indicates CI is more variation-tolerant than CFI.
[2] shown in Fig. 2 (b), a ring oscillator (RO) is connected to tSTART variation of the conventional XO is as high as 201%,
Out and X1 to increase VNOISE during the start-up. RO is while that of the proposed CI and NRB is less than 13%. Fig.
calibrated to have the same frequency as XO. CFI, however, 11 shows a measured temperature dependence of tSTART at VDD
will fail to work, because XO has the high Q and the frequency of 1.5V. The typical temperature is 25ºC and the temperature is
of RO should be the exactly same as that of XO. Even if RO is varied from -30ºC to 125ºC. Similar to Fig. 10 (a), tSTART of CFI
perfectly calibrated, the frequency of RO drifts due to the is longer than that of CI except for 25ºC, because CFI is
variation of the supply voltage (VDD) and the temperature, and calibrated at 25ºC. tSTART variation of the proposed CI and NRB
CFI fails to work. is less than 7% and the lowest in 4 XO’s.
To solve the problem, CI shown in Fig. 2 (c) is proposed. In Fig. 12 shows comparisons of tSTART of 4 XO’s at the typical,
CI, instead of the constant-frequency RO in CFI, a chirp low VDD, and high temperature conditions. tSTART is normalized
generator is used to increase VNOISE. The chirp is a signal in by tSTART of the conventional XO at each condition. In CFI, the
which the frequency decreases with time. Fig. 3 shows a circuit reduction of tSTART is only 31% at the high temperature
schematic of the chirp generator. When CI_en changes from condition, while the proposed CI and NRB reduces tSTART by
low to high, the control voltage (VCNT) of VCO is varied from more than 92% at the all conditions. Therefore, the proposed CI
VDD to 0V. The frequency of the chirp is designed to cross the and NRB is variation-tolerant.
XO frequency (= 39MHz) considering PVT variations. Table II shows a comparison with previously reported XO’s
Therefore, CI is more tolerant to PVT variations than CFI. [3-6]. This work shows the shortest tSTART of 158μs and
To increase |RN| for reducing tSTART, NRB is added to CI and achieves the PVT variation tolerance. Thus, the proposed XO
the finally proposed XO is shown in Fig. 2 (d). Fig. 4 shows a with CI and NRB enables the agile mode transition between the
timing chart of the proposed XO. When a wake-up signal is sleep and active mode, and reduces the power consumption of
received, both CI_en and NRB_en are activated. While CI_en the RF transceiver.
is high, Chirp is injected to Out and X1. When NRB_en is high, Acknowledgment
Inv3 is added to Inv1 to increase |RN|, thereby reducing tSTART. This work was partly supported by STARC. The VLSI
In this paper, tSTART is defined as the time from the wake-up chips were fabricated in the chip fabrication program of VDEC
signal to the timing when the amplitude of Out is equal to 90% in collaboration with Rohm Corp. and Toppan Printing Corp.
of that of the steady-state Out. The activation period of CI_en
(tCI) is shorter than that of NRB_en (tNRB). References
[1] A. Rusznyak, JSSC, pp. 259-268, 1987.
Experimental Results [2] Y. Kwon et al., TCAS-I, pp. 324-336, 2012.
The 4 XO’s in Fig. 2 are fabricated in 180-nm CMOS [3] Y. Chang et al., JSSC, pp. 421-434, 2012.
process and compared. The Inv1 in Fig. 2 is designed to have [4] R. van Langevelde et al., RFIC Symp., pp. 113-116, 2009.
[5] Data sheet of CC2540, Texas Instruments, [Online].
an oscillation allowance of 5 for XO. Fig. 5 shows a die photo [6] S. Iguchi et al., VLSI Symp., pp. C142-C143, 2013.

978-1-4799-3328-0/14/$31.00 ©2014 IEEE 2014 Symposium on VLSI Circuits Digest of Technical Papers
Chirp Injector (CI)
Amplitude of XO / A Chirp
Start-up time (tSTART) generator CI_en
Constant Frequency f
1 Injector (CFI) CI

Ring osc. t
10-1 Chirp Inv3 Negative
Inv2 Inv2 Resistance
Enable CI_en Booster
10-2 |RN| by NRB (NRB)
NRB_en
VNOISE by CI
10-3 X1 X1 X1 X1
Time
Out Inv1 Out Inv1 Out Inv1 Out Inv1
1 A
tSTART ∝ ln R1 R1 R1 R1
RN VNOISE R2 R2 R2 R2
RN : Negative resistance C1 C2 C1 C2 C1 C2 C1 C2
Quartz Quartz Quartz Quartz
A : Steady-state amplitude crystal crystal crystal crystal
VNOISE : Internal noise (a) (b) (c) (d)
Fig. 1. Strategy to reduce tSTART of XO. Fig. 2. (a) Conventional Pierce XO. (b) XO with CFI [2]. (c) XO with CI. (d) Proposed XO with CI and NRB.
VCO
tCI
Table I Performance summary.
CI_en
V Frequency 39MHz
CMOS process 180nm
t
Chirp Chirp Supply voltage 1.5V
CI_en VCNT Core area 0.12mm2
tNRB R1 500kΩ
C3
R3 NRB_en R2 10Ω
Fig. 3. Chirp generator for CI. C 1, C 2 12pF, 12pF
2.4mm 350μm Power 181μW
|RN| Boost Start-up energy 434nJ
0
Start-up time (tSTART)
tSTART 158μs
Resistor at 1.5V, 25ºC
520μm
1.3mm

(R3) Out tSTART variation


0.9 x A A < 13%
(1.2V to 1.8V) at 25ºC
Start-up Steady-state tSTART variation
C3 < 7%
(-30ºC to 125ºC) at 1.5V
XO Wake-up Time
Fig. 5. Die photo and layout. VCO core Fig. 4. Timing chart of proposed XO with CI and NRB.
100 2.5 1.5 2.5

Power consumption [mW]


Start-up time (tSTART) [ms]

Start-up time (tSTART) [ms]


Measured w/o NRB Measured Measured
Chirp frequency [MHz]

80 2.0 tNRB = ∞ 2.0 w/o NRB Gate ratio = 13


tCI = 40μs -87% 1.0
60 1.5 1.5

40 39MHz 1.0 1.0


0.5 164μs is used for NRB.
Gate ratio = 13
20 0.5 is used for NRB. 0.5

0 0 0 0
0 10 20 30 40 50 60 0 5 10 15 20 0 100 200 300
Time after CI_en [μs] Gate ratio = Gate width of Inv3 / Gate width of Inv1 tNRB [μs]
Fig. 6. Measured time dependence of chirp Fig. 7. Measured gate ratio dependence of Fig. 8. Measured tNRB dependence of tSTART
frequency. tSTART and steady-state power in XO with NRB. in XO with NRB.
7 250
[%]
Start-up time (tSTART) [ms]

25ºC -20% +20% 25ºC


6 -20% +20% CI_en
200
tSTART tSTART @ 1.5V

CFI
5 Conv.
150 NRB_en
tSTART @ 1.5V

Conv.
4 CFI
Fig. 9 100
CI (a)
3 Out
CI 50 tSTART = 2.1ms
2

1 Proposed 0
CI + NRB Proposed CI + NRB
0 -50
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 tCI = 40μs CI_en
Supply voltage [V] Supply voltage [V] tNRB = 164μs
(a) (b) NRB_en
tSTART = 158μs
Fig. 10. Measured VDD dependence of (a) tSTART and (b) relative variations of 4 XO’s in Fig. 2 at 25ºC. (b)
3 100 Out
Start-up time (tSTART) [ms]

tSTART / tSTART of Conv. [%]

VDD = 1.5V -31%

80 -43% -57%
Conv. Fig. 9. Measured start-up waveforms. (a) Conv. XO (Fig.
2 -58% -69%
60 2 (a)). (b) Proposed XO with CI and NRB (Fig. 2 (d)).
-88% -94%
-92% Table II Comparison with previously reported XO’s.
CFI 40 -98%
1 [3] [4] [5] [6] This
work
CI 20 Frequency MHz 26 19 32 39 39
Proposed CI + NRB CMOS process nm 65 130 NA 40 180
0 0 Supply voltage V 1.2 1.2 3.0 0.7 1.5
-40 -20 0 20 40 60 80 100 120 CFI CI CI CFI CI CI CFI CI CI
+ + + Power μW 1440 22 180 69 181
Temperature [ºC] NRB NRB NRB
Start-up time μs 3200 1200 250 259 158
Typical Low VDD High temperature (tSTART)
Fig. 11. Measured temperature dependence of (1.5V, 25ºC) (1.2V, 25ºC) (1.5V, 125ºC)
tSTART is robust to No No NA No Yes
tSTART of 4 XO’s in Fig. 2 at VDD = 1.5V. Fig. 12. Comparisons of tSTART of 4 XO’s. PVT variations.

2014 Symposium on VLSI Circuits Digest of Technical Papers

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