APPROVED BY AICTE NEW DELHI, AFFILIATED TO VTU BELGAUM

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING

DIGITAL ELECTRONICS LABORATORY

LAB MANUAL – 15ECL38
III-SEMESTER
2016-2017

Prepared by: Reviewed by: Approved by:

Mrs. A. Deepa Mrs. Kavitha M V Dr. A.A. Powly Thomas

Assistant Professor Head of the Department Principal
Dept. of ECE Dept. of ECE GCEM
GCEM GCEM

81/1, 182/1, Hoodi Village, Sonnenahalli, K.R. Puram, Bengaluru,

Karnataka-560048.
 Contents

S.No Title Page No

1. Syllabus 2-2

2. Course objective 2-2

3. Course outcome 3-3

4. Do‟s & Don‟ts 4-4

5. List of experiments 5-46

6. Viva questions 47-48

7. Appendix-1 49-52

1
 Syllabus
DIGITAL ELECTRONICS LABORATORY
[As per Choice Based Credit System (CBCS) scheme]
SEMESTER – III (EC/TC)

Laboratory Code 15ECL38 IA Marks 20

Number of Lecture 01Hr Tutorial (Instructions) Exam Marks 50
Hours/Week + 02 Hours Laboratory

Laboratory Experiments:
1. Verify
(a) Demorgan‟s Theorem for 2 variables.
(b) The sum-of product and product-of-sum expressions using universal gates.
2. Design and implement
(a) Full Adder using basic logic gates.
(b) Full subtractor using basic logic gates.
3. Design and implement 4-bit Parallel Adder/ subtractor using IC 7483.
4. Design and Implementation of 4-bit Magnitude Comparator using IC 7485.
5. Realize
(a) 4:1 Multiplexer using gates.
(b) 3-variable function using IC 74151(8:1MUX).
6. Realize 1:8 Demux and 3:8 Decoder using IC74138.
7. Realize the following flip-flops using NAND Gates.
(a) Clocked SR Flip-Flop (b) JK Flip-Flop.
8. Realize the following shift registers using IC7474
(a) SISO (b) SIPO (c) PISO (d)PIPO.
9. Realize the Ring Counter and Johnson Counter using
IC7476.
10. Realize the Mod-N Counter using IC7490.
11. Simulate Full- Adder using simulation tool.
12. Simulate Mod-8 Synchronous UP/DOWN Counter using
Simulation tool.

2
Course Objectives:
This laboratory course enables students to get practical experience in design,
realization and verification of

 Demorgan‟s Theorem, SOP, POS forms

 Full/Parallel Adders, Subtractors and Magnitude Comparator

 Multiplexer using logic gates

 Demultiplexers and Decoders

 Flip-Flops, Shift registers and Counters.

Course Outcomes:
 On the completion of this laboratory course, the students will be able to:

 Demonstrate the truth table of various expressions and combinational circuits

 using logic gates.

 Design, test and evaluate various combinational circuits such as adders, subtractors,
comparators, multiplexers and demultiplexers.

 Construct flips-flops, counters and shift registers.

 Simulate full adder and up/down counters.

3
Do’s & Dont’s

Do’s

 Conduct yourself in a responsible manner at all times in the laboratory.

 Dress properly during a laboratory activity.

 Long hair, dangling jewelry and loose or baggy clothing are a hazard in the
laboratory.

 Observe good housekeeping practices.

 Replace the materials in proper place after work to keep the lab area tidy.

Dont’s
 Do not wander around the room, distract other students, startle other students or
interfere with the laboratory experiments of others.

 Do not eat food, drink beverages or chew gum in the laboratory and do not use
laboratory glassware as containers for food or beverages.

 Do not open any irrelevant internet sites on lab computer

 Do not use a flash drive on lab computers.

 Do not upload, delete or alter any software on the lab PC.

 Do not switch on the trainer kit without verifying connection.

4
 List of Experiments
EXPT. PAGE
Name of the Experiment
NO. NO.
Introduction
7
Study of Logic gates
To verify
(a) Demorgan‟s Theorem for 2 variables
01 10
(b) The sum-of product and product-of-sum expressions using universal
gates
To design and implement
02 (a) Full Adder using basic logic gates. 14
(b) Full subtractor using basic logic gates.
03 To design and implement 4-bit Parallel Adder/ subtractor using IC 7483. 18
04 Design and Implementation of 4-bit Magnitude Comparator using IC 7485. 21
To realize
(a) 4:1 Multiplexer using gates
05 23
(b) 3-variable function using IC 74151(8:1 MUX)

06 Realize 1:8 Demux and 3:8 Decoder using IC74138. 27

To realise the following flip-flops using NAND Gates.
07 29
(a) Clocked SR Flip-Flop (b) JK Flip-Flop
To realize the following shift registers using IC7474
08 32
(a) SISO (b) SIPO (c)PISO
09 To realize the Ring Counter and Johnson Counter using IC7476. 39
10 To realize the Mod-N Counter using IC7490. 42
Simulate Full- Adder using simulation tool.
11 44

12 Simulate Mod-8 Synchronous UP/DOWN Counter using simulation tool. 46

5
 INTRODUCTION

STUDY OF LOGIC GATES

Aim: Truth Table verification of logic gates

General Characteristics:

a. Pin „Vcc‟ on an I.C is to be connected to a regulated power supply of +5 volts.

b. Pin „GND‟ on an I.C is to be connected to the power supply ground.
c. = High or „1‟ state implies a voltage between 2.4V and 5.0V in the input state.

Procedure:

1. Fix the I.C on the I.C trainer kit.

2. Connections are made as shown, using the pin details of the gates. Toggle switches and
LED‟s in the trainer are used as inputs and outputs respectively.

3. Switch on the supply on the trainer and verify the truth table of the gates

AND GATE (7408)

1 VCC 14
A Y 13
2
12
B

Truth Table
3
11
A B Y=A.B 7408
4
10

0 0 0 5
9

0 1 0

1 0 0 6

7 GND 8
1 1 1

6
OR GATE (7432)
A 1 VCC 14
Y 13
2
12
B

Truth Table
3
11
A B Y=A+B 7432
4
10

0 0 0 5
9

0 1 1

1 0 1 6

7 GND 8
1 1 1

NOT GATE (7404)

Truth Table

A Y=Ā

0 1

1 0

7
 NAND GATE (7400)

A
Y

Truth Table

A B

0 0 1

0 1 1

1 0 1

1 1 0

NOR GATE (7402)

A
Y 1 VCC 14
13
B

Truth Table 2
3 12

A B 4
7402 11

10
0 0 1

0 1 0
5
6
9
1 0 0 7 GND
8

1 1 0

8
EX-OR GATE (7486)
A 1 VCC 14
Y
13
2
B 12

Truth Table
3
11
A B Y=AB 7486
4
10

0 0 0 5
9

0 1 1
6
1 0 1
7 GND 8
1 1 0

9
Experiment No: 01 Date:

VERIFICATION OF DEMORGAN’S THEOREM & REALIZATION SOP

&POS EXPRESSIONS
AIM:

1. To verify De-Morgan‟s theorem for two variables

2. To realize sum of product (SOP) and product of sum (POS) expressions using
OF SOP AND gates.
universal POS EEEEEEEEXPRESSIONSEXPRESSIONS

COMPONENTS REQUIRED: IC Trainer kit, IC 7400, IC 7402

THEORY:

1. De Morgan theorem states that

a) AB‟=A‟+B‟
b) (A+B)‟=A‟.B‟

De-Morgan‟s theorem is highly useful to simplify the Boolean expression

2. Gates NAND and NOR are known as universal gates, because any logic gates or Boolean
expression can be realized by either NAND or NOR gate alone. Each product term in the SOP
expression is called minterm and each sum term in the POS expression is called maxterm.
SOP expression can be economically realized using NAND gates and POS expression can be
economically realized using NOR gates

Realization of SOP expression

Using NAND gates
i)Use NAND gates for each minterm
ii) Use one NAND gate for whole summation
Using NOR gates
i) Invert all the variables in each minterm
ii) Use NOR gates for each minterm having inverted variables
iii) Use NOR gate for whole summation
iv) Use another NOR gate at the output for inverting.

Realization of POS expression

Using NOR gates
i) Use NOR gates for each maxterm
ii) Use one NOR gate for whole multiplication

10
 Using NAND gates
i) Invert all the variables in each maxterm
ii) Use NAND gates for each maxterm having inverted variables
iii) Use NAND gate for whole multiplication
iv) Use another NAND gate at the output for inverting

DEMORGAN’S THEOREM:

a) AB‟=A‟+B‟

TRUTH TABLE:

A B
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0

CIRCUIT DIAGRAM:

b) (A+B)‟=A‟.B‟

TRUTH TABLE:

A B
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0

11
CIRCUIT DIAGRAM:

b) Realization SOP & POS Expressions:

12
PROCEDURE:

1) Test all the IC packages using digital IC tester.

2) Set up the circuit one by one and verify their truth table.
3) Observe the output corresponding to input combinations and enter it in truth table.

RESULT:

De-Morgan‟s t heorem an d postul at e of Bool ean al gebra were verified.

Sum o f products and product of sum expressions were realized using universal gates

13
Experiment No: 02 (a) Date:
FULL ADDER

AIM:
To realize the Full Adder circuits using basic logic gates and and to verify their truth tables.

COMPONENTS REQUIRED:

Digital Trainer Kit 01

AND Gate IC 7408 01
OR Gate IC 7432 01
NOT Gate IC 7404 01
NAND Gate (2 Input) IC 7400 03
XOR Gate IC 7486 01
Patch chords / Connecting wires 35

THEORY:
Full Adder is a logical circuit, which performs addition of three bits (i.e. addition of two bits
with previous carry) and provides an output with a Sum and Carry. It can be built using 2-half
adders and an OR gate.

PROCEDURE:

1. Connections are made as shown in the logic diagram using the pin details of the gates
2. Connect Vcc & GND to respective pins of each IC
3. Switch on the Trainer kit.
4. Using the toggle switches set up the input code combination and observe the output code
combinations on the LED‟s, as shown in the truth table.

TRUTH TABLE:

Full adder:

INPUT OUTPUTS
A B CIN S (Sum) COUT (Carry)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
14
Logic expressions:

LOGIC DIAGRAM:
Realization of full adder using Basic and EXOR gates

A
1
3
B 2
4 Sum
6
Cin 5

4
6
5
1 Carry
3
2
1
3
2

RESULT:
Thus the Logic circuit of Full Adder Circuit was constructed and the truth table was
verified.

15
Experiment No: 02 (b) Date:
FULL SUBTRACTOR
AIM:
To realize the Full Subtractor circuit using basic logic gates and verify their truth tables.

COMPONENTS REQUIRED:

Digital Trainer Kit 01

AND Gate IC 7408 01
OR Gate IC 7432 01
NOT Gate IC 7404 01
NAND Gate (2 Input) IC 7400 03
XOR Gate IC 7486 01
Patch chords / Connecting wires 35

THEORY:
Full Subtractor is a logical circuit, which performs Subtraction of three bits and provides an
output with a Difference and Borrow, It can be built using 2-half Subtractor and an OR gate.

PROCEDURE:

1. Connections are made as shown in the logic diagram using the pin details of the gates.
2. Connect Vcc & GND to respective pins of each IC
3. Switch on the Trainer kit.
4. Using the toggle switches set up the input code combination and observe the output code
combinations on the LED‟s, as shown in the truth table.

TRUTH TABLE:
Full Subtractor:

INPUTS OUTPUTS
A B BIN D (Difference) BOUT (Borrow)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

16
Logic Expressions:

LOGIC DIAGRAM:

RESULT:
Thus the Logic circuit of Full Subtractor Circuit was constructed and the truth table was
verified.

17
Experiment No: 03 (a) Date:
4-BIT PARALLEL ADDER/SUBTRACTOR USING IC 7483

AIM:
To perform the addition of two 4-bit numbers.
COMPONENTS REQUIRED:

Digital Trainer Kit 01

XOR Gate IC 7486 01
Parallel Adder/ Subtractor IC 7483 01
Patch chords / Connecting wires 25

THEORY:
Parallel adders are ripple carry type in which the carry output of each full adder stage is
connected to the carry input of the next higher order stage, the 7483 IC is a 4-bit parallel
adder used to perform subtraction as well, the two 4-bit binary numbers A4A3A2A1 and
B4B3B2B1 are added to give a sum S4S3S2S1 and carry Cout when carry in (CIN) and „S‟is
„0‟.The 1‟s compliment subtraction is carried out when carry out (Cout) connected to Cin and
„S‟= „1‟, The 2‟s compliment subtraction is carried out when carry in (CIN) and „S‟is „1‟.

PROCEDURE:

1. Connections are made as shown in the logic diagram using the pin details of the gates and
IC 7483.
2. Connect Vcc & GND to respective pins of ICs
3. Switch on the Trainer kit.
4. Apply the inputs and observe the outputs.
5. Compare the practical value with the theoretical value.

18
Observation and calculations:

 4 Bit adder operations.

1. Let A = 1100 (A4 A3 A2 A1) , B = 0011 (B4B3 B2 B1) Then

Sum (S4 S3 S2 S1) = 1111 and Cout = 0 (With S = 0 and Cin = 0).
2. Let A = 1001 (A4 A3 A2 A1) , B = 1101(B4B3 B2 B1) Then
Sum (S4 S3 S2 S1) = 0110 and Cout = 1 (With S = 0 and Cin = 0).

TRUTH TABLE:

PARALLEL ADDER
Parameters Theoretical Practical
Augend 1100 1001 1100 1001
Addend 0011 1101 0011 1101
Sum 1111 0110 1111 0110
Carry 0 1 0 1

 4 Bit subtraction operation.

One‟s Complement Method

Perform Subtraction of: A4 A3 A2 A1= 1 0 0 1

B4B3 B2 B1= 0 0 1 1

One‟s complement of the Subtrahend is

B4B3 B2 B1 = 1 0 0 0
A4 A3 A2 A1 = (+) 1 0 0 1
 0 1 0 1
1 (+)
(S4 S3 S2 S1) = 0 1 1 0

Two‟s Complement Method

Perform Subtraction of: A4 A3 A2 A1= 1 0 0 1

B4B3 B2 B1= 0 0 1 1
One‟s complement of the Subtrahend is

B4B3 B2 B1 = 1 1 0 0
1
1 1 0 1
A4 A3 A2 A1 = 1 0 0 1 (+)
(S4 S3 S2 S1)  0 1 1 0
End around Carry is disregarded
19
TRUTH TABLE:

PARALLEL SUBTRACTOR
One‟s Complement Two‟s Complement
Parameters Theoretical Practical Theoretical Practical
Minuend 1001 1001 1001 1001
Subtrahend 0011 0011 0011 0011
Difference 0110 0110 0110 0110

RESULT:
Thus the operation of Parallel adder and Parallel Subtractor were studied and checked using
IC 7483.

20
Experiment No: 4 Date:

DESIGN AND IMPLEMENTATION OF 4-BIT MAGNITUDE

COMPARATOR USING IC 7485
AIM:
Realization of 7485 magnitude comparator and verify its using truth table.

COMPONENTS REQUIRED:

Digital Trainer Kit 01

4bit comparator IC 7485 01

Patch chords / Connecting wires 25

THEORY:

Four Bit 7485 Magnitude Comparator: The Magnitude comparator is used to compare
binary and natural BCD coded. These IC‟s can be cascaded to compare words of greater
lengths without external gates. The condition A > B, A = B, A < B output stage handling
LSB‟s are connected to corresponding A > B, A = B, A < B cascading inputs of the next
stage handling MSB‟s.

Function Table:

Comparing inputs Cascading inputs Outputs

A>B A>B A=B A<B A>B A=B A<B
A>B X X X 1 0 0
1 0 0 1 0 0
X 1 X 0 1 0
A=B 0 0 1 0 0 1
0 0 0 1 0 1
1 0 1 0 0 0
A<B X X X 0 0 1

21
LOGIC DIAGRAM:

PROCEDURE:

1. Connections are made as shown in the logic diagram using the pin details of the gates.
2. Connect + Vcc & GND to respective pins of each IC
3. Switch on the Trainer kit.
4. Connect the A > B and A < B cascading inputs to logic 0 level and A = B input to logic 1
level.
5. Connect the input bits to be compared to the toggle switches and outputs A > B, A = B
and A = B the LED‟s and verify the compare operation for different input combinations
as shown below.
TRUTH TABLE:

Data Inputs Cascading inputs Outputs

A = A3 A2 A1 A0 A>B A=B A<B A>B A=B A<B
B = B3 B2 B1 B0
A>B 0 1 0 1 0 0
A<B 0 1 0 0 0 1
A=B 0 1 0 0 1 0

RESULT:
Thus the 4 bit magnitude comparator were realized using IC 7485, and the truth tables was
verified.

22
Experiment No: 05 (a) Date:
4:1 MULTIPLEXER USING GATES

AIM:
To realize the 4 to 1 MUX using gates.

COMPONENTS REQUIRED:

Digital Trainer Kit 01

NOT Gate IC 7404 01
AND Gate IC 7408 01
OR Gate IC 7432 01
Patch chords / Connecting wires 20

THEORY:
The Multiplexers or data selector is a logic circuit that selects one out of several inputs to a
single output. The input selected is controlled by a set of select lines. For selecting one output
line from n-input lines, a set of m-select lines is required. The relationship between the
number of input lines and the select lines is given by 2 m = n.

PROCEDURE:

1. Connections are made as shown in the logic diagram using the pin details of the gates.
2. Connect Vcc and GND to respective pins of each IC.
3. Connect the data, select and enable inputs to the toggle switches and outputs to the LED‟s
4. Switch on the Trainer
5. Verify the truth table of the Multiplexer.

LOGIC DIAGRAM:

23
TRUTH TABLE:

S1 S0 DATA
0 0 Y0
0 1 Y1
1 0 Y2
1 1 Y3

RESULT:
Thus the 4 to 1 multiplexer was realized and verified using gates.

24
Experiment No: 05 (b) Date:
3 VARIABLE FUNCTION USING IC 74151

AIM:
To Realize the 3 variable function using IC 74151.

COMPONENTS REQUIRED:

Digital Trainer Kit 01

NOT Gate IC 7404 01
81 MUX IC 74151 01
Patch chords / Connecting wires 20

TRUTH TABLE:

Full Adder using MUX

INPUTS OUTPUTS
S COUT
X Y CIN
(Sum) (Carry)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Implementation table for Sum and Carry:

Sum = Σm (1,2,4,7)
Carry = Σm (3,5,6,7)

25
LOGIC DIAGRAM FOR CARRY:

LOGIC DIAGRAM FOR SUM:

RESULT:
The functions of MUX using 74151 IC & Realization of Arithmetic circuits using MUX IC
74151 were studied.

26
Experiment No:06 Date:
REALIZATION OF 1:8 DEMUX USING IC 74138

AIM:
To study the function of DEMUX using IC 74138.

COMPONENTS REQUIRED:

Digital Trainer Kit 01

NOT Gate IC 7404 01
OR Gate IC 7432 01
NAND Gate (2 Input) IC 7410 01
NAND Gate (3 Input) IC 7420 01
14 DEMUX IC 74139 02
Patch chords / Connecting wires 20

THEORY:
The Demultiplexer is a combinational logic circuit which takes one input data source and
selectively distributes it to N output channels just like a multiposition switch. The data
distributor, known more commonly as a Demultiplexer or “Demux” for short, is the exact
opposite of the Multiplexer.The demultiplexer takes one single input data line and then
switches it to any one of a number of individual output lines one at a time. The
demultiplexer converts a serial data signal at the input to a parallel data at its output lines.

LOGIC SYMBOL:
1:8 DE MUX Using 74138 I.C

27
TRUTH TABLE:

PROCEDURE:

1. Connections are made as shown in the logic diagram using the pin details of the gates.
2. Connect Vcc and GND to respective pins of each IC.
3. Connect the data, select and enable inputs to the toggle switches and outputs to the LED‟s
4. Switch on the supply on the Trainer
5. Verify the truth table of the De-Multiplexer.

RESULT:
The function of DEMUX/DECODER using IC 74138 alization of Code Converters using
DEMUX 74139 were studied.

28
Experiment No:07 Date:
REALIZATION OF CLOCKED SR &JK FLIP FLOP
AIM:
1. To verify the Truth Table of clocked SR Flip Flop
2. To verify the Truth Table of JK Flip Flop

COMPONENTS REQUIRED:

Trainer Kit 01
IC 7400 03
Patch chord 20

THEORY:
clocked SR flip flop

The SR flip-flop can be considered as a 1-bit memory, since it stores the input pulse
even after it has passed. Flip-flops (or bi-stables) of different types can be made
from logic gates and, as with other combinations of logic gates, the NAND and NOR
gates are the most versatile, the NAND being most widely used. This is because, as
well as being universal, i.e. it can be made to mimic any of the other standard logic
functions, it is also cheaper to construct.

LOGIC DIAGRAM:

29
TRUTH TABLE FOR CLOCKED SR FLIP-FLOP:

Inputs Output
Operation
CLK S R Qn+ 1

0 X X Qn No change
0 0 Qn No change
0 1 0 Reset
1 0 1 Set
-
1 1 Indeterminate

JK FLIP FLOP:
Theory:
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type
is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-
flop (note that in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic
1 inputs are applied to both J and K simultaneously, the flip-flop switches to its complement
state, ie., if Q=1, it switches to Q=0 and vice versa.
Logic Diagram:

PROCEDURE:

1. Connections are made as shown in the Logic diagrams, using the pin details of different
IC‟s used.
2. Switch on the power supply of the Trainer Kit.
3. Verify the Truth Tables of JK FF.

30
TRUTH TABLE FOR JK - FF:

Inputs Output
Operation
CLK J K Qn+ 1

0 X X Qn No change
0 0 Qn No change
0 1 0 Reset
1 0 1 Set
1 1 Qn„ Toggles

RESULT:
Thus the truth table for clocked SR FF & JK FF were verified.

31
Experi ment No: 08 Date:
REALIZATION OF SHIFT REGISTERS USING IC7474

AIM:
To implement different types of shift registers like Serial In Serial Out [SISO], Serial In
Parallel Out [SIPO], Parallel In Parallel Out [PIPO] and Parallel In Serial Out [PISO] using
D-flip flops and to verify their observation table.

COMPONENTS REQUIRED:

Trainer Kit 01
IC 7474 02
Ic 7408 01
Patch chord 20

THEORY:

Registers are simply a group of flip flops that can be used to store a binary number. A
shift register is nothing but a register which can accept binary number and shift it. The data
can be entered in the shift register either in serial or in parallel. The output can be taken either
in serial or in parallel. Since there are two ways to shift data in to a register and two ways to
shift data out of the register four types of registers can be constructed. A register capable of
shifting its binary information either to the left or to the right is called a shift register. The
logical configuration of a shift register consists of a chain of flip flops connected in cascade
with the output of one flip flop connected to the input of the next flip flop. All the flip flops
receive a common clock pulse which causes the shift from one stage to the next.

The Q output of a D flip flop is connected to the D input of the flip flop to the left. Each
clock pulse shifts the contents of the register one bit position to the right. The serial input
determines, what goes into the right most flip flop during the shift. The serial output is taken
from the output of the left most flip flop prior to the application of a pulse. Although this
register shifts its contents to its left, if we turn the page upside down we find that the register
shifts its contents to the right. Thus a unidirectional shift register can function either as a
shift right or a shift left register.
The binary information (data) in a register can be moved within or into or out of the register
upon application of clock pulses. This type of bit movement or shifting is essential for certain
arithmetic and logic operations used in microprocessors. This gives rise to group of registers

32
called shift registers. They are very important in applications involving the storage and
transfer of data in a digital system.
TYPES OF SHIFT REGISTERS :
Serial In Serial Out [SISO]:
In this type of register, the output of one flip-flop is connected to the input of the next flip-
flop. Output of the register is obtained from the last flip-flop. Depending on the direction of
the input given shifting takes place in this. Bit by bit loading is done with every clock pulse
and shifting takes place with every clock pulse.
Serial In Parallel Out [SIPO]:
This is similar to SISO except that the output is taken from each flip-flop. Thereby the shifted
value is shown at once.
Parallel In Parallel Out [PIPO]:
Upon giving clock pulse, data is loaded in parallel in all flip-flops. Output is taken from each
of the flip-flop.
Parallel In Serial Out [PISO]:
Here we use a control input Load/ (Shift)‟ such that if Load/ (Shift)‟ = 1, data is loaded in all
flip-flops in parallel and when the Load/ (Shift)‟ = 0, data is shifted with every clock pulse.
Output is obtained from the last flip-flop.

IC 7474 consists of two D flip-flops with PRESET & CLEAR. The pin diagram is as shown
in figure.

PIN DIAGRAM OF IC 7474:

PROCEDURE:
33
1. Test all the ICs manually/ using IC tester.
2. Connect VCC and the ground.
3. Connect the appropriate pins to the input and output LEDs and switches.
4. Verify the truth table with respect to the clock.

FUNCTION TABLE FOR IC 7474:

Inputs Outputs
Preset Clear Clock D Q Q‟
Clear
0 1 Q Q‟
Clock X X 1 0
Clock
1 D Q0 Q‟ X X 0 1
D Q0 Q‟ 0 X X 1 1
1 1 1 0 0 1
1 1 1 1 1 0
1 1 0 X No change No change

LOGIC DIAGRAM:
Serial In Serial Out:

Figure(1). Connection diagram for Serial in Serial out Shift Register (Right Shift)
Observation Table:

34
Serial In Parallel Out:

35
36
RESULT:

The performance of shift registers using D FF are set up and studied

37
Experi ment No: 09 Date:

RING COUNTER AND JOHNSON (TWISTED RING) COUNTER

AIM:

To design and set up four bit Johnson and ring counter using JK FF

COMPONENTS REQUIRED:

Digital IC trainer kit, IC 7476

THEORY:

Ring counter and Johnson counters are basically shift registers Ring

Ring counter:

It is made by connecting Q&Q‟ output of one JK FF to J&K input of next FF

respectively. The output of final FF is connected to the input of first FF. To start the counter
the first FF is set by using preset facility and the remaining FF are reset input. When the clock
arrives the set condition continues to shift around the ring

As it can be seen from the truth table there are four unique output stages for this counter. The
modulus value of a ring counter is n, where n is the number of flip flops. Ring counter is
called divided by N counter where N is the number of FF

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Johnson counter (Twisted ring counter)

The modulus value of a ring counter can be doubled by making a small change in the ring
counter circuit. The Q‟ and Q of the last FFS are connected to the J and K input of the first FF
respectively. This is the Johnson counter

Initially the FFs are reset. After first clock pulse FF0 is set and the remaining FFs are reset.
After the eight clock pulse all the FFS are reset. There are eight different conditions creating a
mode 8 Johnson counter. Johnson counter is called a twisted ring counter or divide by 2N
counter

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PROCEDURE:

1. Set up the ring counter and set clear Q outputs using PRESET and apply mono
pulse.
2. Note down the state of the ring counter on the truth table for successive clock 0.
3. Repeat the steps for Johnsons counter

RESULT :

Four bit ring counter and the Johnson counter were set up using the JK FF and verified

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Experiment No:10 Date:
REALIZATION OF MOD – N COUNTER USING 7490

AIM:
To realize a Modulo N-counter using 7490 and verify the expected truth table and display the
output waveform for a square wave input of given frequency. (N–to be specified, N 9).

COMPONENTS REQUIRED:

Trainer Kit 01
IC 7490 01
IC 7400 01
IC 7410 01
Patch chord 25

THEORY:
7490 is a 10 counter using 4 master slave JK flip-flops.
It contains 2 and 5 counters, which can be cascaded to give a 10 counter.

PROCEDURE:

1. Connections are made as shown in the circuit diagram using 7490 ,7410 and 7400 IC.
2.Apply the clock pulse and verify the truth table

LOGIC DIAGRAM:

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EXPECTED WAVEFORM:

TRUTH TABLE:

Clock Outputs
pulse QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0

RESULT:
Thus the Mod-N Counter is constructed and verified.

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Experiment No:11 Date:
SIMULATION OF FULL ADDER USING PSPICE

AIM:
To design the circuit of full adder.

COMPONENTS REQUIRED:

7486(X-OR), 7408(AND), 7432(OR).

THEORY:
A full adder is a logical circuit that performs an additional operation on three binary digits. The
half adder produces a sum and a carry value which are both binary digits.
A full adder circuit has three inputs A,B and Cin and two outputs – S representing sum and Cout
representing carry.

S = A xor B xor C
C = A.B +C(A xor B)

TRUTH TABLE:

A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

SCHEMATIC DIAGRAM:

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WAVEFORM:

RESULT:
The output waveform of Full Adder is verified.

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Experiment No:12 Date:
SIMULATION OF MOD-8 SYNCHRONOUS UP/DPWN COUNTER USING
PSPICE

AIM:
To design the circuit of MOD-8 Synchronous UP/DOWN Counter.

COMPONENTS REQUIRED:

7476(JK FF), 7408(AND), 7432(OR), 7404(NOT).

THEORY:
The similarities between the implementation of a binary up counter and a binary down counter
leads to the possibility of a binary up/down counter, which is a binary up counter and a binary
down counter combined into one. Since the difference is only in which output of the flip-flop to
use, the normal output or the inverted one, we use two AND gates for each flip-flop to "choose"
which of the output to use.

3-bit Synchronous Binary Up/Down Counter

From the diagram, we can see that COUNT-UP and COUNT-DOWN are used as control inputs
to determine whether the normal flip-flop outputs or the inverted ones are fed into the J-K inputs
of the following flip-flops. If neither is at logic level 1, the counter doesn't count and if both are
at logic level 1, all the bits of the counter toggle at every clock pulse. The OR gate allows either
of the two outputs which have been enabled to be fed into the next flip-flop.

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WAVEFORMS:

RESULT:
The output waveform of MOD-8 Synchronous UP/DOWN Counter is verified.

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 VIVA QUESTIONS

1. What do you mean by Logic Gates?

2. What are the applications of Logic Gates?
3. What is Truth Table?
4. Why we use basic logic gates?
5. Write down the truth table of all logic gates?
6. What do you mean by universal gate?
7. Write truth table for 2 I/P OR, NOR, AND and NAND gate?
8. Implement all logic gate by using Universal gate?
9. Why is they called Universal Gates?
10. Give the name of universal gate?
11. Draw circuit diagram of Half Adder circuit?
12. Draw circuit diagram of Full Adder circuit?
13. Draw Full Adder circuit by using Half Adder circuit and minimum no. of logic gate?
14. Write Boolean function for half adder? Q.5 Write Boolean function for Full adder?
15. Design the half Adder & Full Adder using NAND-NAND Logic.
16. Draw circuit diagram of Half Subtractor circuit?
17. Draw circuit diagram of Full Subtractor circuit?
18. Draw Full Subtractor circuit by using Half Subtractor circuit and minimum no. of logic
gate?
19. Write Boolean function for half Subtractor?
20. Write Boolean function for Full Subtractor?
21. What is Excess-3 code? Why it is called Excess-3 code?
22. What is the application of Excess-3 Code?
23. What is ASCII code?
24. Excess-3 code is Weighted or Unweighted?
25. Out of the possible 16 code combination? How many numbers used in Excess-3
code?
26. What is Demorgan’s Law?
27. Show the truth table for Demorgan’s Theorem?
28. What is Minterm & Maxterm?
29. How Minterm can be converted in Max term?

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30. What is Hybrid function?
31. What is Flip-Flop?
32. What is Latch circuit?
33. Draw a truth –tables of S-R, J-K, D and T?
34. What is the disadvantages of S-R Flip-Flop?
35. How can you remove the problem of S-R Flip –Flop?
36. Make circuit diagram of S-R, J-K, D and T Flip-Flop?
37. What do you understand by Race Aground condition? How it is over come in J-K Flip
Flop?
38. Explain the principle of Multiplexer?
39. Draw a circuit diagram of 4: 1 Multiplexer?
40. What are the advantages of Multiplexer?
41. What are the disadvantages of Multiplexer?
42. Make the Truth-table of Multiplexer?
43. Explain about Demultiplexer?
44. Draw a circuit diagram of 1: 4 Demultiplexer?
45. Make a logic diagram of 1: 4 Demultiplexer?
46. What is the application of Demultiplexer?
47. What is the difference between Multiplexer and Demultiplexer?

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 APPENDIX 1
NAND Gate (Three Input)

NAND Gate (Four Input)

NAND Gate (Three Input)

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50
4 Bit Ripple Counter Divide by 10 Counter

PIN DETAILS of LTS 542

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4 Bit Decade Up-Down Counter

Shift Register

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53
54